2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 /* $FreeBSD: head/sys/dev/usb/controller/xhci_pci.c 276717 2015-01-05 20:22:18Z hselasky $ */
28 #include <sys/stdint.h>
29 #include <sys/param.h>
30 #include <sys/queue.h>
31 #include <sys/types.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/condvar.h>
39 #include <sys/sysctl.h>
40 #include <sys/unistd.h>
41 #include <sys/callout.h>
42 #include <sys/malloc.h>
45 #include <bus/u4b/usb.h>
46 #include <bus/u4b/usbdi.h>
48 #include <bus/u4b/usb_core.h>
49 #include <bus/u4b/usb_busdma.h>
50 #include <bus/u4b/usb_process.h>
51 #include <bus/u4b/usb_util.h>
53 #include <bus/u4b/usb_controller.h>
54 #include <bus/u4b/usb_bus.h>
55 #include <bus/u4b/usb_pci.h>
56 #include <bus/u4b/controller/xhci.h>
57 #include <bus/u4b/controller/xhcireg.h>
60 static device_probe_t xhci_pci_probe;
61 static device_attach_t xhci_pci_attach;
62 static device_detach_t xhci_pci_detach;
63 static usb_take_controller_t xhci_pci_take_controller;
65 static device_method_t xhci_device_methods[] = {
66 /* device interface */
67 DEVMETHOD(device_probe, xhci_pci_probe),
68 DEVMETHOD(device_attach, xhci_pci_attach),
69 DEVMETHOD(device_detach, xhci_pci_detach),
70 DEVMETHOD(device_suspend, bus_generic_suspend),
71 DEVMETHOD(device_resume, bus_generic_resume),
72 DEVMETHOD(device_shutdown, bus_generic_shutdown),
73 DEVMETHOD(usb_take_controller, xhci_pci_take_controller),
78 static driver_t xhci_driver = {
80 .methods = xhci_device_methods,
81 .size = sizeof(struct xhci_softc),
84 static devclass_t xhci_devclass;
86 DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, NULL, NULL);
87 MODULE_DEPEND(xhci, usb, 1, 1, 1);
91 xhci_pci_match(device_t self)
93 uint32_t device_id = pci_get_devid(self);
97 return ("NEC uPD720200 USB 3.0 controller");
100 return ("ASMedia ASM1042 USB 3.0 controller");
103 return ("Intel Intel BayTrail USB 3.0 controller");
106 return ("Intel Panther Point USB 3.0 controller");
108 return ("Intel Lynx Point USB 3.0 controller");
110 return ("Intel Wildcat Point USB 3.0 controller");
112 return ("Intel Wildcat Point-LB USB 3.0 controller");
117 if ((pci_get_class(self) == PCIC_SERIALBUS)
118 && (pci_get_subclass(self) == PCIS_SERIALBUS_USB)
119 && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) {
120 return ("XHCI (generic) USB 3.0 controller");
122 return (NULL); /* dunno */
126 xhci_pci_probe(device_t self)
128 const char *desc = xhci_pci_match(self);
131 device_set_desc(self, desc);
138 static int xhci_use_msi = 1;
139 TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi);
142 xhci_interrupt_poll(void *_sc)
144 struct xhci_softc *sc = _sc;
145 USB_BUS_UNLOCK(&sc->sc_bus);
147 USB_BUS_LOCK(&sc->sc_bus);
148 usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc);
152 xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear)
158 temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) |
159 pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4);
164 /* Don't set bits which the hardware doesn't support */
165 usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4);
166 usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4);
168 pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4);
169 pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4);
171 device_printf(self, "Port routing mask set to 0x%08x\n", temp);
177 xhci_pci_attach(device_t self)
179 struct xhci_softc *sc = device_get_softc(self);
183 rid = PCI_XHCI_CBMEM;
184 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
186 if (!sc->sc_io_res) {
187 device_printf(self, "Could not map memory\n");
190 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
191 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
192 sc->sc_io_size = rman_get_size(sc->sc_io_res);
194 /* check for USB 3.0 controllers which don't support 64-bit DMA */
195 switch (pci_get_devid(self)) {
196 case 0x01941033: /* NEC uPD720200 USB 3.0 controller */
204 if (xhci_init(sc, self, usedma32)) {
205 device_printf(self, "Could not initialize softc\n");
206 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
211 pci_enable_busmaster(self);
213 usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_lock, 0);
217 count = pci_msi_count(self);
220 if (pci_alloc_msi(self, &rid, 1, count) == 0) {
222 device_printf(self, "MSI enabled\n");
227 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ,
228 &sc->sc_irq_rid, RF_SHAREABLE | RF_ACTIVE);
229 if (sc->sc_irq_res == NULL) {
230 pci_release_msi(self);
231 device_printf(self, "Could not allocate IRQ\n");
232 /* goto error; FALLTHROUGH - use polling */
234 sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
235 if (sc->sc_bus.bdev == NULL) {
236 device_printf(self, "Could not add USB device\n");
239 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
241 ksprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self));
243 if (sc->sc_irq_res != NULL) {
244 err = bus_setup_intr(self, sc->sc_irq_res, INTR_MPSAFE,
245 (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl, NULL);
247 bus_release_resource(self, SYS_RES_IRQ,
248 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
249 sc->sc_irq_res = NULL;
250 pci_release_msi(self);
251 device_printf(self, "Could not setup IRQ, err=%d\n", err);
252 sc->sc_intr_hdl = NULL;
255 if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) {
256 if (xhci_use_polling() != 0) {
257 device_printf(self, "Interrupt polling at %dHz\n", hz);
258 USB_BUS_LOCK(&sc->sc_bus);
259 xhci_interrupt_poll(sc);
260 USB_BUS_UNLOCK(&sc->sc_bus);
265 /* On Intel chipsets reroute ports from EHCI to XHCI controller. */
266 switch (pci_get_devid(self)) {
267 case 0x0f358086: /* BayTrail */
268 case 0x9c318086: /* Panther Point */
269 case 0x1e318086: /* Panther Point */
270 case 0x8c318086: /* Lynx Point */
271 case 0x8cb18086: /* Wildcat Point */
272 case 0x9cb18086: /* Wildcat Point-LP */
273 sc->sc_port_route = &xhci_pci_port_route;
274 sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP;
280 xhci_pci_take_controller(self);
282 err = xhci_halt_controller(sc);
285 err = xhci_start_controller(sc);
288 err = device_probe_and_attach(sc->sc_bus.bdev);
291 device_printf(self, "XHCI halt/start/probe failed err=%d\n", err);
297 xhci_pci_detach(self);
302 xhci_pci_detach(device_t self)
304 struct xhci_softc *sc = device_get_softc(self);
307 if (sc->sc_bus.bdev != NULL) {
308 bdev = sc->sc_bus.bdev;
310 device_delete_child(self, bdev);
312 /* during module unload there are lots of children leftover */
313 device_delete_children(self);
315 usb_callout_drain(&sc->sc_callout);
316 xhci_halt_controller(sc);
318 pci_disable_busmaster(self);
320 if (sc->sc_irq_res && sc->sc_intr_hdl) {
321 bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
322 sc->sc_intr_hdl = NULL;
324 if (sc->sc_irq_res) {
325 bus_release_resource(self, SYS_RES_IRQ,
326 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
327 sc->sc_irq_res = NULL;
328 pci_release_msi(self);
331 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
333 sc->sc_io_res = NULL;
342 xhci_pci_take_controller(device_t self)
344 struct xhci_softc *sc = device_get_softc(self);
351 cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0);
355 /* Synchronise with the BIOS if it owns the controller. */
356 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
357 eecp += XHCI_XECP_NEXT(eec) << 2) {
358 eec = XREAD4(sc, capa, eecp);
360 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
362 bios_sem = XREAD1(sc, capa, eecp +
366 device_printf(sc->sc_bus.bdev, "waiting for BIOS "
367 "to give up control\n");
368 XWRITE1(sc, capa, eecp +
369 XHCI_XECP_OS_SEM, 1);
372 bios_sem = XREAD1(sc, capa, eecp +
378 device_printf(sc->sc_bus.bdev,
379 "timed out waiting for BIOS\n");
382 usb_pause_mtx(NULL, hz / 100); /* wait 10ms */