sys/dev/netif/bnx/if_bnx.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  */
  35
  36
  37 #include "opt_polling.h"
  38
  39 #include <sys/param.h>
  40 #include <sys/bus.h>
  41 #include <sys/endian.h>
  42 #include <sys/kernel.h>
  43 #include <sys/interrupt.h>
  44 #include <sys/mbuf.h>
  45 #include <sys/malloc.h>
  46 #include <sys/queue.h>
  47 #include <sys/rman.h>
  48 #include <sys/serialize.h>
  49 #include <sys/socket.h>
  50 #include <sys/sockio.h>
  51 #include <sys/sysctl.h>
  52
  53 #include <net/bpf.h>
  54 #include <net/ethernet.h>
  55 #include <net/if.h>
  56 #include <net/if_arp.h>
  57 #include <net/if_dl.h>
  58 #include <net/if_media.h>
  59 #include <net/if_types.h>
  60 #include <net/ifq_var.h>
  61 #include <net/vlan/if_vlan_var.h>
  62 #include <net/vlan/if_vlan_ether.h>
  63
  64 #include <dev/netif/mii_layer/mii.h>
  65 #include <dev/netif/mii_layer/miivar.h>
  66 #include <dev/netif/mii_layer/brgphyreg.h>
  67
  68 #include <bus/pci/pcidevs.h>
  69 #include <bus/pci/pcireg.h>
  70 #include <bus/pci/pcivar.h>
  71
  72 #include <dev/netif/bge/if_bgereg.h>
  73 #include <dev/netif/bnx/if_bnxvar.h>
  74
  75 /* "device miibus" required.  See GENERIC if you get errors here. */
  76 #include "miibus_if.h"
  77
  78 #define BNX_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
  79
  80 static const struct bnx_type {
  81         uint16_t                bnx_vid;
  82         uint16_t                bnx_did;
  83         char                    *bnx_name;
  84 } bnx_devs[] = {
  85         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717,
  86                 "Broadcom BCM5717 Gigabit Ethernet" },
  87         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718,
  88                 "Broadcom BCM5718 Gigabit Ethernet" },
  89         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719,
  90                 "Broadcom BCM5719 Gigabit Ethernet" },
  91         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT,
  92                 "Broadcom BCM5720 Gigabit Ethernet" },
  93
  94         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761,
  95                 "Broadcom BCM57761 Gigabit Ethernet" },
  96         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781,
  97                 "Broadcom BCM57781 Gigabit Ethernet" },
  98         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791,
  99                 "Broadcom BCM57791 Fast Ethernet" },
 100         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765,
 101                 "Broadcom BCM57765 Gigabit Ethernet" },
 102         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785,
 103                 "Broadcom BCM57785 Gigabit Ethernet" },
 104         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795,
 105                 "Broadcom BCM57795 Fast Ethernet" },
 106
 107         { 0, 0, NULL }
 108 };
 109
 110 #define BNX_IS_JUMBO_CAPABLE(sc)        ((sc)->bnx_flags & BNX_FLAG_JUMBO)
 111 #define BNX_IS_5717_PLUS(sc)            ((sc)->bnx_flags & BNX_FLAG_5717_PLUS)
 112 #define BNX_IS_57765_PLUS(sc)           ((sc)->bnx_flags & BNX_FLAG_57765_PLUS)
 113 #define BNX_IS_57765_FAMILY(sc)  \
 114         ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY)
 115
 116 typedef int     (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]);
 117
 118 static int      bnx_probe(device_t);
 119 static int      bnx_attach(device_t);
 120 static int      bnx_detach(device_t);
 121 static void     bnx_shutdown(device_t);
 122 static int      bnx_suspend(device_t);
 123 static int      bnx_resume(device_t);
 124 static int      bnx_miibus_readreg(device_t, int, int);
 125 static int      bnx_miibus_writereg(device_t, int, int, int);
 126 static void     bnx_miibus_statchg(device_t);
 127
 128 #ifdef DEVICE_POLLING
 129 static void     bnx_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 130 #endif
 131 static void     bnx_intr_legacy(void *);
 132 static void     bnx_msi(void *);
 133 static void     bnx_msi_oneshot(void *);
 134 static void     bnx_intr(struct bnx_softc *);
 135 static void     bnx_enable_intr(struct bnx_softc *);
 136 static void     bnx_disable_intr(struct bnx_softc *);
 137 static void     bnx_txeof(struct bnx_softc *, uint16_t);
 138 static void     bnx_rxeof(struct bnx_softc *, uint16_t);
 139
 140 static void     bnx_start(struct ifnet *);
 141 static int      bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 142 static void     bnx_init(void *);
 143 static void     bnx_stop(struct bnx_softc *);
 144 static void     bnx_watchdog(struct ifnet *);
 145 static int      bnx_ifmedia_upd(struct ifnet *);
 146 static void     bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 147 static void     bnx_tick(void *);
 148
 149 static int      bnx_alloc_jumbo_mem(struct bnx_softc *);
 150 static void     bnx_free_jumbo_mem(struct bnx_softc *);
 151 static struct bnx_jslot
 152                 *bnx_jalloc(struct bnx_softc *);
 153 static void     bnx_jfree(void *);
 154 static void     bnx_jref(void *);
 155 static int      bnx_newbuf_std(struct bnx_softc *, int, int);
 156 static int      bnx_newbuf_jumbo(struct bnx_softc *, int, int);
 157 static void     bnx_setup_rxdesc_std(struct bnx_softc *, int);
 158 static void     bnx_setup_rxdesc_jumbo(struct bnx_softc *, int);
 159 static int      bnx_init_rx_ring_std(struct bnx_softc *);
 160 static void     bnx_free_rx_ring_std(struct bnx_softc *);
 161 static int      bnx_init_rx_ring_jumbo(struct bnx_softc *);
 162 static void     bnx_free_rx_ring_jumbo(struct bnx_softc *);
 163 static void     bnx_free_tx_ring(struct bnx_softc *);
 164 static int      bnx_init_tx_ring(struct bnx_softc *);
 165 static int      bnx_dma_alloc(struct bnx_softc *);
 166 static void     bnx_dma_free(struct bnx_softc *);
 167 static int      bnx_dma_block_alloc(struct bnx_softc *, bus_size_t,
 168                     bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *);
 169 static void     bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 170 static struct mbuf *
 171                 bnx_defrag_shortdma(struct mbuf *);
 172 static int      bnx_encap(struct bnx_softc *, struct mbuf **, uint32_t *);
 173
 174 static void     bnx_reset(struct bnx_softc *);
 175 static int      bnx_chipinit(struct bnx_softc *);
 176 static int      bnx_blockinit(struct bnx_softc *);
 177 static void     bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t);
 178 static void     bnx_enable_msi(struct bnx_softc *sc);
 179 static void     bnx_setmulti(struct bnx_softc *);
 180 static void     bnx_setpromisc(struct bnx_softc *);
 181 static void     bnx_stats_update_regs(struct bnx_softc *);
 182 static uint32_t bnx_dma_swap_options(struct bnx_softc *);
 183
 184 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t);
 185 static void     bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t);
 186 #ifdef notdef
 187 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t);
 188 #endif
 189 static void     bnx_writereg_ind(struct bnx_softc *, uint32_t, uint32_t);
 190 static void     bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t);
 191 static void     bnx_writembx(struct bnx_softc *, int, int);
 192 static uint8_t  bnx_nvram_getbyte(struct bnx_softc *, int, uint8_t *);
 193 static int      bnx_read_nvram(struct bnx_softc *, caddr_t, int, int);
 194 static uint8_t  bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *);
 195 static int      bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t);
 196
 197 static void     bnx_tbi_link_upd(struct bnx_softc *, uint32_t);
 198 static void     bnx_copper_link_upd(struct bnx_softc *, uint32_t);
 199 static void     bnx_autopoll_link_upd(struct bnx_softc *, uint32_t);
 200 static void     bnx_link_poll(struct bnx_softc *);
 201
 202 static int      bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]);
 203 static int      bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]);
 204 static int      bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]);
 205 static int      bnx_get_eaddr(struct bnx_softc *, uint8_t[]);
 206
 207 static void     bnx_coal_change(struct bnx_softc *);
 208 static int      bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 209 static int      bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 210 static int      bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
 211 static int      bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
 212 static int      bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 213 static int      bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 214 static int      bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
 215                     int, int, uint32_t);
 216
 217 static int      bnx_msi_enable = 1;
 218 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable);
 219
 220 static device_method_t bnx_methods[] = {
 221         /* Device interface */
 222         DEVMETHOD(device_probe,         bnx_probe),
 223         DEVMETHOD(device_attach,        bnx_attach),
 224         DEVMETHOD(device_detach,        bnx_detach),
 225         DEVMETHOD(device_shutdown,      bnx_shutdown),
 226         DEVMETHOD(device_suspend,       bnx_suspend),
 227         DEVMETHOD(device_resume,        bnx_resume),
 228
 229         /* bus interface */
 230         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 231         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 232
 233         /* MII interface */
 234         DEVMETHOD(miibus_readreg,       bnx_miibus_readreg),
 235         DEVMETHOD(miibus_writereg,      bnx_miibus_writereg),
 236         DEVMETHOD(miibus_statchg,       bnx_miibus_statchg),
 237
 238         { 0, 0 }
 239 };
 240
 241 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc));
 242 static devclass_t bnx_devclass;
 243
 244 DECLARE_DUMMY_MODULE(if_bnx);
 245 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL);
 246 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL);
 247
 248 static uint32_t
 249 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off)
 250 {
 251         device_t dev = sc->bnx_dev;
 252         uint32_t val;
 253
 254         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
 255             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 256                 return 0;
 257
 258         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 259         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 260         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 261         return (val);
 262 }
 263
 264 static void
 265 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
 266 {
 267         device_t dev = sc->bnx_dev;
 268
 269         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
 270             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 271                 return;
 272
 273         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 274         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 275         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 276 }
 277
 278 #ifdef notdef
 279 static uint32_t
 280 bnx_readreg_ind(struct bnx_softc *sc, uin32_t off)
 281 {
 282         device_t dev = sc->bnx_dev;
 283
 284         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 285         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 286 }
 287 #endif
 288
 289 static void
 290 bnx_writereg_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
 291 {
 292         device_t dev = sc->bnx_dev;
 293
 294         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 295         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 296 }
 297
 298 static void
 299 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val)
 300 {
 301         CSR_WRITE_4(sc, off, val);
 302 }
 303
 304 static void
 305 bnx_writembx(struct bnx_softc *sc, int off, int val)
 306 {
 307         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906)
 308                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 309
 310         CSR_WRITE_4(sc, off, val);
 311 }
 312
 313 static uint8_t
 314 bnx_nvram_getbyte(struct bnx_softc *sc, int addr, uint8_t *dest)
 315 {
 316         uint32_t access, byte = 0;
 317         int i;
 318
 319         /* Lock. */
 320         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 321         for (i = 0; i < 8000; i++) {
 322                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 323                         break;
 324                 DELAY(20);
 325         }
 326         if (i == 8000)
 327                 return (1);
 328
 329         /* Enable access. */
 330         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 331         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 332
 333         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 334         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 335         for (i = 0; i < BNX_TIMEOUT * 10; i++) {
 336                 DELAY(10);
 337                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 338                         DELAY(10);
 339                         break;
 340                 }
 341         }
 342
 343         if (i == BNX_TIMEOUT * 10) {
 344                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
 345                 return (1);
 346         }
 347
 348         /* Get result. */
 349         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 350
 351         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 352
 353         /* Disable access. */
 354         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 355
 356         /* Unlock. */
 357         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 358         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 359
 360         return (0);
 361 }
 362
 363 /*
 364  * Read a sequence of bytes from NVRAM.
 365  */
 366 static int
 367 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt)
 368 {
 369         int err = 0, i;
 370         uint8_t byte = 0;
 371
 372         if (sc->bnx_asicrev != BGE_ASICREV_BCM5906)
 373                 return (1);
 374
 375         for (i = 0; i < cnt; i++) {
 376                 err = bnx_nvram_getbyte(sc, off + i, &byte);
 377                 if (err)
 378                         break;
 379                 *(dest + i) = byte;
 380         }
 381
 382         return (err ? 1 : 0);
 383 }
 384
 385 /*
 386  * Read a byte of data stored in the EEPROM at address 'addr.' The
 387  * BCM570x supports both the traditional bitbang interface and an
 388  * auto access interface for reading the EEPROM. We use the auto
 389  * access method.
 390  */
 391 static uint8_t
 392 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest)
 393 {
 394         int i;
 395         uint32_t byte = 0;
 396
 397         /*
 398          * Enable use of auto EEPROM access so we can avoid
 399          * having to use the bitbang method.
 400          */
 401         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 402
 403         /* Reset the EEPROM, load the clock period. */
 404         CSR_WRITE_4(sc, BGE_EE_ADDR,
 405             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 406         DELAY(20);
 407
 408         /* Issue the read EEPROM command. */
 409         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 410
 411         /* Wait for completion */
 412         for(i = 0; i < BNX_TIMEOUT * 10; i++) {
 413                 DELAY(10);
 414                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 415                         break;
 416         }
 417
 418         if (i == BNX_TIMEOUT) {
 419                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 420                 return(1);
 421         }
 422
 423         /* Get result. */
 424         byte = CSR_READ_4(sc, BGE_EE_DATA);
 425
 426         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 427
 428         return(0);
 429 }
 430
 431 /*
 432  * Read a sequence of bytes from the EEPROM.
 433  */
 434 static int
 435 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len)
 436 {
 437         size_t i;
 438         int err;
 439         uint8_t byte;
 440
 441         for (byte = 0, err = 0, i = 0; i < len; i++) {
 442                 err = bnx_eeprom_getbyte(sc, off + i, &byte);
 443                 if (err)
 444                         break;
 445                 *(dest + i) = byte;
 446         }
 447
 448         return(err ? 1 : 0);
 449 }
 450
 451 static int
 452 bnx_miibus_readreg(device_t dev, int phy, int reg)
 453 {
 454         struct bnx_softc *sc = device_get_softc(dev);
 455         uint32_t val;
 456         int i;
 457
 458         KASSERT(phy == sc->bnx_phyno,
 459             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 460
 461         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 462         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 463                 CSR_WRITE_4(sc, BGE_MI_MODE,
 464                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 465                 DELAY(80);
 466         }
 467
 468         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 469             BGE_MIPHY(phy) | BGE_MIREG(reg));
 470
 471         /* Poll for the PHY register access to complete. */
 472         for (i = 0; i < BNX_TIMEOUT; i++) {
 473                 DELAY(10);
 474                 val = CSR_READ_4(sc, BGE_MI_COMM);
 475                 if ((val & BGE_MICOMM_BUSY) == 0) {
 476                         DELAY(5);
 477                         val = CSR_READ_4(sc, BGE_MI_COMM);
 478                         break;
 479                 }
 480         }
 481         if (i == BNX_TIMEOUT) {
 482                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
 483                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 484                 val = 0;
 485         }
 486
 487         /* Restore the autopoll bit if necessary. */
 488         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 489                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 490                 DELAY(80);
 491         }
 492
 493         if (val & BGE_MICOMM_READFAIL)
 494                 return 0;
 495
 496         return (val & 0xFFFF);
 497 }
 498
 499 static int
 500 bnx_miibus_writereg(device_t dev, int phy, int reg, int val)
 501 {
 502         struct bnx_softc *sc = device_get_softc(dev);
 503         int i;
 504
 505         KASSERT(phy == sc->bnx_phyno,
 506             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 507
 508         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
 509             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 510                return 0;
 511
 512         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 513         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 514                 CSR_WRITE_4(sc, BGE_MI_MODE,
 515                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 516                 DELAY(80);
 517         }
 518
 519         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 520             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 521
 522         for (i = 0; i < BNX_TIMEOUT; i++) {
 523                 DELAY(10);
 524                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 525                         DELAY(5);
 526                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 527                         break;
 528                 }
 529         }
 530         if (i == BNX_TIMEOUT) {
 531                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 532                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
 533         }
 534
 535         /* Restore the autopoll bit if necessary. */
 536         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 537                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 538                 DELAY(80);
 539         }
 540
 541         return 0;
 542 }
 543
 544 static void
 545 bnx_miibus_statchg(device_t dev)
 546 {
 547         struct bnx_softc *sc;
 548         struct mii_data *mii;
 549
 550         sc = device_get_softc(dev);
 551         mii = device_get_softc(sc->bnx_miibus);
 552
 553         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 554             (IFM_ACTIVE | IFM_AVALID)) {
 555                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 556                 case IFM_10_T:
 557                 case IFM_100_TX:
 558                         sc->bnx_link = 1;
 559                         break;
 560                 case IFM_1000_T:
 561                 case IFM_1000_SX:
 562                 case IFM_2500_SX:
 563                         if (sc->bnx_asicrev != BGE_ASICREV_BCM5906)
 564                                 sc->bnx_link = 1;
 565                         else
 566                                 sc->bnx_link = 0;
 567                         break;
 568                 default:
 569                         sc->bnx_link = 0;
 570                         break;
 571                 }
 572         } else {
 573                 sc->bnx_link = 0;
 574         }
 575         if (sc->bnx_link == 0)
 576                 return;
 577
 578         BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 579         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 580             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
 581                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 582         } else {
 583                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 584         }
 585
 586         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 587                 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 588         } else {
 589                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 590         }
 591 }
 592
 593 /*
 594  * Memory management for jumbo frames.
 595  */
 596 static int
 597 bnx_alloc_jumbo_mem(struct bnx_softc *sc)
 598 {
 599         struct ifnet *ifp = &sc->arpcom.ac_if;
 600         struct bnx_jslot *entry;
 601         uint8_t *ptr;
 602         bus_addr_t paddr;
 603         int i, error;
 604
 605         /*
 606          * Create tag for jumbo mbufs.
 607          * This is really a bit of a kludge. We allocate a special
 608          * jumbo buffer pool which (thanks to the way our DMA
 609          * memory allocation works) will consist of contiguous
 610          * pages. This means that even though a jumbo buffer might
 611          * be larger than a page size, we don't really need to
 612          * map it into more than one DMA segment. However, the
 613          * default mbuf tag will result in multi-segment mappings,
 614          * so we have to create a special jumbo mbuf tag that
 615          * lets us get away with mapping the jumbo buffers as
 616          * a single segment. I think eventually the driver should
 617          * be changed so that it uses ordinary mbufs and cluster
 618          * buffers, i.e. jumbo frames can span multiple DMA
 619          * descriptors. But that's a project for another day.
 620          */
 621
 622         /*
 623          * Create DMA stuffs for jumbo RX ring.
 624          */
 625         error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 626                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 627                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 628                                     (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring,
 629                                     &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
 630         if (error) {
 631                 if_printf(ifp, "could not create jumbo RX ring\n");
 632                 return error;
 633         }
 634
 635         /*
 636          * Create DMA stuffs for jumbo buffer block.
 637          */
 638         error = bnx_dma_block_alloc(sc, BNX_JMEM,
 639                                     &sc->bnx_cdata.bnx_jumbo_tag,
 640                                     &sc->bnx_cdata.bnx_jumbo_map,
 641                                     (void **)&sc->bnx_ldata.bnx_jumbo_buf,
 642                                     &paddr);
 643         if (error) {
 644                 if_printf(ifp, "could not create jumbo buffer\n");
 645                 return error;
 646         }
 647
 648         SLIST_INIT(&sc->bnx_jfree_listhead);
 649
 650         /*
 651          * Now divide it up into 9K pieces and save the addresses
 652          * in an array. Note that we play an evil trick here by using
 653          * the first few bytes in the buffer to hold the the address
 654          * of the softc structure for this interface. This is because
 655          * bnx_jfree() needs it, but it is called by the mbuf management
 656          * code which will not pass it to us explicitly.
 657          */
 658         for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) {
 659                 entry = &sc->bnx_cdata.bnx_jslots[i];
 660                 entry->bnx_sc = sc;
 661                 entry->bnx_buf = ptr;
 662                 entry->bnx_paddr = paddr;
 663                 entry->bnx_inuse = 0;
 664                 entry->bnx_slot = i;
 665                 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link);
 666
 667                 ptr += BNX_JLEN;
 668                 paddr += BNX_JLEN;
 669         }
 670         return 0;
 671 }
 672
 673 static void
 674 bnx_free_jumbo_mem(struct bnx_softc *sc)
 675 {
 676         /* Destroy jumbo RX ring. */
 677         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 678                            sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 679                            sc->bnx_ldata.bnx_rx_jumbo_ring);
 680
 681         /* Destroy jumbo buffer block. */
 682         bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag,
 683                            sc->bnx_cdata.bnx_jumbo_map,
 684                            sc->bnx_ldata.bnx_jumbo_buf);
 685 }
 686
 687 /*
 688  * Allocate a jumbo buffer.
 689  */
 690 static struct bnx_jslot *
 691 bnx_jalloc(struct bnx_softc *sc)
 692 {
 693         struct bnx_jslot *entry;
 694
 695         lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 696         entry = SLIST_FIRST(&sc->bnx_jfree_listhead);
 697         if (entry) {
 698                 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link);
 699                 entry->bnx_inuse = 1;
 700         } else {
 701                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 702         }
 703         lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 704         return(entry);
 705 }
 706
 707 /*
 708  * Adjust usage count on a jumbo buffer.
 709  */
 710 static void
 711 bnx_jref(void *arg)
 712 {
 713         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 714         struct bnx_softc *sc = entry->bnx_sc;
 715
 716         if (sc == NULL)
 717                 panic("bnx_jref: can't find softc pointer!");
 718
 719         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 720                 panic("bnx_jref: asked to reference buffer "
 721                     "that we don't manage!");
 722         } else if (entry->bnx_inuse == 0) {
 723                 panic("bnx_jref: buffer already free!");
 724         } else {
 725                 atomic_add_int(&entry->bnx_inuse, 1);
 726         }
 727 }
 728
 729 /*
 730  * Release a jumbo buffer.
 731  */
 732 static void
 733 bnx_jfree(void *arg)
 734 {
 735         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 736         struct bnx_softc *sc = entry->bnx_sc;
 737
 738         if (sc == NULL)
 739                 panic("bnx_jfree: can't find softc pointer!");
 740
 741         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 742                 panic("bnx_jfree: asked to free buffer that we don't manage!");
 743         } else if (entry->bnx_inuse == 0) {
 744                 panic("bnx_jfree: buffer already free!");
 745         } else {
 746                 /*
 747                  * Possible MP race to 0, use the serializer.  The atomic insn
 748                  * is still needed for races against bnx_jref().
 749                  */
 750                 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 751                 atomic_subtract_int(&entry->bnx_inuse, 1);
 752                 if (entry->bnx_inuse == 0) {
 753                         SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead,
 754                                           entry, jslot_link);
 755                 }
 756                 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 757         }
 758 }
 759
 760
 761 /*
 762  * Intialize a standard receive ring descriptor.
 763  */
 764 static int
 765 bnx_newbuf_std(struct bnx_softc *sc, int i, int init)
 766 {
 767         struct mbuf *m_new = NULL;
 768         bus_dma_segment_t seg;
 769         bus_dmamap_t map;
 770         int error, nsegs;
 771
 772         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 773         if (m_new == NULL)
 774                 return ENOBUFS;
 775         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 776         m_adj(m_new, ETHER_ALIGN);
 777
 778         error = bus_dmamap_load_mbuf_segment(sc->bnx_cdata.bnx_rx_mtag,
 779                         sc->bnx_cdata.bnx_rx_tmpmap, m_new,
 780                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
 781         if (error) {
 782                 m_freem(m_new);
 783                 return error;
 784         }
 785
 786         if (!init) {
 787                 bus_dmamap_sync(sc->bnx_cdata.bnx_rx_mtag,
 788                                 sc->bnx_cdata.bnx_rx_std_dmamap[i],
 789                                 BUS_DMASYNC_POSTREAD);
 790                 bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
 791                         sc->bnx_cdata.bnx_rx_std_dmamap[i]);
 792         }
 793
 794         map = sc->bnx_cdata.bnx_rx_tmpmap;
 795         sc->bnx_cdata.bnx_rx_tmpmap = sc->bnx_cdata.bnx_rx_std_dmamap[i];
 796         sc->bnx_cdata.bnx_rx_std_dmamap[i] = map;
 797
 798         sc->bnx_cdata.bnx_rx_std_chain[i].bnx_mbuf = m_new;
 799         sc->bnx_cdata.bnx_rx_std_chain[i].bnx_paddr = seg.ds_addr;
 800
 801         bnx_setup_rxdesc_std(sc, i);
 802         return 0;
 803 }
 804
 805 static void
 806 bnx_setup_rxdesc_std(struct bnx_softc *sc, int i)
 807 {
 808         struct bnx_rxchain *rc;
 809         struct bge_rx_bd *r;
 810
 811         rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
 812         r = &sc->bnx_ldata.bnx_rx_std_ring[i];
 813
 814         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
 815         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
 816         r->bge_len = rc->bnx_mbuf->m_len;
 817         r->bge_idx = i;
 818         r->bge_flags = BGE_RXBDFLAG_END;
 819 }
 820
 821 /*
 822  * Initialize a jumbo receive ring descriptor. This allocates
 823  * a jumbo buffer from the pool managed internally by the driver.
 824  */
 825 static int
 826 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init)
 827 {
 828         struct mbuf *m_new = NULL;
 829         struct bnx_jslot *buf;
 830         bus_addr_t paddr;
 831
 832         /* Allocate the mbuf. */
 833         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
 834         if (m_new == NULL)
 835                 return ENOBUFS;
 836
 837         /* Allocate the jumbo buffer */
 838         buf = bnx_jalloc(sc);
 839         if (buf == NULL) {
 840                 m_freem(m_new);
 841                 return ENOBUFS;
 842         }
 843
 844         /* Attach the buffer to the mbuf. */
 845         m_new->m_ext.ext_arg = buf;
 846         m_new->m_ext.ext_buf = buf->bnx_buf;
 847         m_new->m_ext.ext_free = bnx_jfree;
 848         m_new->m_ext.ext_ref = bnx_jref;
 849         m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN;
 850
 851         m_new->m_flags |= M_EXT;
 852
 853         m_new->m_data = m_new->m_ext.ext_buf;
 854         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 855
 856         paddr = buf->bnx_paddr;
 857         m_adj(m_new, ETHER_ALIGN);
 858         paddr += ETHER_ALIGN;
 859
 860         /* Save necessary information */
 861         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_mbuf = m_new;
 862         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_paddr = paddr;
 863
 864         /* Set up the descriptor. */
 865         bnx_setup_rxdesc_jumbo(sc, i);
 866         return 0;
 867 }
 868
 869 static void
 870 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i)
 871 {
 872         struct bge_rx_bd *r;
 873         struct bnx_rxchain *rc;
 874
 875         r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i];
 876         rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 877
 878         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
 879         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
 880         r->bge_len = rc->bnx_mbuf->m_len;
 881         r->bge_idx = i;
 882         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 883 }
 884
 885 static int
 886 bnx_init_rx_ring_std(struct bnx_softc *sc)
 887 {
 888         int i, error;
 889
 890         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 891                 error = bnx_newbuf_std(sc, i, 1);
 892                 if (error)
 893                         return error;
 894         };
 895
 896         sc->bnx_std = BGE_STD_RX_RING_CNT - 1;
 897         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
 898
 899         return(0);
 900 }
 901
 902 static void
 903 bnx_free_rx_ring_std(struct bnx_softc *sc)
 904 {
 905         int i;
 906
 907         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 908                 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
 909
 910                 if (rc->bnx_mbuf != NULL) {
 911                         bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
 912                                           sc->bnx_cdata.bnx_rx_std_dmamap[i]);
 913                         m_freem(rc->bnx_mbuf);
 914                         rc->bnx_mbuf = NULL;
 915                 }
 916                 bzero(&sc->bnx_ldata.bnx_rx_std_ring[i],
 917                     sizeof(struct bge_rx_bd));
 918         }
 919 }
 920
 921 static int
 922 bnx_init_rx_ring_jumbo(struct bnx_softc *sc)
 923 {
 924         struct bge_rcb *rcb;
 925         int i, error;
 926
 927         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 928                 error = bnx_newbuf_jumbo(sc, i, 1);
 929                 if (error)
 930                         return error;
 931         };
 932
 933         sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
 934
 935         rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
 936         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 937         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 938
 939         bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
 940
 941         return(0);
 942 }
 943
 944 static void
 945 bnx_free_rx_ring_jumbo(struct bnx_softc *sc)
 946 {
 947         int i;
 948
 949         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 950                 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 951
 952                 if (rc->bnx_mbuf != NULL) {
 953                         m_freem(rc->bnx_mbuf);
 954                         rc->bnx_mbuf = NULL;
 955                 }
 956                 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i],
 957                     sizeof(struct bge_rx_bd));
 958         }
 959 }
 960
 961 static void
 962 bnx_free_tx_ring(struct bnx_softc *sc)
 963 {
 964         int i;
 965
 966         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 967                 if (sc->bnx_cdata.bnx_tx_chain[i] != NULL) {
 968                         bus_dmamap_unload(sc->bnx_cdata.bnx_tx_mtag,
 969                                           sc->bnx_cdata.bnx_tx_dmamap[i]);
 970                         m_freem(sc->bnx_cdata.bnx_tx_chain[i]);
 971                         sc->bnx_cdata.bnx_tx_chain[i] = NULL;
 972                 }
 973                 bzero(&sc->bnx_ldata.bnx_tx_ring[i],
 974                     sizeof(struct bge_tx_bd));
 975         }
 976 }
 977
 978 static int
 979 bnx_init_tx_ring(struct bnx_softc *sc)
 980 {
 981         sc->bnx_txcnt = 0;
 982         sc->bnx_tx_saved_considx = 0;
 983         sc->bnx_tx_prodidx = 0;
 984
 985         /* Initialize transmit producer index for host-memory send ring. */
 986         bnx_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bnx_tx_prodidx);
 987         bnx_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 988
 989         return(0);
 990 }
 991
 992 static void
 993 bnx_setmulti(struct bnx_softc *sc)
 994 {
 995         struct ifnet *ifp;
 996         struct ifmultiaddr *ifma;
 997         uint32_t hashes[4] = { 0, 0, 0, 0 };
 998         int h, i;
 999
1000         ifp = &sc->arpcom.ac_if;
1001
1002         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1003                 for (i = 0; i < 4; i++)
1004                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1005                 return;
1006         }
1007
1008         /* First, zot all the existing filters. */
1009         for (i = 0; i < 4; i++)
1010                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1011
1012         /* Now program new ones. */
1013         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1014                 if (ifma->ifma_addr->sa_family != AF_LINK)
1015                         continue;
1016                 h = ether_crc32_le(
1017                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1018                     ETHER_ADDR_LEN) & 0x7f;
1019                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1020         }
1021
1022         for (i = 0; i < 4; i++)
1023                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1024 }
1025
1026 /*
1027  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1028  * self-test results.
1029  */
1030 static int
1031 bnx_chipinit(struct bnx_softc *sc)
1032 {
1033         uint32_t dma_rw_ctl, mode_ctl;
1034         int i;
1035
1036         /* Set endian type before we access any non-PCI registers. */
1037         pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL,
1038             BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4);
1039
1040         /* Clear the MAC control register */
1041         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1042
1043         /*
1044          * Clear the MAC statistics block in the NIC's
1045          * internal memory.
1046          */
1047         for (i = BGE_STATS_BLOCK;
1048             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1049                 BNX_MEMWIN_WRITE(sc, i, 0);
1050
1051         for (i = BGE_STATUS_BLOCK;
1052             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1053                 BNX_MEMWIN_WRITE(sc, i, 0);
1054
1055         if (BNX_IS_57765_FAMILY(sc)) {
1056                 uint32_t val;
1057
1058                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) {
1059                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1060                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1061
1062                         /* Access the lower 1K of PL PCI-E block registers. */
1063                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1064                             val | BGE_MODECTL_PCIE_PL_SEL);
1065
1066                         val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5);
1067                         val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ;
1068                         CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val);
1069
1070                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1071                 }
1072                 if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) {
1073                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1074                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1075
1076                         /* Access the lower 1K of DL PCI-E block registers. */
1077                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1078                             val | BGE_MODECTL_PCIE_DL_SEL);
1079
1080                         val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX);
1081                         val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK;
1082                         val |= BGE_PCIE_DL_LO_FTSMAX_VAL;
1083                         CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val);
1084
1085                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1086                 }
1087
1088                 val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
1089                 val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
1090                 val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
1091                 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val);
1092         }
1093
1094         /*
1095          * Set up the PCI DMA control register.
1096          */
1097         dma_rw_ctl = pci_read_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, 4);
1098         /*
1099          * Disable 32bytes cache alignment for DMA write to host memory
1100          *
1101          * NOTE:
1102          * 64bytes cache alignment for DMA write to host memory is still
1103          * enabled.
1104          */
1105         dma_rw_ctl |= BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1106         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
1107                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1108         /*
1109          * Enable HW workaround for controllers that misinterpret
1110          * a status tag update and leave interrupts permanently
1111          * disabled.
1112          */
1113         if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 &&
1114             !BNX_IS_57765_FAMILY(sc))
1115                 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1116         if (bootverbose) {
1117                 if_printf(&sc->arpcom.ac_if, "DMA read/write %#x\n",
1118                     dma_rw_ctl);
1119         }
1120         pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1121
1122         /*
1123          * Set up general mode register.
1124          */
1125         mode_ctl = bnx_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1126             BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1127         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1128
1129         /*
1130          * Disable memory write invalidate.  Apparently it is not supported
1131          * properly by these devices.  Also ensure that INTx isn't disabled,
1132          * as these chips need it even when using MSI.
1133          */
1134         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD,
1135             (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1136
1137         /* Set the timer prescaler (always 66Mhz) */
1138         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1139
1140         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
1141                 DELAY(40);      /* XXX */
1142
1143                 /* Put PHY into ready state */
1144                 BNX_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1145                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1146                 DELAY(40);
1147         }
1148
1149         return(0);
1150 }
1151
1152 static int
1153 bnx_blockinit(struct bnx_softc *sc)
1154 {
1155         struct bge_rcb *rcb;
1156         bus_size_t vrcb;
1157         bge_hostaddr taddr;
1158         uint32_t val;
1159         int i, limit;
1160
1161         /*
1162          * Initialize the memory window pointer register so that
1163          * we can access the first 32K of internal NIC RAM. This will
1164          * allow us to set up the TX send ring RCBs and the RX return
1165          * ring RCBs, plus other things which live in NIC memory.
1166          */
1167         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1168
1169         /* Configure mbuf pool watermarks */
1170         if (BNX_IS_57765_PLUS(sc)) {
1171                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1172                 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) {
1173                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1174                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1175                 } else {
1176                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1177                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1178                 }
1179         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
1180                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1181                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1182                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1183         } else {
1184                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1185                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1186                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1187         }
1188
1189         /* Configure DMA resource watermarks */
1190         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1191         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1192
1193         /* Enable buffer manager */
1194         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1195         /*
1196          * Change the arbitration algorithm of TXMBUF read request to
1197          * round-robin instead of priority based for BCM5719.  When
1198          * TXFIFO is almost empty, RDMA will hold its request until
1199          * TXFIFO is not almost empty.
1200          */
1201         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719)
1202                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1203         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1204             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0 ||
1205             sc->bnx_chipid == BGE_CHIPID_BCM5720_A0)
1206                 val |= BGE_BMANMODE_LOMBUF_ATTN;
1207         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1208
1209         /* Poll for buffer manager start indication */
1210         for (i = 0; i < BNX_TIMEOUT; i++) {
1211                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1212                         break;
1213                 DELAY(10);
1214         }
1215
1216         if (i == BNX_TIMEOUT) {
1217                 if_printf(&sc->arpcom.ac_if,
1218                           "buffer manager failed to start\n");
1219                 return(ENXIO);
1220         }
1221
1222         /* Enable flow-through queues */
1223         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1224         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1225
1226         /* Wait until queue initialization is complete */
1227         for (i = 0; i < BNX_TIMEOUT; i++) {
1228                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1229                         break;
1230                 DELAY(10);
1231         }
1232
1233         if (i == BNX_TIMEOUT) {
1234                 if_printf(&sc->arpcom.ac_if,
1235                           "flow-through queue init failed\n");
1236                 return(ENXIO);
1237         }
1238
1239         /*
1240          * Summary of rings supported by the controller:
1241          *
1242          * Standard Receive Producer Ring
1243          * - This ring is used to feed receive buffers for "standard"
1244          *   sized frames (typically 1536 bytes) to the controller.
1245          *
1246          * Jumbo Receive Producer Ring
1247          * - This ring is used to feed receive buffers for jumbo sized
1248          *   frames (i.e. anything bigger than the "standard" frames)
1249          *   to the controller.
1250          *
1251          * Mini Receive Producer Ring
1252          * - This ring is used to feed receive buffers for "mini"
1253          *   sized frames to the controller.
1254          * - This feature required external memory for the controller
1255          *   but was never used in a production system.  Should always
1256          *   be disabled.
1257          *
1258          * Receive Return Ring
1259          * - After the controller has placed an incoming frame into a
1260          *   receive buffer that buffer is moved into a receive return
1261          *   ring.  The driver is then responsible to passing the
1262          *   buffer up to the stack.  Many versions of the controller
1263          *   support multiple RR rings.
1264          *
1265          * Send Ring
1266          * - This ring is used for outgoing frames.  Many versions of
1267          *   the controller support multiple send rings.
1268          */
1269
1270         /* Initialize the standard receive producer ring control block. */
1271         rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb;
1272         rcb->bge_hostaddr.bge_addr_lo =
1273             BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1274         rcb->bge_hostaddr.bge_addr_hi =
1275             BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1276         if (BNX_IS_57765_PLUS(sc)) {
1277                 /*
1278                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1279                  * Bits 15-2 : Maximum RX frame size
1280                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
1281                  * Bit 0     : Reserved
1282                  */
1283                 rcb->bge_maxlen_flags =
1284                     BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2);
1285         } else {
1286                 /*
1287                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1288                  * Bits 15-2 : Reserved (should be 0)
1289                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1290                  * Bit 0     : Reserved
1291                  */
1292                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1293         }
1294         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1295             sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1296             sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1297                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1298         else
1299                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1300         /* Write the standard receive producer ring control block. */
1301         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1302         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1303         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1304         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1305         /* Reset the standard receive producer ring producer index. */
1306         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1307
1308         /*
1309          * Initialize the jumbo RX producer ring control
1310          * block.  We set the 'ring disabled' bit in the
1311          * flags field until we're actually ready to start
1312          * using this ring (i.e. once we set the MTU
1313          * high enough to require it).
1314          */
1315         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1316                 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
1317                 /* Get the jumbo receive producer ring RCB parameters. */
1318                 rcb->bge_hostaddr.bge_addr_lo =
1319                     BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1320                 rcb->bge_hostaddr.bge_addr_hi =
1321                     BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1322                 rcb->bge_maxlen_flags =
1323                     BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN,
1324                     BGE_RCB_FLAG_RING_DISABLED);
1325                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1326                     sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1327                     sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1328                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1329                 else
1330                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1331                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1332                     rcb->bge_hostaddr.bge_addr_hi);
1333                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1334                     rcb->bge_hostaddr.bge_addr_lo);
1335                 /* Program the jumbo receive producer ring RCB parameters. */
1336                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1337                     rcb->bge_maxlen_flags);
1338                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1339                 /* Reset the jumbo receive producer ring producer index. */
1340                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1341         }
1342
1343         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1344         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
1345             (sc->bnx_chipid == BGE_CHIPID_BCM5906_A0 ||
1346              sc->bnx_chipid == BGE_CHIPID_BCM5906_A1 ||
1347              sc->bnx_chipid == BGE_CHIPID_BCM5906_A2)) {
1348                 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1349                     (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1350         }
1351
1352         /*
1353          * The BD ring replenish thresholds control how often the
1354          * hardware fetches new BD's from the producer rings in host
1355          * memory.  Setting the value too low on a busy system can
1356          * starve the hardware and recue the throughpout.
1357          *
1358          * Set the BD ring replentish thresholds. The recommended
1359          * values are 1/8th the number of descriptors allocated to
1360          * each ring.
1361          */
1362         val = 8;
1363         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1364         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1365                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1366                     BGE_JUMBO_RX_RING_CNT/8);
1367         }
1368         if (BNX_IS_57765_PLUS(sc)) {
1369                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1370                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1371         }
1372
1373         /*
1374          * Disable all send rings by setting the 'ring disabled' bit
1375          * in the flags field of all the TX send ring control blocks,
1376          * located in NIC memory.
1377          */
1378         if (BNX_IS_5717_PLUS(sc))
1379                 limit = 4;
1380         else if (BNX_IS_57765_FAMILY(sc))
1381                 limit = 2;
1382         else
1383                 limit = 1;
1384         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1385         for (i = 0; i < limit; i++) {
1386                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1387                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1388                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1389                 vrcb += sizeof(struct bge_rcb);
1390         }
1391
1392         /* Configure send ring RCB 0 (we use only the first ring) */
1393         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1394         BGE_HOSTADDR(taddr, sc->bnx_ldata.bnx_tx_ring_paddr);
1395         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1396         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1397         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1398             sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1399             sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1400                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1401         } else {
1402                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1403                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1404         }
1405         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1406             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1407
1408         /*
1409          * Disable all receive return rings by setting the
1410          * 'ring disabled' bit in the flags field of all the receive
1411          * return ring control blocks, located in NIC memory.
1412          */
1413         if (BNX_IS_5717_PLUS(sc)) {
1414                 /* Should be 17, use 16 until we get an SRAM map. */
1415                 limit = 16;
1416         } else if (BNX_IS_57765_FAMILY(sc)) {
1417                 limit = 4;
1418         } else {
1419                 limit = 1;
1420         }
1421         /* Disable all receive return rings. */
1422         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1423         for (i = 0; i < limit; i++) {
1424                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1425                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1426                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1427                     BGE_RCB_FLAG_RING_DISABLED);
1428                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1429                 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO +
1430                     (i * (sizeof(uint64_t))), 0);
1431                 vrcb += sizeof(struct bge_rcb);
1432         }
1433
1434         /*
1435          * Set up receive return ring 0.  Note that the NIC address
1436          * for RX return rings is 0x0.  The return rings live entirely
1437          * within the host, so the nicaddr field in the RCB isn't used.
1438          */
1439         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1440         BGE_HOSTADDR(taddr, sc->bnx_ldata.bnx_rx_return_ring_paddr);
1441         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1442         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1443         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1444         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1445             BGE_RCB_MAXLEN_FLAGS(sc->bnx_return_ring_cnt, 0));
1446
1447         /* Set random backoff seed for TX */
1448         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1449             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1450             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1451             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1452             BGE_TX_BACKOFF_SEED_MASK);
1453
1454         /* Set inter-packet gap */
1455         val = 0x2620;
1456         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1457                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1458                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1459         }
1460         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1461
1462         /*
1463          * Specify which ring to use for packets that don't match
1464          * any RX rules.
1465          */
1466         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1467
1468         /*
1469          * Configure number of RX lists. One interrupt distribution
1470          * list, sixteen active lists, one bad frames class.
1471          */
1472         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1473
1474         /* Inialize RX list placement stats mask. */
1475         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1476         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1477
1478         /* Disable host coalescing until we get it set up */
1479         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1480
1481         /* Poll to make sure it's shut down. */
1482         for (i = 0; i < BNX_TIMEOUT; i++) {
1483                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1484                         break;
1485                 DELAY(10);
1486         }
1487
1488         if (i == BNX_TIMEOUT) {
1489                 if_printf(&sc->arpcom.ac_if,
1490                           "host coalescing engine failed to idle\n");
1491                 return(ENXIO);
1492         }
1493
1494         /* Set up host coalescing defaults */
1495         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bnx_rx_coal_ticks);
1496         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bnx_tx_coal_ticks);
1497         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bnx_rx_coal_bds);
1498         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bnx_tx_coal_bds);
1499         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bnx_rx_coal_bds_int);
1500         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bnx_tx_coal_bds_int);
1501
1502         /* Set up address of status block */
1503         bzero(sc->bnx_ldata.bnx_status_block, BGE_STATUS_BLK_SZ);
1504         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1505             BGE_ADDR_HI(sc->bnx_ldata.bnx_status_block_paddr));
1506         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1507             BGE_ADDR_LO(sc->bnx_ldata.bnx_status_block_paddr));
1508
1509         /* Set up status block partail update size. */
1510         val = BGE_STATBLKSZ_32BYTE;
1511 #if 0
1512         /*
1513          * Does not seem to have visible effect in both
1514          * bulk data (1472B UDP datagram) and tiny data
1515          * (18B UDP datagram) TX tests.
1516          */
1517         val |= BGE_HCCMODE_CLRTICK_TX;
1518 #endif
1519         /* Turn on host coalescing state machine */
1520         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1521
1522         /* Turn on RX BD completion state machine and enable attentions */
1523         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1524             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1525
1526         /* Turn on RX list placement state machine */
1527         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1528
1529         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1530             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1531             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1532             BGE_MACMODE_FRMHDR_DMA_ENB;
1533
1534         if (sc->bnx_flags & BNX_FLAG_TBI)
1535                 val |= BGE_PORTMODE_TBI;
1536         else if (sc->bnx_flags & BNX_FLAG_MII_SERDES)
1537                 val |= BGE_PORTMODE_GMII;
1538         else
1539                 val |= BGE_PORTMODE_MII;
1540
1541         /* Turn on DMA, clear stats */
1542         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1543
1544         /* Set misc. local control, enable interrupts on attentions */
1545         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1546
1547 #ifdef notdef
1548         /* Assert GPIO pins for PHY reset */
1549         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1550             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1551         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1552             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1553 #endif
1554
1555         /* Turn on write DMA state machine */
1556         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1557         /* Enable host coalescing bug fix. */
1558         val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1559         if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) {
1560                 /* Request larger DMA burst size to get better performance. */
1561                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1562         }
1563         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1564         DELAY(40);
1565
1566         if (BNX_IS_57765_PLUS(sc)) {
1567                 uint32_t dmactl;
1568
1569                 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
1570                 /*
1571                  * Adjust tx margin to prevent TX data corruption and
1572                  * fix internal FIFO overflow.
1573                  */
1574                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1575                     sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1576                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
1577                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
1578                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
1579                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
1580                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
1581                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
1582                 }
1583                 /*
1584                  * Enable fix for read DMA FIFO overruns.
1585                  * The fix is to limit the number of RX BDs
1586                  * the hardware would fetch at a fime.
1587                  */
1588                 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
1589                     dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1590         }
1591
1592         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) {
1593                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1594                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1595                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
1596                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1597         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1598                 /*
1599                  * Allow 4KB burst length reads for non-LSO frames.
1600                  * Enable 512B burst length reads for buffer descriptors.
1601                  */
1602                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1603                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1604                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
1605                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1606         }
1607
1608         /* Turn on read DMA state machine */
1609         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1610         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717)
1611                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
1612         if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 ||
1613             sc->bnx_asicrev == BGE_ASICREV_BCM5785 ||
1614             sc->bnx_asicrev == BGE_ASICREV_BCM57780) {
1615                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1616                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1617                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1618         }
1619         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1620                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
1621                     BGE_RDMAMODE_H2BNC_VLAN_DET;
1622                 /*
1623                  * Allow multiple outstanding read requests from
1624                  * non-LSO read DMA engine.
1625                  */
1626                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
1627         }
1628         val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1629         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1630         DELAY(40);
1631
1632         /* Turn on RX data completion state machine */
1633         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1634
1635         /* Turn on RX BD initiator state machine */
1636         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1637
1638         /* Turn on RX data and RX BD initiator state machine */
1639         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1640
1641         /* Turn on send BD completion state machine */
1642         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1643
1644         /* Turn on send data completion state machine */
1645         val = BGE_SDCMODE_ENABLE;
1646         if (sc->bnx_asicrev == BGE_ASICREV_BCM5761)
1647                 val |= BGE_SDCMODE_CDELAY;
1648         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1649
1650         /* Turn on send data initiator state machine */
1651         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1652
1653         /* Turn on send BD initiator state machine */
1654         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1655
1656         /* Turn on send BD selector state machine */
1657         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1658
1659         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1660         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1661             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1662
1663         /* ack/clear link change events */
1664         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1665             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1666             BGE_MACSTAT_LINK_CHANGED);
1667         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1668
1669         /*
1670          * Enable attention when the link has changed state for
1671          * devices that use auto polling.
1672          */
1673         if (sc->bnx_flags & BNX_FLAG_TBI) {
1674                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1675         } else {
1676                 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1677                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
1678                         DELAY(80);
1679                 }
1680         }
1681
1682         /*
1683          * Clear any pending link state attention.
1684          * Otherwise some link state change events may be lost until attention
1685          * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence.
1686          * It's not necessary on newer BCM chips - perhaps enabling link
1687          * state change attentions implies clearing pending attention.
1688          */
1689         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1690             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1691             BGE_MACSTAT_LINK_CHANGED);
1692
1693         /* Enable link state change attentions. */
1694         BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1695
1696         return(0);
1697 }
1698
1699 /*
1700  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1701  * against our list and return its name if we find a match. Note
1702  * that since the Broadcom controller contains VPD support, we
1703  * can get the device name string from the controller itself instead
1704  * of the compiled-in string. This is a little slow, but it guarantees
1705  * we'll always announce the right product name.
1706  */
1707 static int
1708 bnx_probe(device_t dev)
1709 {
1710         const struct bnx_type *t;
1711         uint16_t product, vendor;
1712
1713         if (!pci_is_pcie(dev))
1714                 return ENXIO;
1715
1716         product = pci_get_device(dev);
1717         vendor = pci_get_vendor(dev);
1718
1719         for (t = bnx_devs; t->bnx_name != NULL; t++) {
1720                 if (vendor == t->bnx_vid && product == t->bnx_did)
1721                         break;
1722         }
1723         if (t->bnx_name == NULL)
1724                 return ENXIO;
1725
1726         device_set_desc(dev, t->bnx_name);
1727         return 0;
1728 }
1729
1730 static int
1731 bnx_attach(device_t dev)
1732 {
1733         struct ifnet *ifp;
1734         struct bnx_softc *sc;
1735         uint32_t hwcfg = 0, misccfg;
1736         int error = 0, rid, capmask;
1737         uint8_t ether_addr[ETHER_ADDR_LEN];
1738         uint16_t product, vendor;
1739         driver_intr_t *intr_func;
1740         uintptr_t mii_priv = 0;
1741         u_int intr_flags;
1742
1743         sc = device_get_softc(dev);
1744         sc->bnx_dev = dev;
1745         callout_init(&sc->bnx_stat_timer);
1746         lwkt_serialize_init(&sc->bnx_jslot_serializer);
1747
1748         product = pci_get_device(dev);
1749         vendor = pci_get_vendor(dev);
1750
1751 #ifndef BURN_BRIDGES
1752         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1753                 uint32_t irq, mem;
1754
1755                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1756                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1757
1758                 device_printf(dev, "chip is in D%d power mode "
1759                     "-- setting to D0\n", pci_get_powerstate(dev));
1760
1761                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1762
1763                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1764                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1765         }
1766 #endif  /* !BURN_BRIDGE */
1767
1768         /*
1769          * Map control/status registers.
1770          */
1771         pci_enable_busmaster(dev);
1772
1773         rid = BGE_PCI_BAR0;
1774         sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1775             RF_ACTIVE);
1776
1777         if (sc->bnx_res == NULL) {
1778                 device_printf(dev, "couldn't map memory\n");
1779                 return ENXIO;
1780         }
1781
1782         sc->bnx_btag = rman_get_bustag(sc->bnx_res);
1783         sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res);
1784
1785         /* Save various chip information */
1786         sc->bnx_chipid =
1787             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1788             BGE_PCIMISCCTL_ASICREV_SHIFT;
1789         if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) {
1790                 /* All chips having dedicated ASICREV register have CPMU */
1791                 sc->bnx_flags |= BNX_FLAG_CPMU;
1792
1793                 switch (product) {
1794                 case PCI_PRODUCT_BROADCOM_BCM5717:
1795                 case PCI_PRODUCT_BROADCOM_BCM5718:
1796                 case PCI_PRODUCT_BROADCOM_BCM5719:
1797                 case PCI_PRODUCT_BROADCOM_BCM5720_ALT:
1798                         sc->bnx_chipid = pci_read_config(dev,
1799                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
1800                         break;
1801
1802                 case PCI_PRODUCT_BROADCOM_BCM57761:
1803                 case PCI_PRODUCT_BROADCOM_BCM57765:
1804                 case PCI_PRODUCT_BROADCOM_BCM57781:
1805                 case PCI_PRODUCT_BROADCOM_BCM57785:
1806                 case PCI_PRODUCT_BROADCOM_BCM57791:
1807                 case PCI_PRODUCT_BROADCOM_BCM57795:
1808                         sc->bnx_chipid = pci_read_config(dev,
1809                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
1810                         break;
1811
1812                 default:
1813                         sc->bnx_chipid = pci_read_config(dev,
1814                             BGE_PCI_PRODID_ASICREV, 4);
1815                         break;
1816                 }
1817         }
1818         sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid);
1819         sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid);
1820
1821         switch (sc->bnx_asicrev) {
1822         case BGE_ASICREV_BCM5717:
1823         case BGE_ASICREV_BCM5719:
1824         case BGE_ASICREV_BCM5720:
1825                 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS;
1826                 break;
1827
1828         case BGE_ASICREV_BCM57765:
1829                 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS;
1830                 break;
1831         }
1832         sc->bnx_flags |= BNX_FLAG_SHORTDMA;
1833
1834         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906)
1835                 sc->bnx_flags |= BNX_FLAG_NO_EEPROM;
1836
1837         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
1838
1839         sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev);
1840         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1841             sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1842                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048);
1843         else
1844                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1845         device_printf(dev, "CHIP ID 0x%08x; "
1846                       "ASIC REV 0x%02x; CHIP REV 0x%02x\n",
1847                       sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev);
1848
1849         /*
1850          * Set various PHY quirk flags.
1851          */
1852
1853         capmask = MII_CAPMASK_DEFAULT;
1854         if ((sc->bnx_asicrev == BGE_ASICREV_BCM5703 &&
1855              (misccfg == 0x4000 || misccfg == 0x8000)) ||
1856             (sc->bnx_asicrev == BGE_ASICREV_BCM5705 &&
1857              vendor == PCI_VENDOR_BROADCOM &&
1858              (product == PCI_PRODUCT_BROADCOM_BCM5901 ||
1859               product == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
1860               product == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
1861             (vendor == PCI_VENDOR_BROADCOM &&
1862              (product == PCI_PRODUCT_BROADCOM_BCM5751F ||
1863               product == PCI_PRODUCT_BROADCOM_BCM5753F ||
1864               product == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
1865             product == PCI_PRODUCT_BROADCOM_BCM57790 ||
1866             sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
1867                 /* 10/100 only */
1868                 capmask &= ~BMSR_EXTSTAT;
1869         }
1870
1871         mii_priv |= BRGPHY_FLAG_WIRESPEED;
1872
1873         /*
1874          * Allocate interrupt
1875          */
1876         sc->bnx_irq_type = pci_alloc_1intr(dev, bnx_msi_enable, &sc->bnx_irq_rid,
1877             &intr_flags);
1878
1879         sc->bnx_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bnx_irq_rid,
1880             intr_flags);
1881         if (sc->bnx_irq == NULL) {
1882                 device_printf(dev, "couldn't map interrupt\n");
1883                 error = ENXIO;
1884                 goto fail;
1885         }
1886
1887         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
1888                 sc->bnx_flags |= BNX_FLAG_ONESHOT_MSI;
1889                 bnx_enable_msi(sc);
1890         }
1891
1892         /* Initialize if_name earlier, so if_printf could be used */
1893         ifp = &sc->arpcom.ac_if;
1894         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1895
1896         /* Try to reset the chip. */
1897         bnx_reset(sc);
1898
1899         if (bnx_chipinit(sc)) {
1900                 device_printf(dev, "chip initialization failed\n");
1901                 error = ENXIO;
1902                 goto fail;
1903         }
1904
1905         /*
1906          * Get station address
1907          */
1908         error = bnx_get_eaddr(sc, ether_addr);
1909         if (error) {
1910                 device_printf(dev, "failed to read station address\n");
1911                 goto fail;
1912         }
1913
1914         if (BNX_IS_57765_PLUS(sc)) {
1915                 sc->bnx_return_ring_cnt = BGE_RETURN_RING_CNT;
1916         } else {
1917                 /* 5705/5750 limits RX return ring to 512 entries. */
1918                 sc->bnx_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1919         }
1920
1921         error = bnx_dma_alloc(sc);
1922         if (error)
1923                 goto fail;
1924
1925         /* Set default tuneable values. */
1926         sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF;
1927         sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF;
1928         sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF;
1929         sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF;
1930         sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_DEF;
1931         sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_DEF;
1932
1933         /* Set up ifnet structure */
1934         ifp->if_softc = sc;
1935         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1936         ifp->if_ioctl = bnx_ioctl;
1937         ifp->if_start = bnx_start;
1938 #ifdef DEVICE_POLLING
1939         ifp->if_poll = bnx_poll;
1940 #endif
1941         ifp->if_watchdog = bnx_watchdog;
1942         ifp->if_init = bnx_init;
1943         ifp->if_mtu = ETHERMTU;
1944         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1945         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1946         ifq_set_ready(&ifp->if_snd);
1947
1948         ifp->if_capabilities |= IFCAP_HWCSUM;
1949         ifp->if_hwassist = BNX_CSUM_FEATURES;
1950         ifp->if_capenable = ifp->if_capabilities;
1951
1952         /*
1953          * Figure out what sort of media we have by checking the
1954          * hardware config word in the first 32k of NIC internal memory,
1955          * or fall back to examining the EEPROM if necessary.
1956          * Note: on some BCM5700 cards, this value appears to be unset.
1957          * If that's the case, we have to rely on identifying the NIC
1958          * by its PCI subsystem ID, as we do below for the SysKonnect
1959          * SK-9D41.
1960          */
1961         if (bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
1962                 hwcfg = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1963         } else {
1964                 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1965                                     sizeof(hwcfg))) {
1966                         device_printf(dev, "failed to read EEPROM\n");
1967                         error = ENXIO;
1968                         goto fail;
1969                 }
1970                 hwcfg = ntohl(hwcfg);
1971         }
1972
1973         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1974         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
1975             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1976                 sc->bnx_flags |= BNX_FLAG_TBI;
1977
1978         /* Setup MI MODE */
1979         if (sc->bnx_flags & BNX_FLAG_CPMU)
1980                 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST;
1981         else
1982                 sc->bnx_mi_mode = BGE_MIMODE_BASE;
1983
1984         /* Setup link status update stuffs */
1985         if (sc->bnx_flags & BNX_FLAG_TBI) {
1986                 sc->bnx_link_upd = bnx_tbi_link_upd;
1987                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1988         } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1989                 sc->bnx_link_upd = bnx_autopoll_link_upd;
1990                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1991         } else {
1992                 sc->bnx_link_upd = bnx_copper_link_upd;
1993                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1994         }
1995
1996         /* Set default PHY address */
1997         sc->bnx_phyno = 1;
1998
1999         /*
2000          * PHY address mapping for various devices.
2001          *
2002          *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
2003          * ---------+-------+-------+-------+-------+
2004          * BCM57XX  |   1   |   X   |   X   |   X   |
2005          * BCM5704  |   1   |   X   |   1   |   X   |
2006          * BCM5717  |   1   |   8   |   2   |   9   |
2007          * BCM5719  |   1   |   8   |   2   |   9   |
2008          * BCM5720  |   1   |   8   |   2   |   9   |
2009          *
2010          * Other addresses may respond but they are not
2011          * IEEE compliant PHYs and should be ignored.
2012          */
2013         if (BNX_IS_5717_PLUS(sc)) {
2014                 int f;
2015
2016                 f = pci_get_function(dev);
2017                 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) {
2018                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
2019                             BGE_SGDIGSTS_IS_SERDES)
2020                                 sc->bnx_phyno = f + 8;
2021                         else
2022                                 sc->bnx_phyno = f + 1;
2023                 } else {
2024                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
2025                             BGE_CPMU_PHY_STRAP_IS_SERDES)
2026                                 sc->bnx_phyno = f + 8;
2027                         else
2028                                 sc->bnx_phyno = f + 1;
2029                 }
2030         }
2031
2032         if (sc->bnx_flags & BNX_FLAG_TBI) {
2033                 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK,
2034                     bnx_ifmedia_upd, bnx_ifmedia_sts);
2035                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2036                 ifmedia_add(&sc->bnx_ifmedia,
2037                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2038                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2039                 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO);
2040                 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media;
2041         } else {
2042                 struct mii_probe_args mii_args;
2043
2044                 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts);
2045                 mii_args.mii_probemask = 1 << sc->bnx_phyno;
2046                 mii_args.mii_capmask = capmask;
2047                 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2048                 mii_args.mii_priv = mii_priv;
2049
2050                 error = mii_probe(dev, &sc->bnx_miibus, &mii_args);
2051                 if (error) {
2052                         device_printf(dev, "MII without any PHY!\n");
2053                         goto fail;
2054                 }
2055         }
2056
2057         /*
2058          * Create sysctl nodes.
2059          */
2060         sysctl_ctx_init(&sc->bnx_sysctl_ctx);
2061         sc->bnx_sysctl_tree = SYSCTL_ADD_NODE(&sc->bnx_sysctl_ctx,
2062                                               SYSCTL_STATIC_CHILDREN(_hw),
2063                                               OID_AUTO,
2064                                               device_get_nameunit(dev),
2065                                               CTLFLAG_RD, 0, "");
2066         if (sc->bnx_sysctl_tree == NULL) {
2067                 device_printf(dev, "can't add sysctl node\n");
2068                 error = ENXIO;
2069                 goto fail;
2070         }
2071
2072         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2073                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2074                         OID_AUTO, "rx_coal_ticks",
2075                         CTLTYPE_INT | CTLFLAG_RW,
2076                         sc, 0, bnx_sysctl_rx_coal_ticks, "I",
2077                         "Receive coalescing ticks (usec).");
2078         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2079                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2080                         OID_AUTO, "tx_coal_ticks",
2081                         CTLTYPE_INT | CTLFLAG_RW,
2082                         sc, 0, bnx_sysctl_tx_coal_ticks, "I",
2083                         "Transmit coalescing ticks (usec).");
2084         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2085                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2086                         OID_AUTO, "rx_coal_bds",
2087                         CTLTYPE_INT | CTLFLAG_RW,
2088                         sc, 0, bnx_sysctl_rx_coal_bds, "I",
2089                         "Receive max coalesced BD count.");
2090         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2091                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2092                         OID_AUTO, "tx_coal_bds",
2093                         CTLTYPE_INT | CTLFLAG_RW,
2094                         sc, 0, bnx_sysctl_tx_coal_bds, "I",
2095                         "Transmit max coalesced BD count.");
2096         /*
2097          * A common design characteristic for many Broadcom
2098          * client controllers is that they only support a
2099          * single outstanding DMA read operation on the PCIe
2100          * bus. This means that it will take twice as long to
2101          * fetch a TX frame that is split into header and
2102          * payload buffers as it does to fetch a single,
2103          * contiguous TX frame (2 reads vs. 1 read). For these
2104          * controllers, coalescing buffers to reduce the number
2105          * of memory reads is effective way to get maximum
2106          * performance(about 940Mbps).  Without collapsing TX
2107          * buffers the maximum TCP bulk transfer performance
2108          * is about 850Mbps. However forcing coalescing mbufs
2109          * consumes a lot of CPU cycles, so leave it off by
2110          * default.
2111          */
2112         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2113             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2114             "force_defrag", CTLFLAG_RW, &sc->bnx_force_defrag, 0,
2115             "Force defragment on TX path");
2116
2117         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2118             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2119             "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2120             sc, 0, bnx_sysctl_rx_coal_bds_int, "I",
2121             "Receive max coalesced BD count during interrupt.");
2122         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2123             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2124             "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2125             sc, 0, bnx_sysctl_tx_coal_bds_int, "I",
2126             "Transmit max coalesced BD count during interrupt.");
2127
2128         /*
2129          * Call MI attach routine.
2130          */
2131         ether_ifattach(ifp, ether_addr, NULL);
2132
2133         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
2134                 if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
2135                         intr_func = bnx_msi_oneshot;
2136                         if (bootverbose)
2137                                 device_printf(dev, "oneshot MSI\n");
2138                 } else {
2139                         intr_func = bnx_msi;
2140                 }
2141         } else {
2142                 intr_func = bnx_intr_legacy;
2143         }
2144         error = bus_setup_intr(dev, sc->bnx_irq, INTR_MPSAFE, intr_func, sc,
2145             &sc->bnx_intrhand, ifp->if_serializer);
2146         if (error) {
2147                 ether_ifdetach(ifp);
2148                 device_printf(dev, "couldn't set up irq\n");
2149                 goto fail;
2150         }
2151
2152         ifp->if_cpuid = rman_get_cpuid(sc->bnx_irq);
2153         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2154
2155         return(0);
2156 fail:
2157         bnx_detach(dev);
2158         return(error);
2159 }
2160
2161 static int
2162 bnx_detach(device_t dev)
2163 {
2164         struct bnx_softc *sc = device_get_softc(dev);
2165
2166         if (device_is_attached(dev)) {
2167                 struct ifnet *ifp = &sc->arpcom.ac_if;
2168
2169                 lwkt_serialize_enter(ifp->if_serializer);
2170                 bnx_stop(sc);
2171                 bnx_reset(sc);
2172                 bus_teardown_intr(dev, sc->bnx_irq, sc->bnx_intrhand);
2173                 lwkt_serialize_exit(ifp->if_serializer);
2174
2175                 ether_ifdetach(ifp);
2176         }
2177
2178         if (sc->bnx_flags & BNX_FLAG_TBI)
2179                 ifmedia_removeall(&sc->bnx_ifmedia);
2180         if (sc->bnx_miibus)
2181                 device_delete_child(dev, sc->bnx_miibus);
2182         bus_generic_detach(dev);
2183
2184         if (sc->bnx_irq != NULL) {
2185                 bus_release_resource(dev, SYS_RES_IRQ, sc->bnx_irq_rid,
2186                     sc->bnx_irq);
2187         }
2188         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI)
2189                 pci_release_msi(dev);
2190
2191         if (sc->bnx_res != NULL) {
2192                 bus_release_resource(dev, SYS_RES_MEMORY,
2193                     BGE_PCI_BAR0, sc->bnx_res);
2194         }
2195
2196         if (sc->bnx_sysctl_tree != NULL)
2197                 sysctl_ctx_free(&sc->bnx_sysctl_ctx);
2198
2199         bnx_dma_free(sc);
2200
2201         return 0;
2202 }
2203
2204 static void
2205 bnx_reset(struct bnx_softc *sc)
2206 {
2207         device_t dev;
2208         uint32_t cachesize, command, pcistate, reset;
2209         void (*write_op)(struct bnx_softc *, uint32_t, uint32_t);
2210         int i, val = 0;
2211         uint16_t devctl;
2212
2213         dev = sc->bnx_dev;
2214
2215         if (sc->bnx_asicrev != BGE_ASICREV_BCM5906)
2216                 write_op = bnx_writemem_direct;
2217         else
2218                 write_op = bnx_writereg_ind;
2219
2220         /* Save some important PCI state. */
2221         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2222         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2223         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2224
2225         pci_write_config(dev, BGE_PCI_MISC_CTL,
2226             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2227             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2228             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2229
2230         /* Disable fastboot on controllers that support it. */
2231         if (bootverbose)
2232                 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2233         CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2234
2235         /*
2236          * Write the magic number to SRAM at offset 0xB50.
2237          * When firmware finishes its initialization it will
2238          * write ~BGE_MAGIC_NUMBER to the same location.
2239          */
2240         bnx_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2241
2242         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2243
2244         /* XXX: Broadcom Linux driver. */
2245         /* Force PCI-E 1.0a mode */
2246         if (!BNX_IS_57765_PLUS(sc) &&
2247             CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2248             (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2249              BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2250                 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2251                     BGE_PCIE_PHY_TSTCTL_PSCRAM);
2252         }
2253         if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) {
2254                 /* Prevent PCIE link training during global reset */
2255                 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2256                 reset |= (1<<29);
2257         }
2258
2259         /*
2260          * Set GPHY Power Down Override to leave GPHY
2261          * powered up in D0 uninitialized.
2262          */
2263         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0)
2264                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2265
2266         /* Issue global reset */
2267         write_op(sc, BGE_MISC_CFG, reset);
2268
2269         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
2270                 uint32_t status, ctrl;
2271
2272                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2273                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2274                     status | BGE_VCPU_STATUS_DRV_RESET);
2275                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2276                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2277                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2278         }
2279
2280         DELAY(1000);
2281
2282         /* XXX: Broadcom Linux driver. */
2283         if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) {
2284                 uint32_t v;
2285
2286                 DELAY(500000); /* wait for link training to complete */
2287                 v = pci_read_config(dev, 0xc4, 4);
2288                 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2289         }
2290
2291         devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2);
2292
2293         /* Disable no snoop and disable relaxed ordering. */
2294         devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2295
2296         /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2297         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) {
2298                 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2299                 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2300         }
2301
2302         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL,
2303             devctl, 2);
2304
2305         /* Clear error status. */
2306         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS,
2307             PCIEM_DEVSTS_CORR_ERR |
2308             PCIEM_DEVSTS_NFATAL_ERR |
2309             PCIEM_DEVSTS_FATAL_ERR |
2310             PCIEM_DEVSTS_UNSUPP_REQ, 2);
2311
2312         /* Reset some of the PCI state that got zapped by reset */
2313         pci_write_config(dev, BGE_PCI_MISC_CTL,
2314             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2315             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2316             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2317         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2318         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2319         write_op(sc, BGE_MISC_CFG, (65 << 1));
2320
2321         /* Enable memory arbiter */
2322         CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2323
2324         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
2325                 for (i = 0; i < BNX_TIMEOUT; i++) {
2326                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2327                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2328                                 break;
2329                         DELAY(100);
2330                 }
2331                 if (i == BNX_TIMEOUT) {
2332                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2333                         return;
2334                 }
2335         } else {
2336                 /*
2337                  * Poll until we see the 1's complement of the magic number.
2338                  * This indicates that the firmware initialization
2339                  * is complete.
2340                  */
2341                 for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) {
2342                         val = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2343                         if (val == ~BGE_MAGIC_NUMBER)
2344                                 break;
2345                         DELAY(10);
2346                 }
2347                 if (i == BNX_FIRMWARE_TIMEOUT) {
2348                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2349                                   "timed out, found 0x%08x\n", val);
2350                 }
2351
2352                 /* BCM57765 A0 needs additional time before accessing. */
2353                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
2354                         DELAY(10 * 1000);
2355         }
2356
2357         /*
2358          * XXX Wait for the value of the PCISTATE register to
2359          * return to its original pre-reset state. This is a
2360          * fairly good indicator of reset completion. If we don't
2361          * wait for the reset to fully complete, trying to read
2362          * from the device's non-PCI registers may yield garbage
2363          * results.
2364          */
2365         for (i = 0; i < BNX_TIMEOUT; i++) {
2366                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2367                         break;
2368                 DELAY(10);
2369         }
2370
2371         /* Fix up byte swapping */
2372         CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc));
2373
2374         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2375
2376         /*
2377          * The 5704 in TBI mode apparently needs some special
2378          * adjustment to insure the SERDES drive level is set
2379          * to 1.2V.
2380          */
2381         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 &&
2382             (sc->bnx_flags & BNX_FLAG_TBI)) {
2383                 uint32_t serdescfg;
2384
2385                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2386                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2387                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2388         }
2389
2390         /* XXX: Broadcom Linux driver. */
2391         if (!BNX_IS_57765_PLUS(sc)) {
2392                 uint32_t v;
2393
2394                 /* Enable Data FIFO protection. */
2395                 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2396                 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2397         }
2398
2399         DELAY(10000);
2400
2401         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
2402                 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
2403                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
2404         }
2405 }
2406
2407 /*
2408  * Frame reception handling. This is called if there's a frame
2409  * on the receive return list.
2410  *
2411  * Note: we have to be able to handle two possibilities here:
2412  * 1) the frame is from the jumbo recieve ring
2413  * 2) the frame is from the standard receive ring
2414  */
2415
2416 static void
2417 bnx_rxeof(struct bnx_softc *sc, uint16_t rx_prod)
2418 {
2419         struct ifnet *ifp;
2420         int stdcnt = 0, jumbocnt = 0;
2421
2422         ifp = &sc->arpcom.ac_if;
2423
2424         while (sc->bnx_rx_saved_considx != rx_prod) {
2425                 struct bge_rx_bd        *cur_rx;
2426                 uint32_t                rxidx;
2427                 struct mbuf             *m = NULL;
2428                 uint16_t                vlan_tag = 0;
2429                 int                     have_tag = 0;
2430
2431                 cur_rx =
2432             &sc->bnx_ldata.bnx_rx_return_ring[sc->bnx_rx_saved_considx];
2433
2434                 rxidx = cur_rx->bge_idx;
2435                 BNX_INC(sc->bnx_rx_saved_considx, sc->bnx_return_ring_cnt);
2436
2437                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2438                         have_tag = 1;
2439                         vlan_tag = cur_rx->bge_vlan_tag;
2440                 }
2441
2442                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2443                         BNX_INC(sc->bnx_jumbo, BGE_JUMBO_RX_RING_CNT);
2444                         jumbocnt++;
2445
2446                         if (rxidx != sc->bnx_jumbo) {
2447                                 ifp->if_ierrors++;
2448                                 if_printf(ifp, "sw jumbo index(%d) "
2449                                     "and hw jumbo index(%d) mismatch, drop!\n",
2450                                     sc->bnx_jumbo, rxidx);
2451                                 bnx_setup_rxdesc_jumbo(sc, rxidx);
2452                                 continue;
2453                         }
2454
2455                         m = sc->bnx_cdata.bnx_rx_jumbo_chain[rxidx].bnx_mbuf;
2456                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2457                                 ifp->if_ierrors++;
2458                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2459                                 continue;
2460                         }
2461                         if (bnx_newbuf_jumbo(sc, sc->bnx_jumbo, 0)) {
2462                                 ifp->if_ierrors++;
2463                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2464                                 continue;
2465                         }
2466                 } else {
2467                         BNX_INC(sc->bnx_std, BGE_STD_RX_RING_CNT);
2468                         stdcnt++;
2469
2470                         if (rxidx != sc->bnx_std) {
2471                                 ifp->if_ierrors++;
2472                                 if_printf(ifp, "sw std index(%d) "
2473                                     "and hw std index(%d) mismatch, drop!\n",
2474                                     sc->bnx_std, rxidx);
2475                                 bnx_setup_rxdesc_std(sc, rxidx);
2476                                 continue;
2477                         }
2478
2479                         m = sc->bnx_cdata.bnx_rx_std_chain[rxidx].bnx_mbuf;
2480                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2481                                 ifp->if_ierrors++;
2482                                 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2483                                 continue;
2484                         }
2485                         if (bnx_newbuf_std(sc, sc->bnx_std, 0)) {
2486                                 ifp->if_ierrors++;
2487                                 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2488                                 continue;
2489                         }
2490                 }
2491
2492                 ifp->if_ipackets++;
2493                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2494                 m->m_pkthdr.rcvif = ifp;
2495
2496                 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2497                     (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
2498                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2499                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2500                                 if ((cur_rx->bge_error_flag &
2501                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
2502                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2503                         }
2504                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2505                                 m->m_pkthdr.csum_data =
2506                                     cur_rx->bge_tcp_udp_csum;
2507                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2508                                     CSUM_PSEUDO_HDR;
2509                         }
2510                 }
2511
2512                 /*
2513                  * If we received a packet with a vlan tag, pass it
2514                  * to vlan_input() instead of ether_input().
2515                  */
2516                 if (have_tag) {
2517                         m->m_flags |= M_VLANTAG;
2518                         m->m_pkthdr.ether_vlantag = vlan_tag;
2519                         have_tag = vlan_tag = 0;
2520                 }
2521                 ifp->if_input(ifp, m);
2522         }
2523
2524         bnx_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bnx_rx_saved_considx);
2525         if (stdcnt)
2526                 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
2527         if (jumbocnt)
2528                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
2529 }
2530
2531 static void
2532 bnx_txeof(struct bnx_softc *sc, uint16_t tx_cons)
2533 {
2534         struct bge_tx_bd *cur_tx = NULL;
2535         struct ifnet *ifp;
2536
2537         ifp = &sc->arpcom.ac_if;
2538
2539         /*
2540          * Go through our tx ring and free mbufs for those
2541          * frames that have been sent.
2542          */
2543         while (sc->bnx_tx_saved_considx != tx_cons) {
2544                 uint32_t idx = 0;
2545
2546                 idx = sc->bnx_tx_saved_considx;
2547                 cur_tx = &sc->bnx_ldata.bnx_tx_ring[idx];
2548                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2549                         ifp->if_opackets++;
2550                 if (sc->bnx_cdata.bnx_tx_chain[idx] != NULL) {
2551                         bus_dmamap_unload(sc->bnx_cdata.bnx_tx_mtag,
2552                             sc->bnx_cdata.bnx_tx_dmamap[idx]);
2553                         m_freem(sc->bnx_cdata.bnx_tx_chain[idx]);
2554                         sc->bnx_cdata.bnx_tx_chain[idx] = NULL;
2555                 }
2556                 sc->bnx_txcnt--;
2557                 BNX_INC(sc->bnx_tx_saved_considx, BGE_TX_RING_CNT);
2558         }
2559
2560         if (cur_tx != NULL &&
2561             (BGE_TX_RING_CNT - sc->bnx_txcnt) >=
2562             (BNX_NSEG_RSVD + BNX_NSEG_SPARE))
2563                 ifp->if_flags &= ~IFF_OACTIVE;
2564
2565         if (sc->bnx_txcnt == 0)
2566                 ifp->if_timer = 0;
2567
2568         if (!ifq_is_empty(&ifp->if_snd))
2569                 if_devstart(ifp);
2570 }
2571
2572 #ifdef DEVICE_POLLING
2573
2574 static void
2575 bnx_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2576 {
2577         struct bnx_softc *sc = ifp->if_softc;
2578         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2579         uint16_t rx_prod, tx_cons;
2580
2581         switch(cmd) {
2582         case POLL_REGISTER:
2583                 bnx_disable_intr(sc);
2584                 break;
2585         case POLL_DEREGISTER:
2586                 bnx_enable_intr(sc);
2587                 break;
2588         case POLL_AND_CHECK_STATUS:
2589                 /*
2590                  * Process link state changes.
2591                  */
2592                 bnx_link_poll(sc);
2593                 /* Fall through */
2594         case POLL_ONLY:
2595                 sc->bnx_status_tag = sblk->bge_status_tag;
2596                 /*
2597                  * Use a load fence to ensure that status_tag
2598                  * is saved  before rx_prod and tx_cons.
2599                  */
2600                 cpu_lfence();
2601
2602                 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2603                 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2604                 if (ifp->if_flags & IFF_RUNNING) {
2605                         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2606                         if (sc->bnx_rx_saved_considx != rx_prod)
2607                                 bnx_rxeof(sc, rx_prod);
2608
2609                         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2610                         if (sc->bnx_tx_saved_considx != tx_cons)
2611                                 bnx_txeof(sc, tx_cons);
2612                 }
2613                 break;
2614         }
2615 }
2616
2617 #endif
2618
2619 static void
2620 bnx_intr_legacy(void *xsc)
2621 {
2622         struct bnx_softc *sc = xsc;
2623         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2624
2625         if (sc->bnx_status_tag == sblk->bge_status_tag) {
2626                 uint32_t val;
2627
2628                 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4);
2629                 if (val & BGE_PCISTAT_INTR_NOTACT)
2630                         return;
2631         }
2632
2633         /*
2634          * NOTE:
2635          * Interrupt will have to be disabled if tagged status
2636          * is used, else interrupt will always be asserted on
2637          * certain chips (at least on BCM5750 AX/BX).
2638          */
2639         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2640
2641         bnx_intr(sc);
2642 }
2643
2644 static void
2645 bnx_msi(void *xsc)
2646 {
2647         struct bnx_softc *sc = xsc;
2648
2649         /* Disable interrupt first */
2650         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2651         bnx_intr(sc);
2652 }
2653
2654 static void
2655 bnx_msi_oneshot(void *xsc)
2656 {
2657         bnx_intr(xsc);
2658 }
2659
2660 static void
2661 bnx_intr(struct bnx_softc *sc)
2662 {
2663         struct ifnet *ifp = &sc->arpcom.ac_if;
2664         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2665         uint16_t rx_prod, tx_cons;
2666         uint32_t status;
2667
2668         sc->bnx_status_tag = sblk->bge_status_tag;
2669         /*
2670          * Use a load fence to ensure that status_tag is saved
2671          * before rx_prod, tx_cons and status.
2672          */
2673         cpu_lfence();
2674
2675         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2676         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2677         status = sblk->bge_status;
2678
2679         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt)
2680                 bnx_link_poll(sc);
2681
2682         if (ifp->if_flags & IFF_RUNNING) {
2683                 if (sc->bnx_rx_saved_considx != rx_prod)
2684                         bnx_rxeof(sc, rx_prod);
2685
2686                 if (sc->bnx_tx_saved_considx != tx_cons)
2687                         bnx_txeof(sc, tx_cons);
2688         }
2689
2690         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
2691
2692         if (sc->bnx_coal_chg)
2693                 bnx_coal_change(sc);
2694 }
2695
2696 static void
2697 bnx_tick(void *xsc)
2698 {
2699         struct bnx_softc *sc = xsc;
2700         struct ifnet *ifp = &sc->arpcom.ac_if;
2701
2702         lwkt_serialize_enter(ifp->if_serializer);
2703
2704         bnx_stats_update_regs(sc);
2705
2706         if (sc->bnx_flags & BNX_FLAG_TBI) {
2707                 /*
2708                  * Since in TBI mode auto-polling can't be used we should poll
2709                  * link status manually. Here we register pending link event
2710                  * and trigger interrupt.
2711                  */
2712                 sc->bnx_link_evt++;
2713                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
2714         } else if (!sc->bnx_link) {
2715                 mii_tick(device_get_softc(sc->bnx_miibus));
2716         }
2717
2718         callout_reset(&sc->bnx_stat_timer, hz, bnx_tick, sc);
2719
2720         lwkt_serialize_exit(ifp->if_serializer);
2721 }
2722
2723 static void
2724 bnx_stats_update_regs(struct bnx_softc *sc)
2725 {
2726         struct ifnet *ifp = &sc->arpcom.ac_if;
2727         struct bge_mac_stats_regs stats;
2728         uint32_t *s;
2729         int i;
2730
2731         s = (uint32_t *)&stats;
2732         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2733                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2734                 s++;
2735         }
2736
2737         ifp->if_collisions +=
2738            (stats.dot3StatsSingleCollisionFrames +
2739            stats.dot3StatsMultipleCollisionFrames +
2740            stats.dot3StatsExcessiveCollisions +
2741            stats.dot3StatsLateCollisions) -
2742            ifp->if_collisions;
2743 }
2744
2745 /*
2746  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2747  * pointers to descriptors.
2748  */
2749 static int
2750 bnx_encap(struct bnx_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
2751 {
2752         struct bge_tx_bd *d = NULL;
2753         uint16_t csum_flags = 0;
2754         bus_dma_segment_t segs[BNX_NSEG_NEW];
2755         bus_dmamap_t map;
2756         int error, maxsegs, nsegs, idx, i;
2757         struct mbuf *m_head = *m_head0, *m_new;
2758
2759         if (m_head->m_pkthdr.csum_flags) {
2760                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2761                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2762                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2763                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2764                 if (m_head->m_flags & M_LASTFRAG)
2765                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2766                 else if (m_head->m_flags & M_FRAG)
2767                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2768         }
2769
2770         idx = *txidx;
2771         map = sc->bnx_cdata.bnx_tx_dmamap[idx];
2772
2773         maxsegs = (BGE_TX_RING_CNT - sc->bnx_txcnt) - BNX_NSEG_RSVD;
2774         KASSERT(maxsegs >= BNX_NSEG_SPARE,
2775                 ("not enough segments %d", maxsegs));
2776
2777         if (maxsegs > BNX_NSEG_NEW)
2778                 maxsegs = BNX_NSEG_NEW;
2779
2780         /*
2781          * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
2782          * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
2783          * but when such padded frames employ the bge IP/TCP checksum
2784          * offload, the hardware checksum assist gives incorrect results
2785          * (possibly from incorporating its own padding into the UDP/TCP
2786          * checksum; who knows).  If we pad such runts with zeros, the
2787          * onboard checksum comes out correct.
2788          */
2789         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2790             m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) {
2791                 error = m_devpad(m_head, BNX_MIN_FRAMELEN);
2792                 if (error)
2793                         goto back;
2794         }
2795
2796         if ((sc->bnx_flags & BNX_FLAG_SHORTDMA) && m_head->m_next != NULL) {
2797                 m_new = bnx_defrag_shortdma(m_head);
2798                 if (m_new == NULL) {
2799                         error = ENOBUFS;
2800                         goto back;
2801                 }
2802                 *m_head0 = m_head = m_new;
2803         }
2804         if (sc->bnx_force_defrag && m_head->m_next != NULL) {
2805                 /*
2806                  * Forcefully defragment mbuf chain to overcome hardware
2807                  * limitation which only support a single outstanding
2808                  * DMA read operation.  If it fails, keep moving on using
2809                  * the original mbuf chain.
2810                  */
2811                 m_new = m_defrag(m_head, MB_DONTWAIT);
2812                 if (m_new != NULL)
2813                         *m_head0 = m_head = m_new;
2814         }
2815
2816         error = bus_dmamap_load_mbuf_defrag(sc->bnx_cdata.bnx_tx_mtag, map,
2817                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2818         if (error)
2819                 goto back;
2820
2821         m_head = *m_head0;
2822         bus_dmamap_sync(sc->bnx_cdata.bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2823
2824         for (i = 0; ; i++) {
2825                 d = &sc->bnx_ldata.bnx_tx_ring[idx];
2826
2827                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2828                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2829                 d->bge_len = segs[i].ds_len;
2830                 d->bge_flags = csum_flags;
2831
2832                 if (i == nsegs - 1)
2833                         break;
2834                 BNX_INC(idx, BGE_TX_RING_CNT);
2835         }
2836         /* Mark the last segment as end of packet... */
2837         d->bge_flags |= BGE_TXBDFLAG_END;
2838
2839         /* Set vlan tag to the first segment of the packet. */
2840         d = &sc->bnx_ldata.bnx_tx_ring[*txidx];
2841         if (m_head->m_flags & M_VLANTAG) {
2842                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2843                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
2844         } else {
2845                 d->bge_vlan_tag = 0;
2846         }
2847
2848         /*
2849          * Insure that the map for this transmission is placed at
2850          * the array index of the last descriptor in this chain.
2851          */
2852         sc->bnx_cdata.bnx_tx_dmamap[*txidx] = sc->bnx_cdata.bnx_tx_dmamap[idx];
2853         sc->bnx_cdata.bnx_tx_dmamap[idx] = map;
2854         sc->bnx_cdata.bnx_tx_chain[idx] = m_head;
2855         sc->bnx_txcnt += nsegs;
2856
2857         BNX_INC(idx, BGE_TX_RING_CNT);
2858         *txidx = idx;
2859 back:
2860         if (error) {
2861                 m_freem(*m_head0);
2862                 *m_head0 = NULL;
2863         }
2864         return error;
2865 }
2866
2867 /*
2868  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2869  * to the mbuf data regions directly in the transmit descriptors.
2870  */
2871 static void
2872 bnx_start(struct ifnet *ifp)
2873 {
2874         struct bnx_softc *sc = ifp->if_softc;
2875         struct mbuf *m_head = NULL;
2876         uint32_t prodidx;
2877         int need_trans;
2878
2879         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2880                 return;
2881
2882         prodidx = sc->bnx_tx_prodidx;
2883
2884         need_trans = 0;
2885         while (sc->bnx_cdata.bnx_tx_chain[prodidx] == NULL) {
2886                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2887                 if (m_head == NULL)
2888                         break;
2889
2890                 /*
2891                  * XXX
2892                  * The code inside the if() block is never reached since we
2893                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2894                  * requests to checksum TCP/UDP in a fragmented packet.
2895                  *
2896                  * XXX
2897                  * safety overkill.  If this is a fragmented packet chain
2898                  * with delayed TCP/UDP checksums, then only encapsulate
2899                  * it if we have enough descriptors to handle the entire
2900                  * chain at once.
2901                  * (paranoia -- may not actually be needed)
2902                  */
2903                 if ((m_head->m_flags & M_FIRSTFRAG) &&
2904                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
2905                         if ((BGE_TX_RING_CNT - sc->bnx_txcnt) <
2906                             m_head->m_pkthdr.csum_data + BNX_NSEG_RSVD) {
2907                                 ifp->if_flags |= IFF_OACTIVE;
2908                                 ifq_prepend(&ifp->if_snd, m_head);
2909                                 break;
2910                         }
2911                 }
2912
2913                 /*
2914                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2915                  * descriptors of the end of the ring.  Also make
2916                  * sure there are BGE_NSEG_SPARE descriptors for
2917                  * jumbo buffers' defragmentation.
2918                  */
2919                 if ((BGE_TX_RING_CNT - sc->bnx_txcnt) <
2920                     (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) {
2921                         ifp->if_flags |= IFF_OACTIVE;
2922                         ifq_prepend(&ifp->if_snd, m_head);
2923                         break;
2924                 }
2925
2926                 /*
2927                  * Pack the data into the transmit ring. If we
2928                  * don't have room, set the OACTIVE flag and wait
2929                  * for the NIC to drain the ring.
2930                  */
2931                 if (bnx_encap(sc, &m_head, &prodidx)) {
2932                         ifp->if_flags |= IFF_OACTIVE;
2933                         ifp->if_oerrors++;
2934                         break;
2935                 }
2936                 need_trans = 1;
2937
2938                 ETHER_BPF_MTAP(ifp, m_head);
2939         }
2940
2941         if (!need_trans)
2942                 return;
2943
2944         /* Transmit */
2945         bnx_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2946
2947         sc->bnx_tx_prodidx = prodidx;
2948
2949         /*
2950          * Set a timeout in case the chip goes out to lunch.
2951          */
2952         ifp->if_timer = 5;
2953 }
2954
2955 static void
2956 bnx_init(void *xsc)
2957 {
2958         struct bnx_softc *sc = xsc;
2959         struct ifnet *ifp = &sc->arpcom.ac_if;
2960         uint16_t *m;
2961         uint32_t mode;
2962
2963         ASSERT_SERIALIZED(ifp->if_serializer);
2964
2965         /* Cancel pending I/O and flush buffers. */
2966         bnx_stop(sc);
2967         bnx_reset(sc);
2968         bnx_chipinit(sc);
2969
2970         /*
2971          * Init the various state machines, ring
2972          * control blocks and firmware.
2973          */
2974         if (bnx_blockinit(sc)) {
2975                 if_printf(ifp, "initialization failure\n");
2976                 bnx_stop(sc);
2977                 return;
2978         }
2979
2980         /* Specify MTU. */
2981         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2982             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2983
2984         /* Load our MAC address. */
2985         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2986         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2987         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2988
2989         /* Enable or disable promiscuous mode as needed. */
2990         bnx_setpromisc(sc);
2991
2992         /* Program multicast filter. */
2993         bnx_setmulti(sc);
2994
2995         /* Init RX ring. */
2996         if (bnx_init_rx_ring_std(sc)) {
2997                 if_printf(ifp, "RX ring initialization failed\n");
2998                 bnx_stop(sc);
2999                 return;
3000         }
3001
3002         /* Init jumbo RX ring. */
3003         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3004                 if (bnx_init_rx_ring_jumbo(sc)) {
3005                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3006                         bnx_stop(sc);
3007                         return;
3008                 }
3009         }
3010
3011         /* Init our RX return ring index */
3012         sc->bnx_rx_saved_considx = 0;
3013
3014         /* Init TX ring. */
3015         bnx_init_tx_ring(sc);
3016
3017         /* Enable TX MAC state machine lockup fix. */
3018         mode = CSR_READ_4(sc, BGE_TX_MODE);
3019         mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3020         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
3021                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3022                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
3023                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3024         }
3025         /* Turn on transmitter */
3026         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3027
3028         /* Turn on receiver */
3029         BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3030
3031         /*
3032          * Set the number of good frames to receive after RX MBUF
3033          * Low Watermark has been reached.  After the RX MAC receives
3034          * this number of frames, it will drop subsequent incoming
3035          * frames until the MBUF High Watermark is reached.
3036          */
3037         if (BNX_IS_57765_FAMILY(sc))
3038                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
3039         else
3040                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3041
3042         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
3043                 if (bootverbose) {
3044                         if_printf(ifp, "MSI_MODE: %#x\n",
3045                             CSR_READ_4(sc, BGE_MSI_MODE));
3046                 }
3047         }
3048
3049         /* Tell firmware we're alive. */
3050         BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3051
3052         /* Enable host interrupts if polling(4) is not enabled. */
3053         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3054 #ifdef DEVICE_POLLING
3055         if (ifp->if_flags & IFF_POLLING)
3056                 bnx_disable_intr(sc);
3057         else
3058 #endif
3059         bnx_enable_intr(sc);
3060
3061         bnx_ifmedia_upd(ifp);
3062
3063         ifp->if_flags |= IFF_RUNNING;
3064         ifp->if_flags &= ~IFF_OACTIVE;
3065
3066         callout_reset(&sc->bnx_stat_timer, hz, bnx_tick, sc);
3067 }
3068
3069 /*
3070  * Set media options.
3071  */
3072 static int
3073 bnx_ifmedia_upd(struct ifnet *ifp)
3074 {
3075         struct bnx_softc *sc = ifp->if_softc;
3076
3077         /* If this is a 1000baseX NIC, enable the TBI port. */
3078         if (sc->bnx_flags & BNX_FLAG_TBI) {
3079                 struct ifmedia *ifm = &sc->bnx_ifmedia;
3080
3081                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3082                         return(EINVAL);
3083
3084                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3085                 case IFM_AUTO:
3086                         break;
3087
3088                 case IFM_1000_SX:
3089                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3090                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3091                                     BGE_MACMODE_HALF_DUPLEX);
3092                         } else {
3093                                 BNX_SETBIT(sc, BGE_MAC_MODE,
3094                                     BGE_MACMODE_HALF_DUPLEX);
3095                         }
3096                         break;
3097                 default:
3098                         return(EINVAL);
3099                 }
3100         } else {
3101                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3102
3103                 sc->bnx_link_evt++;
3104                 sc->bnx_link = 0;
3105                 if (mii->mii_instance) {
3106                         struct mii_softc *miisc;
3107
3108                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3109                                 mii_phy_reset(miisc);
3110                 }
3111                 mii_mediachg(mii);
3112
3113                 /*
3114                  * Force an interrupt so that we will call bnx_link_upd
3115                  * if needed and clear any pending link state attention.
3116                  * Without this we are not getting any further interrupts
3117                  * for link state changes and thus will not UP the link and
3118                  * not be able to send in bnx_start.  The only way to get
3119                  * things working was to receive a packet and get an RX
3120                  * intr.
3121                  *
3122                  * bnx_tick should help for fiber cards and we might not
3123                  * need to do this here if BNX_FLAG_TBI is set but as
3124                  * we poll for fiber anyway it should not harm.
3125                  */
3126                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3127         }
3128         return(0);
3129 }
3130
3131 /*
3132  * Report current media status.
3133  */
3134 static void
3135 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3136 {
3137         struct bnx_softc *sc = ifp->if_softc;
3138
3139         if (sc->bnx_flags & BNX_FLAG_TBI) {
3140                 ifmr->ifm_status = IFM_AVALID;
3141                 ifmr->ifm_active = IFM_ETHER;
3142                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3143                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3144                         ifmr->ifm_status |= IFM_ACTIVE;
3145                 } else {
3146                         ifmr->ifm_active |= IFM_NONE;
3147                         return;
3148                 }
3149
3150                 ifmr->ifm_active |= IFM_1000_SX;
3151                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3152                         ifmr->ifm_active |= IFM_HDX;
3153                 else
3154                         ifmr->ifm_active |= IFM_FDX;
3155         } else {
3156                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3157
3158                 mii_pollstat(mii);
3159                 ifmr->ifm_active = mii->mii_media_active;
3160                 ifmr->ifm_status = mii->mii_media_status;
3161         }
3162 }
3163
3164 static int
3165 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3166 {
3167         struct bnx_softc *sc = ifp->if_softc;
3168         struct ifreq *ifr = (struct ifreq *)data;
3169         int mask, error = 0;
3170
3171         ASSERT_SERIALIZED(ifp->if_serializer);
3172
3173         switch (command) {
3174         case SIOCSIFMTU:
3175                 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3176                     (BNX_IS_JUMBO_CAPABLE(sc) &&
3177                      ifr->ifr_mtu > BNX_JUMBO_MTU)) {
3178                         error = EINVAL;
3179                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3180                         ifp->if_mtu = ifr->ifr_mtu;
3181                         if (ifp->if_flags & IFF_RUNNING)
3182                                 bnx_init(sc);
3183                 }
3184                 break;
3185         case SIOCSIFFLAGS:
3186                 if (ifp->if_flags & IFF_UP) {
3187                         if (ifp->if_flags & IFF_RUNNING) {
3188                                 mask = ifp->if_flags ^ sc->bnx_if_flags;
3189
3190                                 /*
3191                                  * If only the state of the PROMISC flag
3192                                  * changed, then just use the 'set promisc
3193                                  * mode' command instead of reinitializing
3194                                  * the entire NIC. Doing a full re-init
3195                                  * means reloading the firmware and waiting
3196                                  * for it to start up, which may take a
3197                                  * second or two.  Similarly for ALLMULTI.
3198                                  */
3199                                 if (mask & IFF_PROMISC)
3200                                         bnx_setpromisc(sc);
3201                                 if (mask & IFF_ALLMULTI)
3202                                         bnx_setmulti(sc);
3203                         } else {
3204                                 bnx_init(sc);
3205                         }
3206                 } else if (ifp->if_flags & IFF_RUNNING) {
3207                         bnx_stop(sc);
3208                 }
3209                 sc->bnx_if_flags = ifp->if_flags;
3210                 break;
3211         case SIOCADDMULTI:
3212         case SIOCDELMULTI:
3213                 if (ifp->if_flags & IFF_RUNNING)
3214                         bnx_setmulti(sc);
3215                 break;
3216         case SIOCSIFMEDIA:
3217         case SIOCGIFMEDIA:
3218                 if (sc->bnx_flags & BNX_FLAG_TBI) {
3219                         error = ifmedia_ioctl(ifp, ifr,
3220                             &sc->bnx_ifmedia, command);
3221                 } else {
3222                         struct mii_data *mii;
3223
3224                         mii = device_get_softc(sc->bnx_miibus);
3225                         error = ifmedia_ioctl(ifp, ifr,
3226                                               &mii->mii_media, command);
3227                 }
3228                 break;
3229         case SIOCSIFCAP:
3230                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3231                 if (mask & IFCAP_HWCSUM) {
3232                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3233                         if (IFCAP_HWCSUM & ifp->if_capenable)
3234                                 ifp->if_hwassist = BNX_CSUM_FEATURES;
3235                         else
3236                                 ifp->if_hwassist = 0;
3237                 }
3238                 break;
3239         default:
3240                 error = ether_ioctl(ifp, command, data);
3241                 break;
3242         }
3243         return error;
3244 }
3245
3246 static void
3247 bnx_watchdog(struct ifnet *ifp)
3248 {
3249         struct bnx_softc *sc = ifp->if_softc;
3250
3251         if_printf(ifp, "watchdog timeout -- resetting\n");
3252
3253         bnx_init(sc);
3254
3255         ifp->if_oerrors++;
3256
3257         if (!ifq_is_empty(&ifp->if_snd))
3258                 if_devstart(ifp);
3259 }
3260
3261 /*
3262  * Stop the adapter and free any mbufs allocated to the
3263  * RX and TX lists.
3264  */
3265 static void
3266 bnx_stop(struct bnx_softc *sc)
3267 {
3268         struct ifnet *ifp = &sc->arpcom.ac_if;
3269
3270         ASSERT_SERIALIZED(ifp->if_serializer);
3271
3272         callout_stop(&sc->bnx_stat_timer);
3273
3274         /*
3275          * Disable all of the receiver blocks
3276          */
3277         bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3278         bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3279         bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3280         bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3281         bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3282         bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3283
3284         /*
3285          * Disable all of the transmit blocks
3286          */
3287         bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3288         bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3289         bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3290         bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3291         bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3292         bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3293
3294         /*
3295          * Shut down all of the memory managers and related
3296          * state machines.
3297          */
3298         bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3299         bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3300         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3301         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3302
3303         /* Disable host interrupts. */
3304         bnx_disable_intr(sc);
3305
3306         /*
3307          * Tell firmware we're shutting down.
3308          */
3309         BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3310
3311         /* Free the RX lists. */
3312         bnx_free_rx_ring_std(sc);
3313
3314         /* Free jumbo RX list. */
3315         if (BNX_IS_JUMBO_CAPABLE(sc))
3316                 bnx_free_rx_ring_jumbo(sc);
3317
3318         /* Free TX buffers. */
3319         bnx_free_tx_ring(sc);
3320
3321         sc->bnx_status_tag = 0;
3322         sc->bnx_link = 0;
3323         sc->bnx_coal_chg = 0;
3324
3325         sc->bnx_tx_saved_considx = BNX_TXCONS_UNSET;
3326
3327         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3328         ifp->if_timer = 0;
3329 }
3330
3331 /*
3332  * Stop all chip I/O so that the kernel's probe routines don't
3333  * get confused by errant DMAs when rebooting.
3334  */
3335 static void
3336 bnx_shutdown(device_t dev)
3337 {
3338         struct bnx_softc *sc = device_get_softc(dev);
3339         struct ifnet *ifp = &sc->arpcom.ac_if;
3340
3341         lwkt_serialize_enter(ifp->if_serializer);
3342         bnx_stop(sc);
3343         bnx_reset(sc);
3344         lwkt_serialize_exit(ifp->if_serializer);
3345 }
3346
3347 static int
3348 bnx_suspend(device_t dev)
3349 {
3350         struct bnx_softc *sc = device_get_softc(dev);
3351         struct ifnet *ifp = &sc->arpcom.ac_if;
3352
3353         lwkt_serialize_enter(ifp->if_serializer);
3354         bnx_stop(sc);
3355         lwkt_serialize_exit(ifp->if_serializer);
3356
3357         return 0;
3358 }
3359
3360 static int
3361 bnx_resume(device_t dev)
3362 {
3363         struct bnx_softc *sc = device_get_softc(dev);
3364         struct ifnet *ifp = &sc->arpcom.ac_if;
3365
3366         lwkt_serialize_enter(ifp->if_serializer);
3367
3368         if (ifp->if_flags & IFF_UP) {
3369                 bnx_init(sc);
3370
3371                 if (!ifq_is_empty(&ifp->if_snd))
3372                         if_devstart(ifp);
3373         }
3374
3375         lwkt_serialize_exit(ifp->if_serializer);
3376
3377         return 0;
3378 }
3379
3380 static void
3381 bnx_setpromisc(struct bnx_softc *sc)
3382 {
3383         struct ifnet *ifp = &sc->arpcom.ac_if;
3384
3385         if (ifp->if_flags & IFF_PROMISC)
3386                 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3387         else
3388                 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3389 }
3390
3391 static void
3392 bnx_dma_free(struct bnx_softc *sc)
3393 {
3394         int i;
3395
3396         /* Destroy RX mbuf DMA stuffs. */
3397         if (sc->bnx_cdata.bnx_rx_mtag != NULL) {
3398                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3399                         bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3400                             sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3401                 }
3402                 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3403                                    sc->bnx_cdata.bnx_rx_tmpmap);
3404                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3405         }
3406
3407         /* Destroy TX mbuf DMA stuffs. */
3408         if (sc->bnx_cdata.bnx_tx_mtag != NULL) {
3409                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3410                         bus_dmamap_destroy(sc->bnx_cdata.bnx_tx_mtag,
3411                             sc->bnx_cdata.bnx_tx_dmamap[i]);
3412                 }
3413                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_tx_mtag);
3414         }
3415
3416         /* Destroy standard RX ring */
3417         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_std_ring_tag,
3418                            sc->bnx_cdata.bnx_rx_std_ring_map,
3419                            sc->bnx_ldata.bnx_rx_std_ring);
3420
3421         if (BNX_IS_JUMBO_CAPABLE(sc))
3422                 bnx_free_jumbo_mem(sc);
3423
3424         /* Destroy RX return ring */
3425         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_return_ring_tag,
3426                            sc->bnx_cdata.bnx_rx_return_ring_map,
3427                            sc->bnx_ldata.bnx_rx_return_ring);
3428
3429         /* Destroy TX ring */
3430         bnx_dma_block_free(sc->bnx_cdata.bnx_tx_ring_tag,
3431                            sc->bnx_cdata.bnx_tx_ring_map,
3432                            sc->bnx_ldata.bnx_tx_ring);
3433
3434         /* Destroy status block */
3435         bnx_dma_block_free(sc->bnx_cdata.bnx_status_tag,
3436                            sc->bnx_cdata.bnx_status_map,
3437                            sc->bnx_ldata.bnx_status_block);
3438
3439         /* Destroy the parent tag */
3440         if (sc->bnx_cdata.bnx_parent_tag != NULL)
3441                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag);
3442 }
3443
3444 static int
3445 bnx_dma_alloc(struct bnx_softc *sc)
3446 {
3447         struct ifnet *ifp = &sc->arpcom.ac_if;
3448         int i, error;
3449
3450         /*
3451          * Allocate the parent bus DMA tag appropriate for PCI.
3452          *
3453          * All of the NetExtreme/NetLink controllers have 4GB boundary
3454          * DMA bug.
3455          * Whenever an address crosses a multiple of the 4GB boundary
3456          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3457          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3458          * state machine will lockup and cause the device to hang.
3459          */
3460         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3461                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3462                                    NULL, NULL,
3463                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3464                                    BUS_SPACE_MAXSIZE_32BIT,
3465                                    0, &sc->bnx_cdata.bnx_parent_tag);
3466         if (error) {
3467                 if_printf(ifp, "could not allocate parent dma tag\n");
3468                 return error;
3469         }
3470
3471         /*
3472          * Create DMA tag and maps for RX mbufs.
3473          */
3474         error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3475                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3476                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3477                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3478                                    &sc->bnx_cdata.bnx_rx_mtag);
3479         if (error) {
3480                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3481                 return error;
3482         }
3483
3484         error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3485                                   BUS_DMA_WAITOK, &sc->bnx_cdata.bnx_rx_tmpmap);
3486         if (error) {
3487                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3488                 sc->bnx_cdata.bnx_rx_mtag = NULL;
3489                 return error;
3490         }
3491
3492         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3493                 error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3494                                           BUS_DMA_WAITOK,
3495                                           &sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3496                 if (error) {
3497                         int j;
3498
3499                         for (j = 0; j < i; ++j) {
3500                                 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3501                                         sc->bnx_cdata.bnx_rx_std_dmamap[j]);
3502                         }
3503                         bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3504                         sc->bnx_cdata.bnx_rx_mtag = NULL;
3505
3506                         if_printf(ifp, "could not create DMA map for RX\n");
3507                         return error;
3508                 }
3509         }
3510
3511         /*
3512          * Create DMA tag and maps for TX mbufs.
3513          */
3514         error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3515                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3516                                    NULL, NULL,
3517                                    BNX_JUMBO_FRAMELEN, BNX_NSEG_NEW, MCLBYTES,
3518                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3519                                    BUS_DMA_ONEBPAGE,
3520                                    &sc->bnx_cdata.bnx_tx_mtag);
3521         if (error) {
3522                 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
3523                 return error;
3524         }
3525
3526         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3527                 error = bus_dmamap_create(sc->bnx_cdata.bnx_tx_mtag,
3528                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3529                                           &sc->bnx_cdata.bnx_tx_dmamap[i]);
3530                 if (error) {
3531                         int j;
3532
3533                         for (j = 0; j < i; ++j) {
3534                                 bus_dmamap_destroy(sc->bnx_cdata.bnx_tx_mtag,
3535                                         sc->bnx_cdata.bnx_tx_dmamap[j]);
3536                         }
3537                         bus_dma_tag_destroy(sc->bnx_cdata.bnx_tx_mtag);
3538                         sc->bnx_cdata.bnx_tx_mtag = NULL;
3539
3540                         if_printf(ifp, "could not create DMA map for TX\n");
3541                         return error;
3542                 }
3543         }
3544
3545         /*
3546          * Create DMA stuffs for standard RX ring.
3547          */
3548         error = bnx_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3549                                     &sc->bnx_cdata.bnx_rx_std_ring_tag,
3550                                     &sc->bnx_cdata.bnx_rx_std_ring_map,
3551                                     (void *)&sc->bnx_ldata.bnx_rx_std_ring,
3552                                     &sc->bnx_ldata.bnx_rx_std_ring_paddr);
3553         if (error) {
3554                 if_printf(ifp, "could not create std RX ring\n");
3555                 return error;
3556         }
3557
3558         /*
3559          * Create jumbo buffer pool.
3560          */
3561         if (BNX_IS_JUMBO_CAPABLE(sc)) {
3562                 error = bnx_alloc_jumbo_mem(sc);
3563                 if (error) {
3564                         if_printf(ifp, "could not create jumbo buffer pool\n");
3565                         return error;
3566                 }
3567         }
3568
3569         /*
3570          * Create DMA stuffs for RX return ring.
3571          */
3572         error = bnx_dma_block_alloc(sc,
3573             BGE_RX_RTN_RING_SZ(sc->bnx_return_ring_cnt),
3574             &sc->bnx_cdata.bnx_rx_return_ring_tag,
3575             &sc->bnx_cdata.bnx_rx_return_ring_map,
3576             (void *)&sc->bnx_ldata.bnx_rx_return_ring,
3577             &sc->bnx_ldata.bnx_rx_return_ring_paddr);
3578         if (error) {
3579                 if_printf(ifp, "could not create RX ret ring\n");
3580                 return error;
3581         }
3582
3583         /*
3584          * Create DMA stuffs for TX ring.
3585          */
3586         error = bnx_dma_block_alloc(sc, BGE_TX_RING_SZ,
3587                                     &sc->bnx_cdata.bnx_tx_ring_tag,
3588                                     &sc->bnx_cdata.bnx_tx_ring_map,
3589                                     (void *)&sc->bnx_ldata.bnx_tx_ring,
3590                                     &sc->bnx_ldata.bnx_tx_ring_paddr);
3591         if (error) {
3592                 if_printf(ifp, "could not create TX ring\n");
3593                 return error;
3594         }
3595
3596         /*
3597          * Create DMA stuffs for status block.
3598          */
3599         error = bnx_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3600                                     &sc->bnx_cdata.bnx_status_tag,
3601                                     &sc->bnx_cdata.bnx_status_map,
3602                                     (void *)&sc->bnx_ldata.bnx_status_block,
3603                                     &sc->bnx_ldata.bnx_status_block_paddr);
3604         if (error) {
3605                 if_printf(ifp, "could not create status block\n");
3606                 return error;
3607         }
3608
3609         return 0;
3610 }
3611
3612 static int
3613 bnx_dma_block_alloc(struct bnx_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3614                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3615 {
3616         bus_dmamem_t dmem;
3617         int error;
3618
3619         error = bus_dmamem_coherent(sc->bnx_cdata.bnx_parent_tag, PAGE_SIZE, 0,
3620                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3621                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3622         if (error)
3623                 return error;
3624
3625         *tag = dmem.dmem_tag;
3626         *map = dmem.dmem_map;
3627         *addr = dmem.dmem_addr;
3628         *paddr = dmem.dmem_busaddr;
3629
3630         return 0;
3631 }
3632
3633 static void
3634 bnx_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3635 {
3636         if (tag != NULL) {
3637                 bus_dmamap_unload(tag, map);
3638                 bus_dmamem_free(tag, addr, map);
3639                 bus_dma_tag_destroy(tag);
3640         }
3641 }
3642
3643 static void
3644 bnx_tbi_link_upd(struct bnx_softc *sc, uint32_t status)
3645 {
3646         struct ifnet *ifp = &sc->arpcom.ac_if;
3647
3648 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3649
3650         /*
3651          * Sometimes PCS encoding errors are detected in
3652          * TBI mode (on fiber NICs), and for some reason
3653          * the chip will signal them as link changes.
3654          * If we get a link change event, but the 'PCS
3655          * encoding error' bit in the MAC status register
3656          * is set, don't bother doing a link check.
3657          * This avoids spurious "gigabit link up" messages
3658          * that sometimes appear on fiber NICs during
3659          * periods of heavy traffic.
3660          */
3661         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3662                 if (!sc->bnx_link) {
3663                         sc->bnx_link++;
3664                         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704) {
3665                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3666                                     BGE_MACMODE_TBI_SEND_CFGS);
3667                         }
3668                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3669
3670                         if (bootverbose)
3671                                 if_printf(ifp, "link UP\n");
3672
3673                         ifp->if_link_state = LINK_STATE_UP;
3674                         if_link_state_change(ifp);
3675                 }
3676         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3677                 if (sc->bnx_link) {
3678                         sc->bnx_link = 0;
3679
3680                         if (bootverbose)
3681                                 if_printf(ifp, "link DOWN\n");
3682
3683                         ifp->if_link_state = LINK_STATE_DOWN;
3684                         if_link_state_change(ifp);
3685                 }
3686         }
3687
3688 #undef PCS_ENCODE_ERR
3689
3690         /* Clear the attention. */
3691         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3692             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3693             BGE_MACSTAT_LINK_CHANGED);
3694 }
3695
3696 static void
3697 bnx_copper_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3698 {
3699         struct ifnet *ifp = &sc->arpcom.ac_if;
3700         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3701
3702         mii_pollstat(mii);
3703         bnx_miibus_statchg(sc->bnx_dev);
3704
3705         if (bootverbose) {
3706                 if (sc->bnx_link)
3707                         if_printf(ifp, "link UP\n");
3708                 else
3709                         if_printf(ifp, "link DOWN\n");
3710         }
3711
3712         /* Clear the attention. */
3713         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3714             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3715             BGE_MACSTAT_LINK_CHANGED);
3716 }
3717
3718 static void
3719 bnx_autopoll_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3720 {
3721         struct ifnet *ifp = &sc->arpcom.ac_if;
3722         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3723
3724         mii_pollstat(mii);
3725
3726         if (!sc->bnx_link &&
3727             (mii->mii_media_status & IFM_ACTIVE) &&
3728             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3729                 sc->bnx_link++;
3730                 if (bootverbose)
3731                         if_printf(ifp, "link UP\n");
3732         } else if (sc->bnx_link &&
3733             (!(mii->mii_media_status & IFM_ACTIVE) ||
3734             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3735                 sc->bnx_link = 0;
3736                 if (bootverbose)
3737                         if_printf(ifp, "link DOWN\n");
3738         }
3739
3740         /* Clear the attention. */
3741         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3742             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3743             BGE_MACSTAT_LINK_CHANGED);
3744 }
3745
3746 static int
3747 bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3748 {
3749         struct bnx_softc *sc = arg1;
3750
3751         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3752             &sc->bnx_rx_coal_ticks,
3753             BNX_RX_COAL_TICKS_MIN, BNX_RX_COAL_TICKS_MAX,
3754             BNX_RX_COAL_TICKS_CHG);
3755 }
3756
3757 static int
3758 bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3759 {
3760         struct bnx_softc *sc = arg1;
3761
3762         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3763             &sc->bnx_tx_coal_ticks,
3764             BNX_TX_COAL_TICKS_MIN, BNX_TX_COAL_TICKS_MAX,
3765             BNX_TX_COAL_TICKS_CHG);
3766 }
3767
3768 static int
3769 bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
3770 {
3771         struct bnx_softc *sc = arg1;
3772
3773         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3774             &sc->bnx_rx_coal_bds,
3775             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3776             BNX_RX_COAL_BDS_CHG);
3777 }
3778
3779 static int
3780 bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
3781 {
3782         struct bnx_softc *sc = arg1;
3783
3784         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3785             &sc->bnx_tx_coal_bds,
3786             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3787             BNX_TX_COAL_BDS_CHG);
3788 }
3789
3790 static int
3791 bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3792 {
3793         struct bnx_softc *sc = arg1;
3794
3795         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3796             &sc->bnx_rx_coal_bds_int,
3797             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3798             BNX_RX_COAL_BDS_INT_CHG);
3799 }
3800
3801 static int
3802 bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3803 {
3804         struct bnx_softc *sc = arg1;
3805
3806         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3807             &sc->bnx_tx_coal_bds_int,
3808             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3809             BNX_TX_COAL_BDS_INT_CHG);
3810 }
3811
3812 static int
3813 bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3814     int coal_min, int coal_max, uint32_t coal_chg_mask)
3815 {
3816         struct bnx_softc *sc = arg1;
3817         struct ifnet *ifp = &sc->arpcom.ac_if;
3818         int error = 0, v;
3819
3820         lwkt_serialize_enter(ifp->if_serializer);
3821
3822         v = *coal;
3823         error = sysctl_handle_int(oidp, &v, 0, req);
3824         if (!error && req->newptr != NULL) {
3825                 if (v < coal_min || v > coal_max) {
3826                         error = EINVAL;
3827                 } else {
3828                         *coal = v;
3829                         sc->bnx_coal_chg |= coal_chg_mask;
3830                 }
3831         }
3832
3833         lwkt_serialize_exit(ifp->if_serializer);
3834         return error;
3835 }
3836
3837 static void
3838 bnx_coal_change(struct bnx_softc *sc)
3839 {
3840         struct ifnet *ifp = &sc->arpcom.ac_if;
3841         uint32_t val;
3842
3843         ASSERT_SERIALIZED(ifp->if_serializer);
3844
3845         if (sc->bnx_coal_chg & BNX_RX_COAL_TICKS_CHG) {
3846                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3847                             sc->bnx_rx_coal_ticks);
3848                 DELAY(10);
3849                 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3850
3851                 if (bootverbose) {
3852                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3853                                   sc->bnx_rx_coal_ticks);
3854                 }
3855         }
3856
3857         if (sc->bnx_coal_chg & BNX_TX_COAL_TICKS_CHG) {
3858                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3859                             sc->bnx_tx_coal_ticks);
3860                 DELAY(10);
3861                 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3862
3863                 if (bootverbose) {
3864                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3865                                   sc->bnx_tx_coal_ticks);
3866                 }
3867         }
3868
3869         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_CHG) {
3870                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3871                             sc->bnx_rx_coal_bds);
3872                 DELAY(10);
3873                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3874
3875                 if (bootverbose) {
3876                         if_printf(ifp, "rx_coal_bds -> %u\n",
3877                                   sc->bnx_rx_coal_bds);
3878                 }
3879         }
3880
3881         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_CHG) {
3882                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3883                             sc->bnx_tx_coal_bds);
3884                 DELAY(10);
3885                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3886
3887                 if (bootverbose) {
3888                         if_printf(ifp, "tx_max_coal_bds -> %u\n",
3889                                   sc->bnx_tx_coal_bds);
3890                 }
3891         }
3892
3893         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_INT_CHG) {
3894                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
3895                     sc->bnx_rx_coal_bds_int);
3896                 DELAY(10);
3897                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);
3898
3899                 if (bootverbose) {
3900                         if_printf(ifp, "rx_coal_bds_int -> %u\n",
3901                             sc->bnx_rx_coal_bds_int);
3902                 }
3903         }
3904
3905         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_INT_CHG) {
3906                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
3907                     sc->bnx_tx_coal_bds_int);
3908                 DELAY(10);
3909                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);
3910
3911                 if (bootverbose) {
3912                         if_printf(ifp, "tx_coal_bds_int -> %u\n",
3913                             sc->bnx_tx_coal_bds_int);
3914                 }
3915         }
3916
3917         sc->bnx_coal_chg = 0;
3918 }
3919
3920 static void
3921 bnx_enable_intr(struct bnx_softc *sc)
3922 {
3923         struct ifnet *ifp = &sc->arpcom.ac_if;
3924
3925         lwkt_serialize_handler_enable(ifp->if_serializer);
3926
3927         /*
3928          * Enable interrupt.
3929          */
3930         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3931         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
3932                 /* XXX Linux driver */
3933                 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3934         }
3935
3936         /*
3937          * Unmask the interrupt when we stop polling.
3938          */
3939         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
3940             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
3941
3942         /*
3943          * Trigger another interrupt, since above writing
3944          * to interrupt mailbox0 may acknowledge pending
3945          * interrupt.
3946          */
3947         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3948 }
3949
3950 static void
3951 bnx_disable_intr(struct bnx_softc *sc)
3952 {
3953         struct ifnet *ifp = &sc->arpcom.ac_if;
3954
3955         /*
3956          * Mask the interrupt when we start polling.
3957          */
3958         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
3959             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
3960
3961         /*
3962          * Acknowledge possible asserted interrupt.
3963          */
3964         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3965
3966         lwkt_serialize_handler_disable(ifp->if_serializer);
3967 }
3968
3969 static int
3970 bnx_get_eaddr_mem(struct bnx_softc *sc, uint8_t ether_addr[])
3971 {
3972         uint32_t mac_addr;
3973         int ret = 1;
3974
3975         mac_addr = bnx_readmem_ind(sc, 0x0c14);
3976         if ((mac_addr >> 16) == 0x484b) {
3977                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
3978                 ether_addr[1] = (uint8_t)mac_addr;
3979                 mac_addr = bnx_readmem_ind(sc, 0x0c18);
3980                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
3981                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
3982                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
3983                 ether_addr[5] = (uint8_t)mac_addr;
3984                 ret = 0;
3985         }
3986         return ret;
3987 }
3988
3989 static int
3990 bnx_get_eaddr_nvram(struct bnx_softc *sc, uint8_t ether_addr[])
3991 {
3992         int mac_offset = BGE_EE_MAC_OFFSET;
3993
3994         if (BNX_IS_5717_PLUS(sc)) {
3995                 int f;
3996
3997                 f = pci_get_function(sc->bnx_dev);
3998                 if (f & 1)
3999                         mac_offset = BGE_EE_MAC_OFFSET_5717;
4000                 if (f > 1)
4001                         mac_offset += BGE_EE_MAC_OFFSET_5717_OFF;
4002         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
4003                 mac_offset = BGE_EE_MAC_OFFSET_5906;
4004         }
4005
4006         return bnx_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4007 }
4008
4009 static int
4010 bnx_get_eaddr_eeprom(struct bnx_softc *sc, uint8_t ether_addr[])
4011 {
4012         if (sc->bnx_flags & BNX_FLAG_NO_EEPROM)
4013                 return 1;
4014
4015         return bnx_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4016                                ETHER_ADDR_LEN);
4017 }
4018
4019 static int
4020 bnx_get_eaddr(struct bnx_softc *sc, uint8_t eaddr[])
4021 {
4022         static const bnx_eaddr_fcn_t bnx_eaddr_funcs[] = {
4023                 /* NOTE: Order is critical */
4024                 bnx_get_eaddr_mem,
4025                 bnx_get_eaddr_nvram,
4026                 bnx_get_eaddr_eeprom,
4027                 NULL
4028         };
4029         const bnx_eaddr_fcn_t *func;
4030
4031         for (func = bnx_eaddr_funcs; *func != NULL; ++func) {
4032                 if ((*func)(sc, eaddr) == 0)
4033                         break;
4034         }
4035         return (*func == NULL ? ENXIO : 0);
4036 }
4037
4038 /*
4039  * NOTE: 'm' is not freed upon failure
4040  */
4041 struct mbuf *
4042 bnx_defrag_shortdma(struct mbuf *m)
4043 {
4044         struct mbuf *n;
4045         int found;
4046
4047         /*
4048          * If device receive two back-to-back send BDs with less than
4049          * or equal to 8 total bytes then the device may hang.  The two
4050          * back-to-back send BDs must in the same frame for this failure
4051          * to occur.  Scan mbuf chains and see whether two back-to-back
4052          * send BDs are there.  If this is the case, allocate new mbuf
4053          * and copy the frame to workaround the silicon bug.
4054          */
4055         for (n = m, found = 0; n != NULL; n = n->m_next) {
4056                 if (n->m_len < 8) {
4057                         found++;
4058                         if (found > 1)
4059                                 break;
4060                         continue;
4061                 }
4062                 found = 0;
4063         }
4064
4065         if (found > 1)
4066                 n = m_defrag(m, MB_DONTWAIT);
4067         else
4068                 n = m;
4069         return n;
4070 }
4071
4072 static void
4073 bnx_stop_block(struct bnx_softc *sc, bus_size_t reg, uint32_t bit)
4074 {
4075         int i;
4076
4077         BNX_CLRBIT(sc, reg, bit);
4078         for (i = 0; i < BNX_TIMEOUT; i++) {
4079                 if ((CSR_READ_4(sc, reg) & bit) == 0)
4080                         return;
4081                 DELAY(100);
4082         }
4083 }
4084
4085 static void
4086 bnx_link_poll(struct bnx_softc *sc)
4087 {
4088         uint32_t status;
4089
4090         status = CSR_READ_4(sc, BGE_MAC_STS);
4091         if ((status & sc->bnx_link_chg) || sc->bnx_link_evt) {
4092                 sc->bnx_link_evt = 0;
4093                 sc->bnx_link_upd(sc, status);
4094         }
4095 }
4096
4097 static void
4098 bnx_enable_msi(struct bnx_softc *sc)
4099 {
4100         uint32_t msi_mode;
4101
4102         msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);
4103         msi_mode |= BGE_MSIMODE_ENABLE;
4104         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
4105                 /*
4106                  * NOTE:
4107                  * 5718-PG105-R says that "one shot" mode
4108                  * does not work if MSI is used, however,
4109                  * it obviously works.
4110                  */
4111                 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE;
4112         }
4113         CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode);
4114 }
4115
4116 static uint32_t
4117 bnx_dma_swap_options(struct bnx_softc *sc)
4118 {
4119         uint32_t dma_options;
4120
4121         dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
4122             BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
4123 #if BYTE_ORDER == BIG_ENDIAN
4124         dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
4125 #endif
4126         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
4127                 dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA |
4128                     BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE |
4129                     BGE_MODECTL_HTX2B_ENABLE;
4130         }
4131         return dma_options;
4132 }