2 * Copyright (c) 1991 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
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12 * documentation and/or other materials provided with the distribution.
13 * 4. Neither the name of the University nor the names of its contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
30 * $FreeBSD: src/sys/i386/include/specialreg.h,v 1.54 2009/09/10 17:27:36 jkim Exp $
33 #ifndef _CPU_SPECIALREG_H_
34 #define _CPU_SPECIALREG_H_
37 * Bits in 386 special registers:
39 #define CR0_PE 0x00000001 /* Protected mode Enable */
40 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */
41 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
43 #define CR0_PG 0x80000000 /* PaGing enable */
46 * Bits in 486 special registers:
48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
49 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in
51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
52 #define CR0_NW 0x20000000 /* Not Write-through */
53 #define CR0_CD 0x40000000 /* Cache Disable */
56 * Bits in PPro special registers
58 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
59 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
60 #define CR4_TSD 0x00000004 /* Time stamp disable */
61 #define CR4_DE 0x00000008 /* Debugging extensions */
62 #define CR4_PSE 0x00000010 /* Page size extensions */
63 #define CR4_PAE 0x00000020 /* Physical address extension */
64 #define CR4_MCE 0x00000040 /* Machine check enable */
65 #define CR4_PGE 0x00000080 /* Page global enable */
66 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
67 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
68 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
71 * Bits in AMD64 special registers. EFER is 64 bits wide.
73 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
76 * CPUID instruction features register
78 #define CPUID_FPU 0x00000001
79 #define CPUID_VME 0x00000002
80 #define CPUID_DE 0x00000004
81 #define CPUID_PSE 0x00000008
82 #define CPUID_TSC 0x00000010
83 #define CPUID_MSR 0x00000020
84 #define CPUID_PAE 0x00000040
85 #define CPUID_MCE 0x00000080
86 #define CPUID_CX8 0x00000100
87 #define CPUID_APIC 0x00000200
88 #define CPUID_B10 0x00000400
89 #define CPUID_SEP 0x00000800
90 #define CPUID_MTRR 0x00001000
91 #define CPUID_PGE 0x00002000
92 #define CPUID_MCA 0x00004000
93 #define CPUID_CMOV 0x00008000
94 #define CPUID_PAT 0x00010000
95 #define CPUID_PSE36 0x00020000
96 #define CPUID_PSN 0x00040000
97 #define CPUID_CLFSH 0x00080000
98 #define CPUID_B20 0x00100000
99 #define CPUID_DS 0x00200000
100 #define CPUID_ACPI 0x00400000
101 #define CPUID_MMX 0x00800000
102 #define CPUID_FXSR 0x01000000
103 #define CPUID_SSE 0x02000000
104 #define CPUID_XMM 0x02000000
105 #define CPUID_SSE2 0x04000000
106 #define CPUID_SS 0x08000000
107 #define CPUID_HTT 0x10000000
108 #define CPUID_TM 0x20000000
109 #define CPUID_IA64 0x40000000
110 #define CPUID_PBE 0x80000000
112 #define CPUID2_SSE3 0x00000001
113 #define CPUID2_PCLMULQDQ 0x00000002
114 #define CPUID2_DTES64 0x00000004
115 #define CPUID2_MON 0x00000008
116 #define CPUID2_DS_CPL 0x00000010
117 #define CPUID2_VMX 0x00000020
118 #define CPUID2_SMX 0x00000040
119 #define CPUID2_EST 0x00000080
120 #define CPUID2_TM2 0x00000100
121 #define CPUID2_SSSE3 0x00000200
122 #define CPUID2_CNXTID 0x00000400
123 #define CPUID2_CX16 0x00002000
124 #define CPUID2_XTPR 0x00004000
125 #define CPUID2_PDCM 0x00008000
126 #define CPUID2_DCA 0x00040000
127 #define CPUID2_SSE41 0x00080000
128 #define CPUID2_SSE42 0x00100000
129 #define CPUID2_X2APIC 0x00200000
130 #define CPUID2_POPCNT 0x00800000
131 #define CPUID2_AESNI 0x02000000
132 #define CPUID2_RDRAND 0x40000000
133 #define CPUID2_VMM 0x80000000 /* AMD 25481 2.34 page 11 */
136 * Important bits in the AMD extended cpuid flags
138 #define AMDID_SYSCALL 0x00000800
139 #define AMDID_MP 0x00080000
140 #define AMDID_NX 0x00100000
141 #define AMDID_EXT_MMX 0x00400000
142 #define AMDID_FFXSR 0x01000000
143 #define AMDID_PAGE1GB 0x04000000
144 #define AMDID_RDTSCP 0x08000000
145 #define AMDID_LM 0x20000000
146 #define AMDID_EXT_3DNOW 0x40000000
147 #define AMDID_3DNOW 0x80000000
149 #define AMDID2_LAHF 0x00000001
150 #define AMDID2_CMP 0x00000002
151 #define AMDID2_SVM 0x00000004
152 #define AMDID2_EXT_APIC 0x00000008
153 #define AMDID2_CR8 0x00000010
154 #define AMDID2_ABM 0x00000020
155 #define AMDID2_SSE4A 0x00000040
156 #define AMDID2_MAS 0x00000080
157 #define AMDID2_PREFETCH 0x00000100
158 #define AMDID2_OSVW 0x00000200
159 #define AMDID2_IBS 0x00000400
160 #define AMDID2_SSE5 0x00000800
161 #define AMDID2_SKINIT 0x00001000
162 #define AMDID2_WDT 0x00002000
165 * CPUID instruction 1 eax info
167 #define CPUID_STEPPING 0x0000000f
168 #define CPUID_MODEL 0x000000f0
169 #define CPUID_FAMILY 0x00000f00
170 #define CPUID_EXT_MODEL 0x000f0000
171 #define CPUID_EXT_FAMILY 0x0ff00000
172 #define CPUID_TO_MODEL(id) \
173 ((((id) & CPUID_MODEL) >> 4) | \
174 ((((id) & CPUID_FAMILY) >= 0x600) ? \
175 (((id) & CPUID_EXT_MODEL) >> 12) : 0))
176 #define CPUID_TO_FAMILY(id) \
177 ((((id) & CPUID_FAMILY) >> 8) + \
178 ((((id) & CPUID_FAMILY) == 0xf00) ? \
179 (((id) & CPUID_EXT_FAMILY) >> 20) : 0))
182 * CPUID instruction 1 ebx info
184 #define CPUID_BRAND_INDEX 0x000000ff
185 #define CPUID_CLFUSH_SIZE 0x0000ff00
186 #define CPUID_HTT_CORES 0x00ff0000
187 #define CPUID_HTT_CORE_SHIFT 16
188 #define CPUID_LOCAL_APIC_ID 0xff000000
191 * CPUID instruction 0xb ebx info.
193 #define CPUID_TYPE_INVAL 0
194 #define CPUID_TYPE_SMT 1
195 #define CPUID_TYPE_CORE 2
198 * INTEL Deterministic Cache Parameters
201 #define FUNC_4_MAX_CORE_NO(eax) ((((eax) >> 26) & 0x3f))
204 * INTEL x2APIC Features / Processor topology
207 #define FUNC_B_THREAD_LEVEL 0
209 #define FUNC_B_INVALID_TYPE 0
210 #define FUNC_B_THREAD_TYPE 1
211 #define FUNC_B_CORE_TYPE 2
213 #define FUNC_B_TYPE(ecx) (((ecx) >> 8) & 0xff)
214 #define FUNC_B_BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
215 #define FUNC_B_LEVEL_MAX_SIBLINGS(ebx) ((ebx) & 0xffff)
219 * AMD extended function 8000_0007h edx info
221 #define AMDPM_TS 0x00000001
222 #define AMDPM_FID 0x00000002
223 #define AMDPM_VID 0x00000004
224 #define AMDPM_TTP 0x00000008
225 #define AMDPM_TM 0x00000010
226 #define AMDPM_STC 0x00000020
227 #define AMDPM_100MHZ_STEPS 0x00000040
228 #define AMDPM_HW_PSTATE 0x00000080
229 #define AMDPM_TSC_INVARIANT 0x00000100
232 * AMD extended function 8000_0008h ecx info
234 #define AMDID_CMP_CORES 0x000000ff
235 #define AMDID_COREID_SIZE 0x0000f000
236 #define AMDID_COREID_SIZE_SHIFT 12
239 * CPUID manufacturers identifiers
241 #define AMD_VENDOR_ID "AuthenticAMD"
242 #define CENTAUR_VENDOR_ID "CentaurHauls"
243 #define CYRIX_VENDOR_ID "CyrixInstead"
244 #define INTEL_VENDOR_ID "GenuineIntel"
245 #define NEXGEN_VENDOR_ID "NexGenDriven"
246 #define NSC_VENDOR_ID "Geode by NSC"
247 #define RISE_VENDOR_ID "RiseRiseRise"
248 #define SIS_VENDOR_ID "SiS SiS SiS "
249 #define TRANSMETA_VENDOR_ID "GenuineTMx86"
250 #define UMC_VENDOR_ID "UMC UMC UMC "
253 * Model-specific registers for the i386 family
255 #define MSR_P5_MC_ADDR 0x000
256 #define MSR_P5_MC_TYPE 0x001
257 #define MSR_TSC 0x010
258 #define MSR_P5_CESR 0x011
259 #define MSR_P5_CTR0 0x012
260 #define MSR_P5_CTR1 0x013
261 #define MSR_IA32_PLATFORM_ID 0x017
262 #define MSR_APICBASE 0x01b
263 #define MSR_EBL_CR_POWERON 0x02a
264 #define MSR_TEST_CTL 0x033
265 #define MSR_BIOS_UPDT_TRIG 0x079
266 #define MSR_BBL_CR_D0 0x088
267 #define MSR_BBL_CR_D1 0x089
268 #define MSR_BBL_CR_D2 0x08a
269 #define MSR_BIOS_SIGN 0x08b
270 #define MSR_PERFCTR0 0x0c1
271 #define MSR_PERFCTR1 0x0c2
272 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
273 #define MSR_MTRRcap 0x0fe
274 #define MSR_BBL_CR_ADDR 0x116
275 #define MSR_BBL_CR_DECC 0x118
276 #define MSR_BBL_CR_CTL 0x119
277 #define MSR_BBL_CR_TRIG 0x11a
278 #define MSR_BBL_CR_BUSY 0x11b
279 #define MSR_BBL_CR_CTL3 0x11e
280 #define MSR_SYSENTER_CS_MSR 0x174
281 #define MSR_SYSENTER_ESP_MSR 0x175
282 #define MSR_SYSENTER_EIP_MSR 0x176
283 #define MSR_MCG_CAP 0x179
284 #define MSR_MCG_STATUS 0x17a
285 #define MSR_MCG_CTL 0x17b
286 #define MSR_EVNTSEL0 0x186
287 #define MSR_EVNTSEL1 0x187
288 #define MSR_THERM_CONTROL 0x19a
289 #define MSR_THERM_INTERRUPT 0x19b
290 #define MSR_THERM_STATUS 0x19c
291 #define MSR_IA32_MISC_ENABLE 0x1a0
292 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2
293 #define MSR_DEBUGCTLMSR 0x1d9
294 #define MSR_LASTBRANCHFROMIP 0x1db
295 #define MSR_LASTBRANCHTOIP 0x1dc
296 #define MSR_LASTINTFROMIP 0x1dd
297 #define MSR_LASTINTTOIP 0x1de
298 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
299 #define MSR_MTRRVarBase 0x200
300 #define MSR_MTRR64kBase 0x250
301 #define MSR_MTRR16kBase 0x258
302 #define MSR_MTRR4kBase 0x268
303 #define MSR_PAT 0x277
304 #define MSR_MTRRdefType 0x2ff
305 #define MSR_MC0_CTL 0x400
306 #define MSR_MC0_STATUS 0x401
307 #define MSR_MC0_ADDR 0x402
308 #define MSR_MC0_MISC 0x403
309 #define MSR_MC1_CTL 0x404
310 #define MSR_MC1_STATUS 0x405
311 #define MSR_MC1_ADDR 0x406
312 #define MSR_MC1_MISC 0x407
313 #define MSR_MC2_CTL 0x408
314 #define MSR_MC2_STATUS 0x409
315 #define MSR_MC2_ADDR 0x40a
316 #define MSR_MC2_MISC 0x40b
317 #define MSR_MC3_CTL 0x40c
318 #define MSR_MC3_STATUS 0x40d
319 #define MSR_MC3_ADDR 0x40e
320 #define MSR_MC3_MISC 0x40f
321 #define MSR_MC4_CTL 0x410
322 #define MSR_MC4_STATUS 0x411
323 #define MSR_MC4_ADDR 0x412
324 #define MSR_MC4_MISC 0x413
327 * Constants related to MSR's.
329 #define APICBASE_RESERVED 0x000006ff
330 #define APICBASE_BSP 0x00000100
331 #define APICBASE_ENABLED 0x00000800
332 #define APICBASE_ADDRESS 0xfffff000
337 #define PAT_UNCACHEABLE 0x00
338 #define PAT_WRITE_COMBINING 0x01
339 #define PAT_WRITE_THROUGH 0x04
340 #define PAT_WRITE_PROTECTED 0x05
341 #define PAT_WRITE_BACK 0x06
342 #define PAT_UNCACHED 0x07
343 #define PAT_VALUE(i, m) ((long long)(m) << (8 * (i)))
344 #define PAT_MASK(i) PAT_VALUE(i, 0xff)
347 * Constants related to MTRRs
349 #define MTRR_UNCACHEABLE 0x00
350 #define MTRR_WRITE_COMBINING 0x01
351 #define MTRR_WRITE_THROUGH 0x04
352 #define MTRR_WRITE_PROTECTED 0x05
353 #define MTRR_WRITE_BACK 0x06
354 #define MTRR_N64K 8 /* numbers of fixed-size entries */
357 #define MTRR_CAP_WC 0x0000000000000400ULL
358 #define MTRR_CAP_FIXED 0x0000000000000100ULL
359 #define MTRR_CAP_VCNT 0x00000000000000ffULL
360 #define MTRR_DEF_ENABLE 0x0000000000000800ULL
361 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400ULL
362 #define MTRR_DEF_TYPE 0x00000000000000ffULL
363 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000ULL
364 #define MTRR_PHYSBASE_TYPE 0x00000000000000ffULL
365 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000ULL
366 #define MTRR_PHYSMASK_VALID 0x0000000000000800ULL
369 * Cyrix configuration registers, accessible as IO ports.
371 #define CCR0 0xc0 /* Configuration control register 0 */
372 #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is
374 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
375 #define CCR0_A20M 0x04 /* Enables A20M# input pin */
376 #define CCR0_KEN 0x08 /* Enables KEN# input pin */
377 #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */
378 #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold
380 #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set
382 #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */
384 #define CCR1 0xc1 /* Configuration control register 1 */
385 #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */
386 #define CCR1_SMI 0x02 /* Enables SMM pins */
387 #define CCR1_SMAC 0x04 /* System management memory access */
388 #define CCR1_MMAC 0x08 /* Main memory access */
389 #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */
390 #define CCR1_SM3 0x80 /* SMM address space address region 3 */
393 #define CCR2_WB 0x02 /* Enables WB cache interface pins */
394 #define CCR2_SADS 0x02 /* Slow ADS */
395 #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */
396 #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */
397 #define CCR2_WT1 0x10 /* WT region 1 */
398 #define CCR2_WPR1 0x10 /* Write-protect region 1 */
399 #define CCR2_BARB 0x20 /* Flushes write-back cache when entering
401 #define CCR2_BWRT 0x40 /* Enables burst write cycles */
402 #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */
405 #define CCR3_SMILOCK 0x01 /* SMM register lock */
406 #define CCR3_NMI 0x02 /* Enables NMI during SMM */
407 #define CCR3_LINBRST 0x04 /* Linear address burst cycles */
408 #define CCR3_SMMMODE 0x08 /* SMM Mode */
409 #define CCR3_MAPEN0 0x10 /* Enables Map0 */
410 #define CCR3_MAPEN1 0x20 /* Enables Map1 */
411 #define CCR3_MAPEN2 0x40 /* Enables Map2 */
412 #define CCR3_MAPEN3 0x80 /* Enables Map3 */
415 #define CCR4_IOMASK 0x07
416 #define CCR4_MEM 0x08 /* Enables momory bypassing */
417 #define CCR4_DTE 0x10 /* Enables directory table entry cache */
418 #define CCR4_FASTFPE 0x20 /* Fast FPU exception */
419 #define CCR4_CPUID 0x80 /* Enables CPUID instruction */
422 #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */
423 #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */
424 #define CCR5_LBR1 0x10 /* Local bus region 1 */
425 #define CCR5_ARREN 0x20 /* Enables ARR region */
431 /* Performance Control Register (5x86 only). */
433 #define PCR0_RSTK 0x01 /* Enables return stack */
434 #define PCR0_BTB 0x02 /* Enables branch target buffer */
435 #define PCR0_LOOP 0x04 /* Enables loop */
436 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
438 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
439 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */
440 #define PCR0_LSSER 0x80 /* Disable reorder */
442 /* Device Identification Registers */
447 * Machine Check register constants.
449 #define MCG_CAP_COUNT 0x000000ff
450 #define MCG_CAP_CTL_P 0x00000100
451 #define MCG_CAP_EXT_P 0x00000200
452 #define MCG_CAP_TES_P 0x00000800
453 #define MCG_CAP_EXT_CNT 0x00ff0000
454 #define MCG_STATUS_RIPV 0x00000001
455 #define MCG_STATUS_EIPV 0x00000002
456 #define MCG_STATUS_MCIP 0x00000004
457 #define MCG_CTL_ENABLE 0xffffffffffffffffUL
458 #define MCG_CTL_DISABLE 0x0000000000000000UL
459 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4)
460 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4)
461 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4)
462 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4)
463 #define MC_STATUS_MCA_ERROR 0x000000000000ffffUL
464 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000UL
465 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000UL
466 #define MC_STATUS_PCC 0x0200000000000000UL
467 #define MC_STATUS_ADDRV 0x0400000000000000UL
468 #define MC_STATUS_MISCV 0x0800000000000000UL
469 #define MC_STATUS_EN 0x1000000000000000UL
470 #define MC_STATUS_UC 0x2000000000000000UL
471 #define MC_STATUS_OVER 0x4000000000000000UL
472 #define MC_STATUS_VAL 0x8000000000000000UL
475 * The following four 3-byte registers control the non-cacheable regions.
476 * These registers must be written as three separate bytes.
478 * NCRx+0: A31-A24 of starting address
479 * NCRx+1: A23-A16 of starting address
480 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
482 * The non-cacheable region's starting address must be aligned to the
483 * size indicated by the NCR_SIZE_xx field.
490 #define NCR_SIZE_0K 0
491 #define NCR_SIZE_4K 1
492 #define NCR_SIZE_8K 2
493 #define NCR_SIZE_16K 3
494 #define NCR_SIZE_32K 4
495 #define NCR_SIZE_64K 5
496 #define NCR_SIZE_128K 6
497 #define NCR_SIZE_256K 7
498 #define NCR_SIZE_512K 8
499 #define NCR_SIZE_1M 9
500 #define NCR_SIZE_2M 10
501 #define NCR_SIZE_4M 11
502 #define NCR_SIZE_8M 12
503 #define NCR_SIZE_16M 13
504 #define NCR_SIZE_32M 14
505 #define NCR_SIZE_4G 15
508 * The address region registers are used to specify the location and
509 * size for the eight address regions.
511 * ARRx + 0: A31-A24 of start address
512 * ARRx + 1: A23-A16 of start address
513 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
524 #define ARR_SIZE_0K 0
525 #define ARR_SIZE_4K 1
526 #define ARR_SIZE_8K 2
527 #define ARR_SIZE_16K 3
528 #define ARR_SIZE_32K 4
529 #define ARR_SIZE_64K 5
530 #define ARR_SIZE_128K 6
531 #define ARR_SIZE_256K 7
532 #define ARR_SIZE_512K 8
533 #define ARR_SIZE_1M 9
534 #define ARR_SIZE_2M 10
535 #define ARR_SIZE_4M 11
536 #define ARR_SIZE_8M 12
537 #define ARR_SIZE_16M 13
538 #define ARR_SIZE_32M 14
539 #define ARR_SIZE_4G 15
542 * The region control registers specify the attributes associated with
543 * the ARRx addres regions.
554 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
555 #define RCR_RCE 0x01 /* Enables caching for ARR7. */
556 #define RCR_WWO 0x02 /* Weak write ordering. */
557 #define RCR_WL 0x04 /* Weak locking. */
558 #define RCR_WG 0x08 /* Write gathering. */
559 #define RCR_WT 0x10 /* Write-through. */
560 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */
562 /* AMD Write Allocate Top-Of-Memory and Control Register */
563 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
564 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
565 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
568 #define MSR_EFER 0xc0000080 /* extended features */
569 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
571 /* VIA ACE crypto featureset: for via_feature_rng */
572 #define VIA_HAS_RNG 1 /* cpu has RNG */
574 /* VIA ACE crypto featureset: for via_feature_xcrypt */
575 #define VIA_HAS_AES 1 /* cpu has AES */
576 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */
577 #define VIA_HAS_MM 4 /* cpu has RSA instructions */
578 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
580 /* Centaur Extended Feature flags */
581 #define VIA_CPUID_HAS_RNG 0x000004
582 #define VIA_CPUID_DO_RNG 0x000008
583 #define VIA_CPUID_HAS_ACE 0x000040
584 #define VIA_CPUID_DO_ACE 0x000080
585 #define VIA_CPUID_HAS_ACE2 0x000100
586 #define VIA_CPUID_DO_ACE2 0x000200
587 #define VIA_CPUID_HAS_PHE 0x000400
588 #define VIA_CPUID_DO_PHE 0x000800
589 #define VIA_CPUID_HAS_PMM 0x001000
590 #define VIA_CPUID_DO_PMM 0x002000
592 /* VIA ACE xcrypt-* instruction context control options */
593 #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f
594 #define VIA_CRYPT_CWLO_ALG_M 0x00000070
595 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000
596 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080
597 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000
598 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080
599 #define VIA_CRYPT_CWLO_NORMAL 0x00000000
600 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100
601 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000
602 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200
603 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */
604 #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */
605 #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */
609 #ifndef _SYS_TYPES_H_
610 #include <sys/types.h>
612 #ifndef _CPU_CPUFUNC_H_
613 #include <cpu/cpufunc.h>
616 static __inline u_char
617 read_cyrix_reg(u_char reg)
624 write_cyrix_reg(u_char reg, u_char data)
631 #endif /* !_CPU_SPECIALREG_H_ */