- In re_stop(), call re_reset(), which is supposed to stop TX/RX engines.
[dragonfly.git] / sys / dev / netif / re / if_revar.h
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1/*
2 * Copyright (c) 2004
3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 *
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.42 2004/05/24 19:39:23 jhb Exp $
0d73dcef 36 * $DragonFly: src/sys/dev/netif/re/if_revar.h,v 1.30 2008/10/19 06:00:24 sephe Exp $
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37 */
38
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39#define RE_RX_DESC_CNT_8139CP 64
40#define RE_TX_DESC_CNT_8139CP 64
41
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42#define RE_RX_DESC_CNT_DEF 256
43#define RE_TX_DESC_CNT_DEF 256
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44#define RE_RX_DESC_CNT_MAX 1024
45#define RE_TX_DESC_CNT_MAX 1024
46
47#define RE_RX_LIST_SZ(sc) ((sc)->re_rx_desc_cnt * sizeof(struct re_desc))
48#define RE_TX_LIST_SZ(sc) ((sc)->re_tx_desc_cnt * sizeof(struct re_desc))
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49#define RE_RING_ALIGN 256
50#define RE_IFQ_MAXLEN 512
51#define RE_MAXSEGS 16
52#define RE_TXDESC_SPARE 4
a7d57e62 53#define RE_JBUF_COUNT(sc) (((sc)->re_rx_desc_cnt * 3) / 2)
998e7079 54
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55#define RE_RXDESC_INC(sc, x) (x = (x + 1) % (sc)->re_rx_desc_cnt)
56#define RE_TXDESC_INC(sc, x) (x = (x + 1) % (sc)->re_tx_desc_cnt)
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57#define RE_OWN(x) (le32toh((x)->re_cmdstat) & RE_RDESC_STAT_OWN)
58#define RE_RXBYTES(x) (le32toh((x)->re_cmdstat) & sc->re_rxlenmask)
59#define RE_PKTSZ(x) ((x)/* >> 3*/)
60
61#define RE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
62#define RE_ADDR_HI(y) ((uint64_t) (y) >> 32)
63
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64#define RE_MTU_6K (6 * 1024)
65#define RE_MTU_9K (9 * 1024)
66
67#define RE_ETHER_EXTRA (ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN)
68#define RE_FRAMELEN(mtu) ((mtu) + RE_ETHER_EXTRA)
69
70#define RE_FRAMELEN_6K RE_FRAMELEN(RE_MTU_6K)
71#define RE_FRAMELEN_9K RE_FRAMELEN(RE_MTU_9K)
72#define RE_FRAMELEN_MAX RE_FRAMELEN_9K
73
998e7079 74#define RE_SWCSUM_LIM_8169 2038
b0c15aad 75#define RE_SWCSUM_UNLIMITED 65536 /* XXX should be enough */
998e7079 76
a7d57e62 77#define RE_BUF_ALIGN 8
b0c15aad 78#define RE_JBUF_SIZE roundup2(RE_FRAMELEN_MAX, RE_BUF_ALIGN)
a7d57e62 79
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80#define RE_TIMEOUT 1000
81
5d686fbb 82struct re_hwrev {
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83 uint32_t re_hwrev;
84 uint32_t re_macver; /* see RE_MACVER_ */
b0c15aad 85 int re_maxmtu;
5bed1fbd 86 uint32_t re_caps; /* see RE_C_ */
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87};
88
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89#define RE_MACVER_UNKN 0
90#define RE_MACVER_03 0x03
91#define RE_MACVER_04 0x04
92#define RE_MACVER_05 0x05
93#define RE_MACVER_06 0x06
94#define RE_MACVER_11 0x11
95#define RE_MACVER_12 0x12
96#define RE_MACVER_13 0x13
97#define RE_MACVER_14 0x14
98#define RE_MACVER_15 0x15
99#define RE_MACVER_16 0x16
100#define RE_MACVER_21 0x21
101#define RE_MACVER_22 0x22
102#define RE_MACVER_23 0x23
103#define RE_MACVER_24 0x24
104#define RE_MACVER_25 0x25
105#define RE_MACVER_26 0x26
106#define RE_MACVER_27 0x27
107#define RE_MACVER_28 0x28
108#define RE_MACVER_29 0x29
109#define RE_MACVER_2A 0x2a
110#define RE_MACVER_2B 0x2b
5d686fbb 111
5d686fbb 112struct re_dmaload_arg {
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113 int re_nsegs;
114 bus_dma_segment_t *re_segs;
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115};
116
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117struct re_softc;
118struct re_jbuf {
119 struct re_softc *re_sc;
120 int re_inuse;
121 int re_slot;
122 caddr_t re_buf;
123 bus_addr_t re_paddr;
124 SLIST_ENTRY(re_jbuf) re_link;
125};
126
5d686fbb 127struct re_list_data {
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128 struct mbuf **re_tx_mbuf;
129 struct mbuf **re_rx_mbuf;
130 bus_addr_t *re_rx_paddr;
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131 int re_tx_prodidx;
132 int re_rx_prodidx;
133 int re_tx_considx;
134 int re_tx_free;
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135 bus_dmamap_t *re_tx_dmamap;
136 bus_dmamap_t *re_rx_dmamap;
3580fc56 137 bus_dmamap_t re_rx_spare;
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138 bus_dma_tag_t re_mtag; /* mbuf mapping tag */
139 bus_dma_tag_t re_stag; /* stats mapping tag */
140 bus_dmamap_t re_smap; /* stats map */
141 struct re_stats *re_stats;
142 bus_addr_t re_stats_addr;
143 bus_dma_tag_t re_rx_list_tag;
144 bus_dmamap_t re_rx_list_map;
145 struct re_desc *re_rx_list;
146 bus_addr_t re_rx_list_addr;
147 bus_dma_tag_t re_tx_list_tag;
148 bus_dmamap_t re_tx_list_map;
149 struct re_desc *re_tx_list;
150 bus_addr_t re_tx_list_addr;
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151
152 bus_dma_tag_t re_jpool_tag;
153 bus_dmamap_t re_jpool_map;
154 caddr_t re_jpool;
155 struct re_jbuf *re_jbuf;
156 struct lwkt_serialize re_jbuf_serializer;
157 SLIST_HEAD(, re_jbuf) re_jbuf_free;
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158};
159
160struct re_softc {
161 struct arpcom arpcom; /* interface info */
5d686fbb 162 device_t re_dev;
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163 bus_space_handle_t re_bhandle; /* bus space handle */
164 bus_space_tag_t re_btag; /* bus space tag */
165 struct resource *re_res;
166 struct resource *re_irq;
167 void *re_intrhand;
168 device_t re_miibus;
169 bus_dma_tag_t re_parent_tag;
170 bus_dma_tag_t re_tag;
089dc1b7 171 uint32_t re_hwrev;
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172 struct re_list_data re_ldata;
173 struct callout re_timer;
174 struct mbuf *re_head;
175 struct mbuf *re_tail;
5bed1fbd 176 uint32_t re_caps; /* see RE_C_ */
a1b67fc3 177 uint32_t re_macver; /* see RE_MACVER_ */
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178 uint32_t re_rxlenmask;
179 int re_txstart;
5d686fbb 180 int re_eewidth;
043ecbf0 181 int re_swcsum_lim;
089dc1b7 182 int re_maxmtu;
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183 int re_rx_desc_cnt;
184 int re_tx_desc_cnt;
957a8760 185 int re_bus_speed;
5d686fbb 186 int rxcycles;
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187 int re_rxbuf_size;
188 int (*re_newbuf)(struct re_softc *, int, int);
5d686fbb 189
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190 uint32_t re_flags; /* see RE_F_ */
191
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192 struct sysctl_ctx_list re_sysctl_ctx;
193 struct sysctl_oid *re_sysctl_tree;
194 uint16_t re_intrs;
195 uint16_t re_tx_ack;
1bdb2a81 196 uint16_t re_rx_ack;
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197 int re_tx_time;
198 int re_rx_time;
199 int re_sim_time;
200 int re_imtype; /* see RE_IMTYPE_ */
5d686fbb 201
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202 uint32_t saved_maps[5]; /* pci data */
203 uint32_t saved_biosaddr;
204 uint8_t saved_intline;
205 uint8_t saved_cachelnsz;
206 uint8_t saved_lattimer;
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207};
208
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209#define RE_C_PCIE 0x1 /* PCI-E */
210#define RE_C_PCI64 0x2 /* PCI-X */
5bed1fbd 211#define RE_C_HWIM 0x4 /* hardware interrupt moderation */
b7bb5f55 212#define RE_C_HWCSUM 0x8 /* hardware csum offload */
a1b67fc3 213#define RE_C_8139CP 0x20 /* is 8139C+ */
b7bb5f55 214#define RE_C_MAC2 0x40 /* MAC style 2 */
b24ce995 215#define RE_C_PHYPMGT 0x80 /* PHY supports power mgmt */
b7bb5f55 216#define RE_C_8169 0x100 /* is 8110/8169 */
afdeb9da 217#define RE_C_AUTOPAD 0x200 /* hardware auto-pad short frames */
a7d57e62 218#define RE_C_CONTIGRX 0x400 /* need contig buf to RX jumbo frames */
0d73dcef 219#define RE_C_STOP_RXTX 0x800 /* could stop RX/TX engine */
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220
221#define RE_IS_8139CP(sc) ((sc)->re_caps & RE_C_8139CP)
0d73dcef 222#define RE_IS_8169(sc) ((sc)->re_caps & RE_C_8169)
043ecbf0 223
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224/* Interrupt moderation types */
225#define RE_IMTYPE_NONE 0
226#define RE_IMTYPE_SIM 1 /* simulated */
227#define RE_IMTYPE_HW 2 /* hardware based */
228
229#define RE_F_TIMER_INTR 0x1
a7d57e62 230#define RE_F_USE_JPOOL 0x2
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231#define RE_F_DROP_RXFRAG 0x4
232#define RE_F_LINKED 0x8
233#define RE_F_SUSPENDED 0x10
234#define RE_F_TESTMODE 0x20
d4d77345 235
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236/*
237 * register space access macros
238 */
239#define CSR_WRITE_STREAM_4(sc, reg, val) \
240 bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val)
241#define CSR_WRITE_4(sc, reg, val) \
242 bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val)
243#define CSR_WRITE_2(sc, reg, val) \
244 bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val)
245#define CSR_WRITE_1(sc, reg, val) \
246 bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val)
247
248#define CSR_READ_4(sc, reg) \
249 bus_space_read_4(sc->re_btag, sc->re_bhandle, reg)
250#define CSR_READ_2(sc, reg) \
251 bus_space_read_2(sc->re_btag, sc->re_bhandle, reg)
252#define CSR_READ_1(sc, reg) \
253 bus_space_read_1(sc->re_btag, sc->re_bhandle, reg)
254
255#define CSR_SETBIT_1(sc, reg, val) \
256 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (val))
257#define CSR_CLRBIT_1(sc, reg, val) \
258 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(val))