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[dragonfly.git] / sys / bus / pci / pci.c
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1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
1f7d9fe0 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.42 2007/11/23 14:36:17 sephe Exp $
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28 *
29 */
30
31#include "opt_bus.h"
32#include "opt_pci.h"
33
dc5a7bd2 34#include "opt_compat_oldpci.h"
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35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/malloc.h>
39#include <sys/module.h>
40#include <sys/fcntl.h>
41#include <sys/conf.h>
42#include <sys/kernel.h>
43#include <sys/queue.h>
44#include <sys/types.h>
45#include <sys/buf.h>
46
47#include <vm/vm.h>
48#include <vm/pmap.h>
49#include <vm/vm_extern.h>
50
51#include <sys/bus.h>
984263bc 52#include <sys/rman.h>
97359a5b 53#include <machine/smp.h>
984263bc 54#ifdef __i386__
bbca97bc 55#include <bus/pci/i386/pci_cfgreg.h>
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56#endif
57
dc5a7bd2 58#include <sys/pciio.h>
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59#include "pcireg.h"
60#include "pcivar.h"
22457186 61#include "pci_private.h"
984263bc 62
4a5a2d63
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63#include "pcib_if.h"
64
e126caf1 65devclass_t pci_devclass;
2581072f 66const char *pcib_owner;
dc5a7bd2 67
4a5a2d63 68static void pci_read_extcap(device_t dev, pcicfgregs *cfg);
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69
70struct pci_quirk {
71 u_int32_t devid; /* Vendor/device of the card */
72 int type;
3e4db402 73#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
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74 int arg1;
75 int arg2;
76};
77
78struct pci_quirk pci_quirks[] = {
79 /*
80 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
81 */
82 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
83 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
f1f0bfb2
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84 /* As does the Serverworks OSB4 (the SMBus mapping register) */
85 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
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86
87 { 0 }
88};
89
90/* map register information */
91#define PCI_MAPMEM 0x01 /* memory map */
92#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
93#define PCI_MAPPORT 0x04 /* port map */
94
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95static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
96u_int32_t pci_numdevs = 0;
97static u_int32_t pci_generation = 0;
98
99device_t
100pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func)
101{
102 struct pci_devinfo *dinfo;
103
104 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
105 if ((dinfo->cfg.bus == bus) &&
106 (dinfo->cfg.slot == slot) &&
107 (dinfo->cfg.func == func)) {
108 return (dinfo->cfg.dev);
109 }
110 }
111
112 return (NULL);
113}
114
115device_t
116pci_find_device (u_int16_t vendor, u_int16_t device)
117{
118 struct pci_devinfo *dinfo;
119
120 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
121 if ((dinfo->cfg.vendor == vendor) &&
122 (dinfo->cfg.device == device)) {
123 return (dinfo->cfg.dev);
124 }
125 }
126
127 return (NULL);
128}
129
130/* return base address of memory or port map */
131
132static u_int32_t
133pci_mapbase(unsigned mapreg)
134{
135 int mask = 0x03;
136 if ((mapreg & 0x01) == 0)
137 mask = 0x0f;
138 return (mapreg & ~mask);
139}
140
141/* return map type of memory or port map */
142
143static int
144pci_maptype(unsigned mapreg)
145{
146 static u_int8_t maptype[0x10] = {
147 PCI_MAPMEM, PCI_MAPPORT,
148 PCI_MAPMEM, 0,
149 PCI_MAPMEM, PCI_MAPPORT,
150 0, 0,
151 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
152 PCI_MAPMEM|PCI_MAPMEMP, 0,
153 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
154 0, 0,
155 };
156
157 return maptype[mapreg & 0x0f];
158}
159
160/* return log2 of map size decoded for memory or port map */
161
162static int
163pci_mapsize(unsigned testval)
164{
165 int ln2size;
166
167 testval = pci_mapbase(testval);
168 ln2size = 0;
169 if (testval != 0) {
170 while ((testval & 1) == 0)
171 {
172 ln2size++;
173 testval >>= 1;
174 }
175 }
176 return (ln2size);
177}
178
179/* return log2 of address range supported by map register */
180
181static int
182pci_maprange(unsigned mapreg)
183{
184 int ln2range = 0;
185 switch (mapreg & 0x07) {
186 case 0x00:
187 case 0x01:
188 case 0x05:
189 ln2range = 32;
190 break;
191 case 0x02:
192 ln2range = 20;
193 break;
194 case 0x04:
195 ln2range = 64;
196 break;
197 }
198 return (ln2range);
199}
200
201/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
202
203static void
204pci_fixancient(pcicfgregs *cfg)
205{
206 if (cfg->hdrtype != 0)
207 return;
208
209 /* PCI to PCI bridges use header type 1 */
210 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
211 cfg->hdrtype = 1;
212}
213
214/* read config data specific to header type 1 device (PCI to PCI bridge) */
215
216static void *
4a5a2d63 217pci_readppb(device_t pcib, int b, int s, int f)
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218{
219 pcih1cfgregs *p;
220
efda3bd0 221 p = kmalloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
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222 if (p == NULL)
223 return (NULL);
224
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225 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
226 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
984263bc 227
4a5a2d63 228 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
984263bc 229
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230 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
231 PCIR_IOBASEH_1, 2),
232 PCIB_READ_CONFIG(pcib, b, s, f,
233 PCIR_IOBASEL_1, 1));
234 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
235 PCIR_IOLIMITH_1, 2),
236 PCIB_READ_CONFIG(pcib, b, s, f,
237 PCIR_IOLIMITL_1, 1));
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238
239 p->membase = PCI_PPBMEMBASE (0,
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240 PCIB_READ_CONFIG(pcib, b, s, f,
241 PCIR_MEMBASE_1, 2));
984263bc 242 p->memlimit = PCI_PPBMEMLIMIT (0,
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243 PCIB_READ_CONFIG(pcib, b, s, f,
244 PCIR_MEMLIMIT_1, 2));
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245
246 p->pmembase = PCI_PPBMEMBASE (
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247 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
248 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
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249
250 p->pmemlimit = PCI_PPBMEMLIMIT (
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251 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
252 PCIR_PMLIMITH_1, 4),
253 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
254
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255 return (p);
256}
257
258/* read config data specific to header type 2 device (PCI to CardBus bridge) */
259
260static void *
4a5a2d63 261pci_readpcb(device_t pcib, int b, int s, int f)
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262{
263 pcih2cfgregs *p;
264
efda3bd0 265 p = kmalloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
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266 if (p == NULL)
267 return (NULL);
268
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269 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
270 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
984263bc 271
4a5a2d63 272 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
984263bc 273
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274 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
275 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
276 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
277 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
984263bc 278
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279 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
280 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
281 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
282 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
984263bc 283
4a5a2d63 284 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
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285 return p;
286}
287
288/* extract header type specific config data */
289
290static void
4a5a2d63 291pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
984263bc 292{
4a5a2d63 293#define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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294 switch (cfg->hdrtype) {
295 case 0:
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296 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
297 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
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298 cfg->nummaps = PCI_MAXMAPS_0;
299 break;
300 case 1:
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301 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
302 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
303 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
304 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
984263bc 305 cfg->nummaps = PCI_MAXMAPS_1;
4a5a2d63 306 cfg->hdrspec = pci_readppb(pcib, b, s, f);
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307 break;
308 case 2:
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309 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
310 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
311 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
312 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
984263bc 313 cfg->nummaps = PCI_MAXMAPS_2;
4a5a2d63 314 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
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315 break;
316 }
4a5a2d63 317#undef REG
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318}
319
320/* read configuration header into pcicfgrect structure */
321
22457186 322struct pci_devinfo *
c01b8d84 323pci_read_device(device_t pcib, int b, int s, int f, size_t size)
984263bc 324{
4a5a2d63 325#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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326
327 pcicfgregs *cfg = NULL;
328 struct pci_devinfo *devlist_entry;
329 struct devlist *devlist_head;
330
331 devlist_head = &pci_devq;
332
333 devlist_entry = NULL;
334
4a5a2d63 335 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
984263bc 336
efda3bd0 337 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
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338 if (devlist_entry == NULL)
339 return (NULL);
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340
341 cfg = &devlist_entry->cfg;
342
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343 cfg->bus = b;
344 cfg->slot = s;
345 cfg->func = f;
346 cfg->vendor = REG(PCIR_VENDOR, 2);
347 cfg->device = REG(PCIR_DEVICE, 2);
348 cfg->cmdreg = REG(PCIR_COMMAND, 2);
349 cfg->statreg = REG(PCIR_STATUS, 2);
350 cfg->baseclass = REG(PCIR_CLASS, 1);
351 cfg->subclass = REG(PCIR_SUBCLASS, 1);
352 cfg->progif = REG(PCIR_PROGIF, 1);
353 cfg->revid = REG(PCIR_REVID, 1);
e126caf1 354 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
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355 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
356 cfg->lattimer = REG(PCIR_LATTIMER, 1);
357 cfg->intpin = REG(PCIR_INTPIN, 1);
358 cfg->intline = REG(PCIR_INTLINE, 1);
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359
360#ifdef APIC_IO
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361 /*
362 * If using the APIC the intpin is probably wrong, since it
363 * is often setup by the BIOS with the PIC in mind.
364 */
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365 if (cfg->intpin != 0) {
366 int airq;
367
368 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
369 if (airq >= 0) {
370 /* PCI specific entry found in MP table */
371 if (airq != cfg->intline) {
372 undirect_pci_irq(cfg->intline);
373 cfg->intline = airq;
374 }
375 } else {
376 /*
377 * PCI interrupts might be redirected to the
378 * ISA bus according to some MP tables. Use the
379 * same methods as used by the ISA devices
380 * devices to find the proper IOAPIC int pin.
381 */
382 airq = isa_apic_irq(cfg->intline);
383 if ((airq >= 0) && (airq != cfg->intline)) {
384 /* XXX: undirect_pci_irq() ? */
385 undirect_isa_irq(cfg->intline);
386 cfg->intline = airq;
387 }
388 }
389 }
390#endif /* APIC_IO */
391
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392 cfg->mingnt = REG(PCIR_MINGNT, 1);
393 cfg->maxlat = REG(PCIR_MAXLAT, 1);
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394
395 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
396 cfg->hdrtype &= ~PCIM_MFDEV;
397
398 pci_fixancient(cfg);
4a5a2d63 399 pci_hdrtypedata(pcib, b, s, f, cfg);
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400
401 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
4a5a2d63 402 pci_read_extcap(pcib, cfg);
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403
404 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
405
406 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
407 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
408 devlist_entry->conf.pc_sel.pc_func = cfg->func;
409 devlist_entry->conf.pc_hdr = cfg->hdrtype;
410
411 devlist_entry->conf.pc_subvendor = cfg->subvendor;
412 devlist_entry->conf.pc_subdevice = cfg->subdevice;
413 devlist_entry->conf.pc_vendor = cfg->vendor;
414 devlist_entry->conf.pc_device = cfg->device;
415
416 devlist_entry->conf.pc_class = cfg->baseclass;
417 devlist_entry->conf.pc_subclass = cfg->subclass;
418 devlist_entry->conf.pc_progif = cfg->progif;
419 devlist_entry->conf.pc_revid = cfg->revid;
420
421 pci_numdevs++;
422 pci_generation++;
423 }
424 return (devlist_entry);
425#undef REG
426}
427
428static void
4a5a2d63 429pci_read_extcap(device_t pcib, pcicfgregs *cfg)
984263bc 430{
4a5a2d63 431#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
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432 int ptr, nextptr, ptrptr;
433
434 switch (cfg->hdrtype) {
435 case 0:
81c29ce4
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436 case 1:
437 ptrptr = PCIR_CAP_PTR;
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438 break;
439 case 2:
81c29ce4 440 ptrptr = PCIR_CAP_PTR_2;
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441 break;
442 default:
443 return; /* no extended capabilities support */
444 }
445 nextptr = REG(ptrptr, 1); /* sanity check? */
446
447 /*
448 * Read capability entries.
449 */
450 while (nextptr != 0) {
451 /* Sanity check */
452 if (nextptr > 255) {
85f8e2ea 453 kprintf("illegal PCI extended capability offset %d\n",
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454 nextptr);
455 return;
456 }
457 /* Find the next entry */
458 ptr = nextptr;
459 nextptr = REG(ptr + 1, 1);
460
461 /* Process this entry */
462 switch (REG(ptr, 1)) {
81c29ce4 463 case PCIY_PMG: /* PCI power management */
1f7d9fe0
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464 if (cfg->pmgt.pp_cap == 0) {
465 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
466
467 pmgt->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
468 pmgt->pp_status = ptr + PCIR_POWER_STATUS;
469 pmgt->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
984263bc 470 if ((nextptr - ptr) > PCIR_POWER_DATA)
1f7d9fe0 471 pmgt->pp_data = ptr + PCIR_POWER_DATA;
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472 }
473 break;
474 default:
475 break;
476 }
477 }
478#undef REG
479}
480
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481/* free pcicfgregs structure and all depending data structures */
482
22457186 483int
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484pci_freecfg(struct pci_devinfo *dinfo)
485{
486 struct devlist *devlist_head;
487
488 devlist_head = &pci_devq;
489
490 if (dinfo->cfg.hdrspec != NULL)
efda3bd0 491 kfree(dinfo->cfg.hdrspec, M_DEVBUF);
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492 /* XXX this hasn't been tested */
493 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
efda3bd0 494 kfree(dinfo, M_DEVBUF);
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495
496 /* increment the generation count */
497 pci_generation++;
498
499 /* we're losing one device */
500 pci_numdevs--;
501 return (0);
502}
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503
504
505/*
506 * PCI power manangement
507 */
e126caf1 508int
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509pci_set_powerstate_method(device_t dev, device_t child, int state)
510{
511 struct pci_devinfo *dinfo = device_get_ivars(child);
512 pcicfgregs *cfg = &dinfo->cfg;
1f7d9fe0 513 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
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514 u_int16_t status;
515 int result;
516
1f7d9fe0
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517 if (pmgt->pp_cap != 0) {
518 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2) & ~PCIM_PSTAT_DMASK;
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519 result = 0;
520 switch (state) {
521 case PCI_POWERSTATE_D0:
522 status |= PCIM_PSTAT_D0;
523 break;
524 case PCI_POWERSTATE_D1:
1f7d9fe0 525 if (pmgt->pp_cap & PCIM_PCAP_D1SUPP) {
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526 status |= PCIM_PSTAT_D1;
527 } else {
528 result = EOPNOTSUPP;
529 }
530 break;
531 case PCI_POWERSTATE_D2:
1f7d9fe0 532 if (pmgt->pp_cap & PCIM_PCAP_D2SUPP) {
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533 status |= PCIM_PSTAT_D2;
534 } else {
535 result = EOPNOTSUPP;
536 }
537 break;
538 case PCI_POWERSTATE_D3:
539 status |= PCIM_PSTAT_D3;
540 break;
541 default:
542 result = EINVAL;
543 }
544 if (result == 0)
1f7d9fe0 545 PCI_WRITE_CONFIG(dev, child, pmgt->pp_status, status, 2);
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546 } else {
547 result = ENXIO;
548 }
549 return(result);
550}
551
e126caf1 552int
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553pci_get_powerstate_method(device_t dev, device_t child)
554{
555 struct pci_devinfo *dinfo = device_get_ivars(child);
556 pcicfgregs *cfg = &dinfo->cfg;
1f7d9fe0 557 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
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558 u_int16_t status;
559 int result;
560
1f7d9fe0
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561 if (pmgt->pp_cap != 0) {
562 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2);
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563 switch (status & PCIM_PSTAT_DMASK) {
564 case PCIM_PSTAT_D0:
565 result = PCI_POWERSTATE_D0;
566 break;
567 case PCIM_PSTAT_D1:
568 result = PCI_POWERSTATE_D1;
569 break;
570 case PCIM_PSTAT_D2:
571 result = PCI_POWERSTATE_D2;
572 break;
573 case PCIM_PSTAT_D3:
574 result = PCI_POWERSTATE_D3;
575 break;
576 default:
577 result = PCI_POWERSTATE_UNKNOWN;
578 break;
579 }
580 } else {
581 /* No support, device is always at D0 */
582 result = PCI_POWERSTATE_D0;
583 }
584 return(result);
585}
586
587/*
588 * Some convenience functions for PCI device drivers.
589 */
590
591static __inline void
592pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
593{
594 u_int16_t command;
595
596 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
597 command |= bit;
598 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
599}
600
601static __inline void
602pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
603{
604 u_int16_t command;
605
606 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
607 command &= ~bit;
608 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
609}
610
e126caf1 611int
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612pci_enable_busmaster_method(device_t dev, device_t child)
613{
614 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 615 return(0);
984263bc
MD
616}
617
e126caf1 618int
984263bc
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619pci_disable_busmaster_method(device_t dev, device_t child)
620{
621 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 622 return(0);
984263bc
MD
623}
624
e126caf1 625int
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MD
626pci_enable_io_method(device_t dev, device_t child, int space)
627{
e126caf1
MD
628 uint16_t command;
629 uint16_t bit;
630 char *error;
631
632 bit = 0;
633 error = NULL;
634
984263bc
MD
635 switch(space) {
636 case SYS_RES_IOPORT:
e126caf1
MD
637 bit = PCIM_CMD_PORTEN;
638 error = "port";
984263bc
MD
639 break;
640 case SYS_RES_MEMORY:
e126caf1
MD
641 bit = PCIM_CMD_MEMEN;
642 error = "memory";
984263bc 643 break;
e126caf1
MD
644 default:
645 return(EINVAL);
984263bc 646 }
e126caf1
MD
647 pci_set_command_bit(dev, child, bit);
648 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
649 if (command & bit)
650 return(0);
651 device_printf(child, "failed to enable %s mapping!\n", error);
652 return(ENXIO);
984263bc
MD
653}
654
e126caf1 655int
984263bc
MD
656pci_disable_io_method(device_t dev, device_t child, int space)
657{
e126caf1
MD
658 uint16_t command;
659 uint16_t bit;
660 char *error;
661
662 bit = 0;
663 error = NULL;
664
984263bc
MD
665 switch(space) {
666 case SYS_RES_IOPORT:
e126caf1
MD
667 bit = PCIM_CMD_PORTEN;
668 error = "port";
984263bc
MD
669 break;
670 case SYS_RES_MEMORY:
e126caf1
MD
671 bit = PCIM_CMD_MEMEN;
672 error = "memory";
984263bc 673 break;
e126caf1
MD
674 default:
675 return (EINVAL);
984263bc 676 }
e126caf1
MD
677 pci_clear_command_bit(dev, child, bit);
678 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
679 if (command & bit) {
680 device_printf(child, "failed to disable %s mapping!\n", error);
681 return (ENXIO);
682 }
683 return (0);
984263bc
MD
684}
685
686/*
687 * This is the user interface to PCI configuration space.
688 */
689
690static int
fef8985e 691pci_open(struct dev_open_args *ap)
984263bc 692{
fef8985e 693 if ((ap->a_oflags & FWRITE) && securelevel > 0) {
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MD
694 return EPERM;
695 }
696 return 0;
697}
698
699static int
fef8985e 700pci_close(struct dev_close_args *ap)
984263bc
MD
701{
702 return 0;
703}
704
705/*
706 * Match a single pci_conf structure against an array of pci_match_conf
707 * structures. The first argument, 'matches', is an array of num_matches
708 * pci_match_conf structures. match_buf is a pointer to the pci_conf
709 * structure that will be compared to every entry in the matches array.
710 * This function returns 1 on failure, 0 on success.
711 */
712static int
713pci_conf_match(struct pci_match_conf *matches, int num_matches,
714 struct pci_conf *match_buf)
715{
716 int i;
717
718 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
719 return(1);
720
721 for (i = 0; i < num_matches; i++) {
722 /*
723 * I'm not sure why someone would do this...but...
724 */
725 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
726 continue;
727
728 /*
729 * Look at each of the match flags. If it's set, do the
730 * comparison. If the comparison fails, we don't have a
731 * match, go on to the next item if there is one.
732 */
733 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
734 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
735 continue;
736
737 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
738 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
739 continue;
740
741 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
742 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
743 continue;
744
745 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
746 && (match_buf->pc_vendor != matches[i].pc_vendor))
747 continue;
748
749 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
750 && (match_buf->pc_device != matches[i].pc_device))
751 continue;
752
753 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
754 && (match_buf->pc_class != matches[i].pc_class))
755 continue;
756
757 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
758 && (match_buf->pd_unit != matches[i].pd_unit))
759 continue;
760
761 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
762 && (strncmp(matches[i].pd_name, match_buf->pd_name,
763 sizeof(match_buf->pd_name)) != 0))
764 continue;
765
766 return(0);
767 }
768
769 return(1);
770}
771
772/*
773 * Locate the parent of a PCI device by scanning the PCI devlist
774 * and return the entry for the parent.
775 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
776 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
777 */
778
779pcicfgregs *
780pci_devlist_get_parent(pcicfgregs *cfg)
781{
782 struct devlist *devlist_head;
783 struct pci_devinfo *dinfo;
784 pcicfgregs *bridge_cfg;
785 int i;
786
787 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
788
789 /* If the device is on PCI bus 0, look for the host */
790 if (cfg->bus == 0) {
791 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
792 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
793 bridge_cfg = &dinfo->cfg;
794 if (bridge_cfg->baseclass == PCIC_BRIDGE
795 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
796 && bridge_cfg->bus == cfg->bus) {
797 return bridge_cfg;
798 }
799 }
800 }
801
802 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
803 if (cfg->bus > 0) {
804 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
805 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
806 bridge_cfg = &dinfo->cfg;
807 if (bridge_cfg->baseclass == PCIC_BRIDGE
808 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
809 && bridge_cfg->secondarybus == cfg->bus) {
810 return bridge_cfg;
811 }
812 }
813 }
814
815 return NULL;
816}
817
818static int
fef8985e 819pci_ioctl(struct dev_ioctl_args *ap)
984263bc 820{
4a5a2d63 821 device_t pci, pcib;
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MD
822 struct pci_io *io;
823 const char *name;
824 int error;
825
fef8985e 826 if (!(ap->a_fflag & FWRITE))
984263bc
MD
827 return EPERM;
828
fef8985e 829 switch(ap->a_cmd) {
984263bc
MD
830 case PCIOCGETCONF:
831 {
832 struct pci_devinfo *dinfo;
833 struct pci_conf_io *cio;
834 struct devlist *devlist_head;
835 struct pci_match_conf *pattern_buf;
836 int num_patterns;
837 size_t iolen;
838 int ionum, i;
839
fef8985e 840 cio = (struct pci_conf_io *)ap->a_data;
984263bc
MD
841
842 num_patterns = 0;
843 dinfo = NULL;
844
845 /*
846 * Hopefully the user won't pass in a null pointer, but it
847 * can't hurt to check.
848 */
849 if (cio == NULL) {
850 error = EINVAL;
851 break;
852 }
853
854 /*
855 * If the user specified an offset into the device list,
856 * but the list has changed since they last called this
857 * ioctl, tell them that the list has changed. They will
858 * have to get the list from the beginning.
859 */
860 if ((cio->offset != 0)
861 && (cio->generation != pci_generation)){
862 cio->num_matches = 0;
863 cio->status = PCI_GETCONF_LIST_CHANGED;
864 error = 0;
865 break;
866 }
867
868 /*
869 * Check to see whether the user has asked for an offset
870 * past the end of our list.
871 */
872 if (cio->offset >= pci_numdevs) {
873 cio->num_matches = 0;
874 cio->status = PCI_GETCONF_LAST_DEVICE;
875 error = 0;
876 break;
877 }
878
879 /* get the head of the device queue */
880 devlist_head = &pci_devq;
881
882 /*
883 * Determine how much room we have for pci_conf structures.
884 * Round the user's buffer size down to the nearest
885 * multiple of sizeof(struct pci_conf) in case the user
886 * didn't specify a multiple of that size.
887 */
888 iolen = min(cio->match_buf_len -
889 (cio->match_buf_len % sizeof(struct pci_conf)),
890 pci_numdevs * sizeof(struct pci_conf));
891
892 /*
893 * Since we know that iolen is a multiple of the size of
894 * the pciconf union, it's okay to do this.
895 */
896 ionum = iolen / sizeof(struct pci_conf);
897
898 /*
899 * If this test is true, the user wants the pci_conf
900 * structures returned to match the supplied entries.
901 */
902 if ((cio->num_patterns > 0)
903 && (cio->pat_buf_len > 0)) {
904 /*
905 * pat_buf_len needs to be:
906 * num_patterns * sizeof(struct pci_match_conf)
907 * While it is certainly possible the user just
908 * allocated a large buffer, but set the number of
909 * matches correctly, it is far more likely that
910 * their kernel doesn't match the userland utility
911 * they're using. It's also possible that the user
912 * forgot to initialize some variables. Yes, this
913 * may be overly picky, but I hazard to guess that
914 * it's far more likely to just catch folks that
915 * updated their kernel but not their userland.
916 */
917 if ((cio->num_patterns *
918 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
919 /* The user made a mistake, return an error*/
920 cio->status = PCI_GETCONF_ERROR;
85f8e2ea 921 kprintf("pci_ioctl: pat_buf_len %d != "
984263bc
MD
922 "num_patterns (%d) * sizeof(struct "
923 "pci_match_conf) (%d)\npci_ioctl: "
924 "pat_buf_len should be = %d\n",
925 cio->pat_buf_len, cio->num_patterns,
926 (int)sizeof(struct pci_match_conf),
927 (int)sizeof(struct pci_match_conf) *
928 cio->num_patterns);
85f8e2ea 929 kprintf("pci_ioctl: do your headers match your "
984263bc
MD
930 "kernel?\n");
931 cio->num_matches = 0;
932 error = EINVAL;
933 break;
934 }
935
936 /*
937 * Check the user's buffer to make sure it's readable.
938 */
939 if (!useracc((caddr_t)cio->patterns,
940 cio->pat_buf_len, VM_PROT_READ)) {
85f8e2ea 941 kprintf("pci_ioctl: pattern buffer %p, "
984263bc
MD
942 "length %u isn't user accessible for"
943 " READ\n", cio->patterns,
944 cio->pat_buf_len);
945 error = EACCES;
946 break;
947 }
948 /*
949 * Allocate a buffer to hold the patterns.
950 */
efda3bd0 951 pattern_buf = kmalloc(cio->pat_buf_len, M_TEMP,
984263bc
MD
952 M_WAITOK);
953 error = copyin(cio->patterns, pattern_buf,
954 cio->pat_buf_len);
955 if (error != 0)
956 break;
957 num_patterns = cio->num_patterns;
958
959 } else if ((cio->num_patterns > 0)
960 || (cio->pat_buf_len > 0)) {
961 /*
962 * The user made a mistake, spit out an error.
963 */
964 cio->status = PCI_GETCONF_ERROR;
965 cio->num_matches = 0;
85f8e2ea 966 kprintf("pci_ioctl: invalid GETCONF arguments\n");
984263bc
MD
967 error = EINVAL;
968 break;
969 } else
970 pattern_buf = NULL;
971
972 /*
973 * Make sure we can write to the match buffer.
974 */
975 if (!useracc((caddr_t)cio->matches,
976 cio->match_buf_len, VM_PROT_WRITE)) {
85f8e2ea 977 kprintf("pci_ioctl: match buffer %p, length %u "
984263bc
MD
978 "isn't user accessible for WRITE\n",
979 cio->matches, cio->match_buf_len);
980 error = EACCES;
981 break;
982 }
983
984 /*
985 * Go through the list of devices and copy out the devices
986 * that match the user's criteria.
987 */
988 for (cio->num_matches = 0, error = 0, i = 0,
989 dinfo = STAILQ_FIRST(devlist_head);
990 (dinfo != NULL) && (cio->num_matches < ionum)
991 && (error == 0) && (i < pci_numdevs);
992 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
993
994 if (i < cio->offset)
995 continue;
996
997 /* Populate pd_name and pd_unit */
998 name = NULL;
999 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
1000 name = device_get_name(dinfo->cfg.dev);
1001 if (name) {
1002 strncpy(dinfo->conf.pd_name, name,
1003 sizeof(dinfo->conf.pd_name));
1004 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
1005 dinfo->conf.pd_unit =
1006 device_get_unit(dinfo->cfg.dev);
1007 }
1008
1009 if ((pattern_buf == NULL) ||
1010 (pci_conf_match(pattern_buf, num_patterns,
1011 &dinfo->conf) == 0)) {
1012
1013 /*
1014 * If we've filled up the user's buffer,
1015 * break out at this point. Since we've
1016 * got a match here, we'll pick right back
1017 * up at the matching entry. We can also
1018 * tell the user that there are more matches
1019 * left.
1020 */
1021 if (cio->num_matches >= ionum)
1022 break;
1023
1024 error = copyout(&dinfo->conf,
1025 &cio->matches[cio->num_matches],
1026 sizeof(struct pci_conf));
1027 cio->num_matches++;
1028 }
1029 }
1030
1031 /*
1032 * Set the pointer into the list, so if the user is getting
1033 * n records at a time, where n < pci_numdevs,
1034 */
1035 cio->offset = i;
1036
1037 /*
1038 * Set the generation, the user will need this if they make
1039 * another ioctl call with offset != 0.
1040 */
1041 cio->generation = pci_generation;
1042
1043 /*
1044 * If this is the last device, inform the user so he won't
1045 * bother asking for more devices. If dinfo isn't NULL, we
1046 * know that there are more matches in the list because of
1047 * the way the traversal is done.
1048 */
1049 if (dinfo == NULL)
1050 cio->status = PCI_GETCONF_LAST_DEVICE;
1051 else
1052 cio->status = PCI_GETCONF_MORE_DEVS;
1053
1054 if (pattern_buf != NULL)
efda3bd0 1055 kfree(pattern_buf, M_TEMP);
984263bc
MD
1056
1057 break;
1058 }
1059 case PCIOCREAD:
fef8985e 1060 io = (struct pci_io *)ap->a_data;
984263bc 1061 switch(io->pi_width) {
984263bc
MD
1062 case 4:
1063 case 2:
1064 case 1:
4a5a2d63
JS
1065 /*
1066 * Assume that the user-level bus number is
1067 * actually the pciN instance number. We map
1068 * from that to the real pcib+bus combination.
1069 */
1070 pci = devclass_get_device(pci_devclass,
1071 io->pi_sel.pc_bus);
1072 if (pci) {
2581072f
MD
1073 /*
1074 * pci is the pci device and may contain
1075 * several children (for each function code).
1076 * The governing pci bus is the parent to
1077 * the pci device.
1078 */
1079 int b;
1080
4a5a2d63 1081 pcib = device_get_parent(pci);
2581072f 1082 b = pcib_get_bus(pcib);
4a5a2d63
JS
1083 io->pi_data =
1084 PCIB_READ_CONFIG(pcib,
1085 b,
1086 io->pi_sel.pc_dev,
1087 io->pi_sel.pc_func,
1088 io->pi_reg,
1089 io->pi_width);
1090 error = 0;
1091 } else {
1092 error = ENODEV;
1093 }
984263bc
MD
1094 break;
1095 default:
1096 error = ENODEV;
1097 break;
1098 }
1099 break;
1100
1101 case PCIOCWRITE:
fef8985e 1102 io = (struct pci_io *)ap->a_data;
984263bc 1103 switch(io->pi_width) {
984263bc
MD
1104 case 4:
1105 case 2:
1106 case 1:
4a5a2d63
JS
1107 /*
1108 * Assume that the user-level bus number is
1109 * actually the pciN instance number. We map
1110 * from that to the real pcib+bus combination.
1111 */
1112 pci = devclass_get_device(pci_devclass,
1113 io->pi_sel.pc_bus);
1114 if (pci) {
2581072f
MD
1115 /*
1116 * pci is the pci device and may contain
1117 * several children (for each function code).
1118 * The governing pci bus is the parent to
1119 * the pci device.
1120 */
1121 int b;
1122
4a5a2d63 1123 pcib = device_get_parent(pci);
2581072f 1124 b = pcib_get_bus(pcib);
4a5a2d63
JS
1125 PCIB_WRITE_CONFIG(pcib,
1126 b,
1127 io->pi_sel.pc_dev,
1128 io->pi_sel.pc_func,
1129 io->pi_reg,
1130 io->pi_data,
1131 io->pi_width);
1132 error = 0;
1133 } else {
1134 error = ENODEV;
1135 }
984263bc
MD
1136 break;
1137 default:
1138 error = ENODEV;
1139 break;
1140 }
1141 break;
1142
1143 default:
1144 error = ENOTTY;
1145 break;
1146 }
1147
1148 return (error);
1149}
1150
1151#define PCI_CDEV 78
1152
fef8985e
MD
1153static struct dev_ops pcic_ops = {
1154 { "pci", PCI_CDEV, 0 },
1155 .d_open = pci_open,
1156 .d_close = pci_close,
1157 .d_ioctl = pci_ioctl,
984263bc
MD
1158};
1159
1160#include "pci_if.h"
1161
984263bc
MD
1162/*
1163 * New style pci driver. Parent device is either a pci-host-bridge or a
1164 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1165 */
ed1bd994
MD
1166const char *
1167pci_class_to_string(int baseclass)
1168{
1169 const char *name;
1170
1171 switch(baseclass) {
1172 case PCIC_OLD:
1173 name = "OLD";
1174 break;
1175 case PCIC_STORAGE:
1176 name = "STORAGE";
1177 break;
1178 case PCIC_NETWORK:
1179 name = "NETWORK";
1180 break;
1181 case PCIC_DISPLAY:
1182 name = "DISPLAY";
1183 break;
1184 case PCIC_MULTIMEDIA:
1185 name = "MULTIMEDIA";
1186 break;
1187 case PCIC_MEMORY:
1188 name = "MEMORY";
1189 break;
1190 case PCIC_BRIDGE:
1191 name = "BRIDGE";
1192 break;
1193 case PCIC_SIMPLECOMM:
1194 name = "SIMPLECOMM";
1195 break;
1196 case PCIC_BASEPERIPH:
1197 name = "BASEPERIPH";
1198 break;
1199 case PCIC_INPUTDEV:
1200 name = "INPUTDEV";
1201 break;
1202 case PCIC_DOCKING:
1203 name = "DOCKING";
1204 break;
1205 case PCIC_PROCESSOR:
1206 name = "PROCESSOR";
1207 break;
1208 case PCIC_SERIALBUS:
1209 name = "SERIALBUS";
1210 break;
1211 case PCIC_WIRELESS:
1212 name = "WIRELESS";
1213 break;
1214 case PCIC_I2O:
1215 name = "I20";
1216 break;
1217 case PCIC_SATELLITE:
1218 name = "SATELLITE";
1219 break;
1220 case PCIC_CRYPTO:
1221 name = "CRYPTO";
1222 break;
1223 case PCIC_SIGPROC:
1224 name = "SIGPROC";
1225 break;
1226 case PCIC_OTHER:
1227 name = "OTHER";
1228 break;
1229 default:
1230 name = "?";
1231 break;
1232 }
1233 return(name);
1234}
984263bc 1235
22457186 1236void
984263bc
MD
1237pci_print_verbose(struct pci_devinfo *dinfo)
1238{
1239 if (bootverbose) {
1240 pcicfgregs *cfg = &dinfo->cfg;
1241
85f8e2ea 1242 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
984263bc 1243 cfg->vendor, cfg->device, cfg->revid);
85f8e2ea 1244 kprintf("\tbus=%d, slot=%d, func=%d\n",
4a5a2d63 1245 cfg->bus, cfg->slot, cfg->func);
85f8e2ea 1246 kprintf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
ed1bd994 1247 pci_class_to_string(cfg->baseclass),
984263bc
MD
1248 cfg->baseclass, cfg->subclass, cfg->progif,
1249 cfg->hdrtype, cfg->mfdev);
85f8e2ea 1250 kprintf("\tsubordinatebus=%x \tsecondarybus=%x\n",
984263bc
MD
1251 cfg->subordinatebus, cfg->secondarybus);
1252#ifdef PCI_DEBUG
85f8e2ea 1253 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
984263bc 1254 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
85f8e2ea 1255 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
984263bc
MD
1256 cfg->lattimer, cfg->lattimer * 30,
1257 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1258#endif /* PCI_DEBUG */
1259 if (cfg->intpin > 0)
85f8e2ea 1260 kprintf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
984263bc
MD
1261 }
1262}
1263
1264static int
4a5a2d63 1265pci_porten(device_t pcib, int b, int s, int f)
984263bc 1266{
4a5a2d63
JS
1267 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1268 & PCIM_CMD_PORTEN) != 0;
984263bc
MD
1269}
1270
1271static int
4a5a2d63 1272pci_memen(device_t pcib, int b, int s, int f)
984263bc 1273{
4a5a2d63
JS
1274 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1275 & PCIM_CMD_MEMEN) != 0;
984263bc
MD
1276}
1277
1278/*
1279 * Add a resource based on a pci map register. Return 1 if the map
1280 * register is a 32bit map register or 2 if it is a 64bit register.
1281 */
1282static int
4a5a2d63
JS
1283pci_add_map(device_t pcib, int b, int s, int f, int reg,
1284 struct resource_list *rl)
984263bc 1285{
984263bc
MD
1286 u_int32_t map;
1287 u_int64_t base;
1288 u_int8_t ln2size;
1289 u_int8_t ln2range;
1290 u_int32_t testval;
4a5a2d63
JS
1291
1292
1293#ifdef PCI_ENABLE_IO_MODES
1294 u_int16_t cmd;
1295#endif
984263bc
MD
1296 int type;
1297
4a5a2d63 1298 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
984263bc
MD
1299
1300 if (map == 0 || map == 0xffffffff)
1301 return 1; /* skip invalid entry */
1302
4a5a2d63
JS
1303 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1304 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1305 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
984263bc
MD
1306
1307 base = pci_mapbase(map);
1308 if (pci_maptype(map) & PCI_MAPMEM)
1309 type = SYS_RES_MEMORY;
1310 else
1311 type = SYS_RES_IOPORT;
1312 ln2size = pci_mapsize(testval);
1313 ln2range = pci_maprange(testval);
1314 if (ln2range == 64) {
1315 /* Read the other half of a 64bit map register */
4a5a2d63 1316 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
984263bc
MD
1317 }
1318
984263bc
MD
1319 /*
1320 * This code theoretically does the right thing, but has
1321 * undesirable side effects in some cases where
1322 * peripherals respond oddly to having these bits
1323 * enabled. Leave them alone by default.
1324 */
1325#ifdef PCI_ENABLE_IO_MODES
4a5a2d63
JS
1326 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1327 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1328 cmd |= PCIM_CMD_PORTEN;
1329 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc 1330 }
4a5a2d63
JS
1331 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1332 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1333 cmd |= PCIM_CMD_MEMEN;
1334 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc
MD
1335 }
1336#else
4a5a2d63 1337 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
984263bc 1338 return 1;
4a5a2d63 1339 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
984263bc
MD
1340 return 1;
1341#endif
1342
1343 resource_list_add(rl, type, reg,
1344 base, base + (1 << ln2size) - 1,
1345 (1 << ln2size));
1346
1347 if (bootverbose) {
85f8e2ea 1348 kprintf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
984263bc
MD
1349 reg, pci_maptype(base), ln2range,
1350 (unsigned int) base, ln2size);
1351 }
1352
1353 return (ln2range == 64) ? 2 : 1;
1354}
1355
201eb0a7
TS
1356#ifdef PCI_MAP_FIXUP
1357/*
1358 * For ATA devices we need to decide early on what addressing mode to use.
1359 * Legacy demands that the primary and secondary ATA ports sits on the
1360 * same addresses that old ISA hardware did. This dictates that we use
1361 * those addresses and ignore the BARs if we cannot set PCI native
1362 * addressing mode.
1363 */
1364static void
1365pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, int s, int f,
1366 struct resource_list *rl)
1367{
1368 int rid, type, progif;
1369#if 0
1370 /* if this device supports PCI native addressing use it */
1371 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1372 if ((progif &0x8a) == 0x8a) {
1373 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
1374 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
85f8e2ea 1375 kprintf("Trying ATA native PCI addressing mode\n");
201eb0a7
TS
1376 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
1377 }
1378 }
1379#endif
1380 /*
1381 * Because we return any preallocated resources for lazy
1382 * allocation for PCI devices in pci_alloc_resource(), we can
1383 * allocate our legacy resources here.
1384 */
1385 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1386 type = SYS_RES_IOPORT;
1387 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
1388 pci_add_map(pcib, b, s, f, PCIR_BAR(0), rl);
1389 pci_add_map(pcib, b, s, f, PCIR_BAR(1), rl);
1390 } else {
1391 rid = PCIR_BAR(0);
1392 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
1393 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
1394 0);
1395 rid = PCIR_BAR(1);
1396 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
1397 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
1398 0);
1399 }
1400 if (progif & PCIP_STORAGE_IDE_MODESEC) {
1401 pci_add_map(pcib, b, s, f, PCIR_BAR(2), rl);
1402 pci_add_map(pcib, b, s, f, PCIR_BAR(3), rl);
1403 } else {
1404 rid = PCIR_BAR(2);
1405 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
1406 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
1407 0);
1408 rid = PCIR_BAR(3);
1409 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
1410 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
1411 0);
1412 }
1413 pci_add_map(pcib, b, s, f, PCIR_BAR(4), rl);
1414 pci_add_map(pcib, b, s, f, PCIR_BAR(5), rl);
1415}
1416#endif /* PCI_MAP_FIXUP */
1417
984263bc 1418static void
e126caf1 1419pci_add_resources(device_t pcib, device_t bus, device_t dev)
984263bc
MD
1420{
1421 struct pci_devinfo *dinfo = device_get_ivars(dev);
4a5a2d63 1422 pcicfgregs *cfg = &dinfo->cfg;
984263bc
MD
1423 struct resource_list *rl = &dinfo->resources;
1424 struct pci_quirk *q;
e126caf1
MD
1425 int b, i, f, s;
1426#if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */
1427 int irq;
1428#endif
984263bc 1429
e126caf1
MD
1430 b = cfg->bus;
1431 s = cfg->slot;
1432 f = cfg->func;
201eb0a7
TS
1433#ifdef PCI_MAP_FIXUP
1434 /* atapci devices in legacy mode need special map treatment */
1435 if ((pci_get_class(dev) == PCIC_STORAGE) &&
1436 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
d3d1ea7a
MD
1437 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
1438 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
1439 !pci_read_config(dev, PCIR_BAR(2), 4))) )
201eb0a7
TS
1440 pci_ata_maps(pcib, bus, dev, b, s, f, rl);
1441 else
1442#endif /* PCI_MAP_FIXUP */
1443 for (i = 0; i < cfg->nummaps;) {
1444 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl);
1445 }
984263bc
MD
1446
1447 for (q = &pci_quirks[0]; q->devid; q++) {
1448 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1449 && q->type == PCI_QUIRK_MAP_REG)
4a5a2d63 1450 pci_add_map(pcib, b, s, f, q->arg1, rl);
984263bc
MD
1451 }
1452
1453 if (cfg->intpin > 0 && cfg->intline != 255)
1454 resource_list_add(rl, SYS_RES_IRQ, 0,
1455 cfg->intline, cfg->intline, 1);
1456}
1457
e126caf1
MD
1458void
1459pci_add_children(device_t dev, int busno, size_t dinfo_size)
984263bc 1460{
e126caf1 1461#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
4a5a2d63 1462 device_t pcib = device_get_parent(dev);
e126caf1 1463 struct pci_devinfo *dinfo;
4a5a2d63 1464 int maxslots;
e126caf1
MD
1465 int s, f, pcifunchigh;
1466 uint8_t hdrtype;
1467
1468 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo));
984263bc 1469
4a5a2d63 1470 maxslots = PCIB_MAXSLOTS(pcib);
984263bc 1471
57e943f7 1472 for (s = 0; s <= maxslots; s++) {
e126caf1
MD
1473 pcifunchigh = 0;
1474 f = 0;
1475 hdrtype = REG(PCIR_HDRTYPE, 1);
1476 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1477 continue;
1478 if (hdrtype & PCIM_MFDEV)
1479 pcifunchigh = PCI_FUNCMAX;
5e658043 1480 for (f = 0; f <= pcifunchigh; f++) {
e126caf1 1481 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
984263bc 1482 if (dinfo != NULL) {
e126caf1 1483 pci_add_child(dev, dinfo);
984263bc
MD
1484 }
1485 }
1486 }
e126caf1
MD
1487#undef REG
1488}
1489
2581072f
MD
1490/*
1491 * The actual PCI child that we add has a NULL driver whos parent
1492 * device will be "pci". The child contains the ivars, not the parent.
1493 */
e126caf1
MD
1494void
1495pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1496{
1497 device_t pcib;
1498
1499 pcib = device_get_parent(bus);
1500 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1501 device_set_ivars(dinfo->cfg.dev, dinfo);
1502 pci_add_resources(pcib, bus, dinfo->cfg.dev);
1503 pci_print_verbose(dinfo);
984263bc
MD
1504}
1505
c01b8d84
MD
1506/*
1507 * Probe the PCI bus. Note: probe code is not supposed to add children
1508 * or call attach.
1509 */
984263bc 1510static int
4a5a2d63 1511pci_probe(device_t dev)
984263bc 1512{
984263bc 1513 device_set_desc(dev, "PCI bus");
4a5a2d63 1514
c01b8d84
MD
1515 /* Allow other subclasses to override this driver */
1516 return(-1000);
984263bc
MD
1517}
1518
e126caf1
MD
1519static int
1520pci_attach(device_t dev)
1521{
1522 int busno;
e4c9c0c8
MD
1523 int lunit = device_get_unit(dev);
1524
fef8985e
MD
1525 dev_ops_add(&pcic_ops, -1, lunit);
1526 make_dev(&pcic_ops, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit);
e126caf1
MD
1527
1528 /*
1529 * Since there can be multiple independantly numbered PCI
1530 * busses on some large alpha systems, we can't use the unit
1531 * number to decide what bus we are probing. We ask the parent
1532 * pcib what our bus number is.
2581072f
MD
1533 *
1534 * pcib_get_bus() must act on the pci bus device, not on the pci
1535 * device, because it uses badly hacked nexus-based ivars to
1536 * store and retrieve the physical bus number. XXX
e126caf1 1537 */
2581072f 1538 busno = pcib_get_bus(device_get_parent(dev));
e126caf1 1539 if (bootverbose)
ed1bd994 1540 device_printf(dev, "pci_attach() physical bus=%d\n", busno);
e126caf1
MD
1541
1542 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1543
1544 return (bus_generic_attach(dev));
1545}
1546
984263bc
MD
1547static int
1548pci_print_resources(struct resource_list *rl, const char *name, int type,
1549 const char *format)
1550{
1551 struct resource_list_entry *rle;
1552 int printed, retval;
1553
1554 printed = 0;
1555 retval = 0;
1556 /* Yes, this is kinda cheating */
1557 SLIST_FOREACH(rle, rl, link) {
1558 if (rle->type == type) {
1559 if (printed == 0)
85f8e2ea 1560 retval += kprintf(" %s ", name);
984263bc 1561 else if (printed > 0)
85f8e2ea 1562 retval += kprintf(",");
984263bc 1563 printed++;
85f8e2ea 1564 retval += kprintf(format, rle->start);
984263bc 1565 if (rle->count > 1) {
85f8e2ea
SW
1566 retval += kprintf("-");
1567 retval += kprintf(format, rle->start +
984263bc
MD
1568 rle->count - 1);
1569 }
1570 }
1571 }
1572 return retval;
1573}
1574
e126caf1 1575int
984263bc
MD
1576pci_print_child(device_t dev, device_t child)
1577{
1578 struct pci_devinfo *dinfo;
1579 struct resource_list *rl;
1580 pcicfgregs *cfg;
1581 int retval = 0;
1582
1583 dinfo = device_get_ivars(child);
1584 cfg = &dinfo->cfg;
1585 rl = &dinfo->resources;
1586
1587 retval += bus_print_child_header(dev, child);
1588
1589 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1590 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1591 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1592 if (device_get_flags(dev))
85f8e2ea 1593 retval += kprintf(" flags %#x", device_get_flags(dev));
984263bc 1594
85f8e2ea 1595 retval += kprintf(" at device %d.%d", pci_get_slot(child),
984263bc
MD
1596 pci_get_function(child));
1597
1598 retval += bus_print_child_footer(dev, child);
1599
1600 return (retval);
1601}
1602
e126caf1 1603void
984263bc
MD
1604pci_probe_nomatch(device_t dev, device_t child)
1605{
1606 struct pci_devinfo *dinfo;
1607 pcicfgregs *cfg;
1608 const char *desc;
1609 int unknown;
1610
1611 unknown = 0;
1612 dinfo = device_get_ivars(child);
1613 cfg = &dinfo->cfg;
1614 desc = pci_ata_match(child);
1615 if (!desc) desc = pci_usb_match(child);
1616 if (!desc) desc = pci_vga_match(child);
27c23c6b 1617 if (!desc) desc = pci_chip_match(child);
984263bc
MD
1618 if (!desc) {
1619 desc = "unknown card";
1620 unknown++;
1621 }
1622 device_printf(dev, "<%s>", desc);
1623 if (bootverbose || unknown) {
85f8e2ea 1624 kprintf(" (vendor=0x%04x, dev=0x%04x)",
984263bc
MD
1625 cfg->vendor,
1626 cfg->device);
1627 }
85f8e2ea 1628 kprintf(" at %d.%d",
984263bc
MD
1629 pci_get_slot(child),
1630 pci_get_function(child));
1631 if (cfg->intpin > 0 && cfg->intline != 255) {
85f8e2ea 1632 kprintf(" irq %d", cfg->intline);
984263bc 1633 }
85f8e2ea 1634 kprintf("\n");
984263bc
MD
1635
1636 return;
1637}
1638
22457186 1639int
4a5a2d63 1640pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
984263bc
MD
1641{
1642 struct pci_devinfo *dinfo;
1643 pcicfgregs *cfg;
1644
1645 dinfo = device_get_ivars(child);
1646 cfg = &dinfo->cfg;
1647
1648 switch (which) {
1649 case PCI_IVAR_SUBVENDOR:
1650 *result = cfg->subvendor;
1651 break;
1652 case PCI_IVAR_SUBDEVICE:
1653 *result = cfg->subdevice;
1654 break;
1655 case PCI_IVAR_VENDOR:
1656 *result = cfg->vendor;
1657 break;
1658 case PCI_IVAR_DEVICE:
1659 *result = cfg->device;
1660 break;
1661 case PCI_IVAR_DEVID:
1662 *result = (cfg->device << 16) | cfg->vendor;
1663 break;
1664 case PCI_IVAR_CLASS:
1665 *result = cfg->baseclass;
1666 break;
1667 case PCI_IVAR_SUBCLASS:
1668 *result = cfg->subclass;
1669 break;
1670 case PCI_IVAR_PROGIF:
1671 *result = cfg->progif;
1672 break;
1673 case PCI_IVAR_REVID:
1674 *result = cfg->revid;
1675 break;
1676 case PCI_IVAR_INTPIN:
1677 *result = cfg->intpin;
1678 break;
1679 case PCI_IVAR_IRQ:
1680 *result = cfg->intline;
1681 break;
1682 case PCI_IVAR_BUS:
1683 *result = cfg->bus;
1684 break;
1685 case PCI_IVAR_SLOT:
1686 *result = cfg->slot;
1687 break;
1688 case PCI_IVAR_FUNCTION:
1689 *result = cfg->func;
1690 break;
1691 case PCI_IVAR_SECONDARYBUS:
1692 *result = cfg->secondarybus;
1693 break;
1694 case PCI_IVAR_SUBORDINATEBUS:
1695 *result = cfg->subordinatebus;
1696 break;
f72d3d23
JS
1697 case PCI_IVAR_ETHADDR:
1698 /*
1699 * The generic accessor doesn't deal with failure, so
1700 * we set the return value, then return an error.
1701 */
1702 *result = NULL;
1703 return (EINVAL);
984263bc
MD
1704 default:
1705 return ENOENT;
1706 }
1707 return 0;
1708}
1709
22457186 1710int
984263bc
MD
1711pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1712{
1713 struct pci_devinfo *dinfo;
1714 pcicfgregs *cfg;
1715
1716 dinfo = device_get_ivars(child);
1717 cfg = &dinfo->cfg;
1718
1719 switch (which) {
1720 case PCI_IVAR_SUBVENDOR:
1721 case PCI_IVAR_SUBDEVICE:
1722 case PCI_IVAR_VENDOR:
1723 case PCI_IVAR_DEVICE:
1724 case PCI_IVAR_DEVID:
1725 case PCI_IVAR_CLASS:
1726 case PCI_IVAR_SUBCLASS:
1727 case PCI_IVAR_PROGIF:
1728 case PCI_IVAR_REVID:
1729 case PCI_IVAR_INTPIN:
1730 case PCI_IVAR_IRQ:
1731 case PCI_IVAR_BUS:
1732 case PCI_IVAR_SLOT:
1733 case PCI_IVAR_FUNCTION:
f72d3d23 1734 case PCI_IVAR_ETHADDR:
984263bc
MD
1735 return EINVAL; /* disallow for now */
1736
1737 case PCI_IVAR_SECONDARYBUS:
1738 cfg->secondarybus = value;
1739 break;
1740 case PCI_IVAR_SUBORDINATEBUS:
1741 cfg->subordinatebus = value;
1742 break;
1743 default:
1744 return ENOENT;
1745 }
1746 return 0;
1747}
1748
201eb0a7
TS
1749#ifdef PCI_MAP_FIXUP
1750static struct resource *
1751pci_alloc_map(device_t dev, device_t child, int type, int *rid, u_long start,
1752 u_long end, u_long count, u_int flags)
1753{
1754 struct pci_devinfo *dinfo = device_get_ivars(child);
1755 struct resource_list *rl = &dinfo->resources;
1756 struct resource_list_entry *rle;
1757 struct resource *res;
1758 uint32_t map, testval;
1759 int mapsize;
1760
1761 /*
1762 * Weed out the bogons, and figure out how large the BAR/map
1763 * is. BARs that read back 0 here are bogus and unimplemented.
1764 *
1765 * Note: atapci in legacy mode are special and handled elsewhere
1766 * in the code. If you have an atapci device in legacy mode and
1767 * it fails here, that other code is broken.
1768 */
1769 res = NULL;
1770 map = pci_read_config(child, *rid, 4);
1771 pci_write_config(child, *rid, 0xffffffff, 4);
1772 testval = pci_read_config(child, *rid, 4);
1773 if (pci_mapbase(testval) == 0)
1774 goto out;
1775 if (pci_maptype(testval) & PCI_MAPMEM) {
1776 if (type != SYS_RES_MEMORY) {
1777 if (bootverbose)
1778 device_printf(dev, "child %s requested type %d"
1779 " for rid %#x, but the BAR says "
1780 "it is a memio\n",
1781 device_get_nameunit(child), type,
1782 *rid);
1783 goto out;
1784 }
1785 } else {
1786 if (type != SYS_RES_IOPORT) {
1787 if (bootverbose)
1788 device_printf(dev, "child %s requested type %d"
1789 " for rid %#x, but the BAR says "
1790 "it is an ioport\n",
1791 device_get_nameunit(child), type,
1792 *rid);
1793 goto out;
1794 }
1795 }
1796 /*
1797 * For real BARs, we need to override the size that
1798 * the driver requests, because that's what the BAR
1799 * actually uses and we would otherwise have a
1800 * situation where we might allocate the excess to
1801 * another driver, which won't work.
1802 */
1803 mapsize = pci_mapsize(testval);
1804 count = 1 << mapsize;
1805 if (RF_ALIGNMENT(flags) < mapsize)
1806 flags = (flags & ~RF_ALIGNMENT_MASK) |
1807 RF_ALIGNMENT_LOG2(mapsize);
1808 /*
1809 * Allocate enough resource, and then write back the
1810 * appropriate BAR for that resource.
1811 */
1812 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
1813 start, end, count, flags);
1814 if (res == NULL) {
1815 device_printf(child, "%#lx bytes at rid %#x res %d failed "
1816 "(%#lx, %#lx)\n", count, *rid, type, start, end);
1817 goto out;
1818 }
1819 resource_list_add(rl, type, *rid, start, end, count);
1820 rle = resource_list_find(rl, type, *rid);
1821 if (rle == NULL)
1822 panic("pci_alloc_map: unexpectedly can't find resource.");
1823 rle->res = res;
1824 rle->start = rman_get_start(res);
1825 rle->end = rman_get_end(res);
1826 rle->count = count;
1827 if (bootverbose)
1828 device_printf(child, "lazy allocation of %#lx bytes rid %#x "
1829 "type %d at %#lx\n", count, *rid, type,
1830 rman_get_start(res));
1831 map = rman_get_start(res);
1832out:;
1833 pci_write_config(child, *rid, map, 4);
1834 return res;
1835}
1836#endif /* PCI_MAP_FIXUP */
1837
261fa16d 1838struct resource *
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1839pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1840 u_long start, u_long end, u_long count, u_int flags)
1841{
1842 struct pci_devinfo *dinfo = device_get_ivars(child);
1843 struct resource_list *rl = &dinfo->resources;
201eb0a7
TS
1844#ifdef PCI_MAP_FIXUP
1845 struct resource_list_entry *rle;
1846#endif /* PCI_MAP_FIXUP */
984263bc 1847 pcicfgregs *cfg = &dinfo->cfg;
de67e43b 1848
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1849 /*
1850 * Perform lazy resource allocation
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1851 */
1852 if (device_get_parent(child) == dev) {
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JS
1853 switch (type) {
1854 case SYS_RES_IRQ:
1855#ifdef __i386__
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1856 /*
1857 * If device doesn't have an interrupt routed, and is
1858 * deserving of an interrupt, try to assign it one.
1859 */
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1860 if ((cfg->intline == 255 || cfg->intline == 0) &&
1861 (cfg->intpin != 0) &&
1862 (start == 0) && (end == ~0UL)) {
1863 cfg->intline = PCIB_ROUTE_INTERRUPT(
1864 device_get_parent(dev), child,
1865 cfg->intpin);
1866 if (cfg->intline != 255) {
1867 pci_write_config(child, PCIR_INTLINE,
1868 cfg->intline, 1);
1869 resource_list_add(rl, SYS_RES_IRQ, 0,
1870 cfg->intline, cfg->intline, 1);
1871 }
1872 }
820c1612 1873 break;
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JS
1874#endif
1875 case SYS_RES_IOPORT:
201eb0a7 1876 /* FALLTHROUGH */
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1877 case SYS_RES_MEMORY:
1878 if (*rid < PCIR_BAR(cfg->nummaps)) {
1879 /*
1880 * Enable the I/O mode. We should
1881 * also be assigning resources too
1882 * when none are present. The
1883 * resource_list_alloc kind of sorta does
1884 * this...
1885 */
1886 if (PCI_ENABLE_IO(dev, child, type))
1887 return (NULL);
984263bc 1888 }
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1889#ifdef PCI_MAP_FIXUP
1890 rle = resource_list_find(rl, type, *rid);
1891 if (rle == NULL)
1892 return pci_alloc_map(dev, child, type, rid,
1893 start, end, count, flags);
1894#endif /* PCI_MAP_FIXUP */
820c1612 1895 break;
984263bc 1896 }
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1897#ifdef PCI_MAP_FIXUP
1898 /*
1899 * If we've already allocated the resource, then
1900 * return it now. But first we may need to activate
1901 * it, since we don't allocate the resource as active
1902 * above. Normally this would be done down in the
1903 * nexus, but since we short-circuit that path we have
1904 * to do its job here. Not sure if we should free the
1905 * resource if it fails to activate.
1906 *
1907 * Note: this also finds and returns resources for
1908 * atapci devices in legacy mode as allocated in
1909 * pci_ata_maps().
1910 */
1911 rle = resource_list_find(rl, type, *rid);
1912 if (rle != NULL && rle->res != NULL) {
1913 if (bootverbose)
1914 device_printf(child, "reserved %#lx bytes for "
1915 "rid %#x type %d at %#lx\n",
1916 rman_get_size(rle->res), *rid,
1917 type, rman_get_start(rle->res));
1918 if ((flags & RF_ACTIVE) &&
1919 bus_generic_activate_resource(dev, child, type,
1920 *rid, rle->res) != 0)
1921 return NULL;
1922 return rle->res;
1923 }
1924#endif /* PCI_MAP_FIXUP */
984263bc 1925 }
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1926 return resource_list_alloc(rl, dev, child, type, rid,
1927 start, end, count, flags);
1928}
1929
1930static int
1931pci_release_resource(device_t dev, device_t child, int type, int rid,
1932 struct resource *r)
1933{
1934 struct pci_devinfo *dinfo = device_get_ivars(child);
1935 struct resource_list *rl = &dinfo->resources;
1936
1937 return resource_list_release(rl, dev, child, type, rid, r);
1938}
1939
1940static int
1941pci_set_resource(device_t dev, device_t child, int type, int rid,
1942 u_long start, u_long count)
1943{
1944 struct pci_devinfo *dinfo = device_get_ivars(child);
1945 struct resource_list *rl = &dinfo->resources;
1946
1947 resource_list_add(rl, type, rid, start, start + count - 1, count);
1948 return 0;
1949}
1950
1951static int
1952pci_get_resource(device_t dev, device_t child, int type, int rid,
1953 u_long *startp, u_long *countp)
1954{
1955 struct pci_devinfo *dinfo = device_get_ivars(child);
1956 struct resource_list *rl = &dinfo->resources;
1957 struct resource_list_entry *rle;
1958
1959 rle = resource_list_find(rl, type, rid);
1960 if (!rle)
1961 return ENOENT;
1962
1963 if (startp)
1964 *startp = rle->start;
1965 if (countp)
1966 *countp = rle->count;
1967
1968 return 0;
1969}
1970
e126caf1 1971void
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1972pci_delete_resource(device_t dev, device_t child, int type, int rid)
1973{
85f8e2ea 1974 kprintf("pci_delete_resource: PCI resources can not be deleted\n");
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MD
1975}
1976
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1977struct resource_list *
1978pci_get_resource_list (device_t dev, device_t child)
1979{
b0486c83 1980 struct pci_devinfo *dinfo = device_get_ivars(child);
e126caf1 1981
b0486c83 1982 if (dinfo == NULL)
e126caf1 1983 return (NULL);
b0486c83 1984 return (&dinfo->resources);
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MD
1985}
1986
1987u_int32_t
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1988pci_read_config_method(device_t dev, device_t child, int reg, int width)
1989{
1990 struct pci_devinfo *dinfo = device_get_ivars(child);
1991 pcicfgregs *cfg = &dinfo->cfg;
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JS
1992
1993 return PCIB_READ_CONFIG(device_get_parent(dev),
1994 cfg->bus, cfg->slot, cfg->func,
1995 reg, width);
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1996}
1997
e126caf1 1998void
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1999pci_write_config_method(device_t dev, device_t child, int reg,
2000 u_int32_t val, int width)
2001{
2002 struct pci_devinfo *dinfo = device_get_ivars(child);
2003 pcicfgregs *cfg = &dinfo->cfg;
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2004
2005 PCIB_WRITE_CONFIG(device_get_parent(dev),
2006 cfg->bus, cfg->slot, cfg->func,
2007 reg, val, width);
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2008}
2009
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2010int
2011pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
2012 size_t buflen)
2013{
2014 struct pci_devinfo *dinfo;
2015
2016 dinfo = device_get_ivars(child);
f8c7a42d 2017 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
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2018 pci_get_function(child));
2019 return (0);
2020}
2021
2022int
2023pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
2024 size_t buflen)
2025{
2026 struct pci_devinfo *dinfo;
2027 pcicfgregs *cfg;
2028
2029 dinfo = device_get_ivars(child);
2030 cfg = &dinfo->cfg;
f8c7a42d 2031 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
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2032 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
2033 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
2034 cfg->progif);
2035 return (0);
2036}
2037
2038int
2039pci_assign_interrupt_method(device_t dev, device_t child)
2040{
2041 struct pci_devinfo *dinfo = device_get_ivars(child);
2042 pcicfgregs *cfg = &dinfo->cfg;
2043
2044 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
2045 cfg->intpin));
2046}
2047
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2048static int
2049pci_modevent(module_t mod, int what, void *arg)
2050{
2051 switch (what) {
2052 case MOD_LOAD:
2053 STAILQ_INIT(&pci_devq);
2054 break;
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2055 case MOD_UNLOAD:
2056 break;
2057 }
2058
2059 return 0;
2060}
2061
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2062int
2063pci_resume(device_t dev)
2064{
2065 int numdevs;
2066 int i;
2067 device_t *children;
2068 device_t child;
2069 struct pci_devinfo *dinfo;
2070 pcicfgregs *cfg;
2071
2072 device_get_children(dev, &children, &numdevs);
2073
2074 for (i = 0; i < numdevs; i++) {
2075 child = children[i];
2076
2077 dinfo = device_get_ivars(child);
2078 cfg = &dinfo->cfg;
2079 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2080 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
2081 if (PCI_INTERRUPT_VALID(cfg->intline)) {
2082 pci_write_config(child, PCIR_INTLINE,
2083 cfg->intline, 1);
2084 }
2085 }
2086 }
2087
efda3bd0 2088 kfree(children, M_TEMP);
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2089
2090 return (bus_generic_resume(dev));
2091}
2092
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2093static device_method_t pci_methods[] = {
2094 /* Device interface */
4a5a2d63 2095 DEVMETHOD(device_probe, pci_probe),
e126caf1 2096 DEVMETHOD(device_attach, pci_attach),
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2097 DEVMETHOD(device_shutdown, bus_generic_shutdown),
2098 DEVMETHOD(device_suspend, bus_generic_suspend),
e126caf1 2099 DEVMETHOD(device_resume, pci_resume),
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2100
2101 /* Bus interface */
2102 DEVMETHOD(bus_print_child, pci_print_child),
2103 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
2104 DEVMETHOD(bus_read_ivar, pci_read_ivar),
2105 DEVMETHOD(bus_write_ivar, pci_write_ivar),
2106 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
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2107 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
2108 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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2109
2110 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
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2111 DEVMETHOD(bus_set_resource, pci_set_resource),
2112 DEVMETHOD(bus_get_resource, pci_get_resource),
2113 DEVMETHOD(bus_delete_resource, pci_delete_resource),
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2114 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
2115 DEVMETHOD(bus_release_resource, pci_release_resource),
2116 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
2117 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
2118 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
2119 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
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MD
2120
2121 /* PCI interface */
2122 DEVMETHOD(pci_read_config, pci_read_config_method),
2123 DEVMETHOD(pci_write_config, pci_write_config_method),
2124 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
2125 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
2126 DEVMETHOD(pci_enable_io, pci_enable_io_method),
2127 DEVMETHOD(pci_disable_io, pci_disable_io_method),
2128 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
2129 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
e126caf1 2130 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
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MD
2131
2132 { 0, 0 }
2133};
2134
3aef8050 2135driver_t pci_driver = {
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MD
2136 "pci",
2137 pci_methods,
2138 1, /* no softc */
2139};
2140
2141DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
261fa16d 2142MODULE_VERSION(pci, 1);