If we boot verbose, then print out 'interesting' CAM errors that otherwise
[dragonfly.git] / sys / bus / pci / pci.c
CommitLineData
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1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
0c78fe3f 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.43 2007/11/24 03:42:24 sephe Exp $
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28 *
29 */
30
31#include "opt_bus.h"
32#include "opt_pci.h"
33
dc5a7bd2 34#include "opt_compat_oldpci.h"
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35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/malloc.h>
39#include <sys/module.h>
40#include <sys/fcntl.h>
41#include <sys/conf.h>
42#include <sys/kernel.h>
43#include <sys/queue.h>
44#include <sys/types.h>
45#include <sys/buf.h>
46
47#include <vm/vm.h>
48#include <vm/pmap.h>
49#include <vm/vm_extern.h>
50
51#include <sys/bus.h>
984263bc 52#include <sys/rman.h>
97359a5b 53#include <machine/smp.h>
984263bc 54#ifdef __i386__
bbca97bc 55#include <bus/pci/i386/pci_cfgreg.h>
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56#endif
57
dc5a7bd2 58#include <sys/pciio.h>
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59#include "pcireg.h"
60#include "pcivar.h"
22457186 61#include "pci_private.h"
984263bc 62
4a5a2d63
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63#include "pcib_if.h"
64
e126caf1 65devclass_t pci_devclass;
2581072f 66const char *pcib_owner;
dc5a7bd2 67
4a5a2d63 68static void pci_read_extcap(device_t dev, pcicfgregs *cfg);
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69
70struct pci_quirk {
71 u_int32_t devid; /* Vendor/device of the card */
72 int type;
3e4db402 73#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
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74 int arg1;
75 int arg2;
76};
77
78struct pci_quirk pci_quirks[] = {
79 /*
80 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
81 */
82 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
83 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
f1f0bfb2
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84 /* As does the Serverworks OSB4 (the SMBus mapping register) */
85 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
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86
87 { 0 }
88};
89
90/* map register information */
91#define PCI_MAPMEM 0x01 /* memory map */
92#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
93#define PCI_MAPPORT 0x04 /* port map */
94
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95static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
96u_int32_t pci_numdevs = 0;
97static u_int32_t pci_generation = 0;
98
99device_t
100pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func)
101{
102 struct pci_devinfo *dinfo;
103
104 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
105 if ((dinfo->cfg.bus == bus) &&
106 (dinfo->cfg.slot == slot) &&
107 (dinfo->cfg.func == func)) {
108 return (dinfo->cfg.dev);
109 }
110 }
111
112 return (NULL);
113}
114
115device_t
116pci_find_device (u_int16_t vendor, u_int16_t device)
117{
118 struct pci_devinfo *dinfo;
119
120 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
121 if ((dinfo->cfg.vendor == vendor) &&
122 (dinfo->cfg.device == device)) {
123 return (dinfo->cfg.dev);
124 }
125 }
126
127 return (NULL);
128}
129
130/* return base address of memory or port map */
131
132static u_int32_t
133pci_mapbase(unsigned mapreg)
134{
135 int mask = 0x03;
136 if ((mapreg & 0x01) == 0)
137 mask = 0x0f;
138 return (mapreg & ~mask);
139}
140
141/* return map type of memory or port map */
142
143static int
144pci_maptype(unsigned mapreg)
145{
146 static u_int8_t maptype[0x10] = {
147 PCI_MAPMEM, PCI_MAPPORT,
148 PCI_MAPMEM, 0,
149 PCI_MAPMEM, PCI_MAPPORT,
150 0, 0,
151 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
152 PCI_MAPMEM|PCI_MAPMEMP, 0,
153 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
154 0, 0,
155 };
156
157 return maptype[mapreg & 0x0f];
158}
159
160/* return log2 of map size decoded for memory or port map */
161
162static int
163pci_mapsize(unsigned testval)
164{
165 int ln2size;
166
167 testval = pci_mapbase(testval);
168 ln2size = 0;
169 if (testval != 0) {
170 while ((testval & 1) == 0)
171 {
172 ln2size++;
173 testval >>= 1;
174 }
175 }
176 return (ln2size);
177}
178
179/* return log2 of address range supported by map register */
180
181static int
182pci_maprange(unsigned mapreg)
183{
184 int ln2range = 0;
185 switch (mapreg & 0x07) {
186 case 0x00:
187 case 0x01:
188 case 0x05:
189 ln2range = 32;
190 break;
191 case 0x02:
192 ln2range = 20;
193 break;
194 case 0x04:
195 ln2range = 64;
196 break;
197 }
198 return (ln2range);
199}
200
201/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
202
203static void
204pci_fixancient(pcicfgregs *cfg)
205{
206 if (cfg->hdrtype != 0)
207 return;
208
209 /* PCI to PCI bridges use header type 1 */
210 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
211 cfg->hdrtype = 1;
212}
213
214/* read config data specific to header type 1 device (PCI to PCI bridge) */
215
216static void *
4a5a2d63 217pci_readppb(device_t pcib, int b, int s, int f)
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218{
219 pcih1cfgregs *p;
220
efda3bd0 221 p = kmalloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
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222 if (p == NULL)
223 return (NULL);
224
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225 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
226 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
984263bc 227
4a5a2d63 228 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
984263bc 229
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230 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
231 PCIR_IOBASEH_1, 2),
232 PCIB_READ_CONFIG(pcib, b, s, f,
233 PCIR_IOBASEL_1, 1));
234 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
235 PCIR_IOLIMITH_1, 2),
236 PCIB_READ_CONFIG(pcib, b, s, f,
237 PCIR_IOLIMITL_1, 1));
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238
239 p->membase = PCI_PPBMEMBASE (0,
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240 PCIB_READ_CONFIG(pcib, b, s, f,
241 PCIR_MEMBASE_1, 2));
984263bc 242 p->memlimit = PCI_PPBMEMLIMIT (0,
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243 PCIB_READ_CONFIG(pcib, b, s, f,
244 PCIR_MEMLIMIT_1, 2));
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245
246 p->pmembase = PCI_PPBMEMBASE (
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247 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
248 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
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249
250 p->pmemlimit = PCI_PPBMEMLIMIT (
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251 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
252 PCIR_PMLIMITH_1, 4),
253 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
254
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255 return (p);
256}
257
258/* read config data specific to header type 2 device (PCI to CardBus bridge) */
259
260static void *
4a5a2d63 261pci_readpcb(device_t pcib, int b, int s, int f)
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262{
263 pcih2cfgregs *p;
264
efda3bd0 265 p = kmalloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
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266 if (p == NULL)
267 return (NULL);
268
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269 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
270 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
984263bc 271
4a5a2d63 272 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
984263bc 273
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274 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
275 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
276 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
277 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
984263bc 278
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279 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
280 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
281 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
282 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
984263bc 283
4a5a2d63 284 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
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285 return p;
286}
287
288/* extract header type specific config data */
289
290static void
4a5a2d63 291pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
984263bc 292{
4a5a2d63 293#define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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294 switch (cfg->hdrtype) {
295 case 0:
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296 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
297 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
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298 cfg->nummaps = PCI_MAXMAPS_0;
299 break;
300 case 1:
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301 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
302 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
303 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
304 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
984263bc 305 cfg->nummaps = PCI_MAXMAPS_1;
4a5a2d63 306 cfg->hdrspec = pci_readppb(pcib, b, s, f);
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307 break;
308 case 2:
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309 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
310 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
311 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
312 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
984263bc 313 cfg->nummaps = PCI_MAXMAPS_2;
4a5a2d63 314 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
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315 break;
316 }
4a5a2d63 317#undef REG
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318}
319
320/* read configuration header into pcicfgrect structure */
321
22457186 322struct pci_devinfo *
c01b8d84 323pci_read_device(device_t pcib, int b, int s, int f, size_t size)
984263bc 324{
4a5a2d63 325#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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326
327 pcicfgregs *cfg = NULL;
328 struct pci_devinfo *devlist_entry;
329 struct devlist *devlist_head;
330
331 devlist_head = &pci_devq;
332
333 devlist_entry = NULL;
334
4a5a2d63 335 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
984263bc 336
efda3bd0 337 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
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338 if (devlist_entry == NULL)
339 return (NULL);
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340
341 cfg = &devlist_entry->cfg;
342
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343 cfg->bus = b;
344 cfg->slot = s;
345 cfg->func = f;
346 cfg->vendor = REG(PCIR_VENDOR, 2);
347 cfg->device = REG(PCIR_DEVICE, 2);
348 cfg->cmdreg = REG(PCIR_COMMAND, 2);
349 cfg->statreg = REG(PCIR_STATUS, 2);
350 cfg->baseclass = REG(PCIR_CLASS, 1);
351 cfg->subclass = REG(PCIR_SUBCLASS, 1);
352 cfg->progif = REG(PCIR_PROGIF, 1);
353 cfg->revid = REG(PCIR_REVID, 1);
e126caf1 354 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
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355 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
356 cfg->lattimer = REG(PCIR_LATTIMER, 1);
357 cfg->intpin = REG(PCIR_INTPIN, 1);
358 cfg->intline = REG(PCIR_INTLINE, 1);
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359
360#ifdef APIC_IO
97359a5b
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361 /*
362 * If using the APIC the intpin is probably wrong, since it
363 * is often setup by the BIOS with the PIC in mind.
364 */
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365 if (cfg->intpin != 0) {
366 int airq;
367
368 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
369 if (airq >= 0) {
370 /* PCI specific entry found in MP table */
371 if (airq != cfg->intline) {
372 undirect_pci_irq(cfg->intline);
373 cfg->intline = airq;
374 }
375 } else {
376 /*
377 * PCI interrupts might be redirected to the
378 * ISA bus according to some MP tables. Use the
379 * same methods as used by the ISA devices
380 * devices to find the proper IOAPIC int pin.
381 */
382 airq = isa_apic_irq(cfg->intline);
383 if ((airq >= 0) && (airq != cfg->intline)) {
384 /* XXX: undirect_pci_irq() ? */
385 undirect_isa_irq(cfg->intline);
386 cfg->intline = airq;
387 }
388 }
389 }
390#endif /* APIC_IO */
391
4a5a2d63
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392 cfg->mingnt = REG(PCIR_MINGNT, 1);
393 cfg->maxlat = REG(PCIR_MAXLAT, 1);
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394
395 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
396 cfg->hdrtype &= ~PCIM_MFDEV;
397
398 pci_fixancient(cfg);
4a5a2d63 399 pci_hdrtypedata(pcib, b, s, f, cfg);
0c78fe3f 400 pci_read_extcap(pcib, cfg);
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401
402 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
403
404 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
405 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
406 devlist_entry->conf.pc_sel.pc_func = cfg->func;
407 devlist_entry->conf.pc_hdr = cfg->hdrtype;
408
409 devlist_entry->conf.pc_subvendor = cfg->subvendor;
410 devlist_entry->conf.pc_subdevice = cfg->subdevice;
411 devlist_entry->conf.pc_vendor = cfg->vendor;
412 devlist_entry->conf.pc_device = cfg->device;
413
414 devlist_entry->conf.pc_class = cfg->baseclass;
415 devlist_entry->conf.pc_subclass = cfg->subclass;
416 devlist_entry->conf.pc_progif = cfg->progif;
417 devlist_entry->conf.pc_revid = cfg->revid;
418
419 pci_numdevs++;
420 pci_generation++;
421 }
422 return (devlist_entry);
423#undef REG
424}
425
426static void
4a5a2d63 427pci_read_extcap(device_t pcib, pcicfgregs *cfg)
984263bc 428{
4a5a2d63 429#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
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430 int ptr, nextptr, ptrptr;
431
0c78fe3f
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432 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
433 /* No capabilities */
434 return;
435 }
436
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437 switch (cfg->hdrtype) {
438 case 0:
81c29ce4
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439 case 1:
440 ptrptr = PCIR_CAP_PTR;
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441 break;
442 case 2:
81c29ce4 443 ptrptr = PCIR_CAP_PTR_2;
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444 break;
445 default:
0c78fe3f 446 return; /* No capabilities support */
984263bc 447 }
0c78fe3f 448 nextptr = REG(ptrptr, 1);
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449
450 /*
451 * Read capability entries.
452 */
0c78fe3f
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453 for (;;) {
454 /* "Next pointer" is only one byte */
455 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
456
984263bc 457 /* Sanity check */
0c78fe3f
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458 if (nextptr & 0x3) {
459 /*
460 * PCI local bus spec 3.0:
461 *
462 * "... The bottom two bits of all pointers are
463 * reserved and must be implemented as 00b
464 * although software must mask them to allow
465 * for future uses of these bits ..."
466 */
467 if (bootverbose) {
468 kprintf("Illegal PCI extended capability "
469 "offset, adjust 0x%02x -> 0x%02x\n",
470 nextptr, nextptr & ~0x3);
471 }
472 nextptr &= ~0x3;
473 }
474
475 if (nextptr < 0x40) {
476 if (nextptr != 0) {
477 kprintf("Illegal PCI extended capability "
478 "offset 0x%02x", nextptr);
479 }
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480 return;
481 }
0c78fe3f 482
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483 /* Find the next entry */
484 ptr = nextptr;
485 nextptr = REG(ptr + 1, 1);
486
487 /* Process this entry */
488 switch (REG(ptr, 1)) {
81c29ce4 489 case PCIY_PMG: /* PCI power management */
1f7d9fe0
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490 if (cfg->pmgt.pp_cap == 0) {
491 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
492
493 pmgt->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
494 pmgt->pp_status = ptr + PCIR_POWER_STATUS;
495 pmgt->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
984263bc 496 if ((nextptr - ptr) > PCIR_POWER_DATA)
1f7d9fe0 497 pmgt->pp_data = ptr + PCIR_POWER_DATA;
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498 }
499 break;
500 default:
501 break;
502 }
503 }
504#undef REG
505}
506
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507/* free pcicfgregs structure and all depending data structures */
508
22457186 509int
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510pci_freecfg(struct pci_devinfo *dinfo)
511{
512 struct devlist *devlist_head;
513
514 devlist_head = &pci_devq;
515
516 if (dinfo->cfg.hdrspec != NULL)
efda3bd0 517 kfree(dinfo->cfg.hdrspec, M_DEVBUF);
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518 /* XXX this hasn't been tested */
519 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
efda3bd0 520 kfree(dinfo, M_DEVBUF);
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521
522 /* increment the generation count */
523 pci_generation++;
524
525 /* we're losing one device */
526 pci_numdevs--;
527 return (0);
528}
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529
530
531/*
532 * PCI power manangement
533 */
e126caf1 534int
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535pci_set_powerstate_method(device_t dev, device_t child, int state)
536{
537 struct pci_devinfo *dinfo = device_get_ivars(child);
538 pcicfgregs *cfg = &dinfo->cfg;
1f7d9fe0 539 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
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540 u_int16_t status;
541 int result;
542
1f7d9fe0
SZ
543 if (pmgt->pp_cap != 0) {
544 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2) & ~PCIM_PSTAT_DMASK;
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545 result = 0;
546 switch (state) {
547 case PCI_POWERSTATE_D0:
548 status |= PCIM_PSTAT_D0;
549 break;
550 case PCI_POWERSTATE_D1:
1f7d9fe0 551 if (pmgt->pp_cap & PCIM_PCAP_D1SUPP) {
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552 status |= PCIM_PSTAT_D1;
553 } else {
554 result = EOPNOTSUPP;
555 }
556 break;
557 case PCI_POWERSTATE_D2:
1f7d9fe0 558 if (pmgt->pp_cap & PCIM_PCAP_D2SUPP) {
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559 status |= PCIM_PSTAT_D2;
560 } else {
561 result = EOPNOTSUPP;
562 }
563 break;
564 case PCI_POWERSTATE_D3:
565 status |= PCIM_PSTAT_D3;
566 break;
567 default:
568 result = EINVAL;
569 }
570 if (result == 0)
1f7d9fe0 571 PCI_WRITE_CONFIG(dev, child, pmgt->pp_status, status, 2);
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572 } else {
573 result = ENXIO;
574 }
575 return(result);
576}
577
e126caf1 578int
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579pci_get_powerstate_method(device_t dev, device_t child)
580{
581 struct pci_devinfo *dinfo = device_get_ivars(child);
582 pcicfgregs *cfg = &dinfo->cfg;
1f7d9fe0 583 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
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584 u_int16_t status;
585 int result;
586
1f7d9fe0
SZ
587 if (pmgt->pp_cap != 0) {
588 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2);
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589 switch (status & PCIM_PSTAT_DMASK) {
590 case PCIM_PSTAT_D0:
591 result = PCI_POWERSTATE_D0;
592 break;
593 case PCIM_PSTAT_D1:
594 result = PCI_POWERSTATE_D1;
595 break;
596 case PCIM_PSTAT_D2:
597 result = PCI_POWERSTATE_D2;
598 break;
599 case PCIM_PSTAT_D3:
600 result = PCI_POWERSTATE_D3;
601 break;
602 default:
603 result = PCI_POWERSTATE_UNKNOWN;
604 break;
605 }
606 } else {
607 /* No support, device is always at D0 */
608 result = PCI_POWERSTATE_D0;
609 }
610 return(result);
611}
612
613/*
614 * Some convenience functions for PCI device drivers.
615 */
616
617static __inline void
618pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
619{
620 u_int16_t command;
621
622 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
623 command |= bit;
624 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
625}
626
627static __inline void
628pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
629{
630 u_int16_t command;
631
632 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
633 command &= ~bit;
634 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
635}
636
e126caf1 637int
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638pci_enable_busmaster_method(device_t dev, device_t child)
639{
640 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 641 return(0);
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MD
642}
643
e126caf1 644int
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645pci_disable_busmaster_method(device_t dev, device_t child)
646{
647 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 648 return(0);
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649}
650
e126caf1 651int
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652pci_enable_io_method(device_t dev, device_t child, int space)
653{
e126caf1
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654 uint16_t command;
655 uint16_t bit;
656 char *error;
657
658 bit = 0;
659 error = NULL;
660
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661 switch(space) {
662 case SYS_RES_IOPORT:
e126caf1
MD
663 bit = PCIM_CMD_PORTEN;
664 error = "port";
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MD
665 break;
666 case SYS_RES_MEMORY:
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667 bit = PCIM_CMD_MEMEN;
668 error = "memory";
984263bc 669 break;
e126caf1
MD
670 default:
671 return(EINVAL);
984263bc 672 }
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MD
673 pci_set_command_bit(dev, child, bit);
674 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
675 if (command & bit)
676 return(0);
677 device_printf(child, "failed to enable %s mapping!\n", error);
678 return(ENXIO);
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MD
679}
680
e126caf1 681int
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682pci_disable_io_method(device_t dev, device_t child, int space)
683{
e126caf1
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684 uint16_t command;
685 uint16_t bit;
686 char *error;
687
688 bit = 0;
689 error = NULL;
690
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691 switch(space) {
692 case SYS_RES_IOPORT:
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693 bit = PCIM_CMD_PORTEN;
694 error = "port";
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695 break;
696 case SYS_RES_MEMORY:
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697 bit = PCIM_CMD_MEMEN;
698 error = "memory";
984263bc 699 break;
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700 default:
701 return (EINVAL);
984263bc 702 }
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703 pci_clear_command_bit(dev, child, bit);
704 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
705 if (command & bit) {
706 device_printf(child, "failed to disable %s mapping!\n", error);
707 return (ENXIO);
708 }
709 return (0);
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710}
711
712/*
713 * This is the user interface to PCI configuration space.
714 */
715
716static int
fef8985e 717pci_open(struct dev_open_args *ap)
984263bc 718{
fef8985e 719 if ((ap->a_oflags & FWRITE) && securelevel > 0) {
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720 return EPERM;
721 }
722 return 0;
723}
724
725static int
fef8985e 726pci_close(struct dev_close_args *ap)
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MD
727{
728 return 0;
729}
730
731/*
732 * Match a single pci_conf structure against an array of pci_match_conf
733 * structures. The first argument, 'matches', is an array of num_matches
734 * pci_match_conf structures. match_buf is a pointer to the pci_conf
735 * structure that will be compared to every entry in the matches array.
736 * This function returns 1 on failure, 0 on success.
737 */
738static int
739pci_conf_match(struct pci_match_conf *matches, int num_matches,
740 struct pci_conf *match_buf)
741{
742 int i;
743
744 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
745 return(1);
746
747 for (i = 0; i < num_matches; i++) {
748 /*
749 * I'm not sure why someone would do this...but...
750 */
751 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
752 continue;
753
754 /*
755 * Look at each of the match flags. If it's set, do the
756 * comparison. If the comparison fails, we don't have a
757 * match, go on to the next item if there is one.
758 */
759 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
760 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
761 continue;
762
763 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
764 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
765 continue;
766
767 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
768 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
769 continue;
770
771 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
772 && (match_buf->pc_vendor != matches[i].pc_vendor))
773 continue;
774
775 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
776 && (match_buf->pc_device != matches[i].pc_device))
777 continue;
778
779 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
780 && (match_buf->pc_class != matches[i].pc_class))
781 continue;
782
783 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
784 && (match_buf->pd_unit != matches[i].pd_unit))
785 continue;
786
787 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
788 && (strncmp(matches[i].pd_name, match_buf->pd_name,
789 sizeof(match_buf->pd_name)) != 0))
790 continue;
791
792 return(0);
793 }
794
795 return(1);
796}
797
798/*
799 * Locate the parent of a PCI device by scanning the PCI devlist
800 * and return the entry for the parent.
801 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
802 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
803 */
804
805pcicfgregs *
806pci_devlist_get_parent(pcicfgregs *cfg)
807{
808 struct devlist *devlist_head;
809 struct pci_devinfo *dinfo;
810 pcicfgregs *bridge_cfg;
811 int i;
812
813 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
814
815 /* If the device is on PCI bus 0, look for the host */
816 if (cfg->bus == 0) {
817 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
818 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
819 bridge_cfg = &dinfo->cfg;
820 if (bridge_cfg->baseclass == PCIC_BRIDGE
821 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
822 && bridge_cfg->bus == cfg->bus) {
823 return bridge_cfg;
824 }
825 }
826 }
827
828 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
829 if (cfg->bus > 0) {
830 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
831 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
832 bridge_cfg = &dinfo->cfg;
833 if (bridge_cfg->baseclass == PCIC_BRIDGE
834 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
835 && bridge_cfg->secondarybus == cfg->bus) {
836 return bridge_cfg;
837 }
838 }
839 }
840
841 return NULL;
842}
843
844static int
fef8985e 845pci_ioctl(struct dev_ioctl_args *ap)
984263bc 846{
4a5a2d63 847 device_t pci, pcib;
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MD
848 struct pci_io *io;
849 const char *name;
850 int error;
851
fef8985e 852 if (!(ap->a_fflag & FWRITE))
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853 return EPERM;
854
fef8985e 855 switch(ap->a_cmd) {
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MD
856 case PCIOCGETCONF:
857 {
858 struct pci_devinfo *dinfo;
859 struct pci_conf_io *cio;
860 struct devlist *devlist_head;
861 struct pci_match_conf *pattern_buf;
862 int num_patterns;
863 size_t iolen;
864 int ionum, i;
865
fef8985e 866 cio = (struct pci_conf_io *)ap->a_data;
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867
868 num_patterns = 0;
869 dinfo = NULL;
870
871 /*
872 * Hopefully the user won't pass in a null pointer, but it
873 * can't hurt to check.
874 */
875 if (cio == NULL) {
876 error = EINVAL;
877 break;
878 }
879
880 /*
881 * If the user specified an offset into the device list,
882 * but the list has changed since they last called this
883 * ioctl, tell them that the list has changed. They will
884 * have to get the list from the beginning.
885 */
886 if ((cio->offset != 0)
887 && (cio->generation != pci_generation)){
888 cio->num_matches = 0;
889 cio->status = PCI_GETCONF_LIST_CHANGED;
890 error = 0;
891 break;
892 }
893
894 /*
895 * Check to see whether the user has asked for an offset
896 * past the end of our list.
897 */
898 if (cio->offset >= pci_numdevs) {
899 cio->num_matches = 0;
900 cio->status = PCI_GETCONF_LAST_DEVICE;
901 error = 0;
902 break;
903 }
904
905 /* get the head of the device queue */
906 devlist_head = &pci_devq;
907
908 /*
909 * Determine how much room we have for pci_conf structures.
910 * Round the user's buffer size down to the nearest
911 * multiple of sizeof(struct pci_conf) in case the user
912 * didn't specify a multiple of that size.
913 */
914 iolen = min(cio->match_buf_len -
915 (cio->match_buf_len % sizeof(struct pci_conf)),
916 pci_numdevs * sizeof(struct pci_conf));
917
918 /*
919 * Since we know that iolen is a multiple of the size of
920 * the pciconf union, it's okay to do this.
921 */
922 ionum = iolen / sizeof(struct pci_conf);
923
924 /*
925 * If this test is true, the user wants the pci_conf
926 * structures returned to match the supplied entries.
927 */
928 if ((cio->num_patterns > 0)
929 && (cio->pat_buf_len > 0)) {
930 /*
931 * pat_buf_len needs to be:
932 * num_patterns * sizeof(struct pci_match_conf)
933 * While it is certainly possible the user just
934 * allocated a large buffer, but set the number of
935 * matches correctly, it is far more likely that
936 * their kernel doesn't match the userland utility
937 * they're using. It's also possible that the user
938 * forgot to initialize some variables. Yes, this
939 * may be overly picky, but I hazard to guess that
940 * it's far more likely to just catch folks that
941 * updated their kernel but not their userland.
942 */
943 if ((cio->num_patterns *
944 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
945 /* The user made a mistake, return an error*/
946 cio->status = PCI_GETCONF_ERROR;
85f8e2ea 947 kprintf("pci_ioctl: pat_buf_len %d != "
984263bc
MD
948 "num_patterns (%d) * sizeof(struct "
949 "pci_match_conf) (%d)\npci_ioctl: "
950 "pat_buf_len should be = %d\n",
951 cio->pat_buf_len, cio->num_patterns,
952 (int)sizeof(struct pci_match_conf),
953 (int)sizeof(struct pci_match_conf) *
954 cio->num_patterns);
85f8e2ea 955 kprintf("pci_ioctl: do your headers match your "
984263bc
MD
956 "kernel?\n");
957 cio->num_matches = 0;
958 error = EINVAL;
959 break;
960 }
961
962 /*
963 * Check the user's buffer to make sure it's readable.
964 */
965 if (!useracc((caddr_t)cio->patterns,
966 cio->pat_buf_len, VM_PROT_READ)) {
85f8e2ea 967 kprintf("pci_ioctl: pattern buffer %p, "
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968 "length %u isn't user accessible for"
969 " READ\n", cio->patterns,
970 cio->pat_buf_len);
971 error = EACCES;
972 break;
973 }
974 /*
975 * Allocate a buffer to hold the patterns.
976 */
efda3bd0 977 pattern_buf = kmalloc(cio->pat_buf_len, M_TEMP,
984263bc
MD
978 M_WAITOK);
979 error = copyin(cio->patterns, pattern_buf,
980 cio->pat_buf_len);
981 if (error != 0)
982 break;
983 num_patterns = cio->num_patterns;
984
985 } else if ((cio->num_patterns > 0)
986 || (cio->pat_buf_len > 0)) {
987 /*
988 * The user made a mistake, spit out an error.
989 */
990 cio->status = PCI_GETCONF_ERROR;
991 cio->num_matches = 0;
85f8e2ea 992 kprintf("pci_ioctl: invalid GETCONF arguments\n");
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993 error = EINVAL;
994 break;
995 } else
996 pattern_buf = NULL;
997
998 /*
999 * Make sure we can write to the match buffer.
1000 */
1001 if (!useracc((caddr_t)cio->matches,
1002 cio->match_buf_len, VM_PROT_WRITE)) {
85f8e2ea 1003 kprintf("pci_ioctl: match buffer %p, length %u "
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MD
1004 "isn't user accessible for WRITE\n",
1005 cio->matches, cio->match_buf_len);
1006 error = EACCES;
1007 break;
1008 }
1009
1010 /*
1011 * Go through the list of devices and copy out the devices
1012 * that match the user's criteria.
1013 */
1014 for (cio->num_matches = 0, error = 0, i = 0,
1015 dinfo = STAILQ_FIRST(devlist_head);
1016 (dinfo != NULL) && (cio->num_matches < ionum)
1017 && (error == 0) && (i < pci_numdevs);
1018 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
1019
1020 if (i < cio->offset)
1021 continue;
1022
1023 /* Populate pd_name and pd_unit */
1024 name = NULL;
1025 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
1026 name = device_get_name(dinfo->cfg.dev);
1027 if (name) {
1028 strncpy(dinfo->conf.pd_name, name,
1029 sizeof(dinfo->conf.pd_name));
1030 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
1031 dinfo->conf.pd_unit =
1032 device_get_unit(dinfo->cfg.dev);
1033 }
1034
1035 if ((pattern_buf == NULL) ||
1036 (pci_conf_match(pattern_buf, num_patterns,
1037 &dinfo->conf) == 0)) {
1038
1039 /*
1040 * If we've filled up the user's buffer,
1041 * break out at this point. Since we've
1042 * got a match here, we'll pick right back
1043 * up at the matching entry. We can also
1044 * tell the user that there are more matches
1045 * left.
1046 */
1047 if (cio->num_matches >= ionum)
1048 break;
1049
1050 error = copyout(&dinfo->conf,
1051 &cio->matches[cio->num_matches],
1052 sizeof(struct pci_conf));
1053 cio->num_matches++;
1054 }
1055 }
1056
1057 /*
1058 * Set the pointer into the list, so if the user is getting
1059 * n records at a time, where n < pci_numdevs,
1060 */
1061 cio->offset = i;
1062
1063 /*
1064 * Set the generation, the user will need this if they make
1065 * another ioctl call with offset != 0.
1066 */
1067 cio->generation = pci_generation;
1068
1069 /*
1070 * If this is the last device, inform the user so he won't
1071 * bother asking for more devices. If dinfo isn't NULL, we
1072 * know that there are more matches in the list because of
1073 * the way the traversal is done.
1074 */
1075 if (dinfo == NULL)
1076 cio->status = PCI_GETCONF_LAST_DEVICE;
1077 else
1078 cio->status = PCI_GETCONF_MORE_DEVS;
1079
1080 if (pattern_buf != NULL)
efda3bd0 1081 kfree(pattern_buf, M_TEMP);
984263bc
MD
1082
1083 break;
1084 }
1085 case PCIOCREAD:
fef8985e 1086 io = (struct pci_io *)ap->a_data;
984263bc 1087 switch(io->pi_width) {
984263bc
MD
1088 case 4:
1089 case 2:
1090 case 1:
4a5a2d63
JS
1091 /*
1092 * Assume that the user-level bus number is
1093 * actually the pciN instance number. We map
1094 * from that to the real pcib+bus combination.
1095 */
1096 pci = devclass_get_device(pci_devclass,
1097 io->pi_sel.pc_bus);
1098 if (pci) {
2581072f
MD
1099 /*
1100 * pci is the pci device and may contain
1101 * several children (for each function code).
1102 * The governing pci bus is the parent to
1103 * the pci device.
1104 */
1105 int b;
1106
4a5a2d63 1107 pcib = device_get_parent(pci);
2581072f 1108 b = pcib_get_bus(pcib);
4a5a2d63
JS
1109 io->pi_data =
1110 PCIB_READ_CONFIG(pcib,
1111 b,
1112 io->pi_sel.pc_dev,
1113 io->pi_sel.pc_func,
1114 io->pi_reg,
1115 io->pi_width);
1116 error = 0;
1117 } else {
1118 error = ENODEV;
1119 }
984263bc
MD
1120 break;
1121 default:
1122 error = ENODEV;
1123 break;
1124 }
1125 break;
1126
1127 case PCIOCWRITE:
fef8985e 1128 io = (struct pci_io *)ap->a_data;
984263bc 1129 switch(io->pi_width) {
984263bc
MD
1130 case 4:
1131 case 2:
1132 case 1:
4a5a2d63
JS
1133 /*
1134 * Assume that the user-level bus number is
1135 * actually the pciN instance number. We map
1136 * from that to the real pcib+bus combination.
1137 */
1138 pci = devclass_get_device(pci_devclass,
1139 io->pi_sel.pc_bus);
1140 if (pci) {
2581072f
MD
1141 /*
1142 * pci is the pci device and may contain
1143 * several children (for each function code).
1144 * The governing pci bus is the parent to
1145 * the pci device.
1146 */
1147 int b;
1148
4a5a2d63 1149 pcib = device_get_parent(pci);
2581072f 1150 b = pcib_get_bus(pcib);
4a5a2d63
JS
1151 PCIB_WRITE_CONFIG(pcib,
1152 b,
1153 io->pi_sel.pc_dev,
1154 io->pi_sel.pc_func,
1155 io->pi_reg,
1156 io->pi_data,
1157 io->pi_width);
1158 error = 0;
1159 } else {
1160 error = ENODEV;
1161 }
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MD
1162 break;
1163 default:
1164 error = ENODEV;
1165 break;
1166 }
1167 break;
1168
1169 default:
1170 error = ENOTTY;
1171 break;
1172 }
1173
1174 return (error);
1175}
1176
1177#define PCI_CDEV 78
1178
fef8985e
MD
1179static struct dev_ops pcic_ops = {
1180 { "pci", PCI_CDEV, 0 },
1181 .d_open = pci_open,
1182 .d_close = pci_close,
1183 .d_ioctl = pci_ioctl,
984263bc
MD
1184};
1185
1186#include "pci_if.h"
1187
984263bc
MD
1188/*
1189 * New style pci driver. Parent device is either a pci-host-bridge or a
1190 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1191 */
ed1bd994
MD
1192const char *
1193pci_class_to_string(int baseclass)
1194{
1195 const char *name;
1196
1197 switch(baseclass) {
1198 case PCIC_OLD:
1199 name = "OLD";
1200 break;
1201 case PCIC_STORAGE:
1202 name = "STORAGE";
1203 break;
1204 case PCIC_NETWORK:
1205 name = "NETWORK";
1206 break;
1207 case PCIC_DISPLAY:
1208 name = "DISPLAY";
1209 break;
1210 case PCIC_MULTIMEDIA:
1211 name = "MULTIMEDIA";
1212 break;
1213 case PCIC_MEMORY:
1214 name = "MEMORY";
1215 break;
1216 case PCIC_BRIDGE:
1217 name = "BRIDGE";
1218 break;
1219 case PCIC_SIMPLECOMM:
1220 name = "SIMPLECOMM";
1221 break;
1222 case PCIC_BASEPERIPH:
1223 name = "BASEPERIPH";
1224 break;
1225 case PCIC_INPUTDEV:
1226 name = "INPUTDEV";
1227 break;
1228 case PCIC_DOCKING:
1229 name = "DOCKING";
1230 break;
1231 case PCIC_PROCESSOR:
1232 name = "PROCESSOR";
1233 break;
1234 case PCIC_SERIALBUS:
1235 name = "SERIALBUS";
1236 break;
1237 case PCIC_WIRELESS:
1238 name = "WIRELESS";
1239 break;
1240 case PCIC_I2O:
1241 name = "I20";
1242 break;
1243 case PCIC_SATELLITE:
1244 name = "SATELLITE";
1245 break;
1246 case PCIC_CRYPTO:
1247 name = "CRYPTO";
1248 break;
1249 case PCIC_SIGPROC:
1250 name = "SIGPROC";
1251 break;
1252 case PCIC_OTHER:
1253 name = "OTHER";
1254 break;
1255 default:
1256 name = "?";
1257 break;
1258 }
1259 return(name);
1260}
984263bc 1261
22457186 1262void
984263bc
MD
1263pci_print_verbose(struct pci_devinfo *dinfo)
1264{
1265 if (bootverbose) {
1266 pcicfgregs *cfg = &dinfo->cfg;
1267
85f8e2ea 1268 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
984263bc 1269 cfg->vendor, cfg->device, cfg->revid);
85f8e2ea 1270 kprintf("\tbus=%d, slot=%d, func=%d\n",
4a5a2d63 1271 cfg->bus, cfg->slot, cfg->func);
85f8e2ea 1272 kprintf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
ed1bd994 1273 pci_class_to_string(cfg->baseclass),
984263bc
MD
1274 cfg->baseclass, cfg->subclass, cfg->progif,
1275 cfg->hdrtype, cfg->mfdev);
85f8e2ea 1276 kprintf("\tsubordinatebus=%x \tsecondarybus=%x\n",
984263bc
MD
1277 cfg->subordinatebus, cfg->secondarybus);
1278#ifdef PCI_DEBUG
85f8e2ea 1279 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
984263bc 1280 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
85f8e2ea 1281 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
984263bc
MD
1282 cfg->lattimer, cfg->lattimer * 30,
1283 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1284#endif /* PCI_DEBUG */
1285 if (cfg->intpin > 0)
85f8e2ea 1286 kprintf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
984263bc
MD
1287 }
1288}
1289
1290static int
4a5a2d63 1291pci_porten(device_t pcib, int b, int s, int f)
984263bc 1292{
4a5a2d63
JS
1293 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1294 & PCIM_CMD_PORTEN) != 0;
984263bc
MD
1295}
1296
1297static int
4a5a2d63 1298pci_memen(device_t pcib, int b, int s, int f)
984263bc 1299{
4a5a2d63
JS
1300 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1301 & PCIM_CMD_MEMEN) != 0;
984263bc
MD
1302}
1303
1304/*
1305 * Add a resource based on a pci map register. Return 1 if the map
1306 * register is a 32bit map register or 2 if it is a 64bit register.
1307 */
1308static int
4a5a2d63
JS
1309pci_add_map(device_t pcib, int b, int s, int f, int reg,
1310 struct resource_list *rl)
984263bc 1311{
984263bc
MD
1312 u_int32_t map;
1313 u_int64_t base;
1314 u_int8_t ln2size;
1315 u_int8_t ln2range;
1316 u_int32_t testval;
4a5a2d63
JS
1317
1318
1319#ifdef PCI_ENABLE_IO_MODES
1320 u_int16_t cmd;
1321#endif
984263bc
MD
1322 int type;
1323
4a5a2d63 1324 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
984263bc
MD
1325
1326 if (map == 0 || map == 0xffffffff)
1327 return 1; /* skip invalid entry */
1328
4a5a2d63
JS
1329 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1330 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1331 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
984263bc
MD
1332
1333 base = pci_mapbase(map);
1334 if (pci_maptype(map) & PCI_MAPMEM)
1335 type = SYS_RES_MEMORY;
1336 else
1337 type = SYS_RES_IOPORT;
1338 ln2size = pci_mapsize(testval);
1339 ln2range = pci_maprange(testval);
1340 if (ln2range == 64) {
1341 /* Read the other half of a 64bit map register */
4a5a2d63 1342 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
984263bc
MD
1343 }
1344
984263bc
MD
1345 /*
1346 * This code theoretically does the right thing, but has
1347 * undesirable side effects in some cases where
1348 * peripherals respond oddly to having these bits
1349 * enabled. Leave them alone by default.
1350 */
1351#ifdef PCI_ENABLE_IO_MODES
4a5a2d63
JS
1352 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1353 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1354 cmd |= PCIM_CMD_PORTEN;
1355 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc 1356 }
4a5a2d63
JS
1357 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1358 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1359 cmd |= PCIM_CMD_MEMEN;
1360 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc
MD
1361 }
1362#else
4a5a2d63 1363 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
984263bc 1364 return 1;
4a5a2d63 1365 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
984263bc
MD
1366 return 1;
1367#endif
1368
1369 resource_list_add(rl, type, reg,
1370 base, base + (1 << ln2size) - 1,
1371 (1 << ln2size));
1372
1373 if (bootverbose) {
85f8e2ea 1374 kprintf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
984263bc
MD
1375 reg, pci_maptype(base), ln2range,
1376 (unsigned int) base, ln2size);
1377 }
1378
1379 return (ln2range == 64) ? 2 : 1;
1380}
1381
201eb0a7
TS
1382#ifdef PCI_MAP_FIXUP
1383/*
1384 * For ATA devices we need to decide early on what addressing mode to use.
1385 * Legacy demands that the primary and secondary ATA ports sits on the
1386 * same addresses that old ISA hardware did. This dictates that we use
1387 * those addresses and ignore the BARs if we cannot set PCI native
1388 * addressing mode.
1389 */
1390static void
1391pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, int s, int f,
1392 struct resource_list *rl)
1393{
1394 int rid, type, progif;
1395#if 0
1396 /* if this device supports PCI native addressing use it */
1397 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1398 if ((progif &0x8a) == 0x8a) {
1399 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
1400 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
85f8e2ea 1401 kprintf("Trying ATA native PCI addressing mode\n");
201eb0a7
TS
1402 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
1403 }
1404 }
1405#endif
1406 /*
1407 * Because we return any preallocated resources for lazy
1408 * allocation for PCI devices in pci_alloc_resource(), we can
1409 * allocate our legacy resources here.
1410 */
1411 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1412 type = SYS_RES_IOPORT;
1413 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
1414 pci_add_map(pcib, b, s, f, PCIR_BAR(0), rl);
1415 pci_add_map(pcib, b, s, f, PCIR_BAR(1), rl);
1416 } else {
1417 rid = PCIR_BAR(0);
1418 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
1419 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
1420 0);
1421 rid = PCIR_BAR(1);
1422 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
1423 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
1424 0);
1425 }
1426 if (progif & PCIP_STORAGE_IDE_MODESEC) {
1427 pci_add_map(pcib, b, s, f, PCIR_BAR(2), rl);
1428 pci_add_map(pcib, b, s, f, PCIR_BAR(3), rl);
1429 } else {
1430 rid = PCIR_BAR(2);
1431 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
1432 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
1433 0);
1434 rid = PCIR_BAR(3);
1435 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
1436 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
1437 0);
1438 }
1439 pci_add_map(pcib, b, s, f, PCIR_BAR(4), rl);
1440 pci_add_map(pcib, b, s, f, PCIR_BAR(5), rl);
1441}
1442#endif /* PCI_MAP_FIXUP */
1443
984263bc 1444static void
e126caf1 1445pci_add_resources(device_t pcib, device_t bus, device_t dev)
984263bc
MD
1446{
1447 struct pci_devinfo *dinfo = device_get_ivars(dev);
4a5a2d63 1448 pcicfgregs *cfg = &dinfo->cfg;
984263bc
MD
1449 struct resource_list *rl = &dinfo->resources;
1450 struct pci_quirk *q;
e126caf1
MD
1451 int b, i, f, s;
1452#if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */
1453 int irq;
1454#endif
984263bc 1455
e126caf1
MD
1456 b = cfg->bus;
1457 s = cfg->slot;
1458 f = cfg->func;
201eb0a7
TS
1459#ifdef PCI_MAP_FIXUP
1460 /* atapci devices in legacy mode need special map treatment */
1461 if ((pci_get_class(dev) == PCIC_STORAGE) &&
1462 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
d3d1ea7a
MD
1463 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
1464 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
1465 !pci_read_config(dev, PCIR_BAR(2), 4))) )
201eb0a7
TS
1466 pci_ata_maps(pcib, bus, dev, b, s, f, rl);
1467 else
1468#endif /* PCI_MAP_FIXUP */
1469 for (i = 0; i < cfg->nummaps;) {
1470 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl);
1471 }
984263bc
MD
1472
1473 for (q = &pci_quirks[0]; q->devid; q++) {
1474 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1475 && q->type == PCI_QUIRK_MAP_REG)
4a5a2d63 1476 pci_add_map(pcib, b, s, f, q->arg1, rl);
984263bc
MD
1477 }
1478
1479 if (cfg->intpin > 0 && cfg->intline != 255)
1480 resource_list_add(rl, SYS_RES_IRQ, 0,
1481 cfg->intline, cfg->intline, 1);
1482}
1483
e126caf1
MD
1484void
1485pci_add_children(device_t dev, int busno, size_t dinfo_size)
984263bc 1486{
e126caf1 1487#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
4a5a2d63 1488 device_t pcib = device_get_parent(dev);
e126caf1 1489 struct pci_devinfo *dinfo;
4a5a2d63 1490 int maxslots;
e126caf1
MD
1491 int s, f, pcifunchigh;
1492 uint8_t hdrtype;
1493
1494 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo));
984263bc 1495
4a5a2d63 1496 maxslots = PCIB_MAXSLOTS(pcib);
984263bc 1497
57e943f7 1498 for (s = 0; s <= maxslots; s++) {
e126caf1
MD
1499 pcifunchigh = 0;
1500 f = 0;
1501 hdrtype = REG(PCIR_HDRTYPE, 1);
1502 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1503 continue;
1504 if (hdrtype & PCIM_MFDEV)
1505 pcifunchigh = PCI_FUNCMAX;
5e658043 1506 for (f = 0; f <= pcifunchigh; f++) {
e126caf1 1507 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
984263bc 1508 if (dinfo != NULL) {
e126caf1 1509 pci_add_child(dev, dinfo);
984263bc
MD
1510 }
1511 }
1512 }
e126caf1
MD
1513#undef REG
1514}
1515
2581072f
MD
1516/*
1517 * The actual PCI child that we add has a NULL driver whos parent
1518 * device will be "pci". The child contains the ivars, not the parent.
1519 */
e126caf1
MD
1520void
1521pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1522{
1523 device_t pcib;
1524
1525 pcib = device_get_parent(bus);
1526 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1527 device_set_ivars(dinfo->cfg.dev, dinfo);
1528 pci_add_resources(pcib, bus, dinfo->cfg.dev);
1529 pci_print_verbose(dinfo);
984263bc
MD
1530}
1531
c01b8d84
MD
1532/*
1533 * Probe the PCI bus. Note: probe code is not supposed to add children
1534 * or call attach.
1535 */
984263bc 1536static int
4a5a2d63 1537pci_probe(device_t dev)
984263bc 1538{
984263bc 1539 device_set_desc(dev, "PCI bus");
4a5a2d63 1540
c01b8d84
MD
1541 /* Allow other subclasses to override this driver */
1542 return(-1000);
984263bc
MD
1543}
1544
e126caf1
MD
1545static int
1546pci_attach(device_t dev)
1547{
1548 int busno;
e4c9c0c8
MD
1549 int lunit = device_get_unit(dev);
1550
fef8985e
MD
1551 dev_ops_add(&pcic_ops, -1, lunit);
1552 make_dev(&pcic_ops, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit);
e126caf1
MD
1553
1554 /*
1555 * Since there can be multiple independantly numbered PCI
1556 * busses on some large alpha systems, we can't use the unit
1557 * number to decide what bus we are probing. We ask the parent
1558 * pcib what our bus number is.
2581072f
MD
1559 *
1560 * pcib_get_bus() must act on the pci bus device, not on the pci
1561 * device, because it uses badly hacked nexus-based ivars to
1562 * store and retrieve the physical bus number. XXX
e126caf1 1563 */
2581072f 1564 busno = pcib_get_bus(device_get_parent(dev));
e126caf1 1565 if (bootverbose)
ed1bd994 1566 device_printf(dev, "pci_attach() physical bus=%d\n", busno);
e126caf1
MD
1567
1568 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1569
1570 return (bus_generic_attach(dev));
1571}
1572
984263bc
MD
1573static int
1574pci_print_resources(struct resource_list *rl, const char *name, int type,
1575 const char *format)
1576{
1577 struct resource_list_entry *rle;
1578 int printed, retval;
1579
1580 printed = 0;
1581 retval = 0;
1582 /* Yes, this is kinda cheating */
1583 SLIST_FOREACH(rle, rl, link) {
1584 if (rle->type == type) {
1585 if (printed == 0)
85f8e2ea 1586 retval += kprintf(" %s ", name);
984263bc 1587 else if (printed > 0)
85f8e2ea 1588 retval += kprintf(",");
984263bc 1589 printed++;
85f8e2ea 1590 retval += kprintf(format, rle->start);
984263bc 1591 if (rle->count > 1) {
85f8e2ea
SW
1592 retval += kprintf("-");
1593 retval += kprintf(format, rle->start +
984263bc
MD
1594 rle->count - 1);
1595 }
1596 }
1597 }
1598 return retval;
1599}
1600
e126caf1 1601int
984263bc
MD
1602pci_print_child(device_t dev, device_t child)
1603{
1604 struct pci_devinfo *dinfo;
1605 struct resource_list *rl;
1606 pcicfgregs *cfg;
1607 int retval = 0;
1608
1609 dinfo = device_get_ivars(child);
1610 cfg = &dinfo->cfg;
1611 rl = &dinfo->resources;
1612
1613 retval += bus_print_child_header(dev, child);
1614
1615 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1616 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1617 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1618 if (device_get_flags(dev))
85f8e2ea 1619 retval += kprintf(" flags %#x", device_get_flags(dev));
984263bc 1620
85f8e2ea 1621 retval += kprintf(" at device %d.%d", pci_get_slot(child),
984263bc
MD
1622 pci_get_function(child));
1623
1624 retval += bus_print_child_footer(dev, child);
1625
1626 return (retval);
1627}
1628
e126caf1 1629void
984263bc
MD
1630pci_probe_nomatch(device_t dev, device_t child)
1631{
1632 struct pci_devinfo *dinfo;
1633 pcicfgregs *cfg;
1634 const char *desc;
1635 int unknown;
1636
1637 unknown = 0;
1638 dinfo = device_get_ivars(child);
1639 cfg = &dinfo->cfg;
1640 desc = pci_ata_match(child);
1641 if (!desc) desc = pci_usb_match(child);
1642 if (!desc) desc = pci_vga_match(child);
27c23c6b 1643 if (!desc) desc = pci_chip_match(child);
984263bc
MD
1644 if (!desc) {
1645 desc = "unknown card";
1646 unknown++;
1647 }
1648 device_printf(dev, "<%s>", desc);
1649 if (bootverbose || unknown) {
85f8e2ea 1650 kprintf(" (vendor=0x%04x, dev=0x%04x)",
984263bc
MD
1651 cfg->vendor,
1652 cfg->device);
1653 }
85f8e2ea 1654 kprintf(" at %d.%d",
984263bc
MD
1655 pci_get_slot(child),
1656 pci_get_function(child));
1657 if (cfg->intpin > 0 && cfg->intline != 255) {
85f8e2ea 1658 kprintf(" irq %d", cfg->intline);
984263bc 1659 }
85f8e2ea 1660 kprintf("\n");
984263bc
MD
1661
1662 return;
1663}
1664
22457186 1665int
4a5a2d63 1666pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
984263bc
MD
1667{
1668 struct pci_devinfo *dinfo;
1669 pcicfgregs *cfg;
1670
1671 dinfo = device_get_ivars(child);
1672 cfg = &dinfo->cfg;
1673
1674 switch (which) {
1675 case PCI_IVAR_SUBVENDOR:
1676 *result = cfg->subvendor;
1677 break;
1678 case PCI_IVAR_SUBDEVICE:
1679 *result = cfg->subdevice;
1680 break;
1681 case PCI_IVAR_VENDOR:
1682 *result = cfg->vendor;
1683 break;
1684 case PCI_IVAR_DEVICE:
1685 *result = cfg->device;
1686 break;
1687 case PCI_IVAR_DEVID:
1688 *result = (cfg->device << 16) | cfg->vendor;
1689 break;
1690 case PCI_IVAR_CLASS:
1691 *result = cfg->baseclass;
1692 break;
1693 case PCI_IVAR_SUBCLASS:
1694 *result = cfg->subclass;
1695 break;
1696 case PCI_IVAR_PROGIF:
1697 *result = cfg->progif;
1698 break;
1699 case PCI_IVAR_REVID:
1700 *result = cfg->revid;
1701 break;
1702 case PCI_IVAR_INTPIN:
1703 *result = cfg->intpin;
1704 break;
1705 case PCI_IVAR_IRQ:
1706 *result = cfg->intline;
1707 break;
1708 case PCI_IVAR_BUS:
1709 *result = cfg->bus;
1710 break;
1711 case PCI_IVAR_SLOT:
1712 *result = cfg->slot;
1713 break;
1714 case PCI_IVAR_FUNCTION:
1715 *result = cfg->func;
1716 break;
1717 case PCI_IVAR_SECONDARYBUS:
1718 *result = cfg->secondarybus;
1719 break;
1720 case PCI_IVAR_SUBORDINATEBUS:
1721 *result = cfg->subordinatebus;
1722 break;
f72d3d23
JS
1723 case PCI_IVAR_ETHADDR:
1724 /*
1725 * The generic accessor doesn't deal with failure, so
1726 * we set the return value, then return an error.
1727 */
1728 *result = NULL;
1729 return (EINVAL);
984263bc
MD
1730 default:
1731 return ENOENT;
1732 }
1733 return 0;
1734}
1735
22457186 1736int
984263bc
MD
1737pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1738{
1739 struct pci_devinfo *dinfo;
1740 pcicfgregs *cfg;
1741
1742 dinfo = device_get_ivars(child);
1743 cfg = &dinfo->cfg;
1744
1745 switch (which) {
1746 case PCI_IVAR_SUBVENDOR:
1747 case PCI_IVAR_SUBDEVICE:
1748 case PCI_IVAR_VENDOR:
1749 case PCI_IVAR_DEVICE:
1750 case PCI_IVAR_DEVID:
1751 case PCI_IVAR_CLASS:
1752 case PCI_IVAR_SUBCLASS:
1753 case PCI_IVAR_PROGIF:
1754 case PCI_IVAR_REVID:
1755 case PCI_IVAR_INTPIN:
1756 case PCI_IVAR_IRQ:
1757 case PCI_IVAR_BUS:
1758 case PCI_IVAR_SLOT:
1759 case PCI_IVAR_FUNCTION:
f72d3d23 1760 case PCI_IVAR_ETHADDR:
984263bc
MD
1761 return EINVAL; /* disallow for now */
1762
1763 case PCI_IVAR_SECONDARYBUS:
1764 cfg->secondarybus = value;
1765 break;
1766 case PCI_IVAR_SUBORDINATEBUS:
1767 cfg->subordinatebus = value;
1768 break;
1769 default:
1770 return ENOENT;
1771 }
1772 return 0;
1773}
1774
201eb0a7
TS
1775#ifdef PCI_MAP_FIXUP
1776static struct resource *
1777pci_alloc_map(device_t dev, device_t child, int type, int *rid, u_long start,
1778 u_long end, u_long count, u_int flags)
1779{
1780 struct pci_devinfo *dinfo = device_get_ivars(child);
1781 struct resource_list *rl = &dinfo->resources;
1782 struct resource_list_entry *rle;
1783 struct resource *res;
1784 uint32_t map, testval;
1785 int mapsize;
1786
1787 /*
1788 * Weed out the bogons, and figure out how large the BAR/map
1789 * is. BARs that read back 0 here are bogus and unimplemented.
1790 *
1791 * Note: atapci in legacy mode are special and handled elsewhere
1792 * in the code. If you have an atapci device in legacy mode and
1793 * it fails here, that other code is broken.
1794 */
1795 res = NULL;
1796 map = pci_read_config(child, *rid, 4);
1797 pci_write_config(child, *rid, 0xffffffff, 4);
1798 testval = pci_read_config(child, *rid, 4);
1799 if (pci_mapbase(testval) == 0)
1800 goto out;
1801 if (pci_maptype(testval) & PCI_MAPMEM) {
1802 if (type != SYS_RES_MEMORY) {
1803 if (bootverbose)
1804 device_printf(dev, "child %s requested type %d"
1805 " for rid %#x, but the BAR says "
1806 "it is a memio\n",
1807 device_get_nameunit(child), type,
1808 *rid);
1809 goto out;
1810 }
1811 } else {
1812 if (type != SYS_RES_IOPORT) {
1813 if (bootverbose)
1814 device_printf(dev, "child %s requested type %d"
1815 " for rid %#x, but the BAR says "
1816 "it is an ioport\n",
1817 device_get_nameunit(child), type,
1818 *rid);
1819 goto out;
1820 }
1821 }
1822 /*
1823 * For real BARs, we need to override the size that
1824 * the driver requests, because that's what the BAR
1825 * actually uses and we would otherwise have a
1826 * situation where we might allocate the excess to
1827 * another driver, which won't work.
1828 */
1829 mapsize = pci_mapsize(testval);
1830 count = 1 << mapsize;
1831 if (RF_ALIGNMENT(flags) < mapsize)
1832 flags = (flags & ~RF_ALIGNMENT_MASK) |
1833 RF_ALIGNMENT_LOG2(mapsize);
1834 /*
1835 * Allocate enough resource, and then write back the
1836 * appropriate BAR for that resource.
1837 */
1838 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
1839 start, end, count, flags);
1840 if (res == NULL) {
1841 device_printf(child, "%#lx bytes at rid %#x res %d failed "
1842 "(%#lx, %#lx)\n", count, *rid, type, start, end);
1843 goto out;
1844 }
1845 resource_list_add(rl, type, *rid, start, end, count);
1846 rle = resource_list_find(rl, type, *rid);
1847 if (rle == NULL)
1848 panic("pci_alloc_map: unexpectedly can't find resource.");
1849 rle->res = res;
1850 rle->start = rman_get_start(res);
1851 rle->end = rman_get_end(res);
1852 rle->count = count;
1853 if (bootverbose)
1854 device_printf(child, "lazy allocation of %#lx bytes rid %#x "
1855 "type %d at %#lx\n", count, *rid, type,
1856 rman_get_start(res));
1857 map = rman_get_start(res);
1858out:;
1859 pci_write_config(child, *rid, map, 4);
1860 return res;
1861}
1862#endif /* PCI_MAP_FIXUP */
1863
261fa16d 1864struct resource *
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1865pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1866 u_long start, u_long end, u_long count, u_int flags)
1867{
1868 struct pci_devinfo *dinfo = device_get_ivars(child);
1869 struct resource_list *rl = &dinfo->resources;
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TS
1870#ifdef PCI_MAP_FIXUP
1871 struct resource_list_entry *rle;
1872#endif /* PCI_MAP_FIXUP */
984263bc 1873 pcicfgregs *cfg = &dinfo->cfg;
de67e43b 1874
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1875 /*
1876 * Perform lazy resource allocation
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1877 */
1878 if (device_get_parent(child) == dev) {
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JS
1879 switch (type) {
1880 case SYS_RES_IRQ:
1881#ifdef __i386__
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1882 /*
1883 * If device doesn't have an interrupt routed, and is
1884 * deserving of an interrupt, try to assign it one.
1885 */
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1886 if ((cfg->intline == 255 || cfg->intline == 0) &&
1887 (cfg->intpin != 0) &&
1888 (start == 0) && (end == ~0UL)) {
1889 cfg->intline = PCIB_ROUTE_INTERRUPT(
1890 device_get_parent(dev), child,
1891 cfg->intpin);
1892 if (cfg->intline != 255) {
1893 pci_write_config(child, PCIR_INTLINE,
1894 cfg->intline, 1);
1895 resource_list_add(rl, SYS_RES_IRQ, 0,
1896 cfg->intline, cfg->intline, 1);
1897 }
1898 }
820c1612 1899 break;
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1900#endif
1901 case SYS_RES_IOPORT:
201eb0a7 1902 /* FALLTHROUGH */
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1903 case SYS_RES_MEMORY:
1904 if (*rid < PCIR_BAR(cfg->nummaps)) {
1905 /*
1906 * Enable the I/O mode. We should
1907 * also be assigning resources too
1908 * when none are present. The
1909 * resource_list_alloc kind of sorta does
1910 * this...
1911 */
1912 if (PCI_ENABLE_IO(dev, child, type))
1913 return (NULL);
984263bc 1914 }
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TS
1915#ifdef PCI_MAP_FIXUP
1916 rle = resource_list_find(rl, type, *rid);
1917 if (rle == NULL)
1918 return pci_alloc_map(dev, child, type, rid,
1919 start, end, count, flags);
1920#endif /* PCI_MAP_FIXUP */
820c1612 1921 break;
984263bc 1922 }
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1923#ifdef PCI_MAP_FIXUP
1924 /*
1925 * If we've already allocated the resource, then
1926 * return it now. But first we may need to activate
1927 * it, since we don't allocate the resource as active
1928 * above. Normally this would be done down in the
1929 * nexus, but since we short-circuit that path we have
1930 * to do its job here. Not sure if we should free the
1931 * resource if it fails to activate.
1932 *
1933 * Note: this also finds and returns resources for
1934 * atapci devices in legacy mode as allocated in
1935 * pci_ata_maps().
1936 */
1937 rle = resource_list_find(rl, type, *rid);
1938 if (rle != NULL && rle->res != NULL) {
1939 if (bootverbose)
1940 device_printf(child, "reserved %#lx bytes for "
1941 "rid %#x type %d at %#lx\n",
1942 rman_get_size(rle->res), *rid,
1943 type, rman_get_start(rle->res));
1944 if ((flags & RF_ACTIVE) &&
1945 bus_generic_activate_resource(dev, child, type,
1946 *rid, rle->res) != 0)
1947 return NULL;
1948 return rle->res;
1949 }
1950#endif /* PCI_MAP_FIXUP */
984263bc 1951 }
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1952 return resource_list_alloc(rl, dev, child, type, rid,
1953 start, end, count, flags);
1954}
1955
1956static int
1957pci_release_resource(device_t dev, device_t child, int type, int rid,
1958 struct resource *r)
1959{
1960 struct pci_devinfo *dinfo = device_get_ivars(child);
1961 struct resource_list *rl = &dinfo->resources;
1962
1963 return resource_list_release(rl, dev, child, type, rid, r);
1964}
1965
1966static int
1967pci_set_resource(device_t dev, device_t child, int type, int rid,
1968 u_long start, u_long count)
1969{
1970 struct pci_devinfo *dinfo = device_get_ivars(child);
1971 struct resource_list *rl = &dinfo->resources;
1972
1973 resource_list_add(rl, type, rid, start, start + count - 1, count);
1974 return 0;
1975}
1976
1977static int
1978pci_get_resource(device_t dev, device_t child, int type, int rid,
1979 u_long *startp, u_long *countp)
1980{
1981 struct pci_devinfo *dinfo = device_get_ivars(child);
1982 struct resource_list *rl = &dinfo->resources;
1983 struct resource_list_entry *rle;
1984
1985 rle = resource_list_find(rl, type, rid);
1986 if (!rle)
1987 return ENOENT;
1988
1989 if (startp)
1990 *startp = rle->start;
1991 if (countp)
1992 *countp = rle->count;
1993
1994 return 0;
1995}
1996
e126caf1 1997void
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1998pci_delete_resource(device_t dev, device_t child, int type, int rid)
1999{
85f8e2ea 2000 kprintf("pci_delete_resource: PCI resources can not be deleted\n");
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2001}
2002
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2003struct resource_list *
2004pci_get_resource_list (device_t dev, device_t child)
2005{
b0486c83 2006 struct pci_devinfo *dinfo = device_get_ivars(child);
e126caf1 2007
b0486c83 2008 if (dinfo == NULL)
e126caf1 2009 return (NULL);
b0486c83 2010 return (&dinfo->resources);
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2011}
2012
2013u_int32_t
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2014pci_read_config_method(device_t dev, device_t child, int reg, int width)
2015{
2016 struct pci_devinfo *dinfo = device_get_ivars(child);
2017 pcicfgregs *cfg = &dinfo->cfg;
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2018
2019 return PCIB_READ_CONFIG(device_get_parent(dev),
2020 cfg->bus, cfg->slot, cfg->func,
2021 reg, width);
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2022}
2023
e126caf1 2024void
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2025pci_write_config_method(device_t dev, device_t child, int reg,
2026 u_int32_t val, int width)
2027{
2028 struct pci_devinfo *dinfo = device_get_ivars(child);
2029 pcicfgregs *cfg = &dinfo->cfg;
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JS
2030
2031 PCIB_WRITE_CONFIG(device_get_parent(dev),
2032 cfg->bus, cfg->slot, cfg->func,
2033 reg, val, width);
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2034}
2035
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MD
2036int
2037pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
2038 size_t buflen)
2039{
2040 struct pci_devinfo *dinfo;
2041
2042 dinfo = device_get_ivars(child);
f8c7a42d 2043 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
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MD
2044 pci_get_function(child));
2045 return (0);
2046}
2047
2048int
2049pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
2050 size_t buflen)
2051{
2052 struct pci_devinfo *dinfo;
2053 pcicfgregs *cfg;
2054
2055 dinfo = device_get_ivars(child);
2056 cfg = &dinfo->cfg;
f8c7a42d 2057 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
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MD
2058 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
2059 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
2060 cfg->progif);
2061 return (0);
2062}
2063
2064int
2065pci_assign_interrupt_method(device_t dev, device_t child)
2066{
2067 struct pci_devinfo *dinfo = device_get_ivars(child);
2068 pcicfgregs *cfg = &dinfo->cfg;
2069
2070 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
2071 cfg->intpin));
2072}
2073
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2074static int
2075pci_modevent(module_t mod, int what, void *arg)
2076{
2077 switch (what) {
2078 case MOD_LOAD:
2079 STAILQ_INIT(&pci_devq);
2080 break;
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2081 case MOD_UNLOAD:
2082 break;
2083 }
2084
2085 return 0;
2086}
2087
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MD
2088int
2089pci_resume(device_t dev)
2090{
2091 int numdevs;
2092 int i;
2093 device_t *children;
2094 device_t child;
2095 struct pci_devinfo *dinfo;
2096 pcicfgregs *cfg;
2097
2098 device_get_children(dev, &children, &numdevs);
2099
2100 for (i = 0; i < numdevs; i++) {
2101 child = children[i];
2102
2103 dinfo = device_get_ivars(child);
2104 cfg = &dinfo->cfg;
2105 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2106 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
2107 if (PCI_INTERRUPT_VALID(cfg->intline)) {
2108 pci_write_config(child, PCIR_INTLINE,
2109 cfg->intline, 1);
2110 }
2111 }
2112 }
2113
efda3bd0 2114 kfree(children, M_TEMP);
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2115
2116 return (bus_generic_resume(dev));
2117}
2118
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2119static device_method_t pci_methods[] = {
2120 /* Device interface */
4a5a2d63 2121 DEVMETHOD(device_probe, pci_probe),
e126caf1 2122 DEVMETHOD(device_attach, pci_attach),
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2123 DEVMETHOD(device_shutdown, bus_generic_shutdown),
2124 DEVMETHOD(device_suspend, bus_generic_suspend),
e126caf1 2125 DEVMETHOD(device_resume, pci_resume),
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2126
2127 /* Bus interface */
2128 DEVMETHOD(bus_print_child, pci_print_child),
2129 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
2130 DEVMETHOD(bus_read_ivar, pci_read_ivar),
2131 DEVMETHOD(bus_write_ivar, pci_write_ivar),
2132 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
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2133 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
2134 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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MD
2135
2136 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
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MD
2137 DEVMETHOD(bus_set_resource, pci_set_resource),
2138 DEVMETHOD(bus_get_resource, pci_get_resource),
2139 DEVMETHOD(bus_delete_resource, pci_delete_resource),
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2140 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
2141 DEVMETHOD(bus_release_resource, pci_release_resource),
2142 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
2143 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
2144 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
2145 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
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MD
2146
2147 /* PCI interface */
2148 DEVMETHOD(pci_read_config, pci_read_config_method),
2149 DEVMETHOD(pci_write_config, pci_write_config_method),
2150 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
2151 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
2152 DEVMETHOD(pci_enable_io, pci_enable_io_method),
2153 DEVMETHOD(pci_disable_io, pci_disable_io_method),
2154 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
2155 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
e126caf1 2156 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
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MD
2157
2158 { 0, 0 }
2159};
2160
3aef8050 2161driver_t pci_driver = {
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MD
2162 "pci",
2163 pci_methods,
2164 1, /* no softc */
2165};
2166
2167DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
261fa16d 2168MODULE_VERSION(pci, 1);