Add PCICAP_{ID,NEXTPTR} to avoid using magic number
[dragonfly.git] / sys / bus / pci / pci.c
CommitLineData
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1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
3f607eb6 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.58 2008/11/16 18:44:00 swildner Exp $
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28 *
29 */
30
31#include "opt_bus.h"
32#include "opt_pci.h"
33
dc5a7bd2 34#include "opt_compat_oldpci.h"
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35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/malloc.h>
39#include <sys/module.h>
40#include <sys/fcntl.h>
41#include <sys/conf.h>
42#include <sys/kernel.h>
43#include <sys/queue.h>
44#include <sys/types.h>
638744c5 45#include <sys/sysctl.h>
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46#include <sys/buf.h>
47
48#include <vm/vm.h>
49#include <vm/pmap.h>
50#include <vm/vm_extern.h>
51
52#include <sys/bus.h>
984263bc 53#include <sys/rman.h>
97359a5b 54#include <machine/smp.h>
21ce0dfa 55#include "pci_cfgreg.h"
984263bc 56
dc5a7bd2 57#include <sys/pciio.h>
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58#include "pcireg.h"
59#include "pcivar.h"
22457186 60#include "pci_private.h"
984263bc 61
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62#include "pcib_if.h"
63
e126caf1 64devclass_t pci_devclass;
2581072f 65const char *pcib_owner;
dc5a7bd2 66
e9d8f4df 67static void pci_read_capabilities(device_t dev, pcicfgregs *cfg);
8c5b0f9a 68static int pcie_slotimpl(const pcicfgregs *);
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69
70struct pci_quirk {
71 u_int32_t devid; /* Vendor/device of the card */
72 int type;
3e4db402 73#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
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74 int arg1;
75 int arg2;
76};
77
78struct pci_quirk pci_quirks[] = {
79 /*
80 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
81 */
82 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
83 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
f1f0bfb2
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84 /* As does the Serverworks OSB4 (the SMBus mapping register) */
85 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
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86
87 { 0 }
88};
89
90/* map register information */
91#define PCI_MAPMEM 0x01 /* memory map */
92#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
93#define PCI_MAPPORT 0x04 /* port map */
94
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95static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
96u_int32_t pci_numdevs = 0;
97static u_int32_t pci_generation = 0;
98
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99SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "pci parameters");
100static int pci_do_power_nodriver = 0;
101TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
102SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
103 &pci_do_power_nodriver, 0,
104 "Place a function into D3 state when no driver attaches to it. 0 means\n\
105disable. 1 means conservatively place devices into D3 state. 2 means\n\
3f607eb6 106aggressively place devices into D3 state. 3 means put absolutely everything\n\
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107in D3 state.");
108
984263bc 109device_t
c0f16abb 110pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func)
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111{
112 struct pci_devinfo *dinfo;
113
114 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
115 if ((dinfo->cfg.bus == bus) &&
116 (dinfo->cfg.slot == slot) &&
117 (dinfo->cfg.func == func)) {
118 return (dinfo->cfg.dev);
119 }
120 }
121
122 return (NULL);
123}
124
125device_t
c0f16abb 126pci_find_device(u_int16_t vendor, u_int16_t device)
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127{
128 struct pci_devinfo *dinfo;
129
130 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
131 if ((dinfo->cfg.vendor == vendor) &&
132 (dinfo->cfg.device == device)) {
133 return (dinfo->cfg.dev);
134 }
135 }
136
137 return (NULL);
138}
139
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140int
141pcie_slot_implemented(device_t dev)
142{
143 struct pci_devinfo *dinfo = device_get_ivars(dev);
144
145 return pcie_slotimpl(&dinfo->cfg);
146}
147
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148void
149pcie_set_max_readrq(device_t dev, uint16_t rqsize)
150{
151 uint8_t expr_ptr;
152 uint16_t val;
153
154 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK;
155 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) {
156 panic("%s: invalid max read request size 0x%02x\n",
157 device_get_nameunit(dev), rqsize);
158 }
159
160 expr_ptr = pci_get_pciecap_ptr(dev);
161 if (!expr_ptr)
162 panic("%s: not PCIe device\n", device_get_nameunit(dev));
163
164 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
165 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) {
166 if (bootverbose)
167 device_printf(dev, "adjust device control 0x%04x", val);
168
169 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
170 val |= rqsize;
171 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
172
173 if (bootverbose)
174 kprintf(" -> 0x%04x\n", val);
175 }
176}
177
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178/* return base address of memory or port map */
179
180static u_int32_t
181pci_mapbase(unsigned mapreg)
182{
183 int mask = 0x03;
184 if ((mapreg & 0x01) == 0)
185 mask = 0x0f;
186 return (mapreg & ~mask);
187}
188
189/* return map type of memory or port map */
190
191static int
192pci_maptype(unsigned mapreg)
193{
194 static u_int8_t maptype[0x10] = {
195 PCI_MAPMEM, PCI_MAPPORT,
196 PCI_MAPMEM, 0,
197 PCI_MAPMEM, PCI_MAPPORT,
198 0, 0,
199 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
200 PCI_MAPMEM|PCI_MAPMEMP, 0,
201 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
202 0, 0,
203 };
204
205 return maptype[mapreg & 0x0f];
206}
207
208/* return log2 of map size decoded for memory or port map */
209
210static int
211pci_mapsize(unsigned testval)
212{
213 int ln2size;
214
215 testval = pci_mapbase(testval);
216 ln2size = 0;
217 if (testval != 0) {
218 while ((testval & 1) == 0)
219 {
220 ln2size++;
221 testval >>= 1;
222 }
223 }
224 return (ln2size);
225}
226
227/* return log2 of address range supported by map register */
228
229static int
230pci_maprange(unsigned mapreg)
231{
232 int ln2range = 0;
233 switch (mapreg & 0x07) {
234 case 0x00:
235 case 0x01:
236 case 0x05:
237 ln2range = 32;
238 break;
239 case 0x02:
240 ln2range = 20;
241 break;
242 case 0x04:
243 ln2range = 64;
244 break;
245 }
246 return (ln2range);
247}
248
249/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
250
251static void
252pci_fixancient(pcicfgregs *cfg)
253{
254 if (cfg->hdrtype != 0)
255 return;
256
257 /* PCI to PCI bridges use header type 1 */
258 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
259 cfg->hdrtype = 1;
260}
261
262/* read config data specific to header type 1 device (PCI to PCI bridge) */
263
264static void *
4a5a2d63 265pci_readppb(device_t pcib, int b, int s, int f)
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266{
267 pcih1cfgregs *p;
268
efda3bd0 269 p = kmalloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
984263bc 270
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271 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
272 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
984263bc 273
4a5a2d63 274 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
984263bc 275
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276 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
277 PCIR_IOBASEH_1, 2),
278 PCIB_READ_CONFIG(pcib, b, s, f,
279 PCIR_IOBASEL_1, 1));
280 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
281 PCIR_IOLIMITH_1, 2),
282 PCIB_READ_CONFIG(pcib, b, s, f,
283 PCIR_IOLIMITL_1, 1));
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284
285 p->membase = PCI_PPBMEMBASE (0,
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286 PCIB_READ_CONFIG(pcib, b, s, f,
287 PCIR_MEMBASE_1, 2));
984263bc 288 p->memlimit = PCI_PPBMEMLIMIT (0,
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289 PCIB_READ_CONFIG(pcib, b, s, f,
290 PCIR_MEMLIMIT_1, 2));
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291
292 p->pmembase = PCI_PPBMEMBASE (
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293 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
294 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
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295
296 p->pmemlimit = PCI_PPBMEMLIMIT (
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297 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
298 PCIR_PMLIMITH_1, 4),
299 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
300
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301 return (p);
302}
303
304/* read config data specific to header type 2 device (PCI to CardBus bridge) */
305
306static void *
4a5a2d63 307pci_readpcb(device_t pcib, int b, int s, int f)
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308{
309 pcih2cfgregs *p;
310
efda3bd0 311 p = kmalloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
984263bc 312
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313 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
314 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
984263bc 315
4a5a2d63 316 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
984263bc 317
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318 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
319 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
320 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
321 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
984263bc 322
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323 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
324 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
325 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
326 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
984263bc 327
4a5a2d63 328 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
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329 return p;
330}
331
332/* extract header type specific config data */
333
334static void
4a5a2d63 335pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
984263bc 336{
4a5a2d63 337#define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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338 switch (cfg->hdrtype) {
339 case 0:
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340 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
341 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
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342 cfg->nummaps = PCI_MAXMAPS_0;
343 break;
344 case 1:
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345 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
346 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
347 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
348 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
984263bc 349 cfg->nummaps = PCI_MAXMAPS_1;
4a5a2d63 350 cfg->hdrspec = pci_readppb(pcib, b, s, f);
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351 break;
352 case 2:
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353 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
354 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
355 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
356 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
984263bc 357 cfg->nummaps = PCI_MAXMAPS_2;
4a5a2d63 358 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
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359 break;
360 }
4a5a2d63 361#undef REG
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362}
363
364/* read configuration header into pcicfgrect structure */
365
22457186 366struct pci_devinfo *
c01b8d84 367pci_read_device(device_t pcib, int b, int s, int f, size_t size)
984263bc 368{
4a5a2d63 369#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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370
371 pcicfgregs *cfg = NULL;
372 struct pci_devinfo *devlist_entry;
373 struct devlist *devlist_head;
374
375 devlist_head = &pci_devq;
376
377 devlist_entry = NULL;
378
4a5a2d63 379 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
984263bc 380
efda3bd0 381 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
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382
383 cfg = &devlist_entry->cfg;
384
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385 cfg->bus = b;
386 cfg->slot = s;
387 cfg->func = f;
388 cfg->vendor = REG(PCIR_VENDOR, 2);
389 cfg->device = REG(PCIR_DEVICE, 2);
390 cfg->cmdreg = REG(PCIR_COMMAND, 2);
391 cfg->statreg = REG(PCIR_STATUS, 2);
392 cfg->baseclass = REG(PCIR_CLASS, 1);
393 cfg->subclass = REG(PCIR_SUBCLASS, 1);
394 cfg->progif = REG(PCIR_PROGIF, 1);
395 cfg->revid = REG(PCIR_REVID, 1);
e126caf1 396 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
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397 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
398 cfg->lattimer = REG(PCIR_LATTIMER, 1);
399 cfg->intpin = REG(PCIR_INTPIN, 1);
400 cfg->intline = REG(PCIR_INTLINE, 1);
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401
402#ifdef APIC_IO
97359a5b
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403 /*
404 * If using the APIC the intpin is probably wrong, since it
405 * is often setup by the BIOS with the PIC in mind.
406 */
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407 if (cfg->intpin != 0) {
408 int airq;
409
410 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
411 if (airq >= 0) {
412 /* PCI specific entry found in MP table */
413 if (airq != cfg->intline) {
414 undirect_pci_irq(cfg->intline);
415 cfg->intline = airq;
416 }
417 } else {
418 /*
419 * PCI interrupts might be redirected to the
420 * ISA bus according to some MP tables. Use the
421 * same methods as used by the ISA devices
422 * devices to find the proper IOAPIC int pin.
423 */
424 airq = isa_apic_irq(cfg->intline);
425 if ((airq >= 0) && (airq != cfg->intline)) {
426 /* XXX: undirect_pci_irq() ? */
427 undirect_isa_irq(cfg->intline);
428 cfg->intline = airq;
429 }
430 }
431 }
432#endif /* APIC_IO */
433
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434 cfg->mingnt = REG(PCIR_MINGNT, 1);
435 cfg->maxlat = REG(PCIR_MAXLAT, 1);
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436
437 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
438 cfg->hdrtype &= ~PCIM_MFDEV;
439
440 pci_fixancient(cfg);
4a5a2d63 441 pci_hdrtypedata(pcib, b, s, f, cfg);
e9d8f4df 442 pci_read_capabilities(pcib, cfg);
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443
444 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
445
446 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
447 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
448 devlist_entry->conf.pc_sel.pc_func = cfg->func;
449 devlist_entry->conf.pc_hdr = cfg->hdrtype;
450
451 devlist_entry->conf.pc_subvendor = cfg->subvendor;
452 devlist_entry->conf.pc_subdevice = cfg->subdevice;
453 devlist_entry->conf.pc_vendor = cfg->vendor;
454 devlist_entry->conf.pc_device = cfg->device;
455
456 devlist_entry->conf.pc_class = cfg->baseclass;
457 devlist_entry->conf.pc_subclass = cfg->subclass;
458 devlist_entry->conf.pc_progif = cfg->progif;
459 devlist_entry->conf.pc_revid = cfg->revid;
460
461 pci_numdevs++;
462 pci_generation++;
463 }
464 return (devlist_entry);
465#undef REG
466}
467
1361c4cd
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468static int
469pci_fixup_nextptr(int *nextptr0)
470{
471 int nextptr = *nextptr0;
472
473 /* "Next pointer" is only one byte */
474 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
475
476 if (nextptr & 0x3) {
477 /*
478 * PCI local bus spec 3.0:
479 *
480 * "... The bottom two bits of all pointers are reserved
481 * and must be implemented as 00b although software must
482 * mask them to allow for future uses of these bits ..."
483 */
484 if (bootverbose) {
485 kprintf("Illegal PCI extended capability "
486 "offset, fixup 0x%02x -> 0x%02x\n",
487 nextptr, nextptr & ~0x3);
488 }
489 nextptr &= ~0x3;
490 }
491 *nextptr0 = nextptr;
492
493 if (nextptr < 0x40) {
494 if (nextptr != 0) {
495 kprintf("Illegal PCI extended capability "
496 "offset 0x%02x", nextptr);
497 }
498 return 0;
499 }
500 return 1;
501}
502
8475d8bb
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503static void
504pci_read_cap_pmgt(device_t pcib, int ptr, pcicfgregs *cfg)
505{
506#define REG(n, w) \
507 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
508
509 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
510
511 if (pmgt->pp_cap)
512 return;
513
514 pmgt->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
515 pmgt->pp_status = ptr + PCIR_POWER_STATUS;
516 pmgt->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
517 /*
518 * XXX
519 * Following way may be used to to test whether
520 * 'data' register exists:
521 * if 'data_select' register of
522 * PCIR_POWER_STATUS(bits[12,9]) is read-only
523 * then 'data' register is _not_ implemented.
524 */
525 pmgt->pp_data = 0;
526
527#undef REG
528}
529
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SZ
530static int
531pcie_slotimpl(const pcicfgregs *cfg)
b4c0a845 532{
8c5b0f9a 533 const struct pcicfg_expr *expr = &cfg->expr;
b4c0a845
SZ
534 uint16_t port_type;
535
b4c0a845
SZ
536 /*
537 * Only version 1 can be parsed currently
538 */
539 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
8c5b0f9a 540 return 0;
b4c0a845
SZ
541
542 /*
b4c0a845
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543 * - Slot implemented bit is meaningful iff current port is
544 * root port or down stream port.
8c5b0f9a
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545 * - Testing for root port or down stream port is meanningful
546 * iff PCI configure has type 1 header.
b4c0a845 547 */
8c5b0f9a 548
b4c0a845 549 if (cfg->hdrtype != 1)
8c5b0f9a 550 return 0;
b4c0a845
SZ
551
552 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
8c5b0f9a
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553 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT)
554 return 0;
b4c0a845
SZ
555
556 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
8c5b0f9a
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557 return 0;
558
559 return 1;
560}
561
562static void
563pci_read_cap_expr(device_t pcib, int ptr, pcicfgregs *cfg)
564{
565#define REG(n, w) \
566 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
567
568 struct pcicfg_expr *expr = &cfg->expr;
569
570 expr->expr_ptr = ptr;
571 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
572
573 /*
574 * Only version 1 can be parsed currently
575 */
576 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
b4c0a845
SZ
577 return;
578
8c5b0f9a
SZ
579 /*
580 * Read slot capabilities. Slot capabilities exists iff
581 * current port's slot is implemented
582 */
583 if (pcie_slotimpl(cfg))
584 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
b4c0a845
SZ
585
586#undef REG
587}
588
984263bc 589static void
e9d8f4df 590pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
984263bc 591{
8475d8bb
SZ
592#define REG(n, w) \
593 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
594
1361c4cd 595 int nextptr, ptrptr;
984263bc 596
0c78fe3f
SZ
597 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
598 /* No capabilities */
599 return;
600 }
601
984263bc
MD
602 switch (cfg->hdrtype) {
603 case 0:
81c29ce4
SZ
604 case 1:
605 ptrptr = PCIR_CAP_PTR;
984263bc
MD
606 break;
607 case 2:
81c29ce4 608 ptrptr = PCIR_CAP_PTR_2;
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MD
609 break;
610 default:
0c78fe3f 611 return; /* No capabilities support */
984263bc 612 }
0c78fe3f 613 nextptr = REG(ptrptr, 1);
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MD
614
615 /*
616 * Read capability entries.
617 */
1361c4cd
SZ
618 while (pci_fixup_nextptr(&nextptr)) {
619 int ptr = nextptr;
984263bc
MD
620
621 /* Process this entry */
2f3ceba1 622 switch (REG(ptr + PCICAP_ID, 1)) {
81c29ce4 623 case PCIY_PMG: /* PCI power management */
8475d8bb 624 pci_read_cap_pmgt(pcib, ptr, cfg);
984263bc 625 break;
c7e4e7eb
SZ
626 case PCIY_PCIX: /* PCI-X */
627 cfg->pcixcap_ptr = ptr;
628 break;
b4c0a845
SZ
629 case PCIY_EXPRESS: /* PCI Express */
630 pci_read_cap_expr(pcib, ptr, cfg);
631 break;
0254566f
SZ
632 case PCIY_VPD: /* Vital Product Data */
633 cfg->vpdcap_ptr = ptr;
634 break;
984263bc
MD
635 default:
636 break;
637 }
1361c4cd
SZ
638
639 /* Find the next entry */
2f3ceba1 640 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
984263bc 641 }
8475d8bb 642
984263bc
MD
643#undef REG
644}
645
984263bc
MD
646/* free pcicfgregs structure and all depending data structures */
647
22457186 648int
984263bc
MD
649pci_freecfg(struct pci_devinfo *dinfo)
650{
651 struct devlist *devlist_head;
652
653 devlist_head = &pci_devq;
654
655 if (dinfo->cfg.hdrspec != NULL)
efda3bd0 656 kfree(dinfo->cfg.hdrspec, M_DEVBUF);
984263bc
MD
657 /* XXX this hasn't been tested */
658 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
efda3bd0 659 kfree(dinfo, M_DEVBUF);
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MD
660
661 /* increment the generation count */
662 pci_generation++;
663
664 /* we're losing one device */
665 pci_numdevs--;
666 return (0);
667}
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MD
668
669
670/*
671 * PCI power manangement
672 */
e126caf1 673int
984263bc
MD
674pci_set_powerstate_method(device_t dev, device_t child, int state)
675{
676 struct pci_devinfo *dinfo = device_get_ivars(child);
677 pcicfgregs *cfg = &dinfo->cfg;
f4754a59
HT
678 uint16_t status;
679 int result, oldstate, highest, delay;
984263bc 680
f4754a59
HT
681 if (cfg->pmgt.pp_cap == 0)
682 return (EOPNOTSUPP);
683
684 /*
685 * Optimize a no state change request away. While it would be OK to
686 * write to the hardware in theory, some devices have shown odd
687 * behavior when going from D3 -> D3.
688 */
689 oldstate = pci_get_powerstate(child);
690 if (oldstate == state)
691 return (0);
692
693 /*
694 * The PCI power management specification states that after a state
695 * transition between PCI power states, system software must
696 * guarantee a minimal delay before the function accesses the device.
697 * Compute the worst case delay that we need to guarantee before we
698 * access the device. Many devices will be responsive much more
699 * quickly than this delay, but there are some that don't respond
700 * instantly to state changes. Transitions to/from D3 state require
701 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
702 * is done below with DELAY rather than a sleeper function because
703 * this function can be called from contexts where we cannot sleep.
704 */
705 highest = (oldstate > state) ? oldstate : state;
706 if (highest == PCI_POWERSTATE_D3)
707 delay = 10000;
708 else if (highest == PCI_POWERSTATE_D2)
709 delay = 200;
710 else
711 delay = 0;
712 status = PCI_READ_CONFIG(dev, child, cfg->pmgt.pp_status, 2)
713 & ~PCIM_PSTAT_DMASK;
714 result = 0;
715 switch (state) {
716 case PCI_POWERSTATE_D0:
717 status |= PCIM_PSTAT_D0;
718 break;
719 case PCI_POWERSTATE_D1:
720 if ((cfg->pmgt.pp_cap & PCIM_PCAP_D1SUPP) == 0)
721 return (EOPNOTSUPP);
722 status |= PCIM_PSTAT_D1;
723 break;
724 case PCI_POWERSTATE_D2:
725 if ((cfg->pmgt.pp_cap & PCIM_PCAP_D2SUPP) == 0)
726 return (EOPNOTSUPP);
727 status |= PCIM_PSTAT_D2;
728 break;
729 case PCI_POWERSTATE_D3:
730 status |= PCIM_PSTAT_D3;
731 break;
732 default:
733 return (EINVAL);
984263bc 734 }
f4754a59
HT
735
736 if (bootverbose)
737 kprintf(
738 "pci%d:%d:%d: Transition from D%d to D%d\n",
739 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func,
740 oldstate, state);
741
742 PCI_WRITE_CONFIG(dev, child, cfg->pmgt.pp_status, status, 2);
743 if (delay)
744 DELAY(delay);
745 return (0);
984263bc
MD
746}
747
e126caf1 748int
984263bc
MD
749pci_get_powerstate_method(device_t dev, device_t child)
750{
751 struct pci_devinfo *dinfo = device_get_ivars(child);
752 pcicfgregs *cfg = &dinfo->cfg;
f4754a59 753 uint16_t status;
984263bc
MD
754 int result;
755
f4754a59
HT
756 if (cfg->pmgt.pp_cap != 0) {
757 status = PCI_READ_CONFIG(dev, child, cfg->pmgt.pp_status, 2);
984263bc
MD
758 switch (status & PCIM_PSTAT_DMASK) {
759 case PCIM_PSTAT_D0:
760 result = PCI_POWERSTATE_D0;
761 break;
762 case PCIM_PSTAT_D1:
763 result = PCI_POWERSTATE_D1;
764 break;
765 case PCIM_PSTAT_D2:
766 result = PCI_POWERSTATE_D2;
767 break;
768 case PCIM_PSTAT_D3:
769 result = PCI_POWERSTATE_D3;
770 break;
771 default:
772 result = PCI_POWERSTATE_UNKNOWN;
773 break;
774 }
775 } else {
776 /* No support, device is always at D0 */
777 result = PCI_POWERSTATE_D0;
778 }
f4754a59 779 return (result);
984263bc
MD
780}
781
782/*
783 * Some convenience functions for PCI device drivers.
784 */
785
786static __inline void
787pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
788{
789 u_int16_t command;
790
791 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
792 command |= bit;
793 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
794}
795
796static __inline void
797pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
798{
799 u_int16_t command;
800
801 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
802 command &= ~bit;
803 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
804}
805
e126caf1 806int
984263bc
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807pci_enable_busmaster_method(device_t dev, device_t child)
808{
809 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 810 return(0);
984263bc
MD
811}
812
e126caf1 813int
984263bc
MD
814pci_disable_busmaster_method(device_t dev, device_t child)
815{
816 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 817 return(0);
984263bc
MD
818}
819
e126caf1 820int
984263bc
MD
821pci_enable_io_method(device_t dev, device_t child, int space)
822{
e126caf1
MD
823 uint16_t command;
824 uint16_t bit;
825 char *error;
826
827 bit = 0;
828 error = NULL;
829
984263bc
MD
830 switch(space) {
831 case SYS_RES_IOPORT:
e126caf1
MD
832 bit = PCIM_CMD_PORTEN;
833 error = "port";
984263bc
MD
834 break;
835 case SYS_RES_MEMORY:
e126caf1
MD
836 bit = PCIM_CMD_MEMEN;
837 error = "memory";
984263bc 838 break;
e126caf1
MD
839 default:
840 return(EINVAL);
984263bc 841 }
e126caf1
MD
842 pci_set_command_bit(dev, child, bit);
843 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
844 if (command & bit)
845 return(0);
846 device_printf(child, "failed to enable %s mapping!\n", error);
847 return(ENXIO);
984263bc
MD
848}
849
e126caf1 850int
984263bc
MD
851pci_disable_io_method(device_t dev, device_t child, int space)
852{
e126caf1
MD
853 uint16_t command;
854 uint16_t bit;
855 char *error;
856
857 bit = 0;
858 error = NULL;
859
984263bc
MD
860 switch(space) {
861 case SYS_RES_IOPORT:
e126caf1
MD
862 bit = PCIM_CMD_PORTEN;
863 error = "port";
984263bc
MD
864 break;
865 case SYS_RES_MEMORY:
e126caf1
MD
866 bit = PCIM_CMD_MEMEN;
867 error = "memory";
984263bc 868 break;
e126caf1
MD
869 default:
870 return (EINVAL);
984263bc 871 }
e126caf1
MD
872 pci_clear_command_bit(dev, child, bit);
873 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
874 if (command & bit) {
875 device_printf(child, "failed to disable %s mapping!\n", error);
876 return (ENXIO);
877 }
878 return (0);
984263bc
MD
879}
880
881/*
882 * This is the user interface to PCI configuration space.
883 */
884
885static int
fef8985e 886pci_open(struct dev_open_args *ap)
984263bc 887{
fef8985e 888 if ((ap->a_oflags & FWRITE) && securelevel > 0) {
984263bc
MD
889 return EPERM;
890 }
891 return 0;
892}
893
894static int
fef8985e 895pci_close(struct dev_close_args *ap)
984263bc
MD
896{
897 return 0;
898}
899
900/*
901 * Match a single pci_conf structure against an array of pci_match_conf
902 * structures. The first argument, 'matches', is an array of num_matches
903 * pci_match_conf structures. match_buf is a pointer to the pci_conf
904 * structure that will be compared to every entry in the matches array.
905 * This function returns 1 on failure, 0 on success.
906 */
907static int
908pci_conf_match(struct pci_match_conf *matches, int num_matches,
909 struct pci_conf *match_buf)
910{
911 int i;
912
913 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
914 return(1);
915
916 for (i = 0; i < num_matches; i++) {
917 /*
918 * I'm not sure why someone would do this...but...
919 */
920 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
921 continue;
922
923 /*
924 * Look at each of the match flags. If it's set, do the
925 * comparison. If the comparison fails, we don't have a
926 * match, go on to the next item if there is one.
927 */
928 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
929 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
930 continue;
931
932 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
933 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
934 continue;
935
936 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
937 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
938 continue;
939
940 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
941 && (match_buf->pc_vendor != matches[i].pc_vendor))
942 continue;
943
944 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
945 && (match_buf->pc_device != matches[i].pc_device))
946 continue;
947
948 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
949 && (match_buf->pc_class != matches[i].pc_class))
950 continue;
951
952 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
953 && (match_buf->pd_unit != matches[i].pd_unit))
954 continue;
955
956 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
957 && (strncmp(matches[i].pd_name, match_buf->pd_name,
958 sizeof(match_buf->pd_name)) != 0))
959 continue;
960
961 return(0);
962 }
963
964 return(1);
965}
966
967/*
968 * Locate the parent of a PCI device by scanning the PCI devlist
969 * and return the entry for the parent.
970 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
971 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
972 */
973
974pcicfgregs *
975pci_devlist_get_parent(pcicfgregs *cfg)
976{
977 struct devlist *devlist_head;
978 struct pci_devinfo *dinfo;
979 pcicfgregs *bridge_cfg;
980 int i;
981
982 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
983
984 /* If the device is on PCI bus 0, look for the host */
985 if (cfg->bus == 0) {
986 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
987 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
988 bridge_cfg = &dinfo->cfg;
989 if (bridge_cfg->baseclass == PCIC_BRIDGE
990 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
991 && bridge_cfg->bus == cfg->bus) {
992 return bridge_cfg;
993 }
994 }
995 }
996
997 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
998 if (cfg->bus > 0) {
999 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
1000 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
1001 bridge_cfg = &dinfo->cfg;
1002 if (bridge_cfg->baseclass == PCIC_BRIDGE
1003 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
1004 && bridge_cfg->secondarybus == cfg->bus) {
1005 return bridge_cfg;
1006 }
1007 }
1008 }
1009
1010 return NULL;
1011}
1012
1013static int
fef8985e 1014pci_ioctl(struct dev_ioctl_args *ap)
984263bc 1015{
4a5a2d63 1016 device_t pci, pcib;
984263bc
MD
1017 struct pci_io *io;
1018 const char *name;
1019 int error;
1020
fef8985e 1021 if (!(ap->a_fflag & FWRITE))
984263bc
MD
1022 return EPERM;
1023
fef8985e 1024 switch(ap->a_cmd) {
984263bc
MD
1025 case PCIOCGETCONF:
1026 {
1027 struct pci_devinfo *dinfo;
1028 struct pci_conf_io *cio;
1029 struct devlist *devlist_head;
1030 struct pci_match_conf *pattern_buf;
1031 int num_patterns;
1032 size_t iolen;
1033 int ionum, i;
1034
fef8985e 1035 cio = (struct pci_conf_io *)ap->a_data;
984263bc
MD
1036
1037 num_patterns = 0;
1038 dinfo = NULL;
1039
1040 /*
1041 * Hopefully the user won't pass in a null pointer, but it
1042 * can't hurt to check.
1043 */
1044 if (cio == NULL) {
1045 error = EINVAL;
1046 break;
1047 }
1048
1049 /*
1050 * If the user specified an offset into the device list,
1051 * but the list has changed since they last called this
1052 * ioctl, tell them that the list has changed. They will
1053 * have to get the list from the beginning.
1054 */
1055 if ((cio->offset != 0)
1056 && (cio->generation != pci_generation)){
1057 cio->num_matches = 0;
1058 cio->status = PCI_GETCONF_LIST_CHANGED;
1059 error = 0;
1060 break;
1061 }
1062
1063 /*
1064 * Check to see whether the user has asked for an offset
1065 * past the end of our list.
1066 */
1067 if (cio->offset >= pci_numdevs) {
1068 cio->num_matches = 0;
1069 cio->status = PCI_GETCONF_LAST_DEVICE;
1070 error = 0;
1071 break;
1072 }
1073
1074 /* get the head of the device queue */
1075 devlist_head = &pci_devq;
1076
1077 /*
1078 * Determine how much room we have for pci_conf structures.
1079 * Round the user's buffer size down to the nearest
1080 * multiple of sizeof(struct pci_conf) in case the user
1081 * didn't specify a multiple of that size.
1082 */
1083 iolen = min(cio->match_buf_len -
1084 (cio->match_buf_len % sizeof(struct pci_conf)),
1085 pci_numdevs * sizeof(struct pci_conf));
1086
1087 /*
1088 * Since we know that iolen is a multiple of the size of
1089 * the pciconf union, it's okay to do this.
1090 */
1091 ionum = iolen / sizeof(struct pci_conf);
1092
1093 /*
1094 * If this test is true, the user wants the pci_conf
1095 * structures returned to match the supplied entries.
1096 */
1097 if ((cio->num_patterns > 0)
1098 && (cio->pat_buf_len > 0)) {
1099 /*
1100 * pat_buf_len needs to be:
1101 * num_patterns * sizeof(struct pci_match_conf)
1102 * While it is certainly possible the user just
1103 * allocated a large buffer, but set the number of
1104 * matches correctly, it is far more likely that
1105 * their kernel doesn't match the userland utility
1106 * they're using. It's also possible that the user
1107 * forgot to initialize some variables. Yes, this
1108 * may be overly picky, but I hazard to guess that
1109 * it's far more likely to just catch folks that
1110 * updated their kernel but not their userland.
1111 */
1112 if ((cio->num_patterns *
1113 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
1114 /* The user made a mistake, return an error*/
1115 cio->status = PCI_GETCONF_ERROR;
85f8e2ea 1116 kprintf("pci_ioctl: pat_buf_len %d != "
984263bc
MD
1117 "num_patterns (%d) * sizeof(struct "
1118 "pci_match_conf) (%d)\npci_ioctl: "
1119 "pat_buf_len should be = %d\n",
1120 cio->pat_buf_len, cio->num_patterns,
1121 (int)sizeof(struct pci_match_conf),
1122 (int)sizeof(struct pci_match_conf) *
1123 cio->num_patterns);
85f8e2ea 1124 kprintf("pci_ioctl: do your headers match your "
984263bc
MD
1125 "kernel?\n");
1126 cio->num_matches = 0;
1127 error = EINVAL;
1128 break;
1129 }
1130
1131 /*
1132 * Check the user's buffer to make sure it's readable.
1133 */
1134 if (!useracc((caddr_t)cio->patterns,
1135 cio->pat_buf_len, VM_PROT_READ)) {
85f8e2ea 1136 kprintf("pci_ioctl: pattern buffer %p, "
984263bc
MD
1137 "length %u isn't user accessible for"
1138 " READ\n", cio->patterns,
1139 cio->pat_buf_len);
1140 error = EACCES;
1141 break;
1142 }
1143 /*
1144 * Allocate a buffer to hold the patterns.
1145 */
efda3bd0 1146 pattern_buf = kmalloc(cio->pat_buf_len, M_TEMP,
984263bc
MD
1147 M_WAITOK);
1148 error = copyin(cio->patterns, pattern_buf,
1149 cio->pat_buf_len);
1150 if (error != 0)
1151 break;
1152 num_patterns = cio->num_patterns;
1153
1154 } else if ((cio->num_patterns > 0)
1155 || (cio->pat_buf_len > 0)) {
1156 /*
1157 * The user made a mistake, spit out an error.
1158 */
1159 cio->status = PCI_GETCONF_ERROR;
1160 cio->num_matches = 0;
85f8e2ea 1161 kprintf("pci_ioctl: invalid GETCONF arguments\n");
984263bc
MD
1162 error = EINVAL;
1163 break;
1164 } else
1165 pattern_buf = NULL;
1166
1167 /*
1168 * Make sure we can write to the match buffer.
1169 */
1170 if (!useracc((caddr_t)cio->matches,
1171 cio->match_buf_len, VM_PROT_WRITE)) {
85f8e2ea 1172 kprintf("pci_ioctl: match buffer %p, length %u "
984263bc
MD
1173 "isn't user accessible for WRITE\n",
1174 cio->matches, cio->match_buf_len);
1175 error = EACCES;
1176 break;
1177 }
1178
1179 /*
1180 * Go through the list of devices and copy out the devices
1181 * that match the user's criteria.
1182 */
1183 for (cio->num_matches = 0, error = 0, i = 0,
1184 dinfo = STAILQ_FIRST(devlist_head);
1185 (dinfo != NULL) && (cio->num_matches < ionum)
1186 && (error == 0) && (i < pci_numdevs);
1187 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
1188
1189 if (i < cio->offset)
1190 continue;
1191
1192 /* Populate pd_name and pd_unit */
1193 name = NULL;
1194 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
1195 name = device_get_name(dinfo->cfg.dev);
1196 if (name) {
1197 strncpy(dinfo->conf.pd_name, name,
1198 sizeof(dinfo->conf.pd_name));
1199 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
1200 dinfo->conf.pd_unit =
1201 device_get_unit(dinfo->cfg.dev);
1202 }
1203
1204 if ((pattern_buf == NULL) ||
1205 (pci_conf_match(pattern_buf, num_patterns,
1206 &dinfo->conf) == 0)) {
1207
1208 /*
1209 * If we've filled up the user's buffer,
1210 * break out at this point. Since we've
1211 * got a match here, we'll pick right back
1212 * up at the matching entry. We can also
1213 * tell the user that there are more matches
1214 * left.
1215 */
1216 if (cio->num_matches >= ionum)
1217 break;
1218
1219 error = copyout(&dinfo->conf,
1220 &cio->matches[cio->num_matches],
1221 sizeof(struct pci_conf));
1222 cio->num_matches++;
1223 }
1224 }
1225
1226 /*
1227 * Set the pointer into the list, so if the user is getting
1228 * n records at a time, where n < pci_numdevs,
1229 */
1230 cio->offset = i;
1231
1232 /*
1233 * Set the generation, the user will need this if they make
1234 * another ioctl call with offset != 0.
1235 */
1236 cio->generation = pci_generation;
1237
1238 /*
1239 * If this is the last device, inform the user so he won't
1240 * bother asking for more devices. If dinfo isn't NULL, we
1241 * know that there are more matches in the list because of
1242 * the way the traversal is done.
1243 */
1244 if (dinfo == NULL)
1245 cio->status = PCI_GETCONF_LAST_DEVICE;
1246 else
1247 cio->status = PCI_GETCONF_MORE_DEVS;
1248
1249 if (pattern_buf != NULL)
efda3bd0 1250 kfree(pattern_buf, M_TEMP);
984263bc
MD
1251
1252 break;
1253 }
1254 case PCIOCREAD:
fef8985e 1255 io = (struct pci_io *)ap->a_data;
984263bc 1256 switch(io->pi_width) {
984263bc
MD
1257 case 4:
1258 case 2:
1259 case 1:
4a5a2d63
JS
1260 /*
1261 * Assume that the user-level bus number is
1262 * actually the pciN instance number. We map
1263 * from that to the real pcib+bus combination.
1264 */
1265 pci = devclass_get_device(pci_devclass,
1266 io->pi_sel.pc_bus);
1267 if (pci) {
2581072f
MD
1268 /*
1269 * pci is the pci device and may contain
1270 * several children (for each function code).
1271 * The governing pci bus is the parent to
1272 * the pci device.
1273 */
1274 int b;
1275
4a5a2d63 1276 pcib = device_get_parent(pci);
2581072f 1277 b = pcib_get_bus(pcib);
4a5a2d63
JS
1278 io->pi_data =
1279 PCIB_READ_CONFIG(pcib,
1280 b,
1281 io->pi_sel.pc_dev,
1282 io->pi_sel.pc_func,
1283 io->pi_reg,
1284 io->pi_width);
1285 error = 0;
1286 } else {
1287 error = ENODEV;
1288 }
984263bc
MD
1289 break;
1290 default:
1291 error = ENODEV;
1292 break;
1293 }
1294 break;
1295
1296 case PCIOCWRITE:
fef8985e 1297 io = (struct pci_io *)ap->a_data;
984263bc 1298 switch(io->pi_width) {
984263bc
MD
1299 case 4:
1300 case 2:
1301 case 1:
4a5a2d63
JS
1302 /*
1303 * Assume that the user-level bus number is
1304 * actually the pciN instance number. We map
1305 * from that to the real pcib+bus combination.
1306 */
1307 pci = devclass_get_device(pci_devclass,
1308 io->pi_sel.pc_bus);
1309 if (pci) {
2581072f
MD
1310 /*
1311 * pci is the pci device and may contain
1312 * several children (for each function code).
1313 * The governing pci bus is the parent to
1314 * the pci device.
1315 */
1316 int b;
1317
4a5a2d63 1318 pcib = device_get_parent(pci);
2581072f 1319 b = pcib_get_bus(pcib);
4a5a2d63
JS
1320 PCIB_WRITE_CONFIG(pcib,
1321 b,
1322 io->pi_sel.pc_dev,
1323 io->pi_sel.pc_func,
1324 io->pi_reg,
1325 io->pi_data,
1326 io->pi_width);
1327 error = 0;
1328 } else {
1329 error = ENODEV;
1330 }
984263bc
MD
1331 break;
1332 default:
1333 error = ENODEV;
1334 break;
1335 }
1336 break;
1337
1338 default:
1339 error = ENOTTY;
1340 break;
1341 }
1342
1343 return (error);
1344}
1345
1346#define PCI_CDEV 78
1347
fef8985e
MD
1348static struct dev_ops pcic_ops = {
1349 { "pci", PCI_CDEV, 0 },
1350 .d_open = pci_open,
1351 .d_close = pci_close,
1352 .d_ioctl = pci_ioctl,
984263bc
MD
1353};
1354
1355#include "pci_if.h"
1356
984263bc
MD
1357/*
1358 * New style pci driver. Parent device is either a pci-host-bridge or a
1359 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1360 */
ed1bd994
MD
1361const char *
1362pci_class_to_string(int baseclass)
1363{
1364 const char *name;
1365
1366 switch(baseclass) {
1367 case PCIC_OLD:
1368 name = "OLD";
1369 break;
1370 case PCIC_STORAGE:
1371 name = "STORAGE";
1372 break;
1373 case PCIC_NETWORK:
1374 name = "NETWORK";
1375 break;
1376 case PCIC_DISPLAY:
1377 name = "DISPLAY";
1378 break;
1379 case PCIC_MULTIMEDIA:
1380 name = "MULTIMEDIA";
1381 break;
1382 case PCIC_MEMORY:
1383 name = "MEMORY";
1384 break;
1385 case PCIC_BRIDGE:
1386 name = "BRIDGE";
1387 break;
1388 case PCIC_SIMPLECOMM:
1389 name = "SIMPLECOMM";
1390 break;
1391 case PCIC_BASEPERIPH:
1392 name = "BASEPERIPH";
1393 break;
1394 case PCIC_INPUTDEV:
1395 name = "INPUTDEV";
1396 break;
1397 case PCIC_DOCKING:
1398 name = "DOCKING";
1399 break;
1400 case PCIC_PROCESSOR:
1401 name = "PROCESSOR";
1402 break;
1403 case PCIC_SERIALBUS:
1404 name = "SERIALBUS";
1405 break;
1406 case PCIC_WIRELESS:
1407 name = "WIRELESS";
1408 break;
1409 case PCIC_I2O:
1410 name = "I20";
1411 break;
1412 case PCIC_SATELLITE:
1413 name = "SATELLITE";
1414 break;
1415 case PCIC_CRYPTO:
1416 name = "CRYPTO";
1417 break;
1418 case PCIC_SIGPROC:
1419 name = "SIGPROC";
1420 break;
1421 case PCIC_OTHER:
1422 name = "OTHER";
1423 break;
1424 default:
1425 name = "?";
1426 break;
1427 }
1428 return(name);
1429}
984263bc 1430
b4c0a845
SZ
1431static void
1432pci_print_verbose_expr(const pcicfgregs *cfg)
1433{
1434 const struct pcicfg_expr *expr = &cfg->expr;
1435 const char *port_name;
1436 uint16_t port_type;
1437
1438 if (!bootverbose)
1439 return;
1440
1441 if (expr->expr_ptr == 0) /* No PCI Express capability */
1442 return;
1443
1444 kprintf("\tPCI Express ver.%d cap=0x%04x",
1445 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
1446 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
1447 goto back;
1448
1449 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
1450
1451 switch (port_type) {
8c5b0f9a 1452 case PCIE_END_POINT:
b4c0a845
SZ
1453 port_name = "DEVICE";
1454 break;
8c5b0f9a 1455 case PCIE_LEG_END_POINT:
b4c0a845
SZ
1456 port_name = "LEGDEV";
1457 break;
8c5b0f9a 1458 case PCIE_ROOT_PORT:
b4c0a845
SZ
1459 port_name = "ROOT";
1460 break;
8c5b0f9a 1461 case PCIE_UP_STREAM_PORT:
b4c0a845
SZ
1462 port_name = "UPSTREAM";
1463 break;
8c5b0f9a 1464 case PCIE_DOWN_STREAM_PORT:
b4c0a845
SZ
1465 port_name = "DOWNSTRM";
1466 break;
8c5b0f9a 1467 case PCIE_PCIE2PCI_BRIDGE:
b4c0a845
SZ
1468 port_name = "PCIE2PCI";
1469 break;
8c5b0f9a 1470 case PCIE_PCI2PCIE_BRIDGE:
b4c0a845
SZ
1471 port_name = "PCI2PCIE";
1472 break;
1473 default:
1474 port_name = NULL;
1475 break;
1476 }
8c5b0f9a
SZ
1477 if ((port_type == PCIE_ROOT_PORT ||
1478 port_type == PCIE_DOWN_STREAM_PORT) &&
b4c0a845
SZ
1479 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
1480 port_name = NULL;
1481 if (port_name != NULL)
1482 kprintf("[%s]", port_name);
1483
8c5b0f9a 1484 if (pcie_slotimpl(cfg)) {
b4c0a845
SZ
1485 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
1486 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
1487 kprintf("[HOTPLUG]");
1488 }
1489back:
1490 kprintf("\n");
1491}
1492
22457186 1493void
984263bc
MD
1494pci_print_verbose(struct pci_devinfo *dinfo)
1495{
1496 if (bootverbose) {
1497 pcicfgregs *cfg = &dinfo->cfg;
1498
85f8e2ea 1499 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
984263bc 1500 cfg->vendor, cfg->device, cfg->revid);
85f8e2ea 1501 kprintf("\tbus=%d, slot=%d, func=%d\n",
4a5a2d63 1502 cfg->bus, cfg->slot, cfg->func);
85f8e2ea 1503 kprintf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
ed1bd994 1504 pci_class_to_string(cfg->baseclass),
984263bc
MD
1505 cfg->baseclass, cfg->subclass, cfg->progif,
1506 cfg->hdrtype, cfg->mfdev);
85f8e2ea 1507 kprintf("\tsubordinatebus=%x \tsecondarybus=%x\n",
984263bc
MD
1508 cfg->subordinatebus, cfg->secondarybus);
1509#ifdef PCI_DEBUG
85f8e2ea 1510 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
984263bc 1511 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
85f8e2ea 1512 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
984263bc
MD
1513 cfg->lattimer, cfg->lattimer * 30,
1514 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1515#endif /* PCI_DEBUG */
1516 if (cfg->intpin > 0)
85f8e2ea 1517 kprintf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
b4c0a845
SZ
1518
1519 pci_print_verbose_expr(cfg);
984263bc
MD
1520 }
1521}
1522
1523static int
4a5a2d63 1524pci_porten(device_t pcib, int b, int s, int f)
984263bc 1525{
4a5a2d63
JS
1526 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1527 & PCIM_CMD_PORTEN) != 0;
984263bc
MD
1528}
1529
1530static int
4a5a2d63 1531pci_memen(device_t pcib, int b, int s, int f)
984263bc 1532{
4a5a2d63
JS
1533 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1534 & PCIM_CMD_MEMEN) != 0;
984263bc
MD
1535}
1536
1537/*
1538 * Add a resource based on a pci map register. Return 1 if the map
1539 * register is a 32bit map register or 2 if it is a 64bit register.
1540 */
1541static int
4a5a2d63
JS
1542pci_add_map(device_t pcib, int b, int s, int f, int reg,
1543 struct resource_list *rl)
984263bc 1544{
984263bc
MD
1545 u_int32_t map;
1546 u_int64_t base;
1547 u_int8_t ln2size;
1548 u_int8_t ln2range;
1549 u_int32_t testval;
4a5a2d63
JS
1550
1551
1552#ifdef PCI_ENABLE_IO_MODES
1553 u_int16_t cmd;
1554#endif
984263bc
MD
1555 int type;
1556
4a5a2d63 1557 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
984263bc
MD
1558
1559 if (map == 0 || map == 0xffffffff)
1560 return 1; /* skip invalid entry */
1561
4a5a2d63
JS
1562 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1563 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1564 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
984263bc
MD
1565
1566 base = pci_mapbase(map);
1567 if (pci_maptype(map) & PCI_MAPMEM)
1568 type = SYS_RES_MEMORY;
1569 else
1570 type = SYS_RES_IOPORT;
1571 ln2size = pci_mapsize(testval);
1572 ln2range = pci_maprange(testval);
1573 if (ln2range == 64) {
1574 /* Read the other half of a 64bit map register */
4a5a2d63 1575 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
984263bc
MD
1576 }
1577
984263bc
MD
1578 /*
1579 * This code theoretically does the right thing, but has
1580 * undesirable side effects in some cases where
1581 * peripherals respond oddly to having these bits
1582 * enabled. Leave them alone by default.
1583 */
1584#ifdef PCI_ENABLE_IO_MODES
4a5a2d63
JS
1585 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1586 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1587 cmd |= PCIM_CMD_PORTEN;
1588 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc 1589 }
4a5a2d63
JS
1590 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1591 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1592 cmd |= PCIM_CMD_MEMEN;
1593 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc
MD
1594 }
1595#else
4a5a2d63 1596 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
984263bc 1597 return 1;
4a5a2d63 1598 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
984263bc
MD
1599 return 1;
1600#endif
1601
1602 resource_list_add(rl, type, reg,
1603 base, base + (1 << ln2size) - 1,
1604 (1 << ln2size));
1605
1606 if (bootverbose) {
85f8e2ea 1607 kprintf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
984263bc
MD
1608 reg, pci_maptype(base), ln2range,
1609 (unsigned int) base, ln2size);
1610 }
1611
1612 return (ln2range == 64) ? 2 : 1;
1613}
1614
201eb0a7
TS
1615#ifdef PCI_MAP_FIXUP
1616/*
1617 * For ATA devices we need to decide early on what addressing mode to use.
1618 * Legacy demands that the primary and secondary ATA ports sits on the
1619 * same addresses that old ISA hardware did. This dictates that we use
1620 * those addresses and ignore the BARs if we cannot set PCI native
1621 * addressing mode.
1622 */
1623static void
1624pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, int s, int f,
1625 struct resource_list *rl)
1626{
1627 int rid, type, progif;
1628#if 0
1629 /* if this device supports PCI native addressing use it */
1630 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1631 if ((progif &0x8a) == 0x8a) {
1632 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
1633 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
85f8e2ea 1634 kprintf("Trying ATA native PCI addressing mode\n");
201eb0a7
TS
1635 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
1636 }
1637 }
1638#endif
1639 /*
1640 * Because we return any preallocated resources for lazy
1641 * allocation for PCI devices in pci_alloc_resource(), we can
1642 * allocate our legacy resources here.
1643 */
1644 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1645 type = SYS_RES_IOPORT;
1646 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
1647 pci_add_map(pcib, b, s, f, PCIR_BAR(0), rl);
1648 pci_add_map(pcib, b, s, f, PCIR_BAR(1), rl);
1649 } else {
1650 rid = PCIR_BAR(0);
1651 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
1652 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
1653 0);
1654 rid = PCIR_BAR(1);
1655 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
1656 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
1657 0);
1658 }
1659 if (progif & PCIP_STORAGE_IDE_MODESEC) {
1660 pci_add_map(pcib, b, s, f, PCIR_BAR(2), rl);
1661 pci_add_map(pcib, b, s, f, PCIR_BAR(3), rl);
1662 } else {
1663 rid = PCIR_BAR(2);
1664 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
1665 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
1666 0);
1667 rid = PCIR_BAR(3);
1668 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
1669 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
1670 0);
1671 }
1672 pci_add_map(pcib, b, s, f, PCIR_BAR(4), rl);
1673 pci_add_map(pcib, b, s, f, PCIR_BAR(5), rl);
1674}
1675#endif /* PCI_MAP_FIXUP */
1676
984263bc 1677static void
e126caf1 1678pci_add_resources(device_t pcib, device_t bus, device_t dev)
984263bc
MD
1679{
1680 struct pci_devinfo *dinfo = device_get_ivars(dev);
4a5a2d63 1681 pcicfgregs *cfg = &dinfo->cfg;
984263bc
MD
1682 struct resource_list *rl = &dinfo->resources;
1683 struct pci_quirk *q;
e126caf1
MD
1684 int b, i, f, s;
1685#if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */
1686 int irq;
1687#endif
984263bc 1688
e126caf1
MD
1689 b = cfg->bus;
1690 s = cfg->slot;
1691 f = cfg->func;
201eb0a7
TS
1692#ifdef PCI_MAP_FIXUP
1693 /* atapci devices in legacy mode need special map treatment */
1694 if ((pci_get_class(dev) == PCIC_STORAGE) &&
1695 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
d3d1ea7a
MD
1696 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
1697 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
1698 !pci_read_config(dev, PCIR_BAR(2), 4))) )
201eb0a7
TS
1699 pci_ata_maps(pcib, bus, dev, b, s, f, rl);
1700 else
1701#endif /* PCI_MAP_FIXUP */
1702 for (i = 0; i < cfg->nummaps;) {
1703 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl);
1704 }
984263bc
MD
1705
1706 for (q = &pci_quirks[0]; q->devid; q++) {
1707 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1708 && q->type == PCI_QUIRK_MAP_REG)
4a5a2d63 1709 pci_add_map(pcib, b, s, f, q->arg1, rl);
984263bc
MD
1710 }
1711
1712 if (cfg->intpin > 0 && cfg->intline != 255)
1713 resource_list_add(rl, SYS_RES_IRQ, 0,
1714 cfg->intline, cfg->intline, 1);
1715}
1716
e126caf1
MD
1717void
1718pci_add_children(device_t dev, int busno, size_t dinfo_size)
984263bc 1719{
e126caf1 1720#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
4a5a2d63 1721 device_t pcib = device_get_parent(dev);
e126caf1 1722 struct pci_devinfo *dinfo;
4a5a2d63 1723 int maxslots;
e126caf1
MD
1724 int s, f, pcifunchigh;
1725 uint8_t hdrtype;
1726
1727 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo));
984263bc 1728
4a5a2d63 1729 maxslots = PCIB_MAXSLOTS(pcib);
984263bc 1730
57e943f7 1731 for (s = 0; s <= maxslots; s++) {
e126caf1
MD
1732 pcifunchigh = 0;
1733 f = 0;
1734 hdrtype = REG(PCIR_HDRTYPE, 1);
1735 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1736 continue;
1737 if (hdrtype & PCIM_MFDEV)
1738 pcifunchigh = PCI_FUNCMAX;
5e658043 1739 for (f = 0; f <= pcifunchigh; f++) {
e126caf1 1740 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
984263bc 1741 if (dinfo != NULL) {
e126caf1 1742 pci_add_child(dev, dinfo);
984263bc
MD
1743 }
1744 }
1745 }
e126caf1
MD
1746#undef REG
1747}
1748
2581072f
MD
1749/*
1750 * The actual PCI child that we add has a NULL driver whos parent
1751 * device will be "pci". The child contains the ivars, not the parent.
1752 */
e126caf1
MD
1753void
1754pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1755{
1756 device_t pcib;
1757
1758 pcib = device_get_parent(bus);
1759 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1760 device_set_ivars(dinfo->cfg.dev, dinfo);
638744c5
HT
1761 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
1762 pci_cfg_restore(dinfo->cfg.dev, dinfo);
e126caf1
MD
1763 pci_add_resources(pcib, bus, dinfo->cfg.dev);
1764 pci_print_verbose(dinfo);
984263bc
MD
1765}
1766
c01b8d84
MD
1767/*
1768 * Probe the PCI bus. Note: probe code is not supposed to add children
1769 * or call attach.
1770 */
984263bc 1771static int
4a5a2d63 1772pci_probe(device_t dev)
984263bc 1773{
984263bc 1774 device_set_desc(dev, "PCI bus");
4a5a2d63 1775
c01b8d84
MD
1776 /* Allow other subclasses to override this driver */
1777 return(-1000);
984263bc
MD
1778}
1779
e126caf1
MD
1780static int
1781pci_attach(device_t dev)
1782{
1783 int busno;
e4c9c0c8
MD
1784 int lunit = device_get_unit(dev);
1785
fef8985e
MD
1786 dev_ops_add(&pcic_ops, -1, lunit);
1787 make_dev(&pcic_ops, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit);
e126caf1
MD
1788
1789 /*
1790 * Since there can be multiple independantly numbered PCI
1791 * busses on some large alpha systems, we can't use the unit
1792 * number to decide what bus we are probing. We ask the parent
1793 * pcib what our bus number is.
2581072f
MD
1794 *
1795 * pcib_get_bus() must act on the pci bus device, not on the pci
1796 * device, because it uses badly hacked nexus-based ivars to
1797 * store and retrieve the physical bus number. XXX
e126caf1 1798 */
2581072f 1799 busno = pcib_get_bus(device_get_parent(dev));
e126caf1 1800 if (bootverbose)
ed1bd994 1801 device_printf(dev, "pci_attach() physical bus=%d\n", busno);
e126caf1
MD
1802
1803 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1804
1805 return (bus_generic_attach(dev));
1806}
1807
984263bc
MD
1808static int
1809pci_print_resources(struct resource_list *rl, const char *name, int type,
1810 const char *format)
1811{
1812 struct resource_list_entry *rle;
1813 int printed, retval;
1814
1815 printed = 0;
1816 retval = 0;
1817 /* Yes, this is kinda cheating */
1818 SLIST_FOREACH(rle, rl, link) {
1819 if (rle->type == type) {
1820 if (printed == 0)
85f8e2ea 1821 retval += kprintf(" %s ", name);
984263bc 1822 else if (printed > 0)
85f8e2ea 1823 retval += kprintf(",");
984263bc 1824 printed++;
85f8e2ea 1825 retval += kprintf(format, rle->start);
984263bc 1826 if (rle->count > 1) {
85f8e2ea
SW
1827 retval += kprintf("-");
1828 retval += kprintf(format, rle->start +
984263bc
MD
1829 rle->count - 1);
1830 }
1831 }
1832 }
1833 return retval;
1834}
1835
e126caf1 1836int
984263bc
MD
1837pci_print_child(device_t dev, device_t child)
1838{
1839 struct pci_devinfo *dinfo;
1840 struct resource_list *rl;
1841 pcicfgregs *cfg;
1842 int retval = 0;
1843
1844 dinfo = device_get_ivars(child);
1845 cfg = &dinfo->cfg;
1846 rl = &dinfo->resources;
1847
1848 retval += bus_print_child_header(dev, child);
1849
1850 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1851 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1852 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1853 if (device_get_flags(dev))
85f8e2ea 1854 retval += kprintf(" flags %#x", device_get_flags(dev));
984263bc 1855
85f8e2ea 1856 retval += kprintf(" at device %d.%d", pci_get_slot(child),
984263bc
MD
1857 pci_get_function(child));
1858
1859 retval += bus_print_child_footer(dev, child);
1860
1861 return (retval);
1862}
1863
e126caf1 1864void
984263bc
MD
1865pci_probe_nomatch(device_t dev, device_t child)
1866{
1867 struct pci_devinfo *dinfo;
1868 pcicfgregs *cfg;
1869 const char *desc;
1870 int unknown;
1871
1872 unknown = 0;
1873 dinfo = device_get_ivars(child);
1874 cfg = &dinfo->cfg;
1875 desc = pci_ata_match(child);
1876 if (!desc) desc = pci_usb_match(child);
1877 if (!desc) desc = pci_vga_match(child);
27c23c6b 1878 if (!desc) desc = pci_chip_match(child);
984263bc
MD
1879 if (!desc) {
1880 desc = "unknown card";
1881 unknown++;
1882 }
1883 device_printf(dev, "<%s>", desc);
1884 if (bootverbose || unknown) {
85f8e2ea 1885 kprintf(" (vendor=0x%04x, dev=0x%04x)",
984263bc
MD
1886 cfg->vendor,
1887 cfg->device);
1888 }
85f8e2ea 1889 kprintf(" at %d.%d",
984263bc
MD
1890 pci_get_slot(child),
1891 pci_get_function(child));
1892 if (cfg->intpin > 0 && cfg->intline != 255) {
85f8e2ea 1893 kprintf(" irq %d", cfg->intline);
984263bc 1894 }
85f8e2ea 1895 kprintf("\n");
638744c5 1896 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
984263bc
MD
1897
1898 return;
1899}
1900
22457186 1901int
4a5a2d63 1902pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
984263bc
MD
1903{
1904 struct pci_devinfo *dinfo;
1905 pcicfgregs *cfg;
1906
1907 dinfo = device_get_ivars(child);
1908 cfg = &dinfo->cfg;
1909
1910 switch (which) {
1911 case PCI_IVAR_SUBVENDOR:
1912 *result = cfg->subvendor;
1913 break;
1914 case PCI_IVAR_SUBDEVICE:
1915 *result = cfg->subdevice;
1916 break;
1917 case PCI_IVAR_VENDOR:
1918 *result = cfg->vendor;
1919 break;
1920 case PCI_IVAR_DEVICE:
1921 *result = cfg->device;
1922 break;
1923 case PCI_IVAR_DEVID:
1924 *result = (cfg->device << 16) | cfg->vendor;
1925 break;
1926 case PCI_IVAR_CLASS:
1927 *result = cfg->baseclass;
1928 break;
1929 case PCI_IVAR_SUBCLASS:
1930 *result = cfg->subclass;
1931 break;
1932 case PCI_IVAR_PROGIF:
1933 *result = cfg->progif;
1934 break;
1935 case PCI_IVAR_REVID:
1936 *result = cfg->revid;
1937 break;
1938 case PCI_IVAR_INTPIN:
1939 *result = cfg->intpin;
1940 break;
1941 case PCI_IVAR_IRQ:
1942 *result = cfg->intline;
1943 break;
1944 case PCI_IVAR_BUS:
1945 *result = cfg->bus;
1946 break;
1947 case PCI_IVAR_SLOT:
1948 *result = cfg->slot;
1949 break;
1950 case PCI_IVAR_FUNCTION:
1951 *result = cfg->func;
1952 break;
1953 case PCI_IVAR_SECONDARYBUS:
1954 *result = cfg->secondarybus;
1955 break;
1956 case PCI_IVAR_SUBORDINATEBUS:
1957 *result = cfg->subordinatebus;
1958 break;
f72d3d23
JS
1959 case PCI_IVAR_ETHADDR:
1960 /*
1961 * The generic accessor doesn't deal with failure, so
1962 * we set the return value, then return an error.
1963 */
3641b7ca 1964 *result = 0;
f72d3d23 1965 return (EINVAL);
c7e4e7eb
SZ
1966 case PCI_IVAR_PCIXCAP_PTR:
1967 *result = cfg->pcixcap_ptr;
1968 break;
1969 case PCI_IVAR_PCIECAP_PTR:
1970 *result = cfg->expr.expr_ptr;
1971 break;
0254566f
SZ
1972 case PCI_IVAR_VPDCAP_PTR:
1973 *result = cfg->vpdcap_ptr;
1974 break;
984263bc
MD
1975 default:
1976 return ENOENT;
1977 }
1978 return 0;
1979}
1980
22457186 1981int
984263bc
MD
1982pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1983{
1984 struct pci_devinfo *dinfo;
1985 pcicfgregs *cfg;
1986
1987 dinfo = device_get_ivars(child);
1988 cfg = &dinfo->cfg;
1989
1990 switch (which) {
1991 case PCI_IVAR_SUBVENDOR:
1992 case PCI_IVAR_SUBDEVICE:
1993 case PCI_IVAR_VENDOR:
1994 case PCI_IVAR_DEVICE:
1995 case PCI_IVAR_DEVID:
1996 case PCI_IVAR_CLASS:
1997 case PCI_IVAR_SUBCLASS:
1998 case PCI_IVAR_PROGIF:
1999 case PCI_IVAR_REVID:
2000 case PCI_IVAR_INTPIN:
2001 case PCI_IVAR_IRQ:
2002 case PCI_IVAR_BUS:
2003 case PCI_IVAR_SLOT:
2004 case PCI_IVAR_FUNCTION:
f72d3d23 2005 case PCI_IVAR_ETHADDR:
c7e4e7eb
SZ
2006 case PCI_IVAR_PCIXCAP_PTR:
2007 case PCI_IVAR_PCIECAP_PTR:
984263bc
MD
2008 return EINVAL; /* disallow for now */
2009
2010 case PCI_IVAR_SECONDARYBUS:
2011 cfg->secondarybus = value;
2012 break;
2013 case PCI_IVAR_SUBORDINATEBUS:
2014 cfg->subordinatebus = value;
2015 break;
2016 default:
2017 return ENOENT;
2018 }
2019 return 0;
2020}
2021
201eb0a7
TS
2022#ifdef PCI_MAP_FIXUP
2023static struct resource *
2024pci_alloc_map(device_t dev, device_t child, int type, int *rid, u_long start,
2025 u_long end, u_long count, u_int flags)
2026{
2027 struct pci_devinfo *dinfo = device_get_ivars(child);
2028 struct resource_list *rl = &dinfo->resources;
2029 struct resource_list_entry *rle;
2030 struct resource *res;
2031 uint32_t map, testval;
2032 int mapsize;
2033
2034 /*
2035 * Weed out the bogons, and figure out how large the BAR/map
2036 * is. BARs that read back 0 here are bogus and unimplemented.
2037 *
2038 * Note: atapci in legacy mode are special and handled elsewhere
2039 * in the code. If you have an atapci device in legacy mode and
2040 * it fails here, that other code is broken.
2041 */
2042 res = NULL;
2043 map = pci_read_config(child, *rid, 4);
2044 pci_write_config(child, *rid, 0xffffffff, 4);
2045 testval = pci_read_config(child, *rid, 4);
2046 if (pci_mapbase(testval) == 0)
2047 goto out;
2048 if (pci_maptype(testval) & PCI_MAPMEM) {
2049 if (type != SYS_RES_MEMORY) {
2050 if (bootverbose)
2051 device_printf(dev, "child %s requested type %d"
2052 " for rid %#x, but the BAR says "
2053 "it is a memio\n",
2054 device_get_nameunit(child), type,
2055 *rid);
2056 goto out;
2057 }
2058 } else {
2059 if (type != SYS_RES_IOPORT) {
2060 if (bootverbose)
2061 device_printf(dev, "child %s requested type %d"
2062 " for rid %#x, but the BAR says "
2063 "it is an ioport\n",
2064 device_get_nameunit(child), type,
2065 *rid);
2066 goto out;
2067 }
2068 }
2069 /*
2070 * For real BARs, we need to override the size that
2071 * the driver requests, because that's what the BAR
2072 * actually uses and we would otherwise have a
2073 * situation where we might allocate the excess to
2074 * another driver, which won't work.
2075 */
2076 mapsize = pci_mapsize(testval);
2077 count = 1 << mapsize;
2078 if (RF_ALIGNMENT(flags) < mapsize)
2079 flags = (flags & ~RF_ALIGNMENT_MASK) |
2080 RF_ALIGNMENT_LOG2(mapsize);
2081 /*
2082 * Allocate enough resource, and then write back the
2083 * appropriate BAR for that resource.
2084 */
2085 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
2086 start, end, count, flags);
2087 if (res == NULL) {
2088 device_printf(child, "%#lx bytes at rid %#x res %d failed "
2089 "(%#lx, %#lx)\n", count, *rid, type, start, end);
2090 goto out;
2091 }
2092 resource_list_add(rl, type, *rid, start, end, count);
2093 rle = resource_list_find(rl, type, *rid);
2094 if (rle == NULL)
2095 panic("pci_alloc_map: unexpectedly can't find resource.");
2096 rle->res = res;
2097 rle->start = rman_get_start(res);
2098 rle->end = rman_get_end(res);
2099 rle->count = count;
2100 if (bootverbose)
2101 device_printf(child, "lazy allocation of %#lx bytes rid %#x "
2102 "type %d at %#lx\n", count, *rid, type,
2103 rman_get_start(res));
2104 map = rman_get_start(res);
2105out:;
2106 pci_write_config(child, *rid, map, 4);
2107 return res;
2108}
2109#endif /* PCI_MAP_FIXUP */
2110
261fa16d 2111struct resource *
984263bc
MD
2112pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
2113 u_long start, u_long end, u_long count, u_int flags)
2114{
2115 struct pci_devinfo *dinfo = device_get_ivars(child);
2116 struct resource_list *rl = &dinfo->resources;
201eb0a7
TS
2117#ifdef PCI_MAP_FIXUP
2118 struct resource_list_entry *rle;
2119#endif /* PCI_MAP_FIXUP */
984263bc 2120 pcicfgregs *cfg = &dinfo->cfg;
de67e43b 2121
984263bc
MD
2122 /*
2123 * Perform lazy resource allocation
984263bc
MD
2124 */
2125 if (device_get_parent(child) == dev) {
de67e43b
JS
2126 switch (type) {
2127 case SYS_RES_IRQ:
0855a2af 2128#if defined(__i386__) || defined(__amd64__)
984263bc
MD
2129 /*
2130 * If device doesn't have an interrupt routed, and is
2131 * deserving of an interrupt, try to assign it one.
2132 */
de67e43b
JS
2133 if ((cfg->intline == 255 || cfg->intline == 0) &&
2134 (cfg->intpin != 0) &&
2135 (start == 0) && (end == ~0UL)) {
2136 cfg->intline = PCIB_ROUTE_INTERRUPT(
2137 device_get_parent(dev), child,
2138 cfg->intpin);
2139 if (cfg->intline != 255) {
2140 pci_write_config(child, PCIR_INTLINE,
2141 cfg->intline, 1);
2142 resource_list_add(rl, SYS_RES_IRQ, 0,
2143 cfg->intline, cfg->intline, 1);
2144 }
2145 }
820c1612 2146 break;
de67e43b
JS
2147#endif
2148 case SYS_RES_IOPORT:
201eb0a7 2149 /* FALLTHROUGH */
de67e43b
JS
2150 case SYS_RES_MEMORY:
2151 if (*rid < PCIR_BAR(cfg->nummaps)) {
2152 /*
2153 * Enable the I/O mode. We should
2154 * also be assigning resources too
2155 * when none are present. The
2156 * resource_list_alloc kind of sorta does
2157 * this...
2158 */
2159 if (PCI_ENABLE_IO(dev, child, type))
2160 return (NULL);
984263bc 2161 }
201eb0a7
TS
2162#ifdef PCI_MAP_FIXUP
2163 rle = resource_list_find(rl, type, *rid);
2164 if (rle == NULL)
2165 return pci_alloc_map(dev, child, type, rid,
2166 start, end, count, flags);
2167#endif /* PCI_MAP_FIXUP */
820c1612 2168 break;
984263bc 2169 }
201eb0a7
TS
2170#ifdef PCI_MAP_FIXUP
2171 /*
2172 * If we've already allocated the resource, then
2173 * return it now. But first we may need to activate
2174 * it, since we don't allocate the resource as active
2175 * above. Normally this would be done down in the
2176 * nexus, but since we short-circuit that path we have
2177 * to do its job here. Not sure if we should free the
2178 * resource if it fails to activate.
2179 *
2180 * Note: this also finds and returns resources for
2181 * atapci devices in legacy mode as allocated in
2182 * pci_ata_maps().
2183 */
2184 rle = resource_list_find(rl, type, *rid);
2185 if (rle != NULL && rle->res != NULL) {
2186 if (bootverbose)
2187 device_printf(child, "reserved %#lx bytes for "
2188 "rid %#x type %d at %#lx\n",
2189 rman_get_size(rle->res), *rid,
2190 type, rman_get_start(rle->res));
2191 if ((flags & RF_ACTIVE) &&
2192 bus_generic_activate_resource(dev, child, type,
2193 *rid, rle->res) != 0)
2194 return NULL;
2195 return rle->res;
2196 }
2197#endif /* PCI_MAP_FIXUP */
984263bc 2198 }
984263bc
MD
2199 return resource_list_alloc(rl, dev, child, type, rid,
2200 start, end, count, flags);
2201}
2202
2203static int
2204pci_release_resource(device_t dev, device_t child, int type, int rid,
2205 struct resource *r)
2206{
2207 struct pci_devinfo *dinfo = device_get_ivars(child);
2208 struct resource_list *rl = &dinfo->resources;
2209
2210 return resource_list_release(rl, dev, child, type, rid, r);
2211}
2212
2213static int
2214pci_set_resource(device_t dev, device_t child, int type, int rid,
2215 u_long start, u_long count)
2216{
2217 struct pci_devinfo *dinfo = device_get_ivars(child);
2218 struct resource_list *rl = &dinfo->resources;
2219
2220 resource_list_add(rl, type, rid, start, start + count - 1, count);
2221 return 0;
2222}
2223
2224static int
2225pci_get_resource(device_t dev, device_t child, int type, int rid,
2226 u_long *startp, u_long *countp)
2227{
2228 struct pci_devinfo *dinfo = device_get_ivars(child);
2229 struct resource_list *rl = &dinfo->resources;
2230 struct resource_list_entry *rle;
2231
2232 rle = resource_list_find(rl, type, rid);
2233 if (!rle)
2234 return ENOENT;
2235
2236 if (startp)
2237 *startp = rle->start;
2238 if (countp)
2239 *countp = rle->count;
2240
2241 return 0;
2242}
2243
e126caf1 2244void
984263bc
MD
2245pci_delete_resource(device_t dev, device_t child, int type, int rid)
2246{
85f8e2ea 2247 kprintf("pci_delete_resource: PCI resources can not be deleted\n");
984263bc
MD
2248}
2249
e126caf1
MD
2250struct resource_list *
2251pci_get_resource_list (device_t dev, device_t child)
2252{
b0486c83 2253 struct pci_devinfo *dinfo = device_get_ivars(child);
e126caf1 2254
b0486c83 2255 if (dinfo == NULL)
e126caf1 2256 return (NULL);
b0486c83 2257 return (&dinfo->resources);
e126caf1
MD
2258}
2259
2260u_int32_t
984263bc
MD
2261pci_read_config_method(device_t dev, device_t child, int reg, int width)
2262{
2263 struct pci_devinfo *dinfo = device_get_ivars(child);
2264 pcicfgregs *cfg = &dinfo->cfg;
4a5a2d63
JS
2265
2266 return PCIB_READ_CONFIG(device_get_parent(dev),
2267 cfg->bus, cfg->slot, cfg->func,
2268 reg, width);
984263bc
MD
2269}
2270
e126caf1 2271void
984263bc
MD
2272pci_write_config_method(device_t dev, device_t child, int reg,
2273 u_int32_t val, int width)
2274{
2275 struct pci_devinfo *dinfo = device_get_ivars(child);
2276 pcicfgregs *cfg = &dinfo->cfg;
4a5a2d63
JS
2277
2278 PCIB_WRITE_CONFIG(device_get_parent(dev),
2279 cfg->bus, cfg->slot, cfg->func,
2280 reg, val, width);
984263bc
MD
2281}
2282
e126caf1
MD
2283int
2284pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
2285 size_t buflen)
2286{
2287 struct pci_devinfo *dinfo;
2288
2289 dinfo = device_get_ivars(child);
f8c7a42d 2290 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
e126caf1
MD
2291 pci_get_function(child));
2292 return (0);
2293}
2294
2295int
2296pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
2297 size_t buflen)
2298{
2299 struct pci_devinfo *dinfo;
2300 pcicfgregs *cfg;
2301
2302 dinfo = device_get_ivars(child);
2303 cfg = &dinfo->cfg;
f8c7a42d 2304 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
e126caf1
MD
2305 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
2306 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
2307 cfg->progif);
2308 return (0);
2309}
2310
2311int
2312pci_assign_interrupt_method(device_t dev, device_t child)
2313{
2314 struct pci_devinfo *dinfo = device_get_ivars(child);
2315 pcicfgregs *cfg = &dinfo->cfg;
2316
2317 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
2318 cfg->intpin));
2319}
2320
984263bc
MD
2321static int
2322pci_modevent(module_t mod, int what, void *arg)
2323{
2324 switch (what) {
2325 case MOD_LOAD:
2326 STAILQ_INIT(&pci_devq);
2327 break;
984263bc
MD
2328 case MOD_UNLOAD:
2329 break;
2330 }
2331
2332 return 0;
2333}
2334
638744c5
HT
2335void
2336pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
2337{
2338 int i;
2339
2340 /*
2341 * Only do header type 0 devices. Type 1 devices are bridges,
2342 * which we know need special treatment. Type 2 devices are
2343 * cardbus bridges which also require special treatment.
2344 * Other types are unknown, and we err on the side of safety
2345 * by ignoring them.
2346 */
2347 if (dinfo->cfg.hdrtype != 0)
2348 return;
2349
2350 /*
2351 * Restore the device to full power mode. We must do this
2352 * before we restore the registers because moving from D3 to
2353 * D0 will cause the chip's BARs and some other registers to
2354 * be reset to some unknown power on reset values. Cut down
2355 * the noise on boot by doing nothing if we are already in
2356 * state D0.
2357 */
2358 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
2359 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
2360 }
2361 for (i = 0; i < dinfo->cfg.nummaps; i++)
2362 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
2363 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
2364 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
2365 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
2366 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
2367 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
2368 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
2369 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
2370 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
2371 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
2372 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
2373#if 0
2374 /* Restore MSI and MSI-X configurations if they are present. */
2375 if (dinfo->cfg.msi.msi_location != 0)
2376 pci_resume_msi(dev);
2377 if (dinfo->cfg.msix.msix_location != 0)
2378 pci_resume_msix(dev);
2379#endif
2380}
2381
2382void
2383pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
2384{
2385 int i;
2386 uint32_t cls;
2387 int ps;
2388
2389 /*
2390 * Only do header type 0 devices. Type 1 devices are bridges, which
2391 * we know need special treatment. Type 2 devices are cardbus bridges
2392 * which also require special treatment. Other types are unknown, and
2393 * we err on the side of safety by ignoring them. Powering down
2394 * bridges should not be undertaken lightly.
2395 */
2396 if (dinfo->cfg.hdrtype != 0)
2397 return;
2398 for (i = 0; i < dinfo->cfg.nummaps; i++)
2399 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
2400 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
2401
2402 /*
2403 * Some drivers apparently write to these registers w/o updating our
2404 * cached copy. No harm happens if we update the copy, so do so here
2405 * so we can restore them. The COMMAND register is modified by the
2406 * bus w/o updating the cache. This should represent the normally
2407 * writable portion of the 'defined' part of type 0 headers. In
2408 * theory we also need to save/restore the PCI capability structures
2409 * we know about, but apart from power we don't know any that are
2410 * writable.
2411 */
2412 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
2413 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
2414 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
2415 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
2416 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
2417 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
2418 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
2419 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
2420 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
2421 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2422 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2423 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
2424 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
2425 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
2426 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
2427
2428 /*
2429 * don't set the state for display devices, base peripherals and
2430 * memory devices since bad things happen when they are powered down.
2431 * We should (a) have drivers that can easily detach and (b) use
2432 * generic drivers for these devices so that some device actually
2433 * attaches. We need to make sure that when we implement (a) we don't
2434 * power the device down on a reattach.
2435 */
2436 cls = pci_get_class(dev);
2437 if (!setstate)
2438 return;
2439
2440 switch (pci_do_power_nodriver)
2441 {
2442 case 0: /* NO powerdown at all */
2443 return;
2444 case 1: /* Conservative about what to power down */
2445 if (cls == PCIC_STORAGE)
2446 return;
2447 /*FALLTHROUGH*/
2448 case 2: /* Agressive about what to power down */
2449 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
2450 cls == PCIC_BASEPERIPH)
2451 return;
2452 /*FALLTHROUGH*/
2453 case 3: /* Power down everything */
2454 break;
2455 }
2456
2457 if (cls == PCIC_STORAGE)
2458 return;
2459
2460 /*
2461 * PCI spec says we can only go into D3 state from D0 state.
2462 * Transition from D[12] into D0 before going to D3 state.
2463 */
2464 ps = pci_get_powerstate(dev);
2465 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
2466 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
2467 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
2468 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
2469}
2470
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2471int
2472pci_resume(device_t dev)
2473{
2474 int numdevs;
2475 int i;
2476 device_t *children;
2477 device_t child;
2478 struct pci_devinfo *dinfo;
2479 pcicfgregs *cfg;
2480
2481 device_get_children(dev, &children, &numdevs);
2482
2483 for (i = 0; i < numdevs; i++) {
2484 child = children[i];
2485
2486 dinfo = device_get_ivars(child);
2487 cfg = &dinfo->cfg;
2488 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2489 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
2490 if (PCI_INTERRUPT_VALID(cfg->intline)) {
2491 pci_write_config(child, PCIR_INTLINE,
2492 cfg->intline, 1);
2493 }
2494 }
2495 }
2496
efda3bd0 2497 kfree(children, M_TEMP);
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2498
2499 return (bus_generic_resume(dev));
2500}
2501
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2502void
2503pci_driver_added(device_t dev, driver_t *driver)
2504{
2505 int numdevs;
2506 device_t *devlist;
2507 device_t child;
2508 struct pci_devinfo *dinfo;
2509 int i;
2510
2511 if (bootverbose)
2512 device_printf(dev, "driver added\n");
2513 DEVICE_IDENTIFY(driver, dev);
2514 device_get_children(dev, &devlist, &numdevs);
2515 for (i = 0; i < numdevs; i++) {
2516 child = devlist[i];
2517 if (device_get_state(child) != DS_NOTPRESENT)
2518 continue;
2519 dinfo = device_get_ivars(child);
2520 pci_print_verbose(dinfo);
2521 if (bootverbose)
2522 kprintf("pci%d:%d:%d: reprobing on driver added\n",
2523 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func);
2524 pci_cfg_restore(child, dinfo);
2525 if (device_probe_and_attach(child) != 0)
2526 pci_cfg_save(child, dinfo, 1);
2527 }
2528 kfree(devlist, M_TEMP);
2529}
2530
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2531static void
2532pci_child_detached(device_t parent __unused, device_t child) {
2533 /* Turn child's power off */
2534 pci_cfg_save(child, device_get_ivars(child), 1);
2535}
2536
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2537static device_method_t pci_methods[] = {
2538 /* Device interface */
4a5a2d63 2539 DEVMETHOD(device_probe, pci_probe),
e126caf1 2540 DEVMETHOD(device_attach, pci_attach),
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2541 DEVMETHOD(device_shutdown, bus_generic_shutdown),
2542 DEVMETHOD(device_suspend, bus_generic_suspend),
e126caf1 2543 DEVMETHOD(device_resume, pci_resume),
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2544
2545 /* Bus interface */
2546 DEVMETHOD(bus_print_child, pci_print_child),
2547 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
2548 DEVMETHOD(bus_read_ivar, pci_read_ivar),
2549 DEVMETHOD(bus_write_ivar, pci_write_ivar),
638744c5 2550 DEVMETHOD(bus_driver_added, pci_driver_added),
72876ce0 2551 DEVMETHOD(bus_child_detached, pci_child_detached),
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2552 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
2553 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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2554
2555 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
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2556 DEVMETHOD(bus_set_resource, pci_set_resource),
2557 DEVMETHOD(bus_get_resource, pci_get_resource),
2558 DEVMETHOD(bus_delete_resource, pci_delete_resource),
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2559 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
2560 DEVMETHOD(bus_release_resource, pci_release_resource),
2561 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
2562 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
2563 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
2564 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
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2565
2566 /* PCI interface */
2567 DEVMETHOD(pci_read_config, pci_read_config_method),
2568 DEVMETHOD(pci_write_config, pci_write_config_method),
2569 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
2570 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
2571 DEVMETHOD(pci_enable_io, pci_enable_io_method),
2572 DEVMETHOD(pci_disable_io, pci_disable_io_method),
2573 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
2574 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
e126caf1 2575 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
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2576
2577 { 0, 0 }
2578};
2579
3aef8050 2580driver_t pci_driver = {
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2581 "pci",
2582 pci_methods,
2583 1, /* no softc */
2584};
2585
2586DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
261fa16d 2587MODULE_VERSION(pci, 1);