* Fix placement of return value.
[dragonfly.git] / sys / bus / pci / pci.c
CommitLineData
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1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
f72d3d23 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.16 2004/02/16 18:51:01 joerg Exp $
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28 *
29 */
30
31#include "opt_bus.h"
32#include "opt_pci.h"
33
34#include "opt_simos.h"
dc5a7bd2 35#include "opt_compat_oldpci.h"
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36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/malloc.h>
40#include <sys/module.h>
41#include <sys/fcntl.h>
42#include <sys/conf.h>
43#include <sys/kernel.h>
44#include <sys/queue.h>
45#include <sys/types.h>
46#include <sys/buf.h>
47
48#include <vm/vm.h>
49#include <vm/pmap.h>
50#include <vm/vm_extern.h>
51
52#include <sys/bus.h>
53#include <machine/bus.h>
54#include <sys/rman.h>
55#include <machine/resource.h>
56#include <machine/md_var.h> /* For the Alpha */
57#ifdef __i386__
bbca97bc 58#include <bus/pci/i386/pci_cfgreg.h>
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59#endif
60
dc5a7bd2 61#include <sys/pciio.h>
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62#include "pcireg.h"
63#include "pcivar.h"
22457186 64#include "pci_private.h"
984263bc 65
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66#include "pcib_if.h"
67
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68#ifdef __alpha__
69#include <machine/rpb.h>
70#endif
71
72#ifdef APIC_IO
73#include <machine/smp.h>
74#endif /* APIC_IO */
75
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76static devclass_t pci_devclass;
77
4a5a2d63 78static void pci_read_extcap(device_t dev, pcicfgregs *cfg);
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79
80struct pci_quirk {
81 u_int32_t devid; /* Vendor/device of the card */
82 int type;
3e4db402 83#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
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84 int arg1;
85 int arg2;
86};
87
88struct pci_quirk pci_quirks[] = {
89 /*
90 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
91 */
92 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
93 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
94
95 { 0 }
96};
97
98/* map register information */
99#define PCI_MAPMEM 0x01 /* memory map */
100#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
101#define PCI_MAPPORT 0x04 /* port map */
102
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103static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
104u_int32_t pci_numdevs = 0;
105static u_int32_t pci_generation = 0;
106
107device_t
108pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func)
109{
110 struct pci_devinfo *dinfo;
111
112 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
113 if ((dinfo->cfg.bus == bus) &&
114 (dinfo->cfg.slot == slot) &&
115 (dinfo->cfg.func == func)) {
116 return (dinfo->cfg.dev);
117 }
118 }
119
120 return (NULL);
121}
122
123device_t
124pci_find_device (u_int16_t vendor, u_int16_t device)
125{
126 struct pci_devinfo *dinfo;
127
128 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
129 if ((dinfo->cfg.vendor == vendor) &&
130 (dinfo->cfg.device == device)) {
131 return (dinfo->cfg.dev);
132 }
133 }
134
135 return (NULL);
136}
137
138/* return base address of memory or port map */
139
140static u_int32_t
141pci_mapbase(unsigned mapreg)
142{
143 int mask = 0x03;
144 if ((mapreg & 0x01) == 0)
145 mask = 0x0f;
146 return (mapreg & ~mask);
147}
148
149/* return map type of memory or port map */
150
151static int
152pci_maptype(unsigned mapreg)
153{
154 static u_int8_t maptype[0x10] = {
155 PCI_MAPMEM, PCI_MAPPORT,
156 PCI_MAPMEM, 0,
157 PCI_MAPMEM, PCI_MAPPORT,
158 0, 0,
159 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
160 PCI_MAPMEM|PCI_MAPMEMP, 0,
161 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
162 0, 0,
163 };
164
165 return maptype[mapreg & 0x0f];
166}
167
168/* return log2 of map size decoded for memory or port map */
169
170static int
171pci_mapsize(unsigned testval)
172{
173 int ln2size;
174
175 testval = pci_mapbase(testval);
176 ln2size = 0;
177 if (testval != 0) {
178 while ((testval & 1) == 0)
179 {
180 ln2size++;
181 testval >>= 1;
182 }
183 }
184 return (ln2size);
185}
186
187/* return log2 of address range supported by map register */
188
189static int
190pci_maprange(unsigned mapreg)
191{
192 int ln2range = 0;
193 switch (mapreg & 0x07) {
194 case 0x00:
195 case 0x01:
196 case 0x05:
197 ln2range = 32;
198 break;
199 case 0x02:
200 ln2range = 20;
201 break;
202 case 0x04:
203 ln2range = 64;
204 break;
205 }
206 return (ln2range);
207}
208
209/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
210
211static void
212pci_fixancient(pcicfgregs *cfg)
213{
214 if (cfg->hdrtype != 0)
215 return;
216
217 /* PCI to PCI bridges use header type 1 */
218 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
219 cfg->hdrtype = 1;
220}
221
222/* read config data specific to header type 1 device (PCI to PCI bridge) */
223
224static void *
4a5a2d63 225pci_readppb(device_t pcib, int b, int s, int f)
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226{
227 pcih1cfgregs *p;
228
4a5a2d63 229 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
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230 if (p == NULL)
231 return (NULL);
232
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233 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
234 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
984263bc 235
4a5a2d63 236 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
984263bc 237
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238 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
239 PCIR_IOBASEH_1, 2),
240 PCIB_READ_CONFIG(pcib, b, s, f,
241 PCIR_IOBASEL_1, 1));
242 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
243 PCIR_IOLIMITH_1, 2),
244 PCIB_READ_CONFIG(pcib, b, s, f,
245 PCIR_IOLIMITL_1, 1));
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246
247 p->membase = PCI_PPBMEMBASE (0,
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248 PCIB_READ_CONFIG(pcib, b, s, f,
249 PCIR_MEMBASE_1, 2));
984263bc 250 p->memlimit = PCI_PPBMEMLIMIT (0,
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251 PCIB_READ_CONFIG(pcib, b, s, f,
252 PCIR_MEMLIMIT_1, 2));
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253
254 p->pmembase = PCI_PPBMEMBASE (
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255 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
256 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
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257
258 p->pmemlimit = PCI_PPBMEMLIMIT (
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259 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
260 PCIR_PMLIMITH_1, 4),
261 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
262
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263 return (p);
264}
265
266/* read config data specific to header type 2 device (PCI to CardBus bridge) */
267
268static void *
4a5a2d63 269pci_readpcb(device_t pcib, int b, int s, int f)
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270{
271 pcih2cfgregs *p;
272
4a5a2d63 273 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
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274 if (p == NULL)
275 return (NULL);
276
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277 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
278 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
984263bc 279
4a5a2d63 280 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
984263bc 281
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282 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
283 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
284 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
285 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
984263bc 286
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287 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
288 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
289 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
290 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
984263bc 291
4a5a2d63 292 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
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293 return p;
294}
295
296/* extract header type specific config data */
297
298static void
4a5a2d63 299pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
984263bc 300{
4a5a2d63 301#define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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302 switch (cfg->hdrtype) {
303 case 0:
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304 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
305 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
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306 cfg->nummaps = PCI_MAXMAPS_0;
307 break;
308 case 1:
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309 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
310 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
311 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
312 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
984263bc 313 cfg->nummaps = PCI_MAXMAPS_1;
4a5a2d63 314 cfg->hdrspec = pci_readppb(pcib, b, s, f);
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315 break;
316 case 2:
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317 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
318 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
319 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
320 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
984263bc 321 cfg->nummaps = PCI_MAXMAPS_2;
4a5a2d63 322 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
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323 break;
324 }
4a5a2d63 325#undef REG
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326}
327
328/* read configuration header into pcicfgrect structure */
329
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330struct pci_devinfo *
331pci_read_device(device_t pcib, int b, int s, int f, int width)
984263bc 332{
4a5a2d63 333#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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334
335 pcicfgregs *cfg = NULL;
336 struct pci_devinfo *devlist_entry;
337 struct devlist *devlist_head;
338
339 devlist_head = &pci_devq;
340
341 devlist_entry = NULL;
342
4a5a2d63 343 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
984263bc 344
22457186 345 devlist_entry = malloc(width,
4a5a2d63 346 M_DEVBUF, M_WAITOK | M_ZERO);
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347 if (devlist_entry == NULL)
348 return (NULL);
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349
350 cfg = &devlist_entry->cfg;
351
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352 cfg->bus = b;
353 cfg->slot = s;
354 cfg->func = f;
355 cfg->vendor = REG(PCIR_VENDOR, 2);
356 cfg->device = REG(PCIR_DEVICE, 2);
357 cfg->cmdreg = REG(PCIR_COMMAND, 2);
358 cfg->statreg = REG(PCIR_STATUS, 2);
359 cfg->baseclass = REG(PCIR_CLASS, 1);
360 cfg->subclass = REG(PCIR_SUBCLASS, 1);
361 cfg->progif = REG(PCIR_PROGIF, 1);
362 cfg->revid = REG(PCIR_REVID, 1);
363 cfg->hdrtype = REG(PCIR_HEADERTYPE, 1);
364 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
365 cfg->lattimer = REG(PCIR_LATTIMER, 1);
366 cfg->intpin = REG(PCIR_INTPIN, 1);
367 cfg->intline = REG(PCIR_INTLINE, 1);
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368#ifdef __alpha__
369 alpha_platform_assign_pciintr(cfg);
370#endif
371
372#ifdef APIC_IO
373 if (cfg->intpin != 0) {
374 int airq;
375
376 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
377 if (airq >= 0) {
378 /* PCI specific entry found in MP table */
379 if (airq != cfg->intline) {
380 undirect_pci_irq(cfg->intline);
381 cfg->intline = airq;
382 }
383 } else {
384 /*
385 * PCI interrupts might be redirected to the
386 * ISA bus according to some MP tables. Use the
387 * same methods as used by the ISA devices
388 * devices to find the proper IOAPIC int pin.
389 */
390 airq = isa_apic_irq(cfg->intline);
391 if ((airq >= 0) && (airq != cfg->intline)) {
392 /* XXX: undirect_pci_irq() ? */
393 undirect_isa_irq(cfg->intline);
394 cfg->intline = airq;
395 }
396 }
397 }
398#endif /* APIC_IO */
399
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400 cfg->mingnt = REG(PCIR_MINGNT, 1);
401 cfg->maxlat = REG(PCIR_MAXLAT, 1);
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402
403 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
404 cfg->hdrtype &= ~PCIM_MFDEV;
405
406 pci_fixancient(cfg);
4a5a2d63 407 pci_hdrtypedata(pcib, b, s, f, cfg);
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408
409 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
4a5a2d63 410 pci_read_extcap(pcib, cfg);
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411
412 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
413
414 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
415 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
416 devlist_entry->conf.pc_sel.pc_func = cfg->func;
417 devlist_entry->conf.pc_hdr = cfg->hdrtype;
418
419 devlist_entry->conf.pc_subvendor = cfg->subvendor;
420 devlist_entry->conf.pc_subdevice = cfg->subdevice;
421 devlist_entry->conf.pc_vendor = cfg->vendor;
422 devlist_entry->conf.pc_device = cfg->device;
423
424 devlist_entry->conf.pc_class = cfg->baseclass;
425 devlist_entry->conf.pc_subclass = cfg->subclass;
426 devlist_entry->conf.pc_progif = cfg->progif;
427 devlist_entry->conf.pc_revid = cfg->revid;
428
429 pci_numdevs++;
430 pci_generation++;
431 }
432 return (devlist_entry);
433#undef REG
434}
435
436static void
4a5a2d63 437pci_read_extcap(device_t pcib, pcicfgregs *cfg)
984263bc 438{
4a5a2d63 439#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
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440 int ptr, nextptr, ptrptr;
441
442 switch (cfg->hdrtype) {
443 case 0:
444 ptrptr = 0x34;
445 break;
446 case 2:
447 ptrptr = 0x14;
448 break;
449 default:
450 return; /* no extended capabilities support */
451 }
452 nextptr = REG(ptrptr, 1); /* sanity check? */
453
454 /*
455 * Read capability entries.
456 */
457 while (nextptr != 0) {
458 /* Sanity check */
459 if (nextptr > 255) {
460 printf("illegal PCI extended capability offset %d\n",
461 nextptr);
462 return;
463 }
464 /* Find the next entry */
465 ptr = nextptr;
466 nextptr = REG(ptr + 1, 1);
467
468 /* Process this entry */
469 switch (REG(ptr, 1)) {
470 case 0x01: /* PCI power management */
471 if (cfg->pp_cap == 0) {
472 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
473 cfg->pp_status = ptr + PCIR_POWER_STATUS;
474 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
475 if ((nextptr - ptr) > PCIR_POWER_DATA)
476 cfg->pp_data = ptr + PCIR_POWER_DATA;
477 }
478 break;
479 default:
480 break;
481 }
482 }
483#undef REG
484}
485
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486/* free pcicfgregs structure and all depending data structures */
487
22457186 488int
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489pci_freecfg(struct pci_devinfo *dinfo)
490{
491 struct devlist *devlist_head;
492
493 devlist_head = &pci_devq;
494
495 if (dinfo->cfg.hdrspec != NULL)
496 free(dinfo->cfg.hdrspec, M_DEVBUF);
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497 /* XXX this hasn't been tested */
498 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
499 free(dinfo, M_DEVBUF);
500
501 /* increment the generation count */
502 pci_generation++;
503
504 /* we're losing one device */
505 pci_numdevs--;
506 return (0);
507}
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508
509
510/*
511 * PCI power manangement
512 */
513static int
514pci_set_powerstate_method(device_t dev, device_t child, int state)
515{
516 struct pci_devinfo *dinfo = device_get_ivars(child);
517 pcicfgregs *cfg = &dinfo->cfg;
518 u_int16_t status;
519 int result;
520
521 if (cfg->pp_cap != 0) {
522 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK;
523 result = 0;
524 switch (state) {
525 case PCI_POWERSTATE_D0:
526 status |= PCIM_PSTAT_D0;
527 break;
528 case PCI_POWERSTATE_D1:
529 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) {
530 status |= PCIM_PSTAT_D1;
531 } else {
532 result = EOPNOTSUPP;
533 }
534 break;
535 case PCI_POWERSTATE_D2:
536 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) {
537 status |= PCIM_PSTAT_D2;
538 } else {
539 result = EOPNOTSUPP;
540 }
541 break;
542 case PCI_POWERSTATE_D3:
543 status |= PCIM_PSTAT_D3;
544 break;
545 default:
546 result = EINVAL;
547 }
548 if (result == 0)
549 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2);
550 } else {
551 result = ENXIO;
552 }
553 return(result);
554}
555
556static int
557pci_get_powerstate_method(device_t dev, device_t child)
558{
559 struct pci_devinfo *dinfo = device_get_ivars(child);
560 pcicfgregs *cfg = &dinfo->cfg;
561 u_int16_t status;
562 int result;
563
564 if (cfg->pp_cap != 0) {
565 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2);
566 switch (status & PCIM_PSTAT_DMASK) {
567 case PCIM_PSTAT_D0:
568 result = PCI_POWERSTATE_D0;
569 break;
570 case PCIM_PSTAT_D1:
571 result = PCI_POWERSTATE_D1;
572 break;
573 case PCIM_PSTAT_D2:
574 result = PCI_POWERSTATE_D2;
575 break;
576 case PCIM_PSTAT_D3:
577 result = PCI_POWERSTATE_D3;
578 break;
579 default:
580 result = PCI_POWERSTATE_UNKNOWN;
581 break;
582 }
583 } else {
584 /* No support, device is always at D0 */
585 result = PCI_POWERSTATE_D0;
586 }
587 return(result);
588}
589
590/*
591 * Some convenience functions for PCI device drivers.
592 */
593
594static __inline void
595pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
596{
597 u_int16_t command;
598
599 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
600 command |= bit;
601 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
602}
603
604static __inline void
605pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
606{
607 u_int16_t command;
608
609 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
610 command &= ~bit;
611 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
612}
613
614static void
615pci_enable_busmaster_method(device_t dev, device_t child)
616{
617 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
618}
619
620static void
621pci_disable_busmaster_method(device_t dev, device_t child)
622{
623 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
624}
625
626static void
627pci_enable_io_method(device_t dev, device_t child, int space)
628{
629 switch(space) {
630 case SYS_RES_IOPORT:
631 pci_set_command_bit(dev, child, PCIM_CMD_PORTEN);
632 break;
633 case SYS_RES_MEMORY:
634 pci_set_command_bit(dev, child, PCIM_CMD_MEMEN);
635 break;
636 }
637}
638
639static void
640pci_disable_io_method(device_t dev, device_t child, int space)
641{
642 switch(space) {
643 case SYS_RES_IOPORT:
644 pci_clear_command_bit(dev, child, PCIM_CMD_PORTEN);
645 break;
646 case SYS_RES_MEMORY:
647 pci_clear_command_bit(dev, child, PCIM_CMD_MEMEN);
648 break;
649 }
650}
651
652/*
653 * This is the user interface to PCI configuration space.
654 */
655
656static int
41c20dac 657pci_open(dev_t dev, int oflags, int devtype, struct thread *td)
984263bc
MD
658{
659 if ((oflags & FWRITE) && securelevel > 0) {
660 return EPERM;
661 }
662 return 0;
663}
664
665static int
41c20dac 666pci_close(dev_t dev, int flag, int devtype, struct thread *td)
984263bc
MD
667{
668 return 0;
669}
670
671/*
672 * Match a single pci_conf structure against an array of pci_match_conf
673 * structures. The first argument, 'matches', is an array of num_matches
674 * pci_match_conf structures. match_buf is a pointer to the pci_conf
675 * structure that will be compared to every entry in the matches array.
676 * This function returns 1 on failure, 0 on success.
677 */
678static int
679pci_conf_match(struct pci_match_conf *matches, int num_matches,
680 struct pci_conf *match_buf)
681{
682 int i;
683
684 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
685 return(1);
686
687 for (i = 0; i < num_matches; i++) {
688 /*
689 * I'm not sure why someone would do this...but...
690 */
691 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
692 continue;
693
694 /*
695 * Look at each of the match flags. If it's set, do the
696 * comparison. If the comparison fails, we don't have a
697 * match, go on to the next item if there is one.
698 */
699 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
700 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
701 continue;
702
703 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
704 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
705 continue;
706
707 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
708 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
709 continue;
710
711 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
712 && (match_buf->pc_vendor != matches[i].pc_vendor))
713 continue;
714
715 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
716 && (match_buf->pc_device != matches[i].pc_device))
717 continue;
718
719 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
720 && (match_buf->pc_class != matches[i].pc_class))
721 continue;
722
723 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
724 && (match_buf->pd_unit != matches[i].pd_unit))
725 continue;
726
727 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
728 && (strncmp(matches[i].pd_name, match_buf->pd_name,
729 sizeof(match_buf->pd_name)) != 0))
730 continue;
731
732 return(0);
733 }
734
735 return(1);
736}
737
738/*
739 * Locate the parent of a PCI device by scanning the PCI devlist
740 * and return the entry for the parent.
741 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
742 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
743 */
744
745pcicfgregs *
746pci_devlist_get_parent(pcicfgregs *cfg)
747{
748 struct devlist *devlist_head;
749 struct pci_devinfo *dinfo;
750 pcicfgregs *bridge_cfg;
751 int i;
752
753 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
754
755 /* If the device is on PCI bus 0, look for the host */
756 if (cfg->bus == 0) {
757 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
758 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
759 bridge_cfg = &dinfo->cfg;
760 if (bridge_cfg->baseclass == PCIC_BRIDGE
761 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
762 && bridge_cfg->bus == cfg->bus) {
763 return bridge_cfg;
764 }
765 }
766 }
767
768 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
769 if (cfg->bus > 0) {
770 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
771 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
772 bridge_cfg = &dinfo->cfg;
773 if (bridge_cfg->baseclass == PCIC_BRIDGE
774 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
775 && bridge_cfg->secondarybus == cfg->bus) {
776 return bridge_cfg;
777 }
778 }
779 }
780
781 return NULL;
782}
783
784static int
41c20dac 785pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td)
984263bc 786{
4a5a2d63 787 device_t pci, pcib;
984263bc
MD
788 struct pci_io *io;
789 const char *name;
790 int error;
791
792 if (!(flag & FWRITE))
793 return EPERM;
794
795
796 switch(cmd) {
797 case PCIOCGETCONF:
798 {
799 struct pci_devinfo *dinfo;
800 struct pci_conf_io *cio;
801 struct devlist *devlist_head;
802 struct pci_match_conf *pattern_buf;
803 int num_patterns;
804 size_t iolen;
805 int ionum, i;
806
807 cio = (struct pci_conf_io *)data;
808
809 num_patterns = 0;
810 dinfo = NULL;
811
812 /*
813 * Hopefully the user won't pass in a null pointer, but it
814 * can't hurt to check.
815 */
816 if (cio == NULL) {
817 error = EINVAL;
818 break;
819 }
820
821 /*
822 * If the user specified an offset into the device list,
823 * but the list has changed since they last called this
824 * ioctl, tell them that the list has changed. They will
825 * have to get the list from the beginning.
826 */
827 if ((cio->offset != 0)
828 && (cio->generation != pci_generation)){
829 cio->num_matches = 0;
830 cio->status = PCI_GETCONF_LIST_CHANGED;
831 error = 0;
832 break;
833 }
834
835 /*
836 * Check to see whether the user has asked for an offset
837 * past the end of our list.
838 */
839 if (cio->offset >= pci_numdevs) {
840 cio->num_matches = 0;
841 cio->status = PCI_GETCONF_LAST_DEVICE;
842 error = 0;
843 break;
844 }
845
846 /* get the head of the device queue */
847 devlist_head = &pci_devq;
848
849 /*
850 * Determine how much room we have for pci_conf structures.
851 * Round the user's buffer size down to the nearest
852 * multiple of sizeof(struct pci_conf) in case the user
853 * didn't specify a multiple of that size.
854 */
855 iolen = min(cio->match_buf_len -
856 (cio->match_buf_len % sizeof(struct pci_conf)),
857 pci_numdevs * sizeof(struct pci_conf));
858
859 /*
860 * Since we know that iolen is a multiple of the size of
861 * the pciconf union, it's okay to do this.
862 */
863 ionum = iolen / sizeof(struct pci_conf);
864
865 /*
866 * If this test is true, the user wants the pci_conf
867 * structures returned to match the supplied entries.
868 */
869 if ((cio->num_patterns > 0)
870 && (cio->pat_buf_len > 0)) {
871 /*
872 * pat_buf_len needs to be:
873 * num_patterns * sizeof(struct pci_match_conf)
874 * While it is certainly possible the user just
875 * allocated a large buffer, but set the number of
876 * matches correctly, it is far more likely that
877 * their kernel doesn't match the userland utility
878 * they're using. It's also possible that the user
879 * forgot to initialize some variables. Yes, this
880 * may be overly picky, but I hazard to guess that
881 * it's far more likely to just catch folks that
882 * updated their kernel but not their userland.
883 */
884 if ((cio->num_patterns *
885 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
886 /* The user made a mistake, return an error*/
887 cio->status = PCI_GETCONF_ERROR;
888 printf("pci_ioctl: pat_buf_len %d != "
889 "num_patterns (%d) * sizeof(struct "
890 "pci_match_conf) (%d)\npci_ioctl: "
891 "pat_buf_len should be = %d\n",
892 cio->pat_buf_len, cio->num_patterns,
893 (int)sizeof(struct pci_match_conf),
894 (int)sizeof(struct pci_match_conf) *
895 cio->num_patterns);
896 printf("pci_ioctl: do your headers match your "
897 "kernel?\n");
898 cio->num_matches = 0;
899 error = EINVAL;
900 break;
901 }
902
903 /*
904 * Check the user's buffer to make sure it's readable.
905 */
906 if (!useracc((caddr_t)cio->patterns,
907 cio->pat_buf_len, VM_PROT_READ)) {
908 printf("pci_ioctl: pattern buffer %p, "
909 "length %u isn't user accessible for"
910 " READ\n", cio->patterns,
911 cio->pat_buf_len);
912 error = EACCES;
913 break;
914 }
915 /*
916 * Allocate a buffer to hold the patterns.
917 */
918 pattern_buf = malloc(cio->pat_buf_len, M_TEMP,
919 M_WAITOK);
920 error = copyin(cio->patterns, pattern_buf,
921 cio->pat_buf_len);
922 if (error != 0)
923 break;
924 num_patterns = cio->num_patterns;
925
926 } else if ((cio->num_patterns > 0)
927 || (cio->pat_buf_len > 0)) {
928 /*
929 * The user made a mistake, spit out an error.
930 */
931 cio->status = PCI_GETCONF_ERROR;
932 cio->num_matches = 0;
933 printf("pci_ioctl: invalid GETCONF arguments\n");
934 error = EINVAL;
935 break;
936 } else
937 pattern_buf = NULL;
938
939 /*
940 * Make sure we can write to the match buffer.
941 */
942 if (!useracc((caddr_t)cio->matches,
943 cio->match_buf_len, VM_PROT_WRITE)) {
944 printf("pci_ioctl: match buffer %p, length %u "
945 "isn't user accessible for WRITE\n",
946 cio->matches, cio->match_buf_len);
947 error = EACCES;
948 break;
949 }
950
951 /*
952 * Go through the list of devices and copy out the devices
953 * that match the user's criteria.
954 */
955 for (cio->num_matches = 0, error = 0, i = 0,
956 dinfo = STAILQ_FIRST(devlist_head);
957 (dinfo != NULL) && (cio->num_matches < ionum)
958 && (error == 0) && (i < pci_numdevs);
959 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
960
961 if (i < cio->offset)
962 continue;
963
964 /* Populate pd_name and pd_unit */
965 name = NULL;
966 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
967 name = device_get_name(dinfo->cfg.dev);
968 if (name) {
969 strncpy(dinfo->conf.pd_name, name,
970 sizeof(dinfo->conf.pd_name));
971 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
972 dinfo->conf.pd_unit =
973 device_get_unit(dinfo->cfg.dev);
974 }
975
976 if ((pattern_buf == NULL) ||
977 (pci_conf_match(pattern_buf, num_patterns,
978 &dinfo->conf) == 0)) {
979
980 /*
981 * If we've filled up the user's buffer,
982 * break out at this point. Since we've
983 * got a match here, we'll pick right back
984 * up at the matching entry. We can also
985 * tell the user that there are more matches
986 * left.
987 */
988 if (cio->num_matches >= ionum)
989 break;
990
991 error = copyout(&dinfo->conf,
992 &cio->matches[cio->num_matches],
993 sizeof(struct pci_conf));
994 cio->num_matches++;
995 }
996 }
997
998 /*
999 * Set the pointer into the list, so if the user is getting
1000 * n records at a time, where n < pci_numdevs,
1001 */
1002 cio->offset = i;
1003
1004 /*
1005 * Set the generation, the user will need this if they make
1006 * another ioctl call with offset != 0.
1007 */
1008 cio->generation = pci_generation;
1009
1010 /*
1011 * If this is the last device, inform the user so he won't
1012 * bother asking for more devices. If dinfo isn't NULL, we
1013 * know that there are more matches in the list because of
1014 * the way the traversal is done.
1015 */
1016 if (dinfo == NULL)
1017 cio->status = PCI_GETCONF_LAST_DEVICE;
1018 else
1019 cio->status = PCI_GETCONF_MORE_DEVS;
1020
1021 if (pattern_buf != NULL)
1022 free(pattern_buf, M_TEMP);
1023
1024 break;
1025 }
1026 case PCIOCREAD:
1027 io = (struct pci_io *)data;
1028 switch(io->pi_width) {
984263bc
MD
1029 case 4:
1030 case 2:
1031 case 1:
4a5a2d63
JS
1032 /*
1033 * Assume that the user-level bus number is
1034 * actually the pciN instance number. We map
1035 * from that to the real pcib+bus combination.
1036 */
1037 pci = devclass_get_device(pci_devclass,
1038 io->pi_sel.pc_bus);
1039 if (pci) {
1040 int b = pcib_get_bus(pci);
1041 pcib = device_get_parent(pci);
1042 io->pi_data =
1043 PCIB_READ_CONFIG(pcib,
1044 b,
1045 io->pi_sel.pc_dev,
1046 io->pi_sel.pc_func,
1047 io->pi_reg,
1048 io->pi_width);
1049 error = 0;
1050 } else {
1051 error = ENODEV;
1052 }
984263bc
MD
1053 break;
1054 default:
1055 error = ENODEV;
1056 break;
1057 }
1058 break;
1059
1060 case PCIOCWRITE:
1061 io = (struct pci_io *)data;
1062 switch(io->pi_width) {
984263bc
MD
1063 case 4:
1064 case 2:
1065 case 1:
4a5a2d63
JS
1066 /*
1067 * Assume that the user-level bus number is
1068 * actually the pciN instance number. We map
1069 * from that to the real pcib+bus combination.
1070 */
1071 pci = devclass_get_device(pci_devclass,
1072 io->pi_sel.pc_bus);
1073 if (pci) {
1074 int b = pcib_get_bus(pci);
1075 pcib = device_get_parent(pci);
1076 PCIB_WRITE_CONFIG(pcib,
1077 b,
1078 io->pi_sel.pc_dev,
1079 io->pi_sel.pc_func,
1080 io->pi_reg,
1081 io->pi_data,
1082 io->pi_width);
1083 error = 0;
1084 } else {
1085 error = ENODEV;
1086 }
984263bc
MD
1087 break;
1088 default:
1089 error = ENODEV;
1090 break;
1091 }
1092 break;
1093
1094 default:
1095 error = ENOTTY;
1096 break;
1097 }
1098
1099 return (error);
1100}
1101
1102#define PCI_CDEV 78
1103
1104static struct cdevsw pcicdev = {
fabb8ceb
MD
1105 /* name */ "pci",
1106 /* maj */ PCI_CDEV,
1107 /* flags */ 0,
1108 /* port */ NULL,
1109 /* autoq */ 0,
1110
984263bc
MD
1111 /* open */ pci_open,
1112 /* close */ pci_close,
1113 /* read */ noread,
1114 /* write */ nowrite,
1115 /* ioctl */ pci_ioctl,
1116 /* poll */ nopoll,
1117 /* mmap */ nommap,
1118 /* strategy */ nostrategy,
984263bc 1119 /* dump */ nodump,
fabb8ceb 1120 /* psize */ nopsize
984263bc
MD
1121};
1122
1123#include "pci_if.h"
1124
984263bc
MD
1125/*
1126 * New style pci driver. Parent device is either a pci-host-bridge or a
1127 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1128 */
1129
22457186 1130void
984263bc
MD
1131pci_print_verbose(struct pci_devinfo *dinfo)
1132{
1133 if (bootverbose) {
1134 pcicfgregs *cfg = &dinfo->cfg;
1135
1136 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
1137 cfg->vendor, cfg->device, cfg->revid);
4a5a2d63
JS
1138 printf("\tbus=%d, slot=%d, func=%d\n",
1139 cfg->bus, cfg->slot, cfg->func);
984263bc
MD
1140 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
1141 cfg->baseclass, cfg->subclass, cfg->progif,
1142 cfg->hdrtype, cfg->mfdev);
1143 printf("\tsubordinatebus=%x \tsecondarybus=%x\n",
1144 cfg->subordinatebus, cfg->secondarybus);
1145#ifdef PCI_DEBUG
1146 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
1147 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
1148 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
1149 cfg->lattimer, cfg->lattimer * 30,
1150 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1151#endif /* PCI_DEBUG */
1152 if (cfg->intpin > 0)
1153 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
1154 }
1155}
1156
1157static int
4a5a2d63 1158pci_porten(device_t pcib, int b, int s, int f)
984263bc 1159{
4a5a2d63
JS
1160 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1161 & PCIM_CMD_PORTEN) != 0;
984263bc
MD
1162}
1163
1164static int
4a5a2d63 1165pci_memen(device_t pcib, int b, int s, int f)
984263bc 1166{
4a5a2d63
JS
1167 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1168 & PCIM_CMD_MEMEN) != 0;
984263bc
MD
1169}
1170
1171/*
1172 * Add a resource based on a pci map register. Return 1 if the map
1173 * register is a 32bit map register or 2 if it is a 64bit register.
1174 */
1175static int
4a5a2d63
JS
1176pci_add_map(device_t pcib, int b, int s, int f, int reg,
1177 struct resource_list *rl)
984263bc 1178{
984263bc
MD
1179 u_int32_t map;
1180 u_int64_t base;
1181 u_int8_t ln2size;
1182 u_int8_t ln2range;
1183 u_int32_t testval;
4a5a2d63
JS
1184
1185
1186#ifdef PCI_ENABLE_IO_MODES
1187 u_int16_t cmd;
1188#endif
984263bc
MD
1189 int type;
1190
4a5a2d63 1191 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
984263bc
MD
1192
1193 if (map == 0 || map == 0xffffffff)
1194 return 1; /* skip invalid entry */
1195
4a5a2d63
JS
1196 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1197 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1198 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
984263bc
MD
1199
1200 base = pci_mapbase(map);
1201 if (pci_maptype(map) & PCI_MAPMEM)
1202 type = SYS_RES_MEMORY;
1203 else
1204 type = SYS_RES_IOPORT;
1205 ln2size = pci_mapsize(testval);
1206 ln2range = pci_maprange(testval);
1207 if (ln2range == 64) {
1208 /* Read the other half of a 64bit map register */
4a5a2d63 1209 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
984263bc
MD
1210 }
1211
984263bc
MD
1212 /*
1213 * This code theoretically does the right thing, but has
1214 * undesirable side effects in some cases where
1215 * peripherals respond oddly to having these bits
1216 * enabled. Leave them alone by default.
1217 */
1218#ifdef PCI_ENABLE_IO_MODES
4a5a2d63
JS
1219 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1220 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1221 cmd |= PCIM_CMD_PORTEN;
1222 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc 1223 }
4a5a2d63
JS
1224 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1225 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1226 cmd |= PCIM_CMD_MEMEN;
1227 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc
MD
1228 }
1229#else
4a5a2d63 1230 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
984263bc 1231 return 1;
4a5a2d63 1232 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
984263bc
MD
1233 return 1;
1234#endif
1235
1236 resource_list_add(rl, type, reg,
1237 base, base + (1 << ln2size) - 1,
1238 (1 << ln2size));
1239
1240 if (bootverbose) {
1241 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
1242 reg, pci_maptype(base), ln2range,
1243 (unsigned int) base, ln2size);
1244 }
1245
1246 return (ln2range == 64) ? 2 : 1;
1247}
1248
1249static void
4a5a2d63 1250pci_add_resources(device_t pcib, int b, int s, int f, device_t dev)
984263bc
MD
1251{
1252 struct pci_devinfo *dinfo = device_get_ivars(dev);
4a5a2d63 1253 pcicfgregs *cfg = &dinfo->cfg;
984263bc
MD
1254 struct resource_list *rl = &dinfo->resources;
1255 struct pci_quirk *q;
1256 int i;
1257
1258 for (i = 0; i < cfg->nummaps;) {
4a5a2d63 1259 i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl);
984263bc
MD
1260 }
1261
1262 for (q = &pci_quirks[0]; q->devid; q++) {
1263 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1264 && q->type == PCI_QUIRK_MAP_REG)
4a5a2d63 1265 pci_add_map(pcib, b, s, f, q->arg1, rl);
984263bc
MD
1266 }
1267
1268 if (cfg->intpin > 0 && cfg->intline != 255)
1269 resource_list_add(rl, SYS_RES_IRQ, 0,
1270 cfg->intline, cfg->intline, 1);
1271}
1272
1273static void
1274pci_add_children(device_t dev, int busno)
1275{
4a5a2d63
JS
1276 device_t pcib = device_get_parent(dev);
1277 int maxslots;
1278 int s, f;
984263bc 1279
4a5a2d63 1280 maxslots = PCIB_MAXSLOTS(pcib);
984263bc 1281
57e943f7 1282 for (s = 0; s <= maxslots; s++) {
984263bc 1283 int pcifunchigh = 0;
5e658043 1284 for (f = 0; f <= pcifunchigh; f++) {
4a5a2d63 1285 struct pci_devinfo *dinfo =
22457186 1286 pci_read_device(pcib, busno, s, f, sizeof *dinfo);
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1287 if (dinfo != NULL) {
1288 if (dinfo->cfg.mfdev)
1289 pcifunchigh = 7;
1290
1291 pci_print_verbose(dinfo);
1292 dinfo->cfg.dev = device_add_child(dev, NULL, -1);
1293 device_set_ivars(dinfo->cfg.dev, dinfo);
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1294 pci_add_resources(pcib, busno, s, f,
1295 dinfo->cfg.dev);
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1296 }
1297 }
1298 }
1299}
1300
1301static int
4a5a2d63 1302pci_probe(device_t dev)
984263bc 1303{
4a5a2d63 1304 static int once, busno;
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1305
1306 device_set_desc(dev, "PCI bus");
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1307
1308 if (bootverbose)
1309 device_printf(dev, "physical bus=%d\n", pcib_get_bus(dev));
1310
1311 /*
1312 * Since there can be multiple independently numbered PCI
1313 * busses on some large alpha systems, we can't use the unit
1314 * number to decide what bus we are probing. We ask the parent
1315 * pcib what our bus number is.
1316 */
1317 busno = pcib_get_bus(dev);
1318 if (busno < 0)
1319 return ENXIO;
1320 pci_add_children(dev, busno);
1321
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1322 if (!once) {
1323 make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci");
1324 once++;
1325 }
1326
1327 return 0;
1328}
1329
1330static int
1331pci_print_resources(struct resource_list *rl, const char *name, int type,
1332 const char *format)
1333{
1334 struct resource_list_entry *rle;
1335 int printed, retval;
1336
1337 printed = 0;
1338 retval = 0;
1339 /* Yes, this is kinda cheating */
1340 SLIST_FOREACH(rle, rl, link) {
1341 if (rle->type == type) {
1342 if (printed == 0)
1343 retval += printf(" %s ", name);
1344 else if (printed > 0)
1345 retval += printf(",");
1346 printed++;
1347 retval += printf(format, rle->start);
1348 if (rle->count > 1) {
1349 retval += printf("-");
1350 retval += printf(format, rle->start +
1351 rle->count - 1);
1352 }
1353 }
1354 }
1355 return retval;
1356}
1357
1358static int
1359pci_print_child(device_t dev, device_t child)
1360{
1361 struct pci_devinfo *dinfo;
1362 struct resource_list *rl;
1363 pcicfgregs *cfg;
1364 int retval = 0;
1365
1366 dinfo = device_get_ivars(child);
1367 cfg = &dinfo->cfg;
1368 rl = &dinfo->resources;
1369
1370 retval += bus_print_child_header(dev, child);
1371
1372 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1373 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1374 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1375 if (device_get_flags(dev))
1376 retval += printf(" flags %#x", device_get_flags(dev));
1377
1378 retval += printf(" at device %d.%d", pci_get_slot(child),
1379 pci_get_function(child));
1380
1381 retval += bus_print_child_footer(dev, child);
1382
1383 return (retval);
1384}
1385
1386static void
1387pci_probe_nomatch(device_t dev, device_t child)
1388{
1389 struct pci_devinfo *dinfo;
1390 pcicfgregs *cfg;
1391 const char *desc;
1392 int unknown;
1393
1394 unknown = 0;
1395 dinfo = device_get_ivars(child);
1396 cfg = &dinfo->cfg;
1397 desc = pci_ata_match(child);
1398 if (!desc) desc = pci_usb_match(child);
1399 if (!desc) desc = pci_vga_match(child);
27c23c6b 1400 if (!desc) desc = pci_chip_match(child);
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1401 if (!desc) {
1402 desc = "unknown card";
1403 unknown++;
1404 }
1405 device_printf(dev, "<%s>", desc);
1406 if (bootverbose || unknown) {
1407 printf(" (vendor=0x%04x, dev=0x%04x)",
1408 cfg->vendor,
1409 cfg->device);
1410 }
1411 printf(" at %d.%d",
1412 pci_get_slot(child),
1413 pci_get_function(child));
1414 if (cfg->intpin > 0 && cfg->intline != 255) {
1415 printf(" irq %d", cfg->intline);
1416 }
1417 printf("\n");
1418
1419 return;
1420}
1421
22457186 1422int
4a5a2d63 1423pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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1424{
1425 struct pci_devinfo *dinfo;
1426 pcicfgregs *cfg;
1427
1428 dinfo = device_get_ivars(child);
1429 cfg = &dinfo->cfg;
1430
1431 switch (which) {
1432 case PCI_IVAR_SUBVENDOR:
1433 *result = cfg->subvendor;
1434 break;
1435 case PCI_IVAR_SUBDEVICE:
1436 *result = cfg->subdevice;
1437 break;
1438 case PCI_IVAR_VENDOR:
1439 *result = cfg->vendor;
1440 break;
1441 case PCI_IVAR_DEVICE:
1442 *result = cfg->device;
1443 break;
1444 case PCI_IVAR_DEVID:
1445 *result = (cfg->device << 16) | cfg->vendor;
1446 break;
1447 case PCI_IVAR_CLASS:
1448 *result = cfg->baseclass;
1449 break;
1450 case PCI_IVAR_SUBCLASS:
1451 *result = cfg->subclass;
1452 break;
1453 case PCI_IVAR_PROGIF:
1454 *result = cfg->progif;
1455 break;
1456 case PCI_IVAR_REVID:
1457 *result = cfg->revid;
1458 break;
1459 case PCI_IVAR_INTPIN:
1460 *result = cfg->intpin;
1461 break;
1462 case PCI_IVAR_IRQ:
1463 *result = cfg->intline;
1464 break;
1465 case PCI_IVAR_BUS:
1466 *result = cfg->bus;
1467 break;
1468 case PCI_IVAR_SLOT:
1469 *result = cfg->slot;
1470 break;
1471 case PCI_IVAR_FUNCTION:
1472 *result = cfg->func;
1473 break;
1474 case PCI_IVAR_SECONDARYBUS:
1475 *result = cfg->secondarybus;
1476 break;
1477 case PCI_IVAR_SUBORDINATEBUS:
1478 *result = cfg->subordinatebus;
1479 break;
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1480 case PCI_IVAR_ETHADDR:
1481 /*
1482 * The generic accessor doesn't deal with failure, so
1483 * we set the return value, then return an error.
1484 */
1485 *result = NULL;
1486 return (EINVAL);
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1487 default:
1488 return ENOENT;
1489 }
1490 return 0;
1491}
1492
22457186 1493int
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1494pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1495{
1496 struct pci_devinfo *dinfo;
1497 pcicfgregs *cfg;
1498
1499 dinfo = device_get_ivars(child);
1500 cfg = &dinfo->cfg;
1501
1502 switch (which) {
1503 case PCI_IVAR_SUBVENDOR:
1504 case PCI_IVAR_SUBDEVICE:
1505 case PCI_IVAR_VENDOR:
1506 case PCI_IVAR_DEVICE:
1507 case PCI_IVAR_DEVID:
1508 case PCI_IVAR_CLASS:
1509 case PCI_IVAR_SUBCLASS:
1510 case PCI_IVAR_PROGIF:
1511 case PCI_IVAR_REVID:
1512 case PCI_IVAR_INTPIN:
1513 case PCI_IVAR_IRQ:
1514 case PCI_IVAR_BUS:
1515 case PCI_IVAR_SLOT:
1516 case PCI_IVAR_FUNCTION:
f72d3d23 1517 case PCI_IVAR_ETHADDR:
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1518 return EINVAL; /* disallow for now */
1519
1520 case PCI_IVAR_SECONDARYBUS:
1521 cfg->secondarybus = value;
1522 break;
1523 case PCI_IVAR_SUBORDINATEBUS:
1524 cfg->subordinatebus = value;
1525 break;
1526 default:
1527 return ENOENT;
1528 }
1529 return 0;
1530}
1531
1532static struct resource *
1533pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1534 u_long start, u_long end, u_long count, u_int flags)
1535{
1536 struct pci_devinfo *dinfo = device_get_ivars(child);
1537 struct resource_list *rl = &dinfo->resources;
1538
4a5a2d63 1539#ifdef __i386__
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1540 pcicfgregs *cfg = &dinfo->cfg;
1541 /*
1542 * Perform lazy resource allocation
1543 *
1544 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY
1545 */
1546 if (device_get_parent(child) == dev) {
1547 /*
1548 * If device doesn't have an interrupt routed, and is
1549 * deserving of an interrupt, try to assign it one.
1550 */
1551 if ((type == SYS_RES_IRQ) &&
1552 (cfg->intline == 255 || cfg->intline == 0) &&
1553 (cfg->intpin != 0) && (start == 0) && (end == ~0UL)) {
4a5a2d63 1554 cfg->intline = PCIB_ROUTE_INTERRUPT(
57e943f7 1555 device_get_parent(dev), child,
4a5a2d63 1556 cfg->intpin);
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1557 if (cfg->intline != 255) {
1558 pci_write_config(child, PCIR_INTLINE,
1559 cfg->intline, 1);
1560 resource_list_add(rl, SYS_RES_IRQ, 0,
1561 cfg->intline, cfg->intline, 1);
1562 }
1563 }
1564 }
1565#endif
1566 return resource_list_alloc(rl, dev, child, type, rid,
1567 start, end, count, flags);
1568}
1569
1570static int
1571pci_release_resource(device_t dev, device_t child, int type, int rid,
1572 struct resource *r)
1573{
1574 struct pci_devinfo *dinfo = device_get_ivars(child);
1575 struct resource_list *rl = &dinfo->resources;
1576
1577 return resource_list_release(rl, dev, child, type, rid, r);
1578}
1579
1580static int
1581pci_set_resource(device_t dev, device_t child, int type, int rid,
1582 u_long start, u_long count)
1583{
1584 struct pci_devinfo *dinfo = device_get_ivars(child);
1585 struct resource_list *rl = &dinfo->resources;
1586
1587 resource_list_add(rl, type, rid, start, start + count - 1, count);
1588 return 0;
1589}
1590
1591static int
1592pci_get_resource(device_t dev, device_t child, int type, int rid,
1593 u_long *startp, u_long *countp)
1594{
1595 struct pci_devinfo *dinfo = device_get_ivars(child);
1596 struct resource_list *rl = &dinfo->resources;
1597 struct resource_list_entry *rle;
1598
1599 rle = resource_list_find(rl, type, rid);
1600 if (!rle)
1601 return ENOENT;
1602
1603 if (startp)
1604 *startp = rle->start;
1605 if (countp)
1606 *countp = rle->count;
1607
1608 return 0;
1609}
1610
1611static void
1612pci_delete_resource(device_t dev, device_t child, int type, int rid)
1613{
1614 printf("pci_delete_resource: PCI resources can not be deleted\n");
1615}
1616
1617static u_int32_t
1618pci_read_config_method(device_t dev, device_t child, int reg, int width)
1619{
1620 struct pci_devinfo *dinfo = device_get_ivars(child);
1621 pcicfgregs *cfg = &dinfo->cfg;
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1622
1623 return PCIB_READ_CONFIG(device_get_parent(dev),
1624 cfg->bus, cfg->slot, cfg->func,
1625 reg, width);
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1626}
1627
1628static void
1629pci_write_config_method(device_t dev, device_t child, int reg,
1630 u_int32_t val, int width)
1631{
1632 struct pci_devinfo *dinfo = device_get_ivars(child);
1633 pcicfgregs *cfg = &dinfo->cfg;
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1634
1635 PCIB_WRITE_CONFIG(device_get_parent(dev),
1636 cfg->bus, cfg->slot, cfg->func,
1637 reg, val, width);
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1638}
1639
1640static int
1641pci_modevent(module_t mod, int what, void *arg)
1642{
1643 switch (what) {
1644 case MOD_LOAD:
1645 STAILQ_INIT(&pci_devq);
1646 break;
1647
1648 case MOD_UNLOAD:
1649 break;
1650 }
1651
1652 return 0;
1653}
1654
1655static device_method_t pci_methods[] = {
1656 /* Device interface */
4a5a2d63 1657 DEVMETHOD(device_probe, pci_probe),
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1658 DEVMETHOD(device_attach, bus_generic_attach),
1659 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1660 DEVMETHOD(device_suspend, bus_generic_suspend),
1661 DEVMETHOD(device_resume, bus_generic_resume),
1662
1663 /* Bus interface */
1664 DEVMETHOD(bus_print_child, pci_print_child),
1665 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
1666 DEVMETHOD(bus_read_ivar, pci_read_ivar),
1667 DEVMETHOD(bus_write_ivar, pci_write_ivar),
1668 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1669 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
1670 DEVMETHOD(bus_release_resource, pci_release_resource),
1671 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1672 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1673 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1674 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1675 DEVMETHOD(bus_set_resource, pci_set_resource),
1676 DEVMETHOD(bus_get_resource, pci_get_resource),
1677 DEVMETHOD(bus_delete_resource, pci_delete_resource),
1678
1679 /* PCI interface */
1680 DEVMETHOD(pci_read_config, pci_read_config_method),
1681 DEVMETHOD(pci_write_config, pci_write_config_method),
1682 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
1683 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
1684 DEVMETHOD(pci_enable_io, pci_enable_io_method),
1685 DEVMETHOD(pci_disable_io, pci_disable_io_method),
1686 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
1687 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
1688
1689 { 0, 0 }
1690};
1691
1692static driver_t pci_driver = {
1693 "pci",
1694 pci_methods,
1695 1, /* no softc */
1696};
1697
1698DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);