Don't use the devstat->busy_count for state decisions in the device
[dragonfly.git] / sys / bus / pci / pci.c
CommitLineData
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1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
b4c0a845 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.48 2007/11/25 04:08:42 sephe Exp $
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28 *
29 */
30
31#include "opt_bus.h"
32#include "opt_pci.h"
33
dc5a7bd2 34#include "opt_compat_oldpci.h"
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35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/malloc.h>
39#include <sys/module.h>
40#include <sys/fcntl.h>
41#include <sys/conf.h>
42#include <sys/kernel.h>
43#include <sys/queue.h>
44#include <sys/types.h>
45#include <sys/buf.h>
46
47#include <vm/vm.h>
48#include <vm/pmap.h>
49#include <vm/vm_extern.h>
50
51#include <sys/bus.h>
984263bc 52#include <sys/rman.h>
97359a5b 53#include <machine/smp.h>
984263bc 54#ifdef __i386__
bbca97bc 55#include <bus/pci/i386/pci_cfgreg.h>
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56#endif
57
dc5a7bd2 58#include <sys/pciio.h>
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59#include "pcireg.h"
60#include "pcivar.h"
22457186 61#include "pci_private.h"
984263bc 62
4a5a2d63
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63#include "pcib_if.h"
64
e126caf1 65devclass_t pci_devclass;
2581072f 66const char *pcib_owner;
dc5a7bd2 67
e9d8f4df 68static void pci_read_capabilities(device_t dev, pcicfgregs *cfg);
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69
70struct pci_quirk {
71 u_int32_t devid; /* Vendor/device of the card */
72 int type;
3e4db402 73#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
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74 int arg1;
75 int arg2;
76};
77
78struct pci_quirk pci_quirks[] = {
79 /*
80 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
81 */
82 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
83 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
f1f0bfb2
JS
84 /* As does the Serverworks OSB4 (the SMBus mapping register) */
85 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
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86
87 { 0 }
88};
89
90/* map register information */
91#define PCI_MAPMEM 0x01 /* memory map */
92#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
93#define PCI_MAPPORT 0x04 /* port map */
94
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95static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
96u_int32_t pci_numdevs = 0;
97static u_int32_t pci_generation = 0;
98
99device_t
c0f16abb 100pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func)
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101{
102 struct pci_devinfo *dinfo;
103
104 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
105 if ((dinfo->cfg.bus == bus) &&
106 (dinfo->cfg.slot == slot) &&
107 (dinfo->cfg.func == func)) {
108 return (dinfo->cfg.dev);
109 }
110 }
111
112 return (NULL);
113}
114
115device_t
c0f16abb 116pci_find_device(u_int16_t vendor, u_int16_t device)
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117{
118 struct pci_devinfo *dinfo;
119
120 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
121 if ((dinfo->cfg.vendor == vendor) &&
122 (dinfo->cfg.device == device)) {
123 return (dinfo->cfg.dev);
124 }
125 }
126
127 return (NULL);
128}
129
130/* return base address of memory or port map */
131
132static u_int32_t
133pci_mapbase(unsigned mapreg)
134{
135 int mask = 0x03;
136 if ((mapreg & 0x01) == 0)
137 mask = 0x0f;
138 return (mapreg & ~mask);
139}
140
141/* return map type of memory or port map */
142
143static int
144pci_maptype(unsigned mapreg)
145{
146 static u_int8_t maptype[0x10] = {
147 PCI_MAPMEM, PCI_MAPPORT,
148 PCI_MAPMEM, 0,
149 PCI_MAPMEM, PCI_MAPPORT,
150 0, 0,
151 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
152 PCI_MAPMEM|PCI_MAPMEMP, 0,
153 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
154 0, 0,
155 };
156
157 return maptype[mapreg & 0x0f];
158}
159
160/* return log2 of map size decoded for memory or port map */
161
162static int
163pci_mapsize(unsigned testval)
164{
165 int ln2size;
166
167 testval = pci_mapbase(testval);
168 ln2size = 0;
169 if (testval != 0) {
170 while ((testval & 1) == 0)
171 {
172 ln2size++;
173 testval >>= 1;
174 }
175 }
176 return (ln2size);
177}
178
179/* return log2 of address range supported by map register */
180
181static int
182pci_maprange(unsigned mapreg)
183{
184 int ln2range = 0;
185 switch (mapreg & 0x07) {
186 case 0x00:
187 case 0x01:
188 case 0x05:
189 ln2range = 32;
190 break;
191 case 0x02:
192 ln2range = 20;
193 break;
194 case 0x04:
195 ln2range = 64;
196 break;
197 }
198 return (ln2range);
199}
200
201/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
202
203static void
204pci_fixancient(pcicfgregs *cfg)
205{
206 if (cfg->hdrtype != 0)
207 return;
208
209 /* PCI to PCI bridges use header type 1 */
210 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
211 cfg->hdrtype = 1;
212}
213
214/* read config data specific to header type 1 device (PCI to PCI bridge) */
215
216static void *
4a5a2d63 217pci_readppb(device_t pcib, int b, int s, int f)
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218{
219 pcih1cfgregs *p;
220
efda3bd0 221 p = kmalloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
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222 if (p == NULL)
223 return (NULL);
224
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225 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
226 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
984263bc 227
4a5a2d63 228 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
984263bc 229
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230 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
231 PCIR_IOBASEH_1, 2),
232 PCIB_READ_CONFIG(pcib, b, s, f,
233 PCIR_IOBASEL_1, 1));
234 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
235 PCIR_IOLIMITH_1, 2),
236 PCIB_READ_CONFIG(pcib, b, s, f,
237 PCIR_IOLIMITL_1, 1));
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238
239 p->membase = PCI_PPBMEMBASE (0,
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240 PCIB_READ_CONFIG(pcib, b, s, f,
241 PCIR_MEMBASE_1, 2));
984263bc 242 p->memlimit = PCI_PPBMEMLIMIT (0,
4a5a2d63
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243 PCIB_READ_CONFIG(pcib, b, s, f,
244 PCIR_MEMLIMIT_1, 2));
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245
246 p->pmembase = PCI_PPBMEMBASE (
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247 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
248 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
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249
250 p->pmemlimit = PCI_PPBMEMLIMIT (
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251 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
252 PCIR_PMLIMITH_1, 4),
253 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
254
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255 return (p);
256}
257
258/* read config data specific to header type 2 device (PCI to CardBus bridge) */
259
260static void *
4a5a2d63 261pci_readpcb(device_t pcib, int b, int s, int f)
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262{
263 pcih2cfgregs *p;
264
efda3bd0 265 p = kmalloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
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266 if (p == NULL)
267 return (NULL);
268
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269 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
270 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
984263bc 271
4a5a2d63 272 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
984263bc 273
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274 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
275 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
276 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
277 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
984263bc 278
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279 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
280 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
281 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
282 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
984263bc 283
4a5a2d63 284 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
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285 return p;
286}
287
288/* extract header type specific config data */
289
290static void
4a5a2d63 291pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
984263bc 292{
4a5a2d63 293#define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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294 switch (cfg->hdrtype) {
295 case 0:
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296 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
297 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
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298 cfg->nummaps = PCI_MAXMAPS_0;
299 break;
300 case 1:
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301 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
302 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
303 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
304 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
984263bc 305 cfg->nummaps = PCI_MAXMAPS_1;
4a5a2d63 306 cfg->hdrspec = pci_readppb(pcib, b, s, f);
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307 break;
308 case 2:
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309 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
310 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
311 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
312 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
984263bc 313 cfg->nummaps = PCI_MAXMAPS_2;
4a5a2d63 314 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
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315 break;
316 }
4a5a2d63 317#undef REG
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318}
319
320/* read configuration header into pcicfgrect structure */
321
22457186 322struct pci_devinfo *
c01b8d84 323pci_read_device(device_t pcib, int b, int s, int f, size_t size)
984263bc 324{
4a5a2d63 325#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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326
327 pcicfgregs *cfg = NULL;
328 struct pci_devinfo *devlist_entry;
329 struct devlist *devlist_head;
330
331 devlist_head = &pci_devq;
332
333 devlist_entry = NULL;
334
4a5a2d63 335 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
984263bc 336
efda3bd0 337 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
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338 if (devlist_entry == NULL)
339 return (NULL);
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340
341 cfg = &devlist_entry->cfg;
342
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343 cfg->bus = b;
344 cfg->slot = s;
345 cfg->func = f;
346 cfg->vendor = REG(PCIR_VENDOR, 2);
347 cfg->device = REG(PCIR_DEVICE, 2);
348 cfg->cmdreg = REG(PCIR_COMMAND, 2);
349 cfg->statreg = REG(PCIR_STATUS, 2);
350 cfg->baseclass = REG(PCIR_CLASS, 1);
351 cfg->subclass = REG(PCIR_SUBCLASS, 1);
352 cfg->progif = REG(PCIR_PROGIF, 1);
353 cfg->revid = REG(PCIR_REVID, 1);
e126caf1 354 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
4a5a2d63
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355 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
356 cfg->lattimer = REG(PCIR_LATTIMER, 1);
357 cfg->intpin = REG(PCIR_INTPIN, 1);
358 cfg->intline = REG(PCIR_INTLINE, 1);
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359
360#ifdef APIC_IO
97359a5b
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361 /*
362 * If using the APIC the intpin is probably wrong, since it
363 * is often setup by the BIOS with the PIC in mind.
364 */
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365 if (cfg->intpin != 0) {
366 int airq;
367
368 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
369 if (airq >= 0) {
370 /* PCI specific entry found in MP table */
371 if (airq != cfg->intline) {
372 undirect_pci_irq(cfg->intline);
373 cfg->intline = airq;
374 }
375 } else {
376 /*
377 * PCI interrupts might be redirected to the
378 * ISA bus according to some MP tables. Use the
379 * same methods as used by the ISA devices
380 * devices to find the proper IOAPIC int pin.
381 */
382 airq = isa_apic_irq(cfg->intline);
383 if ((airq >= 0) && (airq != cfg->intline)) {
384 /* XXX: undirect_pci_irq() ? */
385 undirect_isa_irq(cfg->intline);
386 cfg->intline = airq;
387 }
388 }
389 }
390#endif /* APIC_IO */
391
4a5a2d63
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392 cfg->mingnt = REG(PCIR_MINGNT, 1);
393 cfg->maxlat = REG(PCIR_MAXLAT, 1);
984263bc
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394
395 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
396 cfg->hdrtype &= ~PCIM_MFDEV;
397
398 pci_fixancient(cfg);
4a5a2d63 399 pci_hdrtypedata(pcib, b, s, f, cfg);
e9d8f4df 400 pci_read_capabilities(pcib, cfg);
984263bc
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401
402 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
403
404 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
405 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
406 devlist_entry->conf.pc_sel.pc_func = cfg->func;
407 devlist_entry->conf.pc_hdr = cfg->hdrtype;
408
409 devlist_entry->conf.pc_subvendor = cfg->subvendor;
410 devlist_entry->conf.pc_subdevice = cfg->subdevice;
411 devlist_entry->conf.pc_vendor = cfg->vendor;
412 devlist_entry->conf.pc_device = cfg->device;
413
414 devlist_entry->conf.pc_class = cfg->baseclass;
415 devlist_entry->conf.pc_subclass = cfg->subclass;
416 devlist_entry->conf.pc_progif = cfg->progif;
417 devlist_entry->conf.pc_revid = cfg->revid;
418
419 pci_numdevs++;
420 pci_generation++;
421 }
422 return (devlist_entry);
423#undef REG
424}
425
1361c4cd
SZ
426static int
427pci_fixup_nextptr(int *nextptr0)
428{
429 int nextptr = *nextptr0;
430
431 /* "Next pointer" is only one byte */
432 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
433
434 if (nextptr & 0x3) {
435 /*
436 * PCI local bus spec 3.0:
437 *
438 * "... The bottom two bits of all pointers are reserved
439 * and must be implemented as 00b although software must
440 * mask them to allow for future uses of these bits ..."
441 */
442 if (bootverbose) {
443 kprintf("Illegal PCI extended capability "
444 "offset, fixup 0x%02x -> 0x%02x\n",
445 nextptr, nextptr & ~0x3);
446 }
447 nextptr &= ~0x3;
448 }
449 *nextptr0 = nextptr;
450
451 if (nextptr < 0x40) {
452 if (nextptr != 0) {
453 kprintf("Illegal PCI extended capability "
454 "offset 0x%02x", nextptr);
455 }
456 return 0;
457 }
458 return 1;
459}
460
8475d8bb
SZ
461static void
462pci_read_cap_pmgt(device_t pcib, int ptr, pcicfgregs *cfg)
463{
464#define REG(n, w) \
465 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
466
467 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
468
469 if (pmgt->pp_cap)
470 return;
471
472 pmgt->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
473 pmgt->pp_status = ptr + PCIR_POWER_STATUS;
474 pmgt->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
475 /*
476 * XXX
477 * Following way may be used to to test whether
478 * 'data' register exists:
479 * if 'data_select' register of
480 * PCIR_POWER_STATUS(bits[12,9]) is read-only
481 * then 'data' register is _not_ implemented.
482 */
483 pmgt->pp_data = 0;
484
485#undef REG
486}
487
b4c0a845
SZ
488static void
489pci_read_cap_expr(device_t pcib, int ptr, pcicfgregs *cfg)
490{
491#define REG(n, w) \
492 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
493
494 struct pcicfg_expr *expr = &cfg->expr;
495 uint16_t port_type;
496
497 expr->expr_ptr = ptr;
498 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
499
500 /*
501 * Only version 1 can be parsed currently
502 */
503 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
504 return;
505
506 /*
507 * Read slot capabilities
508 *
509 * Slot capabilities exists iff current port is root port or
510 * down stream port, and the slot is implemented.
511 *
512 * - Testing for root port or down stream port is meanningful
513 * iff PCI configure has type 1 header.
514 * - Slot implemented bit is meaningful iff current port is
515 * root port or down stream port.
516 */
517 if (cfg->hdrtype != 1)
518 return;
519
520 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
521 if (port_type != PCIEM_ROOT_PORT &&
522 port_type != PCIEM_DOWN_STREAM_PORT)
523 return;
524
525 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
526 return;
527
528 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
529
530#undef REG
531}
532
984263bc 533static void
e9d8f4df 534pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
984263bc 535{
8475d8bb
SZ
536#define REG(n, w) \
537 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
538
1361c4cd 539 int nextptr, ptrptr;
984263bc 540
0c78fe3f
SZ
541 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
542 /* No capabilities */
543 return;
544 }
545
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546 switch (cfg->hdrtype) {
547 case 0:
81c29ce4
SZ
548 case 1:
549 ptrptr = PCIR_CAP_PTR;
984263bc
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550 break;
551 case 2:
81c29ce4 552 ptrptr = PCIR_CAP_PTR_2;
984263bc
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553 break;
554 default:
0c78fe3f 555 return; /* No capabilities support */
984263bc 556 }
0c78fe3f 557 nextptr = REG(ptrptr, 1);
984263bc
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558
559 /*
560 * Read capability entries.
561 */
1361c4cd
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562 while (pci_fixup_nextptr(&nextptr)) {
563 int ptr = nextptr;
984263bc
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564
565 /* Process this entry */
566 switch (REG(ptr, 1)) {
81c29ce4 567 case PCIY_PMG: /* PCI power management */
8475d8bb 568 pci_read_cap_pmgt(pcib, ptr, cfg);
984263bc 569 break;
b4c0a845
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570 case PCIY_EXPRESS: /* PCI Express */
571 pci_read_cap_expr(pcib, ptr, cfg);
572 break;
984263bc
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573 default:
574 break;
575 }
1361c4cd
SZ
576
577 /* Find the next entry */
578 nextptr = REG(ptr + 1, 1);
984263bc 579 }
8475d8bb 580
984263bc
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581#undef REG
582}
583
984263bc
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584/* free pcicfgregs structure and all depending data structures */
585
22457186 586int
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587pci_freecfg(struct pci_devinfo *dinfo)
588{
589 struct devlist *devlist_head;
590
591 devlist_head = &pci_devq;
592
593 if (dinfo->cfg.hdrspec != NULL)
efda3bd0 594 kfree(dinfo->cfg.hdrspec, M_DEVBUF);
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595 /* XXX this hasn't been tested */
596 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
efda3bd0 597 kfree(dinfo, M_DEVBUF);
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598
599 /* increment the generation count */
600 pci_generation++;
601
602 /* we're losing one device */
603 pci_numdevs--;
604 return (0);
605}
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606
607
608/*
609 * PCI power manangement
610 */
e126caf1 611int
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612pci_set_powerstate_method(device_t dev, device_t child, int state)
613{
614 struct pci_devinfo *dinfo = device_get_ivars(child);
615 pcicfgregs *cfg = &dinfo->cfg;
1f7d9fe0 616 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
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617 u_int16_t status;
618 int result;
619
1f7d9fe0
SZ
620 if (pmgt->pp_cap != 0) {
621 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2) & ~PCIM_PSTAT_DMASK;
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622 result = 0;
623 switch (state) {
624 case PCI_POWERSTATE_D0:
625 status |= PCIM_PSTAT_D0;
626 break;
627 case PCI_POWERSTATE_D1:
1f7d9fe0 628 if (pmgt->pp_cap & PCIM_PCAP_D1SUPP) {
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629 status |= PCIM_PSTAT_D1;
630 } else {
631 result = EOPNOTSUPP;
632 }
633 break;
634 case PCI_POWERSTATE_D2:
1f7d9fe0 635 if (pmgt->pp_cap & PCIM_PCAP_D2SUPP) {
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636 status |= PCIM_PSTAT_D2;
637 } else {
638 result = EOPNOTSUPP;
639 }
640 break;
641 case PCI_POWERSTATE_D3:
642 status |= PCIM_PSTAT_D3;
643 break;
644 default:
645 result = EINVAL;
646 }
647 if (result == 0)
1f7d9fe0 648 PCI_WRITE_CONFIG(dev, child, pmgt->pp_status, status, 2);
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649 } else {
650 result = ENXIO;
651 }
652 return(result);
653}
654
e126caf1 655int
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656pci_get_powerstate_method(device_t dev, device_t child)
657{
658 struct pci_devinfo *dinfo = device_get_ivars(child);
659 pcicfgregs *cfg = &dinfo->cfg;
1f7d9fe0 660 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
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661 u_int16_t status;
662 int result;
663
1f7d9fe0
SZ
664 if (pmgt->pp_cap != 0) {
665 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2);
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666 switch (status & PCIM_PSTAT_DMASK) {
667 case PCIM_PSTAT_D0:
668 result = PCI_POWERSTATE_D0;
669 break;
670 case PCIM_PSTAT_D1:
671 result = PCI_POWERSTATE_D1;
672 break;
673 case PCIM_PSTAT_D2:
674 result = PCI_POWERSTATE_D2;
675 break;
676 case PCIM_PSTAT_D3:
677 result = PCI_POWERSTATE_D3;
678 break;
679 default:
680 result = PCI_POWERSTATE_UNKNOWN;
681 break;
682 }
683 } else {
684 /* No support, device is always at D0 */
685 result = PCI_POWERSTATE_D0;
686 }
687 return(result);
688}
689
690/*
691 * Some convenience functions for PCI device drivers.
692 */
693
694static __inline void
695pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
696{
697 u_int16_t command;
698
699 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
700 command |= bit;
701 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
702}
703
704static __inline void
705pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
706{
707 u_int16_t command;
708
709 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
710 command &= ~bit;
711 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
712}
713
e126caf1 714int
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715pci_enable_busmaster_method(device_t dev, device_t child)
716{
717 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 718 return(0);
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719}
720
e126caf1 721int
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722pci_disable_busmaster_method(device_t dev, device_t child)
723{
724 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 725 return(0);
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726}
727
e126caf1 728int
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729pci_enable_io_method(device_t dev, device_t child, int space)
730{
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MD
731 uint16_t command;
732 uint16_t bit;
733 char *error;
734
735 bit = 0;
736 error = NULL;
737
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738 switch(space) {
739 case SYS_RES_IOPORT:
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MD
740 bit = PCIM_CMD_PORTEN;
741 error = "port";
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MD
742 break;
743 case SYS_RES_MEMORY:
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744 bit = PCIM_CMD_MEMEN;
745 error = "memory";
984263bc 746 break;
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MD
747 default:
748 return(EINVAL);
984263bc 749 }
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MD
750 pci_set_command_bit(dev, child, bit);
751 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
752 if (command & bit)
753 return(0);
754 device_printf(child, "failed to enable %s mapping!\n", error);
755 return(ENXIO);
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756}
757
e126caf1 758int
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759pci_disable_io_method(device_t dev, device_t child, int space)
760{
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761 uint16_t command;
762 uint16_t bit;
763 char *error;
764
765 bit = 0;
766 error = NULL;
767
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768 switch(space) {
769 case SYS_RES_IOPORT:
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MD
770 bit = PCIM_CMD_PORTEN;
771 error = "port";
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772 break;
773 case SYS_RES_MEMORY:
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774 bit = PCIM_CMD_MEMEN;
775 error = "memory";
984263bc 776 break;
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MD
777 default:
778 return (EINVAL);
984263bc 779 }
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MD
780 pci_clear_command_bit(dev, child, bit);
781 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
782 if (command & bit) {
783 device_printf(child, "failed to disable %s mapping!\n", error);
784 return (ENXIO);
785 }
786 return (0);
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787}
788
789/*
790 * This is the user interface to PCI configuration space.
791 */
792
793static int
fef8985e 794pci_open(struct dev_open_args *ap)
984263bc 795{
fef8985e 796 if ((ap->a_oflags & FWRITE) && securelevel > 0) {
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797 return EPERM;
798 }
799 return 0;
800}
801
802static int
fef8985e 803pci_close(struct dev_close_args *ap)
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804{
805 return 0;
806}
807
808/*
809 * Match a single pci_conf structure against an array of pci_match_conf
810 * structures. The first argument, 'matches', is an array of num_matches
811 * pci_match_conf structures. match_buf is a pointer to the pci_conf
812 * structure that will be compared to every entry in the matches array.
813 * This function returns 1 on failure, 0 on success.
814 */
815static int
816pci_conf_match(struct pci_match_conf *matches, int num_matches,
817 struct pci_conf *match_buf)
818{
819 int i;
820
821 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
822 return(1);
823
824 for (i = 0; i < num_matches; i++) {
825 /*
826 * I'm not sure why someone would do this...but...
827 */
828 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
829 continue;
830
831 /*
832 * Look at each of the match flags. If it's set, do the
833 * comparison. If the comparison fails, we don't have a
834 * match, go on to the next item if there is one.
835 */
836 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
837 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
838 continue;
839
840 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
841 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
842 continue;
843
844 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
845 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
846 continue;
847
848 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
849 && (match_buf->pc_vendor != matches[i].pc_vendor))
850 continue;
851
852 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
853 && (match_buf->pc_device != matches[i].pc_device))
854 continue;
855
856 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
857 && (match_buf->pc_class != matches[i].pc_class))
858 continue;
859
860 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
861 && (match_buf->pd_unit != matches[i].pd_unit))
862 continue;
863
864 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
865 && (strncmp(matches[i].pd_name, match_buf->pd_name,
866 sizeof(match_buf->pd_name)) != 0))
867 continue;
868
869 return(0);
870 }
871
872 return(1);
873}
874
875/*
876 * Locate the parent of a PCI device by scanning the PCI devlist
877 * and return the entry for the parent.
878 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
879 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
880 */
881
882pcicfgregs *
883pci_devlist_get_parent(pcicfgregs *cfg)
884{
885 struct devlist *devlist_head;
886 struct pci_devinfo *dinfo;
887 pcicfgregs *bridge_cfg;
888 int i;
889
890 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
891
892 /* If the device is on PCI bus 0, look for the host */
893 if (cfg->bus == 0) {
894 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
895 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
896 bridge_cfg = &dinfo->cfg;
897 if (bridge_cfg->baseclass == PCIC_BRIDGE
898 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
899 && bridge_cfg->bus == cfg->bus) {
900 return bridge_cfg;
901 }
902 }
903 }
904
905 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
906 if (cfg->bus > 0) {
907 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
908 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
909 bridge_cfg = &dinfo->cfg;
910 if (bridge_cfg->baseclass == PCIC_BRIDGE
911 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
912 && bridge_cfg->secondarybus == cfg->bus) {
913 return bridge_cfg;
914 }
915 }
916 }
917
918 return NULL;
919}
920
921static int
fef8985e 922pci_ioctl(struct dev_ioctl_args *ap)
984263bc 923{
4a5a2d63 924 device_t pci, pcib;
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MD
925 struct pci_io *io;
926 const char *name;
927 int error;
928
fef8985e 929 if (!(ap->a_fflag & FWRITE))
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930 return EPERM;
931
fef8985e 932 switch(ap->a_cmd) {
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MD
933 case PCIOCGETCONF:
934 {
935 struct pci_devinfo *dinfo;
936 struct pci_conf_io *cio;
937 struct devlist *devlist_head;
938 struct pci_match_conf *pattern_buf;
939 int num_patterns;
940 size_t iolen;
941 int ionum, i;
942
fef8985e 943 cio = (struct pci_conf_io *)ap->a_data;
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944
945 num_patterns = 0;
946 dinfo = NULL;
947
948 /*
949 * Hopefully the user won't pass in a null pointer, but it
950 * can't hurt to check.
951 */
952 if (cio == NULL) {
953 error = EINVAL;
954 break;
955 }
956
957 /*
958 * If the user specified an offset into the device list,
959 * but the list has changed since they last called this
960 * ioctl, tell them that the list has changed. They will
961 * have to get the list from the beginning.
962 */
963 if ((cio->offset != 0)
964 && (cio->generation != pci_generation)){
965 cio->num_matches = 0;
966 cio->status = PCI_GETCONF_LIST_CHANGED;
967 error = 0;
968 break;
969 }
970
971 /*
972 * Check to see whether the user has asked for an offset
973 * past the end of our list.
974 */
975 if (cio->offset >= pci_numdevs) {
976 cio->num_matches = 0;
977 cio->status = PCI_GETCONF_LAST_DEVICE;
978 error = 0;
979 break;
980 }
981
982 /* get the head of the device queue */
983 devlist_head = &pci_devq;
984
985 /*
986 * Determine how much room we have for pci_conf structures.
987 * Round the user's buffer size down to the nearest
988 * multiple of sizeof(struct pci_conf) in case the user
989 * didn't specify a multiple of that size.
990 */
991 iolen = min(cio->match_buf_len -
992 (cio->match_buf_len % sizeof(struct pci_conf)),
993 pci_numdevs * sizeof(struct pci_conf));
994
995 /*
996 * Since we know that iolen is a multiple of the size of
997 * the pciconf union, it's okay to do this.
998 */
999 ionum = iolen / sizeof(struct pci_conf);
1000
1001 /*
1002 * If this test is true, the user wants the pci_conf
1003 * structures returned to match the supplied entries.
1004 */
1005 if ((cio->num_patterns > 0)
1006 && (cio->pat_buf_len > 0)) {
1007 /*
1008 * pat_buf_len needs to be:
1009 * num_patterns * sizeof(struct pci_match_conf)
1010 * While it is certainly possible the user just
1011 * allocated a large buffer, but set the number of
1012 * matches correctly, it is far more likely that
1013 * their kernel doesn't match the userland utility
1014 * they're using. It's also possible that the user
1015 * forgot to initialize some variables. Yes, this
1016 * may be overly picky, but I hazard to guess that
1017 * it's far more likely to just catch folks that
1018 * updated their kernel but not their userland.
1019 */
1020 if ((cio->num_patterns *
1021 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
1022 /* The user made a mistake, return an error*/
1023 cio->status = PCI_GETCONF_ERROR;
85f8e2ea 1024 kprintf("pci_ioctl: pat_buf_len %d != "
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MD
1025 "num_patterns (%d) * sizeof(struct "
1026 "pci_match_conf) (%d)\npci_ioctl: "
1027 "pat_buf_len should be = %d\n",
1028 cio->pat_buf_len, cio->num_patterns,
1029 (int)sizeof(struct pci_match_conf),
1030 (int)sizeof(struct pci_match_conf) *
1031 cio->num_patterns);
85f8e2ea 1032 kprintf("pci_ioctl: do your headers match your "
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MD
1033 "kernel?\n");
1034 cio->num_matches = 0;
1035 error = EINVAL;
1036 break;
1037 }
1038
1039 /*
1040 * Check the user's buffer to make sure it's readable.
1041 */
1042 if (!useracc((caddr_t)cio->patterns,
1043 cio->pat_buf_len, VM_PROT_READ)) {
85f8e2ea 1044 kprintf("pci_ioctl: pattern buffer %p, "
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MD
1045 "length %u isn't user accessible for"
1046 " READ\n", cio->patterns,
1047 cio->pat_buf_len);
1048 error = EACCES;
1049 break;
1050 }
1051 /*
1052 * Allocate a buffer to hold the patterns.
1053 */
efda3bd0 1054 pattern_buf = kmalloc(cio->pat_buf_len, M_TEMP,
984263bc
MD
1055 M_WAITOK);
1056 error = copyin(cio->patterns, pattern_buf,
1057 cio->pat_buf_len);
1058 if (error != 0)
1059 break;
1060 num_patterns = cio->num_patterns;
1061
1062 } else if ((cio->num_patterns > 0)
1063 || (cio->pat_buf_len > 0)) {
1064 /*
1065 * The user made a mistake, spit out an error.
1066 */
1067 cio->status = PCI_GETCONF_ERROR;
1068 cio->num_matches = 0;
85f8e2ea 1069 kprintf("pci_ioctl: invalid GETCONF arguments\n");
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MD
1070 error = EINVAL;
1071 break;
1072 } else
1073 pattern_buf = NULL;
1074
1075 /*
1076 * Make sure we can write to the match buffer.
1077 */
1078 if (!useracc((caddr_t)cio->matches,
1079 cio->match_buf_len, VM_PROT_WRITE)) {
85f8e2ea 1080 kprintf("pci_ioctl: match buffer %p, length %u "
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MD
1081 "isn't user accessible for WRITE\n",
1082 cio->matches, cio->match_buf_len);
1083 error = EACCES;
1084 break;
1085 }
1086
1087 /*
1088 * Go through the list of devices and copy out the devices
1089 * that match the user's criteria.
1090 */
1091 for (cio->num_matches = 0, error = 0, i = 0,
1092 dinfo = STAILQ_FIRST(devlist_head);
1093 (dinfo != NULL) && (cio->num_matches < ionum)
1094 && (error == 0) && (i < pci_numdevs);
1095 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
1096
1097 if (i < cio->offset)
1098 continue;
1099
1100 /* Populate pd_name and pd_unit */
1101 name = NULL;
1102 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
1103 name = device_get_name(dinfo->cfg.dev);
1104 if (name) {
1105 strncpy(dinfo->conf.pd_name, name,
1106 sizeof(dinfo->conf.pd_name));
1107 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
1108 dinfo->conf.pd_unit =
1109 device_get_unit(dinfo->cfg.dev);
1110 }
1111
1112 if ((pattern_buf == NULL) ||
1113 (pci_conf_match(pattern_buf, num_patterns,
1114 &dinfo->conf) == 0)) {
1115
1116 /*
1117 * If we've filled up the user's buffer,
1118 * break out at this point. Since we've
1119 * got a match here, we'll pick right back
1120 * up at the matching entry. We can also
1121 * tell the user that there are more matches
1122 * left.
1123 */
1124 if (cio->num_matches >= ionum)
1125 break;
1126
1127 error = copyout(&dinfo->conf,
1128 &cio->matches[cio->num_matches],
1129 sizeof(struct pci_conf));
1130 cio->num_matches++;
1131 }
1132 }
1133
1134 /*
1135 * Set the pointer into the list, so if the user is getting
1136 * n records at a time, where n < pci_numdevs,
1137 */
1138 cio->offset = i;
1139
1140 /*
1141 * Set the generation, the user will need this if they make
1142 * another ioctl call with offset != 0.
1143 */
1144 cio->generation = pci_generation;
1145
1146 /*
1147 * If this is the last device, inform the user so he won't
1148 * bother asking for more devices. If dinfo isn't NULL, we
1149 * know that there are more matches in the list because of
1150 * the way the traversal is done.
1151 */
1152 if (dinfo == NULL)
1153 cio->status = PCI_GETCONF_LAST_DEVICE;
1154 else
1155 cio->status = PCI_GETCONF_MORE_DEVS;
1156
1157 if (pattern_buf != NULL)
efda3bd0 1158 kfree(pattern_buf, M_TEMP);
984263bc
MD
1159
1160 break;
1161 }
1162 case PCIOCREAD:
fef8985e 1163 io = (struct pci_io *)ap->a_data;
984263bc 1164 switch(io->pi_width) {
984263bc
MD
1165 case 4:
1166 case 2:
1167 case 1:
4a5a2d63
JS
1168 /*
1169 * Assume that the user-level bus number is
1170 * actually the pciN instance number. We map
1171 * from that to the real pcib+bus combination.
1172 */
1173 pci = devclass_get_device(pci_devclass,
1174 io->pi_sel.pc_bus);
1175 if (pci) {
2581072f
MD
1176 /*
1177 * pci is the pci device and may contain
1178 * several children (for each function code).
1179 * The governing pci bus is the parent to
1180 * the pci device.
1181 */
1182 int b;
1183
4a5a2d63 1184 pcib = device_get_parent(pci);
2581072f 1185 b = pcib_get_bus(pcib);
4a5a2d63
JS
1186 io->pi_data =
1187 PCIB_READ_CONFIG(pcib,
1188 b,
1189 io->pi_sel.pc_dev,
1190 io->pi_sel.pc_func,
1191 io->pi_reg,
1192 io->pi_width);
1193 error = 0;
1194 } else {
1195 error = ENODEV;
1196 }
984263bc
MD
1197 break;
1198 default:
1199 error = ENODEV;
1200 break;
1201 }
1202 break;
1203
1204 case PCIOCWRITE:
fef8985e 1205 io = (struct pci_io *)ap->a_data;
984263bc 1206 switch(io->pi_width) {
984263bc
MD
1207 case 4:
1208 case 2:
1209 case 1:
4a5a2d63
JS
1210 /*
1211 * Assume that the user-level bus number is
1212 * actually the pciN instance number. We map
1213 * from that to the real pcib+bus combination.
1214 */
1215 pci = devclass_get_device(pci_devclass,
1216 io->pi_sel.pc_bus);
1217 if (pci) {
2581072f
MD
1218 /*
1219 * pci is the pci device and may contain
1220 * several children (for each function code).
1221 * The governing pci bus is the parent to
1222 * the pci device.
1223 */
1224 int b;
1225
4a5a2d63 1226 pcib = device_get_parent(pci);
2581072f 1227 b = pcib_get_bus(pcib);
4a5a2d63
JS
1228 PCIB_WRITE_CONFIG(pcib,
1229 b,
1230 io->pi_sel.pc_dev,
1231 io->pi_sel.pc_func,
1232 io->pi_reg,
1233 io->pi_data,
1234 io->pi_width);
1235 error = 0;
1236 } else {
1237 error = ENODEV;
1238 }
984263bc
MD
1239 break;
1240 default:
1241 error = ENODEV;
1242 break;
1243 }
1244 break;
1245
1246 default:
1247 error = ENOTTY;
1248 break;
1249 }
1250
1251 return (error);
1252}
1253
1254#define PCI_CDEV 78
1255
fef8985e
MD
1256static struct dev_ops pcic_ops = {
1257 { "pci", PCI_CDEV, 0 },
1258 .d_open = pci_open,
1259 .d_close = pci_close,
1260 .d_ioctl = pci_ioctl,
984263bc
MD
1261};
1262
1263#include "pci_if.h"
1264
984263bc
MD
1265/*
1266 * New style pci driver. Parent device is either a pci-host-bridge or a
1267 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1268 */
ed1bd994
MD
1269const char *
1270pci_class_to_string(int baseclass)
1271{
1272 const char *name;
1273
1274 switch(baseclass) {
1275 case PCIC_OLD:
1276 name = "OLD";
1277 break;
1278 case PCIC_STORAGE:
1279 name = "STORAGE";
1280 break;
1281 case PCIC_NETWORK:
1282 name = "NETWORK";
1283 break;
1284 case PCIC_DISPLAY:
1285 name = "DISPLAY";
1286 break;
1287 case PCIC_MULTIMEDIA:
1288 name = "MULTIMEDIA";
1289 break;
1290 case PCIC_MEMORY:
1291 name = "MEMORY";
1292 break;
1293 case PCIC_BRIDGE:
1294 name = "BRIDGE";
1295 break;
1296 case PCIC_SIMPLECOMM:
1297 name = "SIMPLECOMM";
1298 break;
1299 case PCIC_BASEPERIPH:
1300 name = "BASEPERIPH";
1301 break;
1302 case PCIC_INPUTDEV:
1303 name = "INPUTDEV";
1304 break;
1305 case PCIC_DOCKING:
1306 name = "DOCKING";
1307 break;
1308 case PCIC_PROCESSOR:
1309 name = "PROCESSOR";
1310 break;
1311 case PCIC_SERIALBUS:
1312 name = "SERIALBUS";
1313 break;
1314 case PCIC_WIRELESS:
1315 name = "WIRELESS";
1316 break;
1317 case PCIC_I2O:
1318 name = "I20";
1319 break;
1320 case PCIC_SATELLITE:
1321 name = "SATELLITE";
1322 break;
1323 case PCIC_CRYPTO:
1324 name = "CRYPTO";
1325 break;
1326 case PCIC_SIGPROC:
1327 name = "SIGPROC";
1328 break;
1329 case PCIC_OTHER:
1330 name = "OTHER";
1331 break;
1332 default:
1333 name = "?";
1334 break;
1335 }
1336 return(name);
1337}
984263bc 1338
b4c0a845
SZ
1339static void
1340pci_print_verbose_expr(const pcicfgregs *cfg)
1341{
1342 const struct pcicfg_expr *expr = &cfg->expr;
1343 const char *port_name;
1344 uint16_t port_type;
1345
1346 if (!bootverbose)
1347 return;
1348
1349 if (expr->expr_ptr == 0) /* No PCI Express capability */
1350 return;
1351
1352 kprintf("\tPCI Express ver.%d cap=0x%04x",
1353 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
1354 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
1355 goto back;
1356
1357 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
1358
1359 switch (port_type) {
1360 case PCIEM_END_POINT:
1361 port_name = "DEVICE";
1362 break;
1363 case PCIEM_LEG_END_POINT:
1364 port_name = "LEGDEV";
1365 break;
1366 case PCIEM_ROOT_PORT:
1367 port_name = "ROOT";
1368 break;
1369 case PCIEM_UP_STREAM_PORT:
1370 port_name = "UPSTREAM";
1371 break;
1372 case PCIEM_DOWN_STREAM_PORT:
1373 port_name = "DOWNSTRM";
1374 break;
1375 case PCIEM_PCIE2PCI_BRIDGE:
1376 port_name = "PCIE2PCI";
1377 break;
1378 case PCIEM_PCI2PCIE_BRIDGE:
1379 port_name = "PCI2PCIE";
1380 break;
1381 default:
1382 port_name = NULL;
1383 break;
1384 }
1385 if ((port_type == PCIEM_ROOT_PORT ||
1386 port_type == PCIEM_DOWN_STREAM_PORT) &&
1387 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
1388 port_name = NULL;
1389 if (port_name != NULL)
1390 kprintf("[%s]", port_name);
1391
1392 if ((port_type == PCIEM_ROOT_PORT ||
1393 port_type == PCIEM_DOWN_STREAM_PORT) &&
1394 (expr->expr_cap & PCIEM_CAP_SLOT_IMPL)) {
1395 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
1396 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
1397 kprintf("[HOTPLUG]");
1398 }
1399back:
1400 kprintf("\n");
1401}
1402
22457186 1403void
984263bc
MD
1404pci_print_verbose(struct pci_devinfo *dinfo)
1405{
1406 if (bootverbose) {
1407 pcicfgregs *cfg = &dinfo->cfg;
1408
85f8e2ea 1409 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
984263bc 1410 cfg->vendor, cfg->device, cfg->revid);
85f8e2ea 1411 kprintf("\tbus=%d, slot=%d, func=%d\n",
4a5a2d63 1412 cfg->bus, cfg->slot, cfg->func);
85f8e2ea 1413 kprintf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
ed1bd994 1414 pci_class_to_string(cfg->baseclass),
984263bc
MD
1415 cfg->baseclass, cfg->subclass, cfg->progif,
1416 cfg->hdrtype, cfg->mfdev);
85f8e2ea 1417 kprintf("\tsubordinatebus=%x \tsecondarybus=%x\n",
984263bc
MD
1418 cfg->subordinatebus, cfg->secondarybus);
1419#ifdef PCI_DEBUG
85f8e2ea 1420 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
984263bc 1421 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
85f8e2ea 1422 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
984263bc
MD
1423 cfg->lattimer, cfg->lattimer * 30,
1424 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1425#endif /* PCI_DEBUG */
1426 if (cfg->intpin > 0)
85f8e2ea 1427 kprintf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
b4c0a845
SZ
1428
1429 pci_print_verbose_expr(cfg);
984263bc
MD
1430 }
1431}
1432
1433static int
4a5a2d63 1434pci_porten(device_t pcib, int b, int s, int f)
984263bc 1435{
4a5a2d63
JS
1436 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1437 & PCIM_CMD_PORTEN) != 0;
984263bc
MD
1438}
1439
1440static int
4a5a2d63 1441pci_memen(device_t pcib, int b, int s, int f)
984263bc 1442{
4a5a2d63
JS
1443 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1444 & PCIM_CMD_MEMEN) != 0;
984263bc
MD
1445}
1446
1447/*
1448 * Add a resource based on a pci map register. Return 1 if the map
1449 * register is a 32bit map register or 2 if it is a 64bit register.
1450 */
1451static int
4a5a2d63
JS
1452pci_add_map(device_t pcib, int b, int s, int f, int reg,
1453 struct resource_list *rl)
984263bc 1454{
984263bc
MD
1455 u_int32_t map;
1456 u_int64_t base;
1457 u_int8_t ln2size;
1458 u_int8_t ln2range;
1459 u_int32_t testval;
4a5a2d63
JS
1460
1461
1462#ifdef PCI_ENABLE_IO_MODES
1463 u_int16_t cmd;
1464#endif
984263bc
MD
1465 int type;
1466
4a5a2d63 1467 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
984263bc
MD
1468
1469 if (map == 0 || map == 0xffffffff)
1470 return 1; /* skip invalid entry */
1471
4a5a2d63
JS
1472 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1473 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1474 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
984263bc
MD
1475
1476 base = pci_mapbase(map);
1477 if (pci_maptype(map) & PCI_MAPMEM)
1478 type = SYS_RES_MEMORY;
1479 else
1480 type = SYS_RES_IOPORT;
1481 ln2size = pci_mapsize(testval);
1482 ln2range = pci_maprange(testval);
1483 if (ln2range == 64) {
1484 /* Read the other half of a 64bit map register */
4a5a2d63 1485 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
984263bc
MD
1486 }
1487
984263bc
MD
1488 /*
1489 * This code theoretically does the right thing, but has
1490 * undesirable side effects in some cases where
1491 * peripherals respond oddly to having these bits
1492 * enabled. Leave them alone by default.
1493 */
1494#ifdef PCI_ENABLE_IO_MODES
4a5a2d63
JS
1495 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1496 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1497 cmd |= PCIM_CMD_PORTEN;
1498 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc 1499 }
4a5a2d63
JS
1500 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1501 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1502 cmd |= PCIM_CMD_MEMEN;
1503 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc
MD
1504 }
1505#else
4a5a2d63 1506 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
984263bc 1507 return 1;
4a5a2d63 1508 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
984263bc
MD
1509 return 1;
1510#endif
1511
1512 resource_list_add(rl, type, reg,
1513 base, base + (1 << ln2size) - 1,
1514 (1 << ln2size));
1515
1516 if (bootverbose) {
85f8e2ea 1517 kprintf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
984263bc
MD
1518 reg, pci_maptype(base), ln2range,
1519 (unsigned int) base, ln2size);
1520 }
1521
1522 return (ln2range == 64) ? 2 : 1;
1523}
1524
201eb0a7
TS
1525#ifdef PCI_MAP_FIXUP
1526/*
1527 * For ATA devices we need to decide early on what addressing mode to use.
1528 * Legacy demands that the primary and secondary ATA ports sits on the
1529 * same addresses that old ISA hardware did. This dictates that we use
1530 * those addresses and ignore the BARs if we cannot set PCI native
1531 * addressing mode.
1532 */
1533static void
1534pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, int s, int f,
1535 struct resource_list *rl)
1536{
1537 int rid, type, progif;
1538#if 0
1539 /* if this device supports PCI native addressing use it */
1540 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1541 if ((progif &0x8a) == 0x8a) {
1542 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
1543 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
85f8e2ea 1544 kprintf("Trying ATA native PCI addressing mode\n");
201eb0a7
TS
1545 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
1546 }
1547 }
1548#endif
1549 /*
1550 * Because we return any preallocated resources for lazy
1551 * allocation for PCI devices in pci_alloc_resource(), we can
1552 * allocate our legacy resources here.
1553 */
1554 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1555 type = SYS_RES_IOPORT;
1556 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
1557 pci_add_map(pcib, b, s, f, PCIR_BAR(0), rl);
1558 pci_add_map(pcib, b, s, f, PCIR_BAR(1), rl);
1559 } else {
1560 rid = PCIR_BAR(0);
1561 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
1562 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
1563 0);
1564 rid = PCIR_BAR(1);
1565 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
1566 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
1567 0);
1568 }
1569 if (progif & PCIP_STORAGE_IDE_MODESEC) {
1570 pci_add_map(pcib, b, s, f, PCIR_BAR(2), rl);
1571 pci_add_map(pcib, b, s, f, PCIR_BAR(3), rl);
1572 } else {
1573 rid = PCIR_BAR(2);
1574 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
1575 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
1576 0);
1577 rid = PCIR_BAR(3);
1578 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
1579 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
1580 0);
1581 }
1582 pci_add_map(pcib, b, s, f, PCIR_BAR(4), rl);
1583 pci_add_map(pcib, b, s, f, PCIR_BAR(5), rl);
1584}
1585#endif /* PCI_MAP_FIXUP */
1586
984263bc 1587static void
e126caf1 1588pci_add_resources(device_t pcib, device_t bus, device_t dev)
984263bc
MD
1589{
1590 struct pci_devinfo *dinfo = device_get_ivars(dev);
4a5a2d63 1591 pcicfgregs *cfg = &dinfo->cfg;
984263bc
MD
1592 struct resource_list *rl = &dinfo->resources;
1593 struct pci_quirk *q;
e126caf1
MD
1594 int b, i, f, s;
1595#if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */
1596 int irq;
1597#endif
984263bc 1598
e126caf1
MD
1599 b = cfg->bus;
1600 s = cfg->slot;
1601 f = cfg->func;
201eb0a7
TS
1602#ifdef PCI_MAP_FIXUP
1603 /* atapci devices in legacy mode need special map treatment */
1604 if ((pci_get_class(dev) == PCIC_STORAGE) &&
1605 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
d3d1ea7a
MD
1606 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
1607 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
1608 !pci_read_config(dev, PCIR_BAR(2), 4))) )
201eb0a7
TS
1609 pci_ata_maps(pcib, bus, dev, b, s, f, rl);
1610 else
1611#endif /* PCI_MAP_FIXUP */
1612 for (i = 0; i < cfg->nummaps;) {
1613 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl);
1614 }
984263bc
MD
1615
1616 for (q = &pci_quirks[0]; q->devid; q++) {
1617 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1618 && q->type == PCI_QUIRK_MAP_REG)
4a5a2d63 1619 pci_add_map(pcib, b, s, f, q->arg1, rl);
984263bc
MD
1620 }
1621
1622 if (cfg->intpin > 0 && cfg->intline != 255)
1623 resource_list_add(rl, SYS_RES_IRQ, 0,
1624 cfg->intline, cfg->intline, 1);
1625}
1626
e126caf1
MD
1627void
1628pci_add_children(device_t dev, int busno, size_t dinfo_size)
984263bc 1629{
e126caf1 1630#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
4a5a2d63 1631 device_t pcib = device_get_parent(dev);
e126caf1 1632 struct pci_devinfo *dinfo;
4a5a2d63 1633 int maxslots;
e126caf1
MD
1634 int s, f, pcifunchigh;
1635 uint8_t hdrtype;
1636
1637 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo));
984263bc 1638
4a5a2d63 1639 maxslots = PCIB_MAXSLOTS(pcib);
984263bc 1640
57e943f7 1641 for (s = 0; s <= maxslots; s++) {
e126caf1
MD
1642 pcifunchigh = 0;
1643 f = 0;
1644 hdrtype = REG(PCIR_HDRTYPE, 1);
1645 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1646 continue;
1647 if (hdrtype & PCIM_MFDEV)
1648 pcifunchigh = PCI_FUNCMAX;
5e658043 1649 for (f = 0; f <= pcifunchigh; f++) {
e126caf1 1650 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
984263bc 1651 if (dinfo != NULL) {
e126caf1 1652 pci_add_child(dev, dinfo);
984263bc
MD
1653 }
1654 }
1655 }
e126caf1
MD
1656#undef REG
1657}
1658
2581072f
MD
1659/*
1660 * The actual PCI child that we add has a NULL driver whos parent
1661 * device will be "pci". The child contains the ivars, not the parent.
1662 */
e126caf1
MD
1663void
1664pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1665{
1666 device_t pcib;
1667
1668 pcib = device_get_parent(bus);
1669 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1670 device_set_ivars(dinfo->cfg.dev, dinfo);
1671 pci_add_resources(pcib, bus, dinfo->cfg.dev);
1672 pci_print_verbose(dinfo);
984263bc
MD
1673}
1674
c01b8d84
MD
1675/*
1676 * Probe the PCI bus. Note: probe code is not supposed to add children
1677 * or call attach.
1678 */
984263bc 1679static int
4a5a2d63 1680pci_probe(device_t dev)
984263bc 1681{
984263bc 1682 device_set_desc(dev, "PCI bus");
4a5a2d63 1683
c01b8d84
MD
1684 /* Allow other subclasses to override this driver */
1685 return(-1000);
984263bc
MD
1686}
1687
e126caf1
MD
1688static int
1689pci_attach(device_t dev)
1690{
1691 int busno;
e4c9c0c8
MD
1692 int lunit = device_get_unit(dev);
1693
fef8985e
MD
1694 dev_ops_add(&pcic_ops, -1, lunit);
1695 make_dev(&pcic_ops, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit);
e126caf1
MD
1696
1697 /*
1698 * Since there can be multiple independantly numbered PCI
1699 * busses on some large alpha systems, we can't use the unit
1700 * number to decide what bus we are probing. We ask the parent
1701 * pcib what our bus number is.
2581072f
MD
1702 *
1703 * pcib_get_bus() must act on the pci bus device, not on the pci
1704 * device, because it uses badly hacked nexus-based ivars to
1705 * store and retrieve the physical bus number. XXX
e126caf1 1706 */
2581072f 1707 busno = pcib_get_bus(device_get_parent(dev));
e126caf1 1708 if (bootverbose)
ed1bd994 1709 device_printf(dev, "pci_attach() physical bus=%d\n", busno);
e126caf1
MD
1710
1711 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1712
1713 return (bus_generic_attach(dev));
1714}
1715
984263bc
MD
1716static int
1717pci_print_resources(struct resource_list *rl, const char *name, int type,
1718 const char *format)
1719{
1720 struct resource_list_entry *rle;
1721 int printed, retval;
1722
1723 printed = 0;
1724 retval = 0;
1725 /* Yes, this is kinda cheating */
1726 SLIST_FOREACH(rle, rl, link) {
1727 if (rle->type == type) {
1728 if (printed == 0)
85f8e2ea 1729 retval += kprintf(" %s ", name);
984263bc 1730 else if (printed > 0)
85f8e2ea 1731 retval += kprintf(",");
984263bc 1732 printed++;
85f8e2ea 1733 retval += kprintf(format, rle->start);
984263bc 1734 if (rle->count > 1) {
85f8e2ea
SW
1735 retval += kprintf("-");
1736 retval += kprintf(format, rle->start +
984263bc
MD
1737 rle->count - 1);
1738 }
1739 }
1740 }
1741 return retval;
1742}
1743
e126caf1 1744int
984263bc
MD
1745pci_print_child(device_t dev, device_t child)
1746{
1747 struct pci_devinfo *dinfo;
1748 struct resource_list *rl;
1749 pcicfgregs *cfg;
1750 int retval = 0;
1751
1752 dinfo = device_get_ivars(child);
1753 cfg = &dinfo->cfg;
1754 rl = &dinfo->resources;
1755
1756 retval += bus_print_child_header(dev, child);
1757
1758 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1759 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1760 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1761 if (device_get_flags(dev))
85f8e2ea 1762 retval += kprintf(" flags %#x", device_get_flags(dev));
984263bc 1763
85f8e2ea 1764 retval += kprintf(" at device %d.%d", pci_get_slot(child),
984263bc
MD
1765 pci_get_function(child));
1766
1767 retval += bus_print_child_footer(dev, child);
1768
1769 return (retval);
1770}
1771
e126caf1 1772void
984263bc
MD
1773pci_probe_nomatch(device_t dev, device_t child)
1774{
1775 struct pci_devinfo *dinfo;
1776 pcicfgregs *cfg;
1777 const char *desc;
1778 int unknown;
1779
1780 unknown = 0;
1781 dinfo = device_get_ivars(child);
1782 cfg = &dinfo->cfg;
1783 desc = pci_ata_match(child);
1784 if (!desc) desc = pci_usb_match(child);
1785 if (!desc) desc = pci_vga_match(child);
27c23c6b 1786 if (!desc) desc = pci_chip_match(child);
984263bc
MD
1787 if (!desc) {
1788 desc = "unknown card";
1789 unknown++;
1790 }
1791 device_printf(dev, "<%s>", desc);
1792 if (bootverbose || unknown) {
85f8e2ea 1793 kprintf(" (vendor=0x%04x, dev=0x%04x)",
984263bc
MD
1794 cfg->vendor,
1795 cfg->device);
1796 }
85f8e2ea 1797 kprintf(" at %d.%d",
984263bc
MD
1798 pci_get_slot(child),
1799 pci_get_function(child));
1800 if (cfg->intpin > 0 && cfg->intline != 255) {
85f8e2ea 1801 kprintf(" irq %d", cfg->intline);
984263bc 1802 }
85f8e2ea 1803 kprintf("\n");
984263bc
MD
1804
1805 return;
1806}
1807
22457186 1808int
4a5a2d63 1809pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
984263bc
MD
1810{
1811 struct pci_devinfo *dinfo;
1812 pcicfgregs *cfg;
1813
1814 dinfo = device_get_ivars(child);
1815 cfg = &dinfo->cfg;
1816
1817 switch (which) {
1818 case PCI_IVAR_SUBVENDOR:
1819 *result = cfg->subvendor;
1820 break;
1821 case PCI_IVAR_SUBDEVICE:
1822 *result = cfg->subdevice;
1823 break;
1824 case PCI_IVAR_VENDOR:
1825 *result = cfg->vendor;
1826 break;
1827 case PCI_IVAR_DEVICE:
1828 *result = cfg->device;
1829 break;
1830 case PCI_IVAR_DEVID:
1831 *result = (cfg->device << 16) | cfg->vendor;
1832 break;
1833 case PCI_IVAR_CLASS:
1834 *result = cfg->baseclass;
1835 break;
1836 case PCI_IVAR_SUBCLASS:
1837 *result = cfg->subclass;
1838 break;
1839 case PCI_IVAR_PROGIF:
1840 *result = cfg->progif;
1841 break;
1842 case PCI_IVAR_REVID:
1843 *result = cfg->revid;
1844 break;
1845 case PCI_IVAR_INTPIN:
1846 *result = cfg->intpin;
1847 break;
1848 case PCI_IVAR_IRQ:
1849 *result = cfg->intline;
1850 break;
1851 case PCI_IVAR_BUS:
1852 *result = cfg->bus;
1853 break;
1854 case PCI_IVAR_SLOT:
1855 *result = cfg->slot;
1856 break;
1857 case PCI_IVAR_FUNCTION:
1858 *result = cfg->func;
1859 break;
1860 case PCI_IVAR_SECONDARYBUS:
1861 *result = cfg->secondarybus;
1862 break;
1863 case PCI_IVAR_SUBORDINATEBUS:
1864 *result = cfg->subordinatebus;
1865 break;
f72d3d23
JS
1866 case PCI_IVAR_ETHADDR:
1867 /*
1868 * The generic accessor doesn't deal with failure, so
1869 * we set the return value, then return an error.
1870 */
1871 *result = NULL;
1872 return (EINVAL);
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MD
1873 default:
1874 return ENOENT;
1875 }
1876 return 0;
1877}
1878
22457186 1879int
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MD
1880pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1881{
1882 struct pci_devinfo *dinfo;
1883 pcicfgregs *cfg;
1884
1885 dinfo = device_get_ivars(child);
1886 cfg = &dinfo->cfg;
1887
1888 switch (which) {
1889 case PCI_IVAR_SUBVENDOR:
1890 case PCI_IVAR_SUBDEVICE:
1891 case PCI_IVAR_VENDOR:
1892 case PCI_IVAR_DEVICE:
1893 case PCI_IVAR_DEVID:
1894 case PCI_IVAR_CLASS:
1895 case PCI_IVAR_SUBCLASS:
1896 case PCI_IVAR_PROGIF:
1897 case PCI_IVAR_REVID:
1898 case PCI_IVAR_INTPIN:
1899 case PCI_IVAR_IRQ:
1900 case PCI_IVAR_BUS:
1901 case PCI_IVAR_SLOT:
1902 case PCI_IVAR_FUNCTION:
f72d3d23 1903 case PCI_IVAR_ETHADDR:
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MD
1904 return EINVAL; /* disallow for now */
1905
1906 case PCI_IVAR_SECONDARYBUS:
1907 cfg->secondarybus = value;
1908 break;
1909 case PCI_IVAR_SUBORDINATEBUS:
1910 cfg->subordinatebus = value;
1911 break;
1912 default:
1913 return ENOENT;
1914 }
1915 return 0;
1916}
1917
201eb0a7
TS
1918#ifdef PCI_MAP_FIXUP
1919static struct resource *
1920pci_alloc_map(device_t dev, device_t child, int type, int *rid, u_long start,
1921 u_long end, u_long count, u_int flags)
1922{
1923 struct pci_devinfo *dinfo = device_get_ivars(child);
1924 struct resource_list *rl = &dinfo->resources;
1925 struct resource_list_entry *rle;
1926 struct resource *res;
1927 uint32_t map, testval;
1928 int mapsize;
1929
1930 /*
1931 * Weed out the bogons, and figure out how large the BAR/map
1932 * is. BARs that read back 0 here are bogus and unimplemented.
1933 *
1934 * Note: atapci in legacy mode are special and handled elsewhere
1935 * in the code. If you have an atapci device in legacy mode and
1936 * it fails here, that other code is broken.
1937 */
1938 res = NULL;
1939 map = pci_read_config(child, *rid, 4);
1940 pci_write_config(child, *rid, 0xffffffff, 4);
1941 testval = pci_read_config(child, *rid, 4);
1942 if (pci_mapbase(testval) == 0)
1943 goto out;
1944 if (pci_maptype(testval) & PCI_MAPMEM) {
1945 if (type != SYS_RES_MEMORY) {
1946 if (bootverbose)
1947 device_printf(dev, "child %s requested type %d"
1948 " for rid %#x, but the BAR says "
1949 "it is a memio\n",
1950 device_get_nameunit(child), type,
1951 *rid);
1952 goto out;
1953 }
1954 } else {
1955 if (type != SYS_RES_IOPORT) {
1956 if (bootverbose)
1957 device_printf(dev, "child %s requested type %d"
1958 " for rid %#x, but the BAR says "
1959 "it is an ioport\n",
1960 device_get_nameunit(child), type,
1961 *rid);
1962 goto out;
1963 }
1964 }
1965 /*
1966 * For real BARs, we need to override the size that
1967 * the driver requests, because that's what the BAR
1968 * actually uses and we would otherwise have a
1969 * situation where we might allocate the excess to
1970 * another driver, which won't work.
1971 */
1972 mapsize = pci_mapsize(testval);
1973 count = 1 << mapsize;
1974 if (RF_ALIGNMENT(flags) < mapsize)
1975 flags = (flags & ~RF_ALIGNMENT_MASK) |
1976 RF_ALIGNMENT_LOG2(mapsize);
1977 /*
1978 * Allocate enough resource, and then write back the
1979 * appropriate BAR for that resource.
1980 */
1981 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
1982 start, end, count, flags);
1983 if (res == NULL) {
1984 device_printf(child, "%#lx bytes at rid %#x res %d failed "
1985 "(%#lx, %#lx)\n", count, *rid, type, start, end);
1986 goto out;
1987 }
1988 resource_list_add(rl, type, *rid, start, end, count);
1989 rle = resource_list_find(rl, type, *rid);
1990 if (rle == NULL)
1991 panic("pci_alloc_map: unexpectedly can't find resource.");
1992 rle->res = res;
1993 rle->start = rman_get_start(res);
1994 rle->end = rman_get_end(res);
1995 rle->count = count;
1996 if (bootverbose)
1997 device_printf(child, "lazy allocation of %#lx bytes rid %#x "
1998 "type %d at %#lx\n", count, *rid, type,
1999 rman_get_start(res));
2000 map = rman_get_start(res);
2001out:;
2002 pci_write_config(child, *rid, map, 4);
2003 return res;
2004}
2005#endif /* PCI_MAP_FIXUP */
2006
261fa16d 2007struct resource *
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MD
2008pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
2009 u_long start, u_long end, u_long count, u_int flags)
2010{
2011 struct pci_devinfo *dinfo = device_get_ivars(child);
2012 struct resource_list *rl = &dinfo->resources;
201eb0a7
TS
2013#ifdef PCI_MAP_FIXUP
2014 struct resource_list_entry *rle;
2015#endif /* PCI_MAP_FIXUP */
984263bc 2016 pcicfgregs *cfg = &dinfo->cfg;
de67e43b 2017
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MD
2018 /*
2019 * Perform lazy resource allocation
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MD
2020 */
2021 if (device_get_parent(child) == dev) {
de67e43b
JS
2022 switch (type) {
2023 case SYS_RES_IRQ:
2024#ifdef __i386__
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MD
2025 /*
2026 * If device doesn't have an interrupt routed, and is
2027 * deserving of an interrupt, try to assign it one.
2028 */
de67e43b
JS
2029 if ((cfg->intline == 255 || cfg->intline == 0) &&
2030 (cfg->intpin != 0) &&
2031 (start == 0) && (end == ~0UL)) {
2032 cfg->intline = PCIB_ROUTE_INTERRUPT(
2033 device_get_parent(dev), child,
2034 cfg->intpin);
2035 if (cfg->intline != 255) {
2036 pci_write_config(child, PCIR_INTLINE,
2037 cfg->intline, 1);
2038 resource_list_add(rl, SYS_RES_IRQ, 0,
2039 cfg->intline, cfg->intline, 1);
2040 }
2041 }
820c1612 2042 break;
de67e43b
JS
2043#endif
2044 case SYS_RES_IOPORT:
201eb0a7 2045 /* FALLTHROUGH */
de67e43b
JS
2046 case SYS_RES_MEMORY:
2047 if (*rid < PCIR_BAR(cfg->nummaps)) {
2048 /*
2049 * Enable the I/O mode. We should
2050 * also be assigning resources too
2051 * when none are present. The
2052 * resource_list_alloc kind of sorta does
2053 * this...
2054 */
2055 if (PCI_ENABLE_IO(dev, child, type))
2056 return (NULL);
984263bc 2057 }
201eb0a7
TS
2058#ifdef PCI_MAP_FIXUP
2059 rle = resource_list_find(rl, type, *rid);
2060 if (rle == NULL)
2061 return pci_alloc_map(dev, child, type, rid,
2062 start, end, count, flags);
2063#endif /* PCI_MAP_FIXUP */
820c1612 2064 break;
984263bc 2065 }
201eb0a7
TS
2066#ifdef PCI_MAP_FIXUP
2067 /*
2068 * If we've already allocated the resource, then
2069 * return it now. But first we may need to activate
2070 * it, since we don't allocate the resource as active
2071 * above. Normally this would be done down in the
2072 * nexus, but since we short-circuit that path we have
2073 * to do its job here. Not sure if we should free the
2074 * resource if it fails to activate.
2075 *
2076 * Note: this also finds and returns resources for
2077 * atapci devices in legacy mode as allocated in
2078 * pci_ata_maps().
2079 */
2080 rle = resource_list_find(rl, type, *rid);
2081 if (rle != NULL && rle->res != NULL) {
2082 if (bootverbose)
2083 device_printf(child, "reserved %#lx bytes for "
2084 "rid %#x type %d at %#lx\n",
2085 rman_get_size(rle->res), *rid,
2086 type, rman_get_start(rle->res));
2087 if ((flags & RF_ACTIVE) &&
2088 bus_generic_activate_resource(dev, child, type,
2089 *rid, rle->res) != 0)
2090 return NULL;
2091 return rle->res;
2092 }
2093#endif /* PCI_MAP_FIXUP */
984263bc 2094 }
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MD
2095 return resource_list_alloc(rl, dev, child, type, rid,
2096 start, end, count, flags);
2097}
2098
2099static int
2100pci_release_resource(device_t dev, device_t child, int type, int rid,
2101 struct resource *r)
2102{
2103 struct pci_devinfo *dinfo = device_get_ivars(child);
2104 struct resource_list *rl = &dinfo->resources;
2105
2106 return resource_list_release(rl, dev, child, type, rid, r);
2107}
2108
2109static int
2110pci_set_resource(device_t dev, device_t child, int type, int rid,
2111 u_long start, u_long count)
2112{
2113 struct pci_devinfo *dinfo = device_get_ivars(child);
2114 struct resource_list *rl = &dinfo->resources;
2115
2116 resource_list_add(rl, type, rid, start, start + count - 1, count);
2117 return 0;
2118}
2119
2120static int
2121pci_get_resource(device_t dev, device_t child, int type, int rid,
2122 u_long *startp, u_long *countp)
2123{
2124 struct pci_devinfo *dinfo = device_get_ivars(child);
2125 struct resource_list *rl = &dinfo->resources;
2126 struct resource_list_entry *rle;
2127
2128 rle = resource_list_find(rl, type, rid);
2129 if (!rle)
2130 return ENOENT;
2131
2132 if (startp)
2133 *startp = rle->start;
2134 if (countp)
2135 *countp = rle->count;
2136
2137 return 0;
2138}
2139
e126caf1 2140void
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MD
2141pci_delete_resource(device_t dev, device_t child, int type, int rid)
2142{
85f8e2ea 2143 kprintf("pci_delete_resource: PCI resources can not be deleted\n");
984263bc
MD
2144}
2145
e126caf1
MD
2146struct resource_list *
2147pci_get_resource_list (device_t dev, device_t child)
2148{
b0486c83 2149 struct pci_devinfo *dinfo = device_get_ivars(child);
e126caf1 2150
b0486c83 2151 if (dinfo == NULL)
e126caf1 2152 return (NULL);
b0486c83 2153 return (&dinfo->resources);
e126caf1
MD
2154}
2155
2156u_int32_t
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MD
2157pci_read_config_method(device_t dev, device_t child, int reg, int width)
2158{
2159 struct pci_devinfo *dinfo = device_get_ivars(child);
2160 pcicfgregs *cfg = &dinfo->cfg;
4a5a2d63
JS
2161
2162 return PCIB_READ_CONFIG(device_get_parent(dev),
2163 cfg->bus, cfg->slot, cfg->func,
2164 reg, width);
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MD
2165}
2166
e126caf1 2167void
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MD
2168pci_write_config_method(device_t dev, device_t child, int reg,
2169 u_int32_t val, int width)
2170{
2171 struct pci_devinfo *dinfo = device_get_ivars(child);
2172 pcicfgregs *cfg = &dinfo->cfg;
4a5a2d63
JS
2173
2174 PCIB_WRITE_CONFIG(device_get_parent(dev),
2175 cfg->bus, cfg->slot, cfg->func,
2176 reg, val, width);
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MD
2177}
2178
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MD
2179int
2180pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
2181 size_t buflen)
2182{
2183 struct pci_devinfo *dinfo;
2184
2185 dinfo = device_get_ivars(child);
f8c7a42d 2186 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
e126caf1
MD
2187 pci_get_function(child));
2188 return (0);
2189}
2190
2191int
2192pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
2193 size_t buflen)
2194{
2195 struct pci_devinfo *dinfo;
2196 pcicfgregs *cfg;
2197
2198 dinfo = device_get_ivars(child);
2199 cfg = &dinfo->cfg;
f8c7a42d 2200 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
e126caf1
MD
2201 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
2202 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
2203 cfg->progif);
2204 return (0);
2205}
2206
2207int
2208pci_assign_interrupt_method(device_t dev, device_t child)
2209{
2210 struct pci_devinfo *dinfo = device_get_ivars(child);
2211 pcicfgregs *cfg = &dinfo->cfg;
2212
2213 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
2214 cfg->intpin));
2215}
2216
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MD
2217static int
2218pci_modevent(module_t mod, int what, void *arg)
2219{
2220 switch (what) {
2221 case MOD_LOAD:
2222 STAILQ_INIT(&pci_devq);
2223 break;
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MD
2224 case MOD_UNLOAD:
2225 break;
2226 }
2227
2228 return 0;
2229}
2230
e126caf1
MD
2231int
2232pci_resume(device_t dev)
2233{
2234 int numdevs;
2235 int i;
2236 device_t *children;
2237 device_t child;
2238 struct pci_devinfo *dinfo;
2239 pcicfgregs *cfg;
2240
2241 device_get_children(dev, &children, &numdevs);
2242
2243 for (i = 0; i < numdevs; i++) {
2244 child = children[i];
2245
2246 dinfo = device_get_ivars(child);
2247 cfg = &dinfo->cfg;
2248 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2249 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
2250 if (PCI_INTERRUPT_VALID(cfg->intline)) {
2251 pci_write_config(child, PCIR_INTLINE,
2252 cfg->intline, 1);
2253 }
2254 }
2255 }
2256
efda3bd0 2257 kfree(children, M_TEMP);
e126caf1
MD
2258
2259 return (bus_generic_resume(dev));
2260}
2261
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MD
2262static device_method_t pci_methods[] = {
2263 /* Device interface */
4a5a2d63 2264 DEVMETHOD(device_probe, pci_probe),
e126caf1 2265 DEVMETHOD(device_attach, pci_attach),
984263bc
MD
2266 DEVMETHOD(device_shutdown, bus_generic_shutdown),
2267 DEVMETHOD(device_suspend, bus_generic_suspend),
e126caf1 2268 DEVMETHOD(device_resume, pci_resume),
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MD
2269
2270 /* Bus interface */
2271 DEVMETHOD(bus_print_child, pci_print_child),
2272 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
2273 DEVMETHOD(bus_read_ivar, pci_read_ivar),
2274 DEVMETHOD(bus_write_ivar, pci_write_ivar),
2275 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
984263bc
MD
2276 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
2277 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
e126caf1
MD
2278
2279 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
984263bc
MD
2280 DEVMETHOD(bus_set_resource, pci_set_resource),
2281 DEVMETHOD(bus_get_resource, pci_get_resource),
2282 DEVMETHOD(bus_delete_resource, pci_delete_resource),
e126caf1
MD
2283 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
2284 DEVMETHOD(bus_release_resource, pci_release_resource),
2285 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
2286 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
2287 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
2288 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
984263bc
MD
2289
2290 /* PCI interface */
2291 DEVMETHOD(pci_read_config, pci_read_config_method),
2292 DEVMETHOD(pci_write_config, pci_write_config_method),
2293 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
2294 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
2295 DEVMETHOD(pci_enable_io, pci_enable_io_method),
2296 DEVMETHOD(pci_disable_io, pci_disable_io_method),
2297 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
2298 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
e126caf1 2299 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
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MD
2300
2301 { 0, 0 }
2302};
2303
3aef8050 2304driver_t pci_driver = {
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MD
2305 "pci",
2306 pci_methods,
2307 1, /* no softc */
2308};
2309
2310DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
261fa16d 2311MODULE_VERSION(pci, 1);