acpi_cpu(4) update. It's now possible to use higher (lower power usage) C
[dragonfly.git] / sys / bus / pci / pci.c
CommitLineData
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1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
21ce0dfa 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.53 2008/08/02 01:14:40 dillon Exp $
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28 *
29 */
30
31#include "opt_bus.h"
32#include "opt_pci.h"
33
dc5a7bd2 34#include "opt_compat_oldpci.h"
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35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/malloc.h>
39#include <sys/module.h>
40#include <sys/fcntl.h>
41#include <sys/conf.h>
42#include <sys/kernel.h>
43#include <sys/queue.h>
44#include <sys/types.h>
45#include <sys/buf.h>
46
47#include <vm/vm.h>
48#include <vm/pmap.h>
49#include <vm/vm_extern.h>
50
51#include <sys/bus.h>
984263bc 52#include <sys/rman.h>
97359a5b 53#include <machine/smp.h>
21ce0dfa 54#include "pci_cfgreg.h"
984263bc 55
dc5a7bd2 56#include <sys/pciio.h>
1f2de5d4
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57#include "pcireg.h"
58#include "pcivar.h"
22457186 59#include "pci_private.h"
984263bc 60
4a5a2d63
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61#include "pcib_if.h"
62
e126caf1 63devclass_t pci_devclass;
2581072f 64const char *pcib_owner;
dc5a7bd2 65
e9d8f4df 66static void pci_read_capabilities(device_t dev, pcicfgregs *cfg);
8c5b0f9a 67static int pcie_slotimpl(const pcicfgregs *);
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68
69struct pci_quirk {
70 u_int32_t devid; /* Vendor/device of the card */
71 int type;
3e4db402 72#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
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73 int arg1;
74 int arg2;
75};
76
77struct pci_quirk pci_quirks[] = {
78 /*
79 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
80 */
81 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
82 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
f1f0bfb2
JS
83 /* As does the Serverworks OSB4 (the SMBus mapping register) */
84 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
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85
86 { 0 }
87};
88
89/* map register information */
90#define PCI_MAPMEM 0x01 /* memory map */
91#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
92#define PCI_MAPPORT 0x04 /* port map */
93
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94static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
95u_int32_t pci_numdevs = 0;
96static u_int32_t pci_generation = 0;
97
98device_t
c0f16abb 99pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func)
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100{
101 struct pci_devinfo *dinfo;
102
103 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
104 if ((dinfo->cfg.bus == bus) &&
105 (dinfo->cfg.slot == slot) &&
106 (dinfo->cfg.func == func)) {
107 return (dinfo->cfg.dev);
108 }
109 }
110
111 return (NULL);
112}
113
114device_t
c0f16abb 115pci_find_device(u_int16_t vendor, u_int16_t device)
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116{
117 struct pci_devinfo *dinfo;
118
119 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
120 if ((dinfo->cfg.vendor == vendor) &&
121 (dinfo->cfg.device == device)) {
122 return (dinfo->cfg.dev);
123 }
124 }
125
126 return (NULL);
127}
128
8c5b0f9a
SZ
129int
130pcie_slot_implemented(device_t dev)
131{
132 struct pci_devinfo *dinfo = device_get_ivars(dev);
133
134 return pcie_slotimpl(&dinfo->cfg);
135}
136
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137/* return base address of memory or port map */
138
139static u_int32_t
140pci_mapbase(unsigned mapreg)
141{
142 int mask = 0x03;
143 if ((mapreg & 0x01) == 0)
144 mask = 0x0f;
145 return (mapreg & ~mask);
146}
147
148/* return map type of memory or port map */
149
150static int
151pci_maptype(unsigned mapreg)
152{
153 static u_int8_t maptype[0x10] = {
154 PCI_MAPMEM, PCI_MAPPORT,
155 PCI_MAPMEM, 0,
156 PCI_MAPMEM, PCI_MAPPORT,
157 0, 0,
158 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
159 PCI_MAPMEM|PCI_MAPMEMP, 0,
160 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
161 0, 0,
162 };
163
164 return maptype[mapreg & 0x0f];
165}
166
167/* return log2 of map size decoded for memory or port map */
168
169static int
170pci_mapsize(unsigned testval)
171{
172 int ln2size;
173
174 testval = pci_mapbase(testval);
175 ln2size = 0;
176 if (testval != 0) {
177 while ((testval & 1) == 0)
178 {
179 ln2size++;
180 testval >>= 1;
181 }
182 }
183 return (ln2size);
184}
185
186/* return log2 of address range supported by map register */
187
188static int
189pci_maprange(unsigned mapreg)
190{
191 int ln2range = 0;
192 switch (mapreg & 0x07) {
193 case 0x00:
194 case 0x01:
195 case 0x05:
196 ln2range = 32;
197 break;
198 case 0x02:
199 ln2range = 20;
200 break;
201 case 0x04:
202 ln2range = 64;
203 break;
204 }
205 return (ln2range);
206}
207
208/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
209
210static void
211pci_fixancient(pcicfgregs *cfg)
212{
213 if (cfg->hdrtype != 0)
214 return;
215
216 /* PCI to PCI bridges use header type 1 */
217 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
218 cfg->hdrtype = 1;
219}
220
221/* read config data specific to header type 1 device (PCI to PCI bridge) */
222
223static void *
4a5a2d63 224pci_readppb(device_t pcib, int b, int s, int f)
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225{
226 pcih1cfgregs *p;
227
efda3bd0 228 p = kmalloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
984263bc 229
4a5a2d63
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230 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
231 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
984263bc 232
4a5a2d63 233 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
984263bc 234
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235 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
236 PCIR_IOBASEH_1, 2),
237 PCIB_READ_CONFIG(pcib, b, s, f,
238 PCIR_IOBASEL_1, 1));
239 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
240 PCIR_IOLIMITH_1, 2),
241 PCIB_READ_CONFIG(pcib, b, s, f,
242 PCIR_IOLIMITL_1, 1));
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243
244 p->membase = PCI_PPBMEMBASE (0,
4a5a2d63
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245 PCIB_READ_CONFIG(pcib, b, s, f,
246 PCIR_MEMBASE_1, 2));
984263bc 247 p->memlimit = PCI_PPBMEMLIMIT (0,
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248 PCIB_READ_CONFIG(pcib, b, s, f,
249 PCIR_MEMLIMIT_1, 2));
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250
251 p->pmembase = PCI_PPBMEMBASE (
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252 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
253 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
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254
255 p->pmemlimit = PCI_PPBMEMLIMIT (
4a5a2d63
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256 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
257 PCIR_PMLIMITH_1, 4),
258 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
259
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260 return (p);
261}
262
263/* read config data specific to header type 2 device (PCI to CardBus bridge) */
264
265static void *
4a5a2d63 266pci_readpcb(device_t pcib, int b, int s, int f)
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267{
268 pcih2cfgregs *p;
269
efda3bd0 270 p = kmalloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
984263bc 271
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272 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
273 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
984263bc 274
4a5a2d63 275 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
984263bc 276
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277 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
278 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
279 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
280 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
984263bc 281
4a5a2d63
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282 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
283 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
284 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
285 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
984263bc 286
4a5a2d63 287 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
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288 return p;
289}
290
291/* extract header type specific config data */
292
293static void
4a5a2d63 294pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
984263bc 295{
4a5a2d63 296#define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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297 switch (cfg->hdrtype) {
298 case 0:
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299 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
300 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
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301 cfg->nummaps = PCI_MAXMAPS_0;
302 break;
303 case 1:
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304 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
305 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
306 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
307 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
984263bc 308 cfg->nummaps = PCI_MAXMAPS_1;
4a5a2d63 309 cfg->hdrspec = pci_readppb(pcib, b, s, f);
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310 break;
311 case 2:
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312 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
313 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
314 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
315 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
984263bc 316 cfg->nummaps = PCI_MAXMAPS_2;
4a5a2d63 317 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
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318 break;
319 }
4a5a2d63 320#undef REG
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321}
322
323/* read configuration header into pcicfgrect structure */
324
22457186 325struct pci_devinfo *
c01b8d84 326pci_read_device(device_t pcib, int b, int s, int f, size_t size)
984263bc 327{
4a5a2d63 328#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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329
330 pcicfgregs *cfg = NULL;
331 struct pci_devinfo *devlist_entry;
332 struct devlist *devlist_head;
333
334 devlist_head = &pci_devq;
335
336 devlist_entry = NULL;
337
4a5a2d63 338 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
984263bc 339
efda3bd0 340 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
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MD
341
342 cfg = &devlist_entry->cfg;
343
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344 cfg->bus = b;
345 cfg->slot = s;
346 cfg->func = f;
347 cfg->vendor = REG(PCIR_VENDOR, 2);
348 cfg->device = REG(PCIR_DEVICE, 2);
349 cfg->cmdreg = REG(PCIR_COMMAND, 2);
350 cfg->statreg = REG(PCIR_STATUS, 2);
351 cfg->baseclass = REG(PCIR_CLASS, 1);
352 cfg->subclass = REG(PCIR_SUBCLASS, 1);
353 cfg->progif = REG(PCIR_PROGIF, 1);
354 cfg->revid = REG(PCIR_REVID, 1);
e126caf1 355 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
4a5a2d63
JS
356 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
357 cfg->lattimer = REG(PCIR_LATTIMER, 1);
358 cfg->intpin = REG(PCIR_INTPIN, 1);
359 cfg->intline = REG(PCIR_INTLINE, 1);
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360
361#ifdef APIC_IO
97359a5b
MD
362 /*
363 * If using the APIC the intpin is probably wrong, since it
364 * is often setup by the BIOS with the PIC in mind.
365 */
984263bc
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366 if (cfg->intpin != 0) {
367 int airq;
368
369 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
370 if (airq >= 0) {
371 /* PCI specific entry found in MP table */
372 if (airq != cfg->intline) {
373 undirect_pci_irq(cfg->intline);
374 cfg->intline = airq;
375 }
376 } else {
377 /*
378 * PCI interrupts might be redirected to the
379 * ISA bus according to some MP tables. Use the
380 * same methods as used by the ISA devices
381 * devices to find the proper IOAPIC int pin.
382 */
383 airq = isa_apic_irq(cfg->intline);
384 if ((airq >= 0) && (airq != cfg->intline)) {
385 /* XXX: undirect_pci_irq() ? */
386 undirect_isa_irq(cfg->intline);
387 cfg->intline = airq;
388 }
389 }
390 }
391#endif /* APIC_IO */
392
4a5a2d63
JS
393 cfg->mingnt = REG(PCIR_MINGNT, 1);
394 cfg->maxlat = REG(PCIR_MAXLAT, 1);
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395
396 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
397 cfg->hdrtype &= ~PCIM_MFDEV;
398
399 pci_fixancient(cfg);
4a5a2d63 400 pci_hdrtypedata(pcib, b, s, f, cfg);
e9d8f4df 401 pci_read_capabilities(pcib, cfg);
984263bc
MD
402
403 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
404
405 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
406 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
407 devlist_entry->conf.pc_sel.pc_func = cfg->func;
408 devlist_entry->conf.pc_hdr = cfg->hdrtype;
409
410 devlist_entry->conf.pc_subvendor = cfg->subvendor;
411 devlist_entry->conf.pc_subdevice = cfg->subdevice;
412 devlist_entry->conf.pc_vendor = cfg->vendor;
413 devlist_entry->conf.pc_device = cfg->device;
414
415 devlist_entry->conf.pc_class = cfg->baseclass;
416 devlist_entry->conf.pc_subclass = cfg->subclass;
417 devlist_entry->conf.pc_progif = cfg->progif;
418 devlist_entry->conf.pc_revid = cfg->revid;
419
420 pci_numdevs++;
421 pci_generation++;
422 }
423 return (devlist_entry);
424#undef REG
425}
426
1361c4cd
SZ
427static int
428pci_fixup_nextptr(int *nextptr0)
429{
430 int nextptr = *nextptr0;
431
432 /* "Next pointer" is only one byte */
433 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
434
435 if (nextptr & 0x3) {
436 /*
437 * PCI local bus spec 3.0:
438 *
439 * "... The bottom two bits of all pointers are reserved
440 * and must be implemented as 00b although software must
441 * mask them to allow for future uses of these bits ..."
442 */
443 if (bootverbose) {
444 kprintf("Illegal PCI extended capability "
445 "offset, fixup 0x%02x -> 0x%02x\n",
446 nextptr, nextptr & ~0x3);
447 }
448 nextptr &= ~0x3;
449 }
450 *nextptr0 = nextptr;
451
452 if (nextptr < 0x40) {
453 if (nextptr != 0) {
454 kprintf("Illegal PCI extended capability "
455 "offset 0x%02x", nextptr);
456 }
457 return 0;
458 }
459 return 1;
460}
461
8475d8bb
SZ
462static void
463pci_read_cap_pmgt(device_t pcib, int ptr, pcicfgregs *cfg)
464{
465#define REG(n, w) \
466 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
467
468 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
469
470 if (pmgt->pp_cap)
471 return;
472
473 pmgt->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
474 pmgt->pp_status = ptr + PCIR_POWER_STATUS;
475 pmgt->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
476 /*
477 * XXX
478 * Following way may be used to to test whether
479 * 'data' register exists:
480 * if 'data_select' register of
481 * PCIR_POWER_STATUS(bits[12,9]) is read-only
482 * then 'data' register is _not_ implemented.
483 */
484 pmgt->pp_data = 0;
485
486#undef REG
487}
488
8c5b0f9a
SZ
489static int
490pcie_slotimpl(const pcicfgregs *cfg)
b4c0a845 491{
8c5b0f9a 492 const struct pcicfg_expr *expr = &cfg->expr;
b4c0a845
SZ
493 uint16_t port_type;
494
b4c0a845
SZ
495 /*
496 * Only version 1 can be parsed currently
497 */
498 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
8c5b0f9a 499 return 0;
b4c0a845
SZ
500
501 /*
b4c0a845
SZ
502 * - Slot implemented bit is meaningful iff current port is
503 * root port or down stream port.
8c5b0f9a
SZ
504 * - Testing for root port or down stream port is meanningful
505 * iff PCI configure has type 1 header.
b4c0a845 506 */
8c5b0f9a 507
b4c0a845 508 if (cfg->hdrtype != 1)
8c5b0f9a 509 return 0;
b4c0a845
SZ
510
511 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
8c5b0f9a
SZ
512 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT)
513 return 0;
b4c0a845
SZ
514
515 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
8c5b0f9a
SZ
516 return 0;
517
518 return 1;
519}
520
521static void
522pci_read_cap_expr(device_t pcib, int ptr, pcicfgregs *cfg)
523{
524#define REG(n, w) \
525 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
526
527 struct pcicfg_expr *expr = &cfg->expr;
528
529 expr->expr_ptr = ptr;
530 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
531
532 /*
533 * Only version 1 can be parsed currently
534 */
535 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
b4c0a845
SZ
536 return;
537
8c5b0f9a
SZ
538 /*
539 * Read slot capabilities. Slot capabilities exists iff
540 * current port's slot is implemented
541 */
542 if (pcie_slotimpl(cfg))
543 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
b4c0a845
SZ
544
545#undef REG
546}
547
984263bc 548static void
e9d8f4df 549pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
984263bc 550{
8475d8bb
SZ
551#define REG(n, w) \
552 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
553
1361c4cd 554 int nextptr, ptrptr;
984263bc 555
0c78fe3f
SZ
556 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
557 /* No capabilities */
558 return;
559 }
560
984263bc
MD
561 switch (cfg->hdrtype) {
562 case 0:
81c29ce4
SZ
563 case 1:
564 ptrptr = PCIR_CAP_PTR;
984263bc
MD
565 break;
566 case 2:
81c29ce4 567 ptrptr = PCIR_CAP_PTR_2;
984263bc
MD
568 break;
569 default:
0c78fe3f 570 return; /* No capabilities support */
984263bc 571 }
0c78fe3f 572 nextptr = REG(ptrptr, 1);
984263bc
MD
573
574 /*
575 * Read capability entries.
576 */
1361c4cd
SZ
577 while (pci_fixup_nextptr(&nextptr)) {
578 int ptr = nextptr;
984263bc
MD
579
580 /* Process this entry */
581 switch (REG(ptr, 1)) {
81c29ce4 582 case PCIY_PMG: /* PCI power management */
8475d8bb 583 pci_read_cap_pmgt(pcib, ptr, cfg);
984263bc 584 break;
c7e4e7eb
SZ
585 case PCIY_PCIX: /* PCI-X */
586 cfg->pcixcap_ptr = ptr;
587 break;
b4c0a845
SZ
588 case PCIY_EXPRESS: /* PCI Express */
589 pci_read_cap_expr(pcib, ptr, cfg);
590 break;
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591 default:
592 break;
593 }
1361c4cd
SZ
594
595 /* Find the next entry */
596 nextptr = REG(ptr + 1, 1);
984263bc 597 }
8475d8bb 598
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MD
599#undef REG
600}
601
984263bc
MD
602/* free pcicfgregs structure and all depending data structures */
603
22457186 604int
984263bc
MD
605pci_freecfg(struct pci_devinfo *dinfo)
606{
607 struct devlist *devlist_head;
608
609 devlist_head = &pci_devq;
610
611 if (dinfo->cfg.hdrspec != NULL)
efda3bd0 612 kfree(dinfo->cfg.hdrspec, M_DEVBUF);
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MD
613 /* XXX this hasn't been tested */
614 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
efda3bd0 615 kfree(dinfo, M_DEVBUF);
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616
617 /* increment the generation count */
618 pci_generation++;
619
620 /* we're losing one device */
621 pci_numdevs--;
622 return (0);
623}
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624
625
626/*
627 * PCI power manangement
628 */
e126caf1 629int
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630pci_set_powerstate_method(device_t dev, device_t child, int state)
631{
632 struct pci_devinfo *dinfo = device_get_ivars(child);
633 pcicfgregs *cfg = &dinfo->cfg;
1f7d9fe0 634 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
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MD
635 u_int16_t status;
636 int result;
637
1f7d9fe0
SZ
638 if (pmgt->pp_cap != 0) {
639 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2) & ~PCIM_PSTAT_DMASK;
984263bc
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640 result = 0;
641 switch (state) {
642 case PCI_POWERSTATE_D0:
643 status |= PCIM_PSTAT_D0;
644 break;
645 case PCI_POWERSTATE_D1:
1f7d9fe0 646 if (pmgt->pp_cap & PCIM_PCAP_D1SUPP) {
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MD
647 status |= PCIM_PSTAT_D1;
648 } else {
649 result = EOPNOTSUPP;
650 }
651 break;
652 case PCI_POWERSTATE_D2:
1f7d9fe0 653 if (pmgt->pp_cap & PCIM_PCAP_D2SUPP) {
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MD
654 status |= PCIM_PSTAT_D2;
655 } else {
656 result = EOPNOTSUPP;
657 }
658 break;
659 case PCI_POWERSTATE_D3:
660 status |= PCIM_PSTAT_D3;
661 break;
662 default:
663 result = EINVAL;
664 }
665 if (result == 0)
1f7d9fe0 666 PCI_WRITE_CONFIG(dev, child, pmgt->pp_status, status, 2);
984263bc
MD
667 } else {
668 result = ENXIO;
669 }
670 return(result);
671}
672
e126caf1 673int
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674pci_get_powerstate_method(device_t dev, device_t child)
675{
676 struct pci_devinfo *dinfo = device_get_ivars(child);
677 pcicfgregs *cfg = &dinfo->cfg;
1f7d9fe0 678 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
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679 u_int16_t status;
680 int result;
681
1f7d9fe0
SZ
682 if (pmgt->pp_cap != 0) {
683 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2);
984263bc
MD
684 switch (status & PCIM_PSTAT_DMASK) {
685 case PCIM_PSTAT_D0:
686 result = PCI_POWERSTATE_D0;
687 break;
688 case PCIM_PSTAT_D1:
689 result = PCI_POWERSTATE_D1;
690 break;
691 case PCIM_PSTAT_D2:
692 result = PCI_POWERSTATE_D2;
693 break;
694 case PCIM_PSTAT_D3:
695 result = PCI_POWERSTATE_D3;
696 break;
697 default:
698 result = PCI_POWERSTATE_UNKNOWN;
699 break;
700 }
701 } else {
702 /* No support, device is always at D0 */
703 result = PCI_POWERSTATE_D0;
704 }
705 return(result);
706}
707
708/*
709 * Some convenience functions for PCI device drivers.
710 */
711
712static __inline void
713pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
714{
715 u_int16_t command;
716
717 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
718 command |= bit;
719 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
720}
721
722static __inline void
723pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
724{
725 u_int16_t command;
726
727 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
728 command &= ~bit;
729 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
730}
731
e126caf1 732int
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733pci_enable_busmaster_method(device_t dev, device_t child)
734{
735 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 736 return(0);
984263bc
MD
737}
738
e126caf1 739int
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740pci_disable_busmaster_method(device_t dev, device_t child)
741{
742 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 743 return(0);
984263bc
MD
744}
745
e126caf1 746int
984263bc
MD
747pci_enable_io_method(device_t dev, device_t child, int space)
748{
e126caf1
MD
749 uint16_t command;
750 uint16_t bit;
751 char *error;
752
753 bit = 0;
754 error = NULL;
755
984263bc
MD
756 switch(space) {
757 case SYS_RES_IOPORT:
e126caf1
MD
758 bit = PCIM_CMD_PORTEN;
759 error = "port";
984263bc
MD
760 break;
761 case SYS_RES_MEMORY:
e126caf1
MD
762 bit = PCIM_CMD_MEMEN;
763 error = "memory";
984263bc 764 break;
e126caf1
MD
765 default:
766 return(EINVAL);
984263bc 767 }
e126caf1
MD
768 pci_set_command_bit(dev, child, bit);
769 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
770 if (command & bit)
771 return(0);
772 device_printf(child, "failed to enable %s mapping!\n", error);
773 return(ENXIO);
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MD
774}
775
e126caf1 776int
984263bc
MD
777pci_disable_io_method(device_t dev, device_t child, int space)
778{
e126caf1
MD
779 uint16_t command;
780 uint16_t bit;
781 char *error;
782
783 bit = 0;
784 error = NULL;
785
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786 switch(space) {
787 case SYS_RES_IOPORT:
e126caf1
MD
788 bit = PCIM_CMD_PORTEN;
789 error = "port";
984263bc
MD
790 break;
791 case SYS_RES_MEMORY:
e126caf1
MD
792 bit = PCIM_CMD_MEMEN;
793 error = "memory";
984263bc 794 break;
e126caf1
MD
795 default:
796 return (EINVAL);
984263bc 797 }
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MD
798 pci_clear_command_bit(dev, child, bit);
799 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
800 if (command & bit) {
801 device_printf(child, "failed to disable %s mapping!\n", error);
802 return (ENXIO);
803 }
804 return (0);
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805}
806
807/*
808 * This is the user interface to PCI configuration space.
809 */
810
811static int
fef8985e 812pci_open(struct dev_open_args *ap)
984263bc 813{
fef8985e 814 if ((ap->a_oflags & FWRITE) && securelevel > 0) {
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MD
815 return EPERM;
816 }
817 return 0;
818}
819
820static int
fef8985e 821pci_close(struct dev_close_args *ap)
984263bc
MD
822{
823 return 0;
824}
825
826/*
827 * Match a single pci_conf structure against an array of pci_match_conf
828 * structures. The first argument, 'matches', is an array of num_matches
829 * pci_match_conf structures. match_buf is a pointer to the pci_conf
830 * structure that will be compared to every entry in the matches array.
831 * This function returns 1 on failure, 0 on success.
832 */
833static int
834pci_conf_match(struct pci_match_conf *matches, int num_matches,
835 struct pci_conf *match_buf)
836{
837 int i;
838
839 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
840 return(1);
841
842 for (i = 0; i < num_matches; i++) {
843 /*
844 * I'm not sure why someone would do this...but...
845 */
846 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
847 continue;
848
849 /*
850 * Look at each of the match flags. If it's set, do the
851 * comparison. If the comparison fails, we don't have a
852 * match, go on to the next item if there is one.
853 */
854 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
855 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
856 continue;
857
858 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
859 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
860 continue;
861
862 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
863 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
864 continue;
865
866 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
867 && (match_buf->pc_vendor != matches[i].pc_vendor))
868 continue;
869
870 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
871 && (match_buf->pc_device != matches[i].pc_device))
872 continue;
873
874 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
875 && (match_buf->pc_class != matches[i].pc_class))
876 continue;
877
878 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
879 && (match_buf->pd_unit != matches[i].pd_unit))
880 continue;
881
882 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
883 && (strncmp(matches[i].pd_name, match_buf->pd_name,
884 sizeof(match_buf->pd_name)) != 0))
885 continue;
886
887 return(0);
888 }
889
890 return(1);
891}
892
893/*
894 * Locate the parent of a PCI device by scanning the PCI devlist
895 * and return the entry for the parent.
896 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
897 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
898 */
899
900pcicfgregs *
901pci_devlist_get_parent(pcicfgregs *cfg)
902{
903 struct devlist *devlist_head;
904 struct pci_devinfo *dinfo;
905 pcicfgregs *bridge_cfg;
906 int i;
907
908 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
909
910 /* If the device is on PCI bus 0, look for the host */
911 if (cfg->bus == 0) {
912 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
913 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
914 bridge_cfg = &dinfo->cfg;
915 if (bridge_cfg->baseclass == PCIC_BRIDGE
916 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
917 && bridge_cfg->bus == cfg->bus) {
918 return bridge_cfg;
919 }
920 }
921 }
922
923 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
924 if (cfg->bus > 0) {
925 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
926 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
927 bridge_cfg = &dinfo->cfg;
928 if (bridge_cfg->baseclass == PCIC_BRIDGE
929 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
930 && bridge_cfg->secondarybus == cfg->bus) {
931 return bridge_cfg;
932 }
933 }
934 }
935
936 return NULL;
937}
938
939static int
fef8985e 940pci_ioctl(struct dev_ioctl_args *ap)
984263bc 941{
4a5a2d63 942 device_t pci, pcib;
984263bc
MD
943 struct pci_io *io;
944 const char *name;
945 int error;
946
fef8985e 947 if (!(ap->a_fflag & FWRITE))
984263bc
MD
948 return EPERM;
949
fef8985e 950 switch(ap->a_cmd) {
984263bc
MD
951 case PCIOCGETCONF:
952 {
953 struct pci_devinfo *dinfo;
954 struct pci_conf_io *cio;
955 struct devlist *devlist_head;
956 struct pci_match_conf *pattern_buf;
957 int num_patterns;
958 size_t iolen;
959 int ionum, i;
960
fef8985e 961 cio = (struct pci_conf_io *)ap->a_data;
984263bc
MD
962
963 num_patterns = 0;
964 dinfo = NULL;
965
966 /*
967 * Hopefully the user won't pass in a null pointer, but it
968 * can't hurt to check.
969 */
970 if (cio == NULL) {
971 error = EINVAL;
972 break;
973 }
974
975 /*
976 * If the user specified an offset into the device list,
977 * but the list has changed since they last called this
978 * ioctl, tell them that the list has changed. They will
979 * have to get the list from the beginning.
980 */
981 if ((cio->offset != 0)
982 && (cio->generation != pci_generation)){
983 cio->num_matches = 0;
984 cio->status = PCI_GETCONF_LIST_CHANGED;
985 error = 0;
986 break;
987 }
988
989 /*
990 * Check to see whether the user has asked for an offset
991 * past the end of our list.
992 */
993 if (cio->offset >= pci_numdevs) {
994 cio->num_matches = 0;
995 cio->status = PCI_GETCONF_LAST_DEVICE;
996 error = 0;
997 break;
998 }
999
1000 /* get the head of the device queue */
1001 devlist_head = &pci_devq;
1002
1003 /*
1004 * Determine how much room we have for pci_conf structures.
1005 * Round the user's buffer size down to the nearest
1006 * multiple of sizeof(struct pci_conf) in case the user
1007 * didn't specify a multiple of that size.
1008 */
1009 iolen = min(cio->match_buf_len -
1010 (cio->match_buf_len % sizeof(struct pci_conf)),
1011 pci_numdevs * sizeof(struct pci_conf));
1012
1013 /*
1014 * Since we know that iolen is a multiple of the size of
1015 * the pciconf union, it's okay to do this.
1016 */
1017 ionum = iolen / sizeof(struct pci_conf);
1018
1019 /*
1020 * If this test is true, the user wants the pci_conf
1021 * structures returned to match the supplied entries.
1022 */
1023 if ((cio->num_patterns > 0)
1024 && (cio->pat_buf_len > 0)) {
1025 /*
1026 * pat_buf_len needs to be:
1027 * num_patterns * sizeof(struct pci_match_conf)
1028 * While it is certainly possible the user just
1029 * allocated a large buffer, but set the number of
1030 * matches correctly, it is far more likely that
1031 * their kernel doesn't match the userland utility
1032 * they're using. It's also possible that the user
1033 * forgot to initialize some variables. Yes, this
1034 * may be overly picky, but I hazard to guess that
1035 * it's far more likely to just catch folks that
1036 * updated their kernel but not their userland.
1037 */
1038 if ((cio->num_patterns *
1039 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
1040 /* The user made a mistake, return an error*/
1041 cio->status = PCI_GETCONF_ERROR;
85f8e2ea 1042 kprintf("pci_ioctl: pat_buf_len %d != "
984263bc
MD
1043 "num_patterns (%d) * sizeof(struct "
1044 "pci_match_conf) (%d)\npci_ioctl: "
1045 "pat_buf_len should be = %d\n",
1046 cio->pat_buf_len, cio->num_patterns,
1047 (int)sizeof(struct pci_match_conf),
1048 (int)sizeof(struct pci_match_conf) *
1049 cio->num_patterns);
85f8e2ea 1050 kprintf("pci_ioctl: do your headers match your "
984263bc
MD
1051 "kernel?\n");
1052 cio->num_matches = 0;
1053 error = EINVAL;
1054 break;
1055 }
1056
1057 /*
1058 * Check the user's buffer to make sure it's readable.
1059 */
1060 if (!useracc((caddr_t)cio->patterns,
1061 cio->pat_buf_len, VM_PROT_READ)) {
85f8e2ea 1062 kprintf("pci_ioctl: pattern buffer %p, "
984263bc
MD
1063 "length %u isn't user accessible for"
1064 " READ\n", cio->patterns,
1065 cio->pat_buf_len);
1066 error = EACCES;
1067 break;
1068 }
1069 /*
1070 * Allocate a buffer to hold the patterns.
1071 */
efda3bd0 1072 pattern_buf = kmalloc(cio->pat_buf_len, M_TEMP,
984263bc
MD
1073 M_WAITOK);
1074 error = copyin(cio->patterns, pattern_buf,
1075 cio->pat_buf_len);
1076 if (error != 0)
1077 break;
1078 num_patterns = cio->num_patterns;
1079
1080 } else if ((cio->num_patterns > 0)
1081 || (cio->pat_buf_len > 0)) {
1082 /*
1083 * The user made a mistake, spit out an error.
1084 */
1085 cio->status = PCI_GETCONF_ERROR;
1086 cio->num_matches = 0;
85f8e2ea 1087 kprintf("pci_ioctl: invalid GETCONF arguments\n");
984263bc
MD
1088 error = EINVAL;
1089 break;
1090 } else
1091 pattern_buf = NULL;
1092
1093 /*
1094 * Make sure we can write to the match buffer.
1095 */
1096 if (!useracc((caddr_t)cio->matches,
1097 cio->match_buf_len, VM_PROT_WRITE)) {
85f8e2ea 1098 kprintf("pci_ioctl: match buffer %p, length %u "
984263bc
MD
1099 "isn't user accessible for WRITE\n",
1100 cio->matches, cio->match_buf_len);
1101 error = EACCES;
1102 break;
1103 }
1104
1105 /*
1106 * Go through the list of devices and copy out the devices
1107 * that match the user's criteria.
1108 */
1109 for (cio->num_matches = 0, error = 0, i = 0,
1110 dinfo = STAILQ_FIRST(devlist_head);
1111 (dinfo != NULL) && (cio->num_matches < ionum)
1112 && (error == 0) && (i < pci_numdevs);
1113 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
1114
1115 if (i < cio->offset)
1116 continue;
1117
1118 /* Populate pd_name and pd_unit */
1119 name = NULL;
1120 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
1121 name = device_get_name(dinfo->cfg.dev);
1122 if (name) {
1123 strncpy(dinfo->conf.pd_name, name,
1124 sizeof(dinfo->conf.pd_name));
1125 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
1126 dinfo->conf.pd_unit =
1127 device_get_unit(dinfo->cfg.dev);
1128 }
1129
1130 if ((pattern_buf == NULL) ||
1131 (pci_conf_match(pattern_buf, num_patterns,
1132 &dinfo->conf) == 0)) {
1133
1134 /*
1135 * If we've filled up the user's buffer,
1136 * break out at this point. Since we've
1137 * got a match here, we'll pick right back
1138 * up at the matching entry. We can also
1139 * tell the user that there are more matches
1140 * left.
1141 */
1142 if (cio->num_matches >= ionum)
1143 break;
1144
1145 error = copyout(&dinfo->conf,
1146 &cio->matches[cio->num_matches],
1147 sizeof(struct pci_conf));
1148 cio->num_matches++;
1149 }
1150 }
1151
1152 /*
1153 * Set the pointer into the list, so if the user is getting
1154 * n records at a time, where n < pci_numdevs,
1155 */
1156 cio->offset = i;
1157
1158 /*
1159 * Set the generation, the user will need this if they make
1160 * another ioctl call with offset != 0.
1161 */
1162 cio->generation = pci_generation;
1163
1164 /*
1165 * If this is the last device, inform the user so he won't
1166 * bother asking for more devices. If dinfo isn't NULL, we
1167 * know that there are more matches in the list because of
1168 * the way the traversal is done.
1169 */
1170 if (dinfo == NULL)
1171 cio->status = PCI_GETCONF_LAST_DEVICE;
1172 else
1173 cio->status = PCI_GETCONF_MORE_DEVS;
1174
1175 if (pattern_buf != NULL)
efda3bd0 1176 kfree(pattern_buf, M_TEMP);
984263bc
MD
1177
1178 break;
1179 }
1180 case PCIOCREAD:
fef8985e 1181 io = (struct pci_io *)ap->a_data;
984263bc 1182 switch(io->pi_width) {
984263bc
MD
1183 case 4:
1184 case 2:
1185 case 1:
4a5a2d63
JS
1186 /*
1187 * Assume that the user-level bus number is
1188 * actually the pciN instance number. We map
1189 * from that to the real pcib+bus combination.
1190 */
1191 pci = devclass_get_device(pci_devclass,
1192 io->pi_sel.pc_bus);
1193 if (pci) {
2581072f
MD
1194 /*
1195 * pci is the pci device and may contain
1196 * several children (for each function code).
1197 * The governing pci bus is the parent to
1198 * the pci device.
1199 */
1200 int b;
1201
4a5a2d63 1202 pcib = device_get_parent(pci);
2581072f 1203 b = pcib_get_bus(pcib);
4a5a2d63
JS
1204 io->pi_data =
1205 PCIB_READ_CONFIG(pcib,
1206 b,
1207 io->pi_sel.pc_dev,
1208 io->pi_sel.pc_func,
1209 io->pi_reg,
1210 io->pi_width);
1211 error = 0;
1212 } else {
1213 error = ENODEV;
1214 }
984263bc
MD
1215 break;
1216 default:
1217 error = ENODEV;
1218 break;
1219 }
1220 break;
1221
1222 case PCIOCWRITE:
fef8985e 1223 io = (struct pci_io *)ap->a_data;
984263bc 1224 switch(io->pi_width) {
984263bc
MD
1225 case 4:
1226 case 2:
1227 case 1:
4a5a2d63
JS
1228 /*
1229 * Assume that the user-level bus number is
1230 * actually the pciN instance number. We map
1231 * from that to the real pcib+bus combination.
1232 */
1233 pci = devclass_get_device(pci_devclass,
1234 io->pi_sel.pc_bus);
1235 if (pci) {
2581072f
MD
1236 /*
1237 * pci is the pci device and may contain
1238 * several children (for each function code).
1239 * The governing pci bus is the parent to
1240 * the pci device.
1241 */
1242 int b;
1243
4a5a2d63 1244 pcib = device_get_parent(pci);
2581072f 1245 b = pcib_get_bus(pcib);
4a5a2d63
JS
1246 PCIB_WRITE_CONFIG(pcib,
1247 b,
1248 io->pi_sel.pc_dev,
1249 io->pi_sel.pc_func,
1250 io->pi_reg,
1251 io->pi_data,
1252 io->pi_width);
1253 error = 0;
1254 } else {
1255 error = ENODEV;
1256 }
984263bc
MD
1257 break;
1258 default:
1259 error = ENODEV;
1260 break;
1261 }
1262 break;
1263
1264 default:
1265 error = ENOTTY;
1266 break;
1267 }
1268
1269 return (error);
1270}
1271
1272#define PCI_CDEV 78
1273
fef8985e
MD
1274static struct dev_ops pcic_ops = {
1275 { "pci", PCI_CDEV, 0 },
1276 .d_open = pci_open,
1277 .d_close = pci_close,
1278 .d_ioctl = pci_ioctl,
984263bc
MD
1279};
1280
1281#include "pci_if.h"
1282
984263bc
MD
1283/*
1284 * New style pci driver. Parent device is either a pci-host-bridge or a
1285 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1286 */
ed1bd994
MD
1287const char *
1288pci_class_to_string(int baseclass)
1289{
1290 const char *name;
1291
1292 switch(baseclass) {
1293 case PCIC_OLD:
1294 name = "OLD";
1295 break;
1296 case PCIC_STORAGE:
1297 name = "STORAGE";
1298 break;
1299 case PCIC_NETWORK:
1300 name = "NETWORK";
1301 break;
1302 case PCIC_DISPLAY:
1303 name = "DISPLAY";
1304 break;
1305 case PCIC_MULTIMEDIA:
1306 name = "MULTIMEDIA";
1307 break;
1308 case PCIC_MEMORY:
1309 name = "MEMORY";
1310 break;
1311 case PCIC_BRIDGE:
1312 name = "BRIDGE";
1313 break;
1314 case PCIC_SIMPLECOMM:
1315 name = "SIMPLECOMM";
1316 break;
1317 case PCIC_BASEPERIPH:
1318 name = "BASEPERIPH";
1319 break;
1320 case PCIC_INPUTDEV:
1321 name = "INPUTDEV";
1322 break;
1323 case PCIC_DOCKING:
1324 name = "DOCKING";
1325 break;
1326 case PCIC_PROCESSOR:
1327 name = "PROCESSOR";
1328 break;
1329 case PCIC_SERIALBUS:
1330 name = "SERIALBUS";
1331 break;
1332 case PCIC_WIRELESS:
1333 name = "WIRELESS";
1334 break;
1335 case PCIC_I2O:
1336 name = "I20";
1337 break;
1338 case PCIC_SATELLITE:
1339 name = "SATELLITE";
1340 break;
1341 case PCIC_CRYPTO:
1342 name = "CRYPTO";
1343 break;
1344 case PCIC_SIGPROC:
1345 name = "SIGPROC";
1346 break;
1347 case PCIC_OTHER:
1348 name = "OTHER";
1349 break;
1350 default:
1351 name = "?";
1352 break;
1353 }
1354 return(name);
1355}
984263bc 1356
b4c0a845
SZ
1357static void
1358pci_print_verbose_expr(const pcicfgregs *cfg)
1359{
1360 const struct pcicfg_expr *expr = &cfg->expr;
1361 const char *port_name;
1362 uint16_t port_type;
1363
1364 if (!bootverbose)
1365 return;
1366
1367 if (expr->expr_ptr == 0) /* No PCI Express capability */
1368 return;
1369
1370 kprintf("\tPCI Express ver.%d cap=0x%04x",
1371 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
1372 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
1373 goto back;
1374
1375 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
1376
1377 switch (port_type) {
8c5b0f9a 1378 case PCIE_END_POINT:
b4c0a845
SZ
1379 port_name = "DEVICE";
1380 break;
8c5b0f9a 1381 case PCIE_LEG_END_POINT:
b4c0a845
SZ
1382 port_name = "LEGDEV";
1383 break;
8c5b0f9a 1384 case PCIE_ROOT_PORT:
b4c0a845
SZ
1385 port_name = "ROOT";
1386 break;
8c5b0f9a 1387 case PCIE_UP_STREAM_PORT:
b4c0a845
SZ
1388 port_name = "UPSTREAM";
1389 break;
8c5b0f9a 1390 case PCIE_DOWN_STREAM_PORT:
b4c0a845
SZ
1391 port_name = "DOWNSTRM";
1392 break;
8c5b0f9a 1393 case PCIE_PCIE2PCI_BRIDGE:
b4c0a845
SZ
1394 port_name = "PCIE2PCI";
1395 break;
8c5b0f9a 1396 case PCIE_PCI2PCIE_BRIDGE:
b4c0a845
SZ
1397 port_name = "PCI2PCIE";
1398 break;
1399 default:
1400 port_name = NULL;
1401 break;
1402 }
8c5b0f9a
SZ
1403 if ((port_type == PCIE_ROOT_PORT ||
1404 port_type == PCIE_DOWN_STREAM_PORT) &&
b4c0a845
SZ
1405 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
1406 port_name = NULL;
1407 if (port_name != NULL)
1408 kprintf("[%s]", port_name);
1409
8c5b0f9a 1410 if (pcie_slotimpl(cfg)) {
b4c0a845
SZ
1411 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
1412 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
1413 kprintf("[HOTPLUG]");
1414 }
1415back:
1416 kprintf("\n");
1417}
1418
22457186 1419void
984263bc
MD
1420pci_print_verbose(struct pci_devinfo *dinfo)
1421{
1422 if (bootverbose) {
1423 pcicfgregs *cfg = &dinfo->cfg;
1424
85f8e2ea 1425 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
984263bc 1426 cfg->vendor, cfg->device, cfg->revid);
85f8e2ea 1427 kprintf("\tbus=%d, slot=%d, func=%d\n",
4a5a2d63 1428 cfg->bus, cfg->slot, cfg->func);
85f8e2ea 1429 kprintf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
ed1bd994 1430 pci_class_to_string(cfg->baseclass),
984263bc
MD
1431 cfg->baseclass, cfg->subclass, cfg->progif,
1432 cfg->hdrtype, cfg->mfdev);
85f8e2ea 1433 kprintf("\tsubordinatebus=%x \tsecondarybus=%x\n",
984263bc
MD
1434 cfg->subordinatebus, cfg->secondarybus);
1435#ifdef PCI_DEBUG
85f8e2ea 1436 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
984263bc 1437 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
85f8e2ea 1438 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
984263bc
MD
1439 cfg->lattimer, cfg->lattimer * 30,
1440 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1441#endif /* PCI_DEBUG */
1442 if (cfg->intpin > 0)
85f8e2ea 1443 kprintf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
b4c0a845
SZ
1444
1445 pci_print_verbose_expr(cfg);
984263bc
MD
1446 }
1447}
1448
1449static int
4a5a2d63 1450pci_porten(device_t pcib, int b, int s, int f)
984263bc 1451{
4a5a2d63
JS
1452 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1453 & PCIM_CMD_PORTEN) != 0;
984263bc
MD
1454}
1455
1456static int
4a5a2d63 1457pci_memen(device_t pcib, int b, int s, int f)
984263bc 1458{
4a5a2d63
JS
1459 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1460 & PCIM_CMD_MEMEN) != 0;
984263bc
MD
1461}
1462
1463/*
1464 * Add a resource based on a pci map register. Return 1 if the map
1465 * register is a 32bit map register or 2 if it is a 64bit register.
1466 */
1467static int
4a5a2d63
JS
1468pci_add_map(device_t pcib, int b, int s, int f, int reg,
1469 struct resource_list *rl)
984263bc 1470{
984263bc
MD
1471 u_int32_t map;
1472 u_int64_t base;
1473 u_int8_t ln2size;
1474 u_int8_t ln2range;
1475 u_int32_t testval;
4a5a2d63
JS
1476
1477
1478#ifdef PCI_ENABLE_IO_MODES
1479 u_int16_t cmd;
1480#endif
984263bc
MD
1481 int type;
1482
4a5a2d63 1483 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
984263bc
MD
1484
1485 if (map == 0 || map == 0xffffffff)
1486 return 1; /* skip invalid entry */
1487
4a5a2d63
JS
1488 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1489 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1490 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
984263bc
MD
1491
1492 base = pci_mapbase(map);
1493 if (pci_maptype(map) & PCI_MAPMEM)
1494 type = SYS_RES_MEMORY;
1495 else
1496 type = SYS_RES_IOPORT;
1497 ln2size = pci_mapsize(testval);
1498 ln2range = pci_maprange(testval);
1499 if (ln2range == 64) {
1500 /* Read the other half of a 64bit map register */
4a5a2d63 1501 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
984263bc
MD
1502 }
1503
984263bc
MD
1504 /*
1505 * This code theoretically does the right thing, but has
1506 * undesirable side effects in some cases where
1507 * peripherals respond oddly to having these bits
1508 * enabled. Leave them alone by default.
1509 */
1510#ifdef PCI_ENABLE_IO_MODES
4a5a2d63
JS
1511 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1512 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1513 cmd |= PCIM_CMD_PORTEN;
1514 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc 1515 }
4a5a2d63
JS
1516 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1517 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1518 cmd |= PCIM_CMD_MEMEN;
1519 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc
MD
1520 }
1521#else
4a5a2d63 1522 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
984263bc 1523 return 1;
4a5a2d63 1524 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
984263bc
MD
1525 return 1;
1526#endif
1527
1528 resource_list_add(rl, type, reg,
1529 base, base + (1 << ln2size) - 1,
1530 (1 << ln2size));
1531
1532 if (bootverbose) {
85f8e2ea 1533 kprintf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
984263bc
MD
1534 reg, pci_maptype(base), ln2range,
1535 (unsigned int) base, ln2size);
1536 }
1537
1538 return (ln2range == 64) ? 2 : 1;
1539}
1540
201eb0a7
TS
1541#ifdef PCI_MAP_FIXUP
1542/*
1543 * For ATA devices we need to decide early on what addressing mode to use.
1544 * Legacy demands that the primary and secondary ATA ports sits on the
1545 * same addresses that old ISA hardware did. This dictates that we use
1546 * those addresses and ignore the BARs if we cannot set PCI native
1547 * addressing mode.
1548 */
1549static void
1550pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, int s, int f,
1551 struct resource_list *rl)
1552{
1553 int rid, type, progif;
1554#if 0
1555 /* if this device supports PCI native addressing use it */
1556 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1557 if ((progif &0x8a) == 0x8a) {
1558 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
1559 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
85f8e2ea 1560 kprintf("Trying ATA native PCI addressing mode\n");
201eb0a7
TS
1561 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
1562 }
1563 }
1564#endif
1565 /*
1566 * Because we return any preallocated resources for lazy
1567 * allocation for PCI devices in pci_alloc_resource(), we can
1568 * allocate our legacy resources here.
1569 */
1570 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1571 type = SYS_RES_IOPORT;
1572 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
1573 pci_add_map(pcib, b, s, f, PCIR_BAR(0), rl);
1574 pci_add_map(pcib, b, s, f, PCIR_BAR(1), rl);
1575 } else {
1576 rid = PCIR_BAR(0);
1577 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
1578 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
1579 0);
1580 rid = PCIR_BAR(1);
1581 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
1582 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
1583 0);
1584 }
1585 if (progif & PCIP_STORAGE_IDE_MODESEC) {
1586 pci_add_map(pcib, b, s, f, PCIR_BAR(2), rl);
1587 pci_add_map(pcib, b, s, f, PCIR_BAR(3), rl);
1588 } else {
1589 rid = PCIR_BAR(2);
1590 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
1591 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
1592 0);
1593 rid = PCIR_BAR(3);
1594 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
1595 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
1596 0);
1597 }
1598 pci_add_map(pcib, b, s, f, PCIR_BAR(4), rl);
1599 pci_add_map(pcib, b, s, f, PCIR_BAR(5), rl);
1600}
1601#endif /* PCI_MAP_FIXUP */
1602
984263bc 1603static void
e126caf1 1604pci_add_resources(device_t pcib, device_t bus, device_t dev)
984263bc
MD
1605{
1606 struct pci_devinfo *dinfo = device_get_ivars(dev);
4a5a2d63 1607 pcicfgregs *cfg = &dinfo->cfg;
984263bc
MD
1608 struct resource_list *rl = &dinfo->resources;
1609 struct pci_quirk *q;
e126caf1
MD
1610 int b, i, f, s;
1611#if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */
1612 int irq;
1613#endif
984263bc 1614
e126caf1
MD
1615 b = cfg->bus;
1616 s = cfg->slot;
1617 f = cfg->func;
201eb0a7
TS
1618#ifdef PCI_MAP_FIXUP
1619 /* atapci devices in legacy mode need special map treatment */
1620 if ((pci_get_class(dev) == PCIC_STORAGE) &&
1621 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
d3d1ea7a
MD
1622 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
1623 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
1624 !pci_read_config(dev, PCIR_BAR(2), 4))) )
201eb0a7
TS
1625 pci_ata_maps(pcib, bus, dev, b, s, f, rl);
1626 else
1627#endif /* PCI_MAP_FIXUP */
1628 for (i = 0; i < cfg->nummaps;) {
1629 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl);
1630 }
984263bc
MD
1631
1632 for (q = &pci_quirks[0]; q->devid; q++) {
1633 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1634 && q->type == PCI_QUIRK_MAP_REG)
4a5a2d63 1635 pci_add_map(pcib, b, s, f, q->arg1, rl);
984263bc
MD
1636 }
1637
1638 if (cfg->intpin > 0 && cfg->intline != 255)
1639 resource_list_add(rl, SYS_RES_IRQ, 0,
1640 cfg->intline, cfg->intline, 1);
1641}
1642
e126caf1
MD
1643void
1644pci_add_children(device_t dev, int busno, size_t dinfo_size)
984263bc 1645{
e126caf1 1646#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
4a5a2d63 1647 device_t pcib = device_get_parent(dev);
e126caf1 1648 struct pci_devinfo *dinfo;
4a5a2d63 1649 int maxslots;
e126caf1
MD
1650 int s, f, pcifunchigh;
1651 uint8_t hdrtype;
1652
1653 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo));
984263bc 1654
4a5a2d63 1655 maxslots = PCIB_MAXSLOTS(pcib);
984263bc 1656
57e943f7 1657 for (s = 0; s <= maxslots; s++) {
e126caf1
MD
1658 pcifunchigh = 0;
1659 f = 0;
1660 hdrtype = REG(PCIR_HDRTYPE, 1);
1661 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1662 continue;
1663 if (hdrtype & PCIM_MFDEV)
1664 pcifunchigh = PCI_FUNCMAX;
5e658043 1665 for (f = 0; f <= pcifunchigh; f++) {
e126caf1 1666 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
984263bc 1667 if (dinfo != NULL) {
e126caf1 1668 pci_add_child(dev, dinfo);
984263bc
MD
1669 }
1670 }
1671 }
e126caf1
MD
1672#undef REG
1673}
1674
2581072f
MD
1675/*
1676 * The actual PCI child that we add has a NULL driver whos parent
1677 * device will be "pci". The child contains the ivars, not the parent.
1678 */
e126caf1
MD
1679void
1680pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1681{
1682 device_t pcib;
1683
1684 pcib = device_get_parent(bus);
1685 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1686 device_set_ivars(dinfo->cfg.dev, dinfo);
1687 pci_add_resources(pcib, bus, dinfo->cfg.dev);
1688 pci_print_verbose(dinfo);
984263bc
MD
1689}
1690
c01b8d84
MD
1691/*
1692 * Probe the PCI bus. Note: probe code is not supposed to add children
1693 * or call attach.
1694 */
984263bc 1695static int
4a5a2d63 1696pci_probe(device_t dev)
984263bc 1697{
984263bc 1698 device_set_desc(dev, "PCI bus");
4a5a2d63 1699
c01b8d84
MD
1700 /* Allow other subclasses to override this driver */
1701 return(-1000);
984263bc
MD
1702}
1703
e126caf1
MD
1704static int
1705pci_attach(device_t dev)
1706{
1707 int busno;
e4c9c0c8
MD
1708 int lunit = device_get_unit(dev);
1709
fef8985e
MD
1710 dev_ops_add(&pcic_ops, -1, lunit);
1711 make_dev(&pcic_ops, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit);
e126caf1
MD
1712
1713 /*
1714 * Since there can be multiple independantly numbered PCI
1715 * busses on some large alpha systems, we can't use the unit
1716 * number to decide what bus we are probing. We ask the parent
1717 * pcib what our bus number is.
2581072f
MD
1718 *
1719 * pcib_get_bus() must act on the pci bus device, not on the pci
1720 * device, because it uses badly hacked nexus-based ivars to
1721 * store and retrieve the physical bus number. XXX
e126caf1 1722 */
2581072f 1723 busno = pcib_get_bus(device_get_parent(dev));
e126caf1 1724 if (bootverbose)
ed1bd994 1725 device_printf(dev, "pci_attach() physical bus=%d\n", busno);
e126caf1
MD
1726
1727 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1728
1729 return (bus_generic_attach(dev));
1730}
1731
984263bc
MD
1732static int
1733pci_print_resources(struct resource_list *rl, const char *name, int type,
1734 const char *format)
1735{
1736 struct resource_list_entry *rle;
1737 int printed, retval;
1738
1739 printed = 0;
1740 retval = 0;
1741 /* Yes, this is kinda cheating */
1742 SLIST_FOREACH(rle, rl, link) {
1743 if (rle->type == type) {
1744 if (printed == 0)
85f8e2ea 1745 retval += kprintf(" %s ", name);
984263bc 1746 else if (printed > 0)
85f8e2ea 1747 retval += kprintf(",");
984263bc 1748 printed++;
85f8e2ea 1749 retval += kprintf(format, rle->start);
984263bc 1750 if (rle->count > 1) {
85f8e2ea
SW
1751 retval += kprintf("-");
1752 retval += kprintf(format, rle->start +
984263bc
MD
1753 rle->count - 1);
1754 }
1755 }
1756 }
1757 return retval;
1758}
1759
e126caf1 1760int
984263bc
MD
1761pci_print_child(device_t dev, device_t child)
1762{
1763 struct pci_devinfo *dinfo;
1764 struct resource_list *rl;
1765 pcicfgregs *cfg;
1766 int retval = 0;
1767
1768 dinfo = device_get_ivars(child);
1769 cfg = &dinfo->cfg;
1770 rl = &dinfo->resources;
1771
1772 retval += bus_print_child_header(dev, child);
1773
1774 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1775 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1776 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1777 if (device_get_flags(dev))
85f8e2ea 1778 retval += kprintf(" flags %#x", device_get_flags(dev));
984263bc 1779
85f8e2ea 1780 retval += kprintf(" at device %d.%d", pci_get_slot(child),
984263bc
MD
1781 pci_get_function(child));
1782
1783 retval += bus_print_child_footer(dev, child);
1784
1785 return (retval);
1786}
1787
e126caf1 1788void
984263bc
MD
1789pci_probe_nomatch(device_t dev, device_t child)
1790{
1791 struct pci_devinfo *dinfo;
1792 pcicfgregs *cfg;
1793 const char *desc;
1794 int unknown;
1795
1796 unknown = 0;
1797 dinfo = device_get_ivars(child);
1798 cfg = &dinfo->cfg;
1799 desc = pci_ata_match(child);
1800 if (!desc) desc = pci_usb_match(child);
1801 if (!desc) desc = pci_vga_match(child);
27c23c6b 1802 if (!desc) desc = pci_chip_match(child);
984263bc
MD
1803 if (!desc) {
1804 desc = "unknown card";
1805 unknown++;
1806 }
1807 device_printf(dev, "<%s>", desc);
1808 if (bootverbose || unknown) {
85f8e2ea 1809 kprintf(" (vendor=0x%04x, dev=0x%04x)",
984263bc
MD
1810 cfg->vendor,
1811 cfg->device);
1812 }
85f8e2ea 1813 kprintf(" at %d.%d",
984263bc
MD
1814 pci_get_slot(child),
1815 pci_get_function(child));
1816 if (cfg->intpin > 0 && cfg->intline != 255) {
85f8e2ea 1817 kprintf(" irq %d", cfg->intline);
984263bc 1818 }
85f8e2ea 1819 kprintf("\n");
984263bc
MD
1820
1821 return;
1822}
1823
22457186 1824int
4a5a2d63 1825pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
984263bc
MD
1826{
1827 struct pci_devinfo *dinfo;
1828 pcicfgregs *cfg;
1829
1830 dinfo = device_get_ivars(child);
1831 cfg = &dinfo->cfg;
1832
1833 switch (which) {
1834 case PCI_IVAR_SUBVENDOR:
1835 *result = cfg->subvendor;
1836 break;
1837 case PCI_IVAR_SUBDEVICE:
1838 *result = cfg->subdevice;
1839 break;
1840 case PCI_IVAR_VENDOR:
1841 *result = cfg->vendor;
1842 break;
1843 case PCI_IVAR_DEVICE:
1844 *result = cfg->device;
1845 break;
1846 case PCI_IVAR_DEVID:
1847 *result = (cfg->device << 16) | cfg->vendor;
1848 break;
1849 case PCI_IVAR_CLASS:
1850 *result = cfg->baseclass;
1851 break;
1852 case PCI_IVAR_SUBCLASS:
1853 *result = cfg->subclass;
1854 break;
1855 case PCI_IVAR_PROGIF:
1856 *result = cfg->progif;
1857 break;
1858 case PCI_IVAR_REVID:
1859 *result = cfg->revid;
1860 break;
1861 case PCI_IVAR_INTPIN:
1862 *result = cfg->intpin;
1863 break;
1864 case PCI_IVAR_IRQ:
1865 *result = cfg->intline;
1866 break;
1867 case PCI_IVAR_BUS:
1868 *result = cfg->bus;
1869 break;
1870 case PCI_IVAR_SLOT:
1871 *result = cfg->slot;
1872 break;
1873 case PCI_IVAR_FUNCTION:
1874 *result = cfg->func;
1875 break;
1876 case PCI_IVAR_SECONDARYBUS:
1877 *result = cfg->secondarybus;
1878 break;
1879 case PCI_IVAR_SUBORDINATEBUS:
1880 *result = cfg->subordinatebus;
1881 break;
f72d3d23
JS
1882 case PCI_IVAR_ETHADDR:
1883 /*
1884 * The generic accessor doesn't deal with failure, so
1885 * we set the return value, then return an error.
1886 */
3641b7ca 1887 *result = 0;
f72d3d23 1888 return (EINVAL);
c7e4e7eb
SZ
1889 case PCI_IVAR_PCIXCAP_PTR:
1890 *result = cfg->pcixcap_ptr;
1891 break;
1892 case PCI_IVAR_PCIECAP_PTR:
1893 *result = cfg->expr.expr_ptr;
1894 break;
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MD
1895 default:
1896 return ENOENT;
1897 }
1898 return 0;
1899}
1900
22457186 1901int
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MD
1902pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1903{
1904 struct pci_devinfo *dinfo;
1905 pcicfgregs *cfg;
1906
1907 dinfo = device_get_ivars(child);
1908 cfg = &dinfo->cfg;
1909
1910 switch (which) {
1911 case PCI_IVAR_SUBVENDOR:
1912 case PCI_IVAR_SUBDEVICE:
1913 case PCI_IVAR_VENDOR:
1914 case PCI_IVAR_DEVICE:
1915 case PCI_IVAR_DEVID:
1916 case PCI_IVAR_CLASS:
1917 case PCI_IVAR_SUBCLASS:
1918 case PCI_IVAR_PROGIF:
1919 case PCI_IVAR_REVID:
1920 case PCI_IVAR_INTPIN:
1921 case PCI_IVAR_IRQ:
1922 case PCI_IVAR_BUS:
1923 case PCI_IVAR_SLOT:
1924 case PCI_IVAR_FUNCTION:
f72d3d23 1925 case PCI_IVAR_ETHADDR:
c7e4e7eb
SZ
1926 case PCI_IVAR_PCIXCAP_PTR:
1927 case PCI_IVAR_PCIECAP_PTR:
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MD
1928 return EINVAL; /* disallow for now */
1929
1930 case PCI_IVAR_SECONDARYBUS:
1931 cfg->secondarybus = value;
1932 break;
1933 case PCI_IVAR_SUBORDINATEBUS:
1934 cfg->subordinatebus = value;
1935 break;
1936 default:
1937 return ENOENT;
1938 }
1939 return 0;
1940}
1941
201eb0a7
TS
1942#ifdef PCI_MAP_FIXUP
1943static struct resource *
1944pci_alloc_map(device_t dev, device_t child, int type, int *rid, u_long start,
1945 u_long end, u_long count, u_int flags)
1946{
1947 struct pci_devinfo *dinfo = device_get_ivars(child);
1948 struct resource_list *rl = &dinfo->resources;
1949 struct resource_list_entry *rle;
1950 struct resource *res;
1951 uint32_t map, testval;
1952 int mapsize;
1953
1954 /*
1955 * Weed out the bogons, and figure out how large the BAR/map
1956 * is. BARs that read back 0 here are bogus and unimplemented.
1957 *
1958 * Note: atapci in legacy mode are special and handled elsewhere
1959 * in the code. If you have an atapci device in legacy mode and
1960 * it fails here, that other code is broken.
1961 */
1962 res = NULL;
1963 map = pci_read_config(child, *rid, 4);
1964 pci_write_config(child, *rid, 0xffffffff, 4);
1965 testval = pci_read_config(child, *rid, 4);
1966 if (pci_mapbase(testval) == 0)
1967 goto out;
1968 if (pci_maptype(testval) & PCI_MAPMEM) {
1969 if (type != SYS_RES_MEMORY) {
1970 if (bootverbose)
1971 device_printf(dev, "child %s requested type %d"
1972 " for rid %#x, but the BAR says "
1973 "it is a memio\n",
1974 device_get_nameunit(child), type,
1975 *rid);
1976 goto out;
1977 }
1978 } else {
1979 if (type != SYS_RES_IOPORT) {
1980 if (bootverbose)
1981 device_printf(dev, "child %s requested type %d"
1982 " for rid %#x, but the BAR says "
1983 "it is an ioport\n",
1984 device_get_nameunit(child), type,
1985 *rid);
1986 goto out;
1987 }
1988 }
1989 /*
1990 * For real BARs, we need to override the size that
1991 * the driver requests, because that's what the BAR
1992 * actually uses and we would otherwise have a
1993 * situation where we might allocate the excess to
1994 * another driver, which won't work.
1995 */
1996 mapsize = pci_mapsize(testval);
1997 count = 1 << mapsize;
1998 if (RF_ALIGNMENT(flags) < mapsize)
1999 flags = (flags & ~RF_ALIGNMENT_MASK) |
2000 RF_ALIGNMENT_LOG2(mapsize);
2001 /*
2002 * Allocate enough resource, and then write back the
2003 * appropriate BAR for that resource.
2004 */
2005 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
2006 start, end, count, flags);
2007 if (res == NULL) {
2008 device_printf(child, "%#lx bytes at rid %#x res %d failed "
2009 "(%#lx, %#lx)\n", count, *rid, type, start, end);
2010 goto out;
2011 }
2012 resource_list_add(rl, type, *rid, start, end, count);
2013 rle = resource_list_find(rl, type, *rid);
2014 if (rle == NULL)
2015 panic("pci_alloc_map: unexpectedly can't find resource.");
2016 rle->res = res;
2017 rle->start = rman_get_start(res);
2018 rle->end = rman_get_end(res);
2019 rle->count = count;
2020 if (bootverbose)
2021 device_printf(child, "lazy allocation of %#lx bytes rid %#x "
2022 "type %d at %#lx\n", count, *rid, type,
2023 rman_get_start(res));
2024 map = rman_get_start(res);
2025out:;
2026 pci_write_config(child, *rid, map, 4);
2027 return res;
2028}
2029#endif /* PCI_MAP_FIXUP */
2030
261fa16d 2031struct resource *
984263bc
MD
2032pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
2033 u_long start, u_long end, u_long count, u_int flags)
2034{
2035 struct pci_devinfo *dinfo = device_get_ivars(child);
2036 struct resource_list *rl = &dinfo->resources;
201eb0a7
TS
2037#ifdef PCI_MAP_FIXUP
2038 struct resource_list_entry *rle;
2039#endif /* PCI_MAP_FIXUP */
984263bc 2040 pcicfgregs *cfg = &dinfo->cfg;
de67e43b 2041
984263bc
MD
2042 /*
2043 * Perform lazy resource allocation
984263bc
MD
2044 */
2045 if (device_get_parent(child) == dev) {
de67e43b
JS
2046 switch (type) {
2047 case SYS_RES_IRQ:
2048#ifdef __i386__
984263bc
MD
2049 /*
2050 * If device doesn't have an interrupt routed, and is
2051 * deserving of an interrupt, try to assign it one.
2052 */
de67e43b
JS
2053 if ((cfg->intline == 255 || cfg->intline == 0) &&
2054 (cfg->intpin != 0) &&
2055 (start == 0) && (end == ~0UL)) {
2056 cfg->intline = PCIB_ROUTE_INTERRUPT(
2057 device_get_parent(dev), child,
2058 cfg->intpin);
2059 if (cfg->intline != 255) {
2060 pci_write_config(child, PCIR_INTLINE,
2061 cfg->intline, 1);
2062 resource_list_add(rl, SYS_RES_IRQ, 0,
2063 cfg->intline, cfg->intline, 1);
2064 }
2065 }
820c1612 2066 break;
de67e43b
JS
2067#endif
2068 case SYS_RES_IOPORT:
201eb0a7 2069 /* FALLTHROUGH */
de67e43b
JS
2070 case SYS_RES_MEMORY:
2071 if (*rid < PCIR_BAR(cfg->nummaps)) {
2072 /*
2073 * Enable the I/O mode. We should
2074 * also be assigning resources too
2075 * when none are present. The
2076 * resource_list_alloc kind of sorta does
2077 * this...
2078 */
2079 if (PCI_ENABLE_IO(dev, child, type))
2080 return (NULL);
984263bc 2081 }
201eb0a7
TS
2082#ifdef PCI_MAP_FIXUP
2083 rle = resource_list_find(rl, type, *rid);
2084 if (rle == NULL)
2085 return pci_alloc_map(dev, child, type, rid,
2086 start, end, count, flags);
2087#endif /* PCI_MAP_FIXUP */
820c1612 2088 break;
984263bc 2089 }
201eb0a7
TS
2090#ifdef PCI_MAP_FIXUP
2091 /*
2092 * If we've already allocated the resource, then
2093 * return it now. But first we may need to activate
2094 * it, since we don't allocate the resource as active
2095 * above. Normally this would be done down in the
2096 * nexus, but since we short-circuit that path we have
2097 * to do its job here. Not sure if we should free the
2098 * resource if it fails to activate.
2099 *
2100 * Note: this also finds and returns resources for
2101 * atapci devices in legacy mode as allocated in
2102 * pci_ata_maps().
2103 */
2104 rle = resource_list_find(rl, type, *rid);
2105 if (rle != NULL && rle->res != NULL) {
2106 if (bootverbose)
2107 device_printf(child, "reserved %#lx bytes for "
2108 "rid %#x type %d at %#lx\n",
2109 rman_get_size(rle->res), *rid,
2110 type, rman_get_start(rle->res));
2111 if ((flags & RF_ACTIVE) &&
2112 bus_generic_activate_resource(dev, child, type,
2113 *rid, rle->res) != 0)
2114 return NULL;
2115 return rle->res;
2116 }
2117#endif /* PCI_MAP_FIXUP */
984263bc 2118 }
984263bc
MD
2119 return resource_list_alloc(rl, dev, child, type, rid,
2120 start, end, count, flags);
2121}
2122
2123static int
2124pci_release_resource(device_t dev, device_t child, int type, int rid,
2125 struct resource *r)
2126{
2127 struct pci_devinfo *dinfo = device_get_ivars(child);
2128 struct resource_list *rl = &dinfo->resources;
2129
2130 return resource_list_release(rl, dev, child, type, rid, r);
2131}
2132
2133static int
2134pci_set_resource(device_t dev, device_t child, int type, int rid,
2135 u_long start, u_long count)
2136{
2137 struct pci_devinfo *dinfo = device_get_ivars(child);
2138 struct resource_list *rl = &dinfo->resources;
2139
2140 resource_list_add(rl, type, rid, start, start + count - 1, count);
2141 return 0;
2142}
2143
2144static int
2145pci_get_resource(device_t dev, device_t child, int type, int rid,
2146 u_long *startp, u_long *countp)
2147{
2148 struct pci_devinfo *dinfo = device_get_ivars(child);
2149 struct resource_list *rl = &dinfo->resources;
2150 struct resource_list_entry *rle;
2151
2152 rle = resource_list_find(rl, type, rid);
2153 if (!rle)
2154 return ENOENT;
2155
2156 if (startp)
2157 *startp = rle->start;
2158 if (countp)
2159 *countp = rle->count;
2160
2161 return 0;
2162}
2163
e126caf1 2164void
984263bc
MD
2165pci_delete_resource(device_t dev, device_t child, int type, int rid)
2166{
85f8e2ea 2167 kprintf("pci_delete_resource: PCI resources can not be deleted\n");
984263bc
MD
2168}
2169
e126caf1
MD
2170struct resource_list *
2171pci_get_resource_list (device_t dev, device_t child)
2172{
b0486c83 2173 struct pci_devinfo *dinfo = device_get_ivars(child);
e126caf1 2174
b0486c83 2175 if (dinfo == NULL)
e126caf1 2176 return (NULL);
b0486c83 2177 return (&dinfo->resources);
e126caf1
MD
2178}
2179
2180u_int32_t
984263bc
MD
2181pci_read_config_method(device_t dev, device_t child, int reg, int width)
2182{
2183 struct pci_devinfo *dinfo = device_get_ivars(child);
2184 pcicfgregs *cfg = &dinfo->cfg;
4a5a2d63
JS
2185
2186 return PCIB_READ_CONFIG(device_get_parent(dev),
2187 cfg->bus, cfg->slot, cfg->func,
2188 reg, width);
984263bc
MD
2189}
2190
e126caf1 2191void
984263bc
MD
2192pci_write_config_method(device_t dev, device_t child, int reg,
2193 u_int32_t val, int width)
2194{
2195 struct pci_devinfo *dinfo = device_get_ivars(child);
2196 pcicfgregs *cfg = &dinfo->cfg;
4a5a2d63
JS
2197
2198 PCIB_WRITE_CONFIG(device_get_parent(dev),
2199 cfg->bus, cfg->slot, cfg->func,
2200 reg, val, width);
984263bc
MD
2201}
2202
e126caf1
MD
2203int
2204pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
2205 size_t buflen)
2206{
2207 struct pci_devinfo *dinfo;
2208
2209 dinfo = device_get_ivars(child);
f8c7a42d 2210 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
e126caf1
MD
2211 pci_get_function(child));
2212 return (0);
2213}
2214
2215int
2216pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
2217 size_t buflen)
2218{
2219 struct pci_devinfo *dinfo;
2220 pcicfgregs *cfg;
2221
2222 dinfo = device_get_ivars(child);
2223 cfg = &dinfo->cfg;
f8c7a42d 2224 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
e126caf1
MD
2225 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
2226 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
2227 cfg->progif);
2228 return (0);
2229}
2230
2231int
2232pci_assign_interrupt_method(device_t dev, device_t child)
2233{
2234 struct pci_devinfo *dinfo = device_get_ivars(child);
2235 pcicfgregs *cfg = &dinfo->cfg;
2236
2237 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
2238 cfg->intpin));
2239}
2240
984263bc
MD
2241static int
2242pci_modevent(module_t mod, int what, void *arg)
2243{
2244 switch (what) {
2245 case MOD_LOAD:
2246 STAILQ_INIT(&pci_devq);
2247 break;
984263bc
MD
2248 case MOD_UNLOAD:
2249 break;
2250 }
2251
2252 return 0;
2253}
2254
e126caf1
MD
2255int
2256pci_resume(device_t dev)
2257{
2258 int numdevs;
2259 int i;
2260 device_t *children;
2261 device_t child;
2262 struct pci_devinfo *dinfo;
2263 pcicfgregs *cfg;
2264
2265 device_get_children(dev, &children, &numdevs);
2266
2267 for (i = 0; i < numdevs; i++) {
2268 child = children[i];
2269
2270 dinfo = device_get_ivars(child);
2271 cfg = &dinfo->cfg;
2272 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2273 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
2274 if (PCI_INTERRUPT_VALID(cfg->intline)) {
2275 pci_write_config(child, PCIR_INTLINE,
2276 cfg->intline, 1);
2277 }
2278 }
2279 }
2280
efda3bd0 2281 kfree(children, M_TEMP);
e126caf1
MD
2282
2283 return (bus_generic_resume(dev));
2284}
2285
984263bc
MD
2286static device_method_t pci_methods[] = {
2287 /* Device interface */
4a5a2d63 2288 DEVMETHOD(device_probe, pci_probe),
e126caf1 2289 DEVMETHOD(device_attach, pci_attach),
984263bc
MD
2290 DEVMETHOD(device_shutdown, bus_generic_shutdown),
2291 DEVMETHOD(device_suspend, bus_generic_suspend),
e126caf1 2292 DEVMETHOD(device_resume, pci_resume),
984263bc
MD
2293
2294 /* Bus interface */
2295 DEVMETHOD(bus_print_child, pci_print_child),
2296 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
2297 DEVMETHOD(bus_read_ivar, pci_read_ivar),
2298 DEVMETHOD(bus_write_ivar, pci_write_ivar),
2299 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
984263bc
MD
2300 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
2301 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
e126caf1
MD
2302
2303 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
984263bc
MD
2304 DEVMETHOD(bus_set_resource, pci_set_resource),
2305 DEVMETHOD(bus_get_resource, pci_get_resource),
2306 DEVMETHOD(bus_delete_resource, pci_delete_resource),
e126caf1
MD
2307 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
2308 DEVMETHOD(bus_release_resource, pci_release_resource),
2309 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
2310 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
2311 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
2312 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
984263bc
MD
2313
2314 /* PCI interface */
2315 DEVMETHOD(pci_read_config, pci_read_config_method),
2316 DEVMETHOD(pci_write_config, pci_write_config_method),
2317 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
2318 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
2319 DEVMETHOD(pci_enable_io, pci_enable_io_method),
2320 DEVMETHOD(pci_disable_io, pci_disable_io_method),
2321 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
2322 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
e126caf1 2323 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
984263bc
MD
2324
2325 { 0, 0 }
2326};
2327
3aef8050 2328driver_t pci_driver = {
984263bc
MD
2329 "pci",
2330 pci_methods,
2331 1, /* no softc */
2332};
2333
2334DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
261fa16d 2335MODULE_VERSION(pci, 1);