Silence warnings regarding yyunput being defined and never used.
[dragonfly.git] / sys / dev / serial / rc / rc.c
CommitLineData
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1/*
2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/i386/isa/rc.c,v 1.53.2.1 2001/02/26 04:23:10 jlemon Exp $
fef8985e 28 * $DragonFly: src/sys/dev/serial/rc/rc.c,v 1.17 2006/07/28 02:17:38 dillon Exp $
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29 *
30 */
31
32/*
33 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver
34 *
35 */
36
1f2de5d4 37#include "use_rc.h"
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38
39/*#define RCDEBUG*/
40
41#include <sys/param.h>
42#include <sys/systm.h>
43#include <sys/tty.h>
44#include <sys/proc.h>
45#include <sys/conf.h>
46#include <sys/dkstat.h>
47#include <sys/fcntl.h>
48#include <sys/interrupt.h>
49#include <sys/kernel.h>
8d77660e 50#include <sys/thread2.h>
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51#include <machine/clock.h>
52#include <machine/ipl.h>
53
1f2de5d4 54#include <bus/isa/i386/isa_device.h>
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55
56#include <i386/isa/ic/cd180.h>
1f2de5d4 57#include "rcreg.h"
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58
59/* Prototypes */
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60static int rcprobe (struct isa_device *);
61static int rcattach (struct isa_device *);
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62
63#define rcin(port) RC_IN (nec, port)
64#define rcout(port,v) RC_OUT (nec, port, v)
65
66#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__)
67#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd))
68
69#define RC_IBUFSIZE 256
70#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE)
71#define RC_OBUFSIZE 512
72#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4)
73#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE)
74#define LOTS_OF_EVENTS 64
75
76#define RC_FAKEID 0x10
77
78#define RC_PROBED 1
79#define RC_ATTACHED 2
80
81#define GET_UNIT(dev) (minor(dev) & 0x3F)
82#define CALLOUT(dev) (minor(dev) & 0x80)
83
84/* For isa routines */
85struct isa_driver rcdriver = {
86 rcprobe, rcattach, "rc"
87};
88
89static d_open_t rcopen;
90static d_close_t rcclose;
91static d_ioctl_t rcioctl;
92
93#define CDEV_MAJOR 63
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94static struct dev_ops rc_ops = {
95 { "rc", CDEV_MAJOR, D_TTY | D_KQFILTER },
96 .d_open = rcopen,
97 .d_close = rcclose,
98 .d_read = ttyread,
99 .d_write = ttywrite,
100 .d_ioctl = rcioctl,
101 .d_poll = ttypoll,
102 .d_kqfilter = ttykqfilter
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103};
104
105/* Per-board structure */
106static struct rc_softc {
107 u_int rcb_probed; /* 1 - probed, 2 - attached */
108 u_int rcb_addr; /* Base I/O addr */
109 u_int rcb_unit; /* unit # */
110 u_char rcb_dtr; /* DTR status */
111 struct rc_chans *rcb_baserc; /* base rc ptr */
112} rc_softc[NRC];
113
114/* Per-channel structure */
115static struct rc_chans {
116 struct rc_softc *rc_rcb; /* back ptr */
117 u_short rc_flags; /* Misc. flags */
118 int rc_chan; /* Channel # */
119 u_char rc_ier; /* intr. enable reg */
120 u_char rc_msvr; /* modem sig. status */
121 u_char rc_cor2; /* options reg */
122 u_char rc_pendcmd; /* special cmd pending */
123 u_int rc_dtrwait; /* dtr timeout */
124 u_int rc_dcdwaits; /* how many waits DCD in open */
125 u_char rc_hotchar; /* end packed optimize */
126 struct tty *rc_tp; /* tty struct */
127 u_char *rc_iptr; /* Chars input buffer */
128 u_char *rc_hiwat; /* hi-water mark */
129 u_char *rc_bufend; /* end of buffer */
130 u_char *rc_optr; /* ptr in output buf */
131 u_char *rc_obufend; /* end of output buf */
7a08a71e 132 struct callout rc_dtr_ch;
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133 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */
134 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */
135} rc_chans[NRC * CD180_NCHAN];
136
137static int rc_scheduled_event = 0;
7a08a71e 138static struct callout rc_wakeup_ch;
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139
140/* for pstat -t */
141static struct tty rc_tty[NRC * CD180_NCHAN];
142static const int nrc_tty = NRC * CD180_NCHAN;
143
144/* Flags */
145#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */
146#define RC_ACTOUT 0x0002 /* Dial-out port active */
147#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */
148#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */
149#define RC_DORXFER 0x0010 /* RXFER event planned */
150#define RC_DOXXFER 0x0020 /* XXFER event planned */
151#define RC_MODCHG 0x0040 /* Modem status changed */
152#define RC_OSUSP 0x0080 /* Output suspended */
153#define RC_OSBUSY 0x0100 /* start() routine in progress */
154#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */
155#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */
156#define RC_SEND_RDY 0x0800 /* ready to send */
157
158/* Table for translation of RCSR status bits to internal form */
159static int rc_rcsrt[16] = {
160 0, TTY_OE, TTY_FE,
161 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE,
162 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI,
163 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE,
164 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE,
165 TTY_BI|TTY_PE|TTY_FE|TTY_OE
166};
167
168/* Static prototypes */
477d3c1c 169static inthand2_t rcintr;
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170static void rc_hwreset (int, int, unsigned int);
171static int rc_test (int, int);
172static void rc_discard_output (struct rc_chans *);
173static void rc_hardclose (struct rc_chans *);
174static int rc_modctl (struct rc_chans *, int, int);
175static void rc_start (struct tty *);
176static void rc_stop (struct tty *, int rw);
177static int rc_param (struct tty *, struct termios *);
7b95be2a 178static inthand2_t rcpoll;
5ca58d54 179static void rc_reinit (struct rc_softc *);
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180#ifdef RCDEBUG
181static void printrcflags();
182#endif
183static timeout_t rc_dtrwakeup;
184static timeout_t rc_wakeup;
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185static void disc_optim (struct tty *tp, struct termios *t, struct rc_chans *);
186static void rc_wait0 (int nec, int unit, int chan, int line);
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187
188/**********************************************/
189
190/* Quick device probing */
191static int
192rcprobe(dvp)
193 struct isa_device *dvp;
194{
195 int irq = ffs(dvp->id_irq) - 1;
c9faf524 196 int nec = dvp->id_iobase;
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197
198 if (dvp->id_unit > NRC)
199 return 0;
200 if (!RC_VALIDADDR(nec)) {
201 printf("rc%d: illegal base address %x\n", dvp->id_unit, nec);
202 return 0;
203 }
204 if (!RC_VALIDIRQ(irq)) {
205 printf("rc%d: illegal IRQ value %d\n", dvp->id_unit, irq);
206 return 0;
207 }
208 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */
209 rcout(CD180_PPRH, 0x11);
210 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11)
211 return 0;
212 /* Now, test the board more thoroughly, with diagnostic */
213 if (rc_test(nec, dvp->id_unit))
214 return 0;
215 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED;
216
217 return 0xF;
218}
219
220static int
221rcattach(dvp)
222 struct isa_device *dvp;
223{
c9faf524 224 int chan, nec = dvp->id_iobase;
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225 struct rc_softc *rcb = &rc_softc[dvp->id_unit];
226 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN];
227 static int rc_started = 0;
228 struct tty *tp;
229
477d3c1c 230 dvp->id_intr = rcintr;
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231
232 /* Thorooughly test the device */
233 if (rcb->rcb_probed != RC_PROBED)
234 return 0;
235 rcb->rcb_addr = nec;
236 rcb->rcb_dtr = 0;
237 rcb->rcb_baserc = rc;
238 rcb->rcb_unit = dvp->id_unit;
239 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/
240 printf("rc%d: %d chans, firmware rev. %c\n", rcb->rcb_unit,
241 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A');
242
243 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) {
7a08a71e 244 callout_init(&rc->rc_dtr_ch);
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245 rc->rc_rcb = rcb;
246 rc->rc_chan = chan;
247 rc->rc_iptr = rc->rc_ibuf;
248 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
249 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER];
250 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0;
251 rc->rc_cor2 = rc->rc_pendcmd = 0;
252 rc->rc_optr = rc->rc_obufend = rc->rc_obuf;
253 rc->rc_dtrwait = 3 * hz;
254 rc->rc_dcdwaits= 0;
255 rc->rc_hotchar = 0;
256 tp = rc->rc_tp = &rc_tty[chan + (dvp->id_unit * CD180_NCHAN)];
257 ttychars(tp);
258 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0;
259 tp->t_cflag = TTYDEF_CFLAG;
260 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
261 }
262 rcb->rcb_probed = RC_ATTACHED;
263 if (!rc_started) {
fef8985e 264 dev_ops_add(&rc_ops, -1, rcb->rcb_unit);
477d3c1c 265 register_swi(SWI_TTY, rcpoll, NULL, "rcpoll", NULL);
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MD
266 callout_init(&rc_wakeup_ch);
267 rc_wakeup(NULL);
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268 rc_started = 1;
269 }
270 return 1;
271}
272
273/* RC interrupt handling */
274static void
477d3c1c 275rcintr(void *arg, void *frame)
984263bc 276{
477d3c1c 277 int unit = (int)arg;
c9faf524
RG
278 struct rc_softc *rcb = &rc_softc[unit];
279 struct rc_chans *rc;
280 int nec, resid;
281 u_char val, iack, bsr, ucnt, *optr;
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282 int good_data, t_state;
283
284 if (rcb->rcb_probed != RC_ATTACHED) {
285 printf("rc%d: bogus interrupt\n", unit);
286 return;
287 }
288 nec = rcb->rcb_addr;
289
290 bsr = ~(rcin(RC_BSR));
291
292 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) {
293 printf("rc%d: extra interrupt\n", unit);
294 rcout(CD180_EOIR, 0);
295 return;
296 }
297
298 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) {
299#ifdef RCDEBUG_DETAILED
300 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr,
301 (bsr & RC_BSR_TOUT)?"TOUT ":"",
302 (bsr & RC_BSR_RXINT)?"RXINT ":"",
303 (bsr & RC_BSR_TXINT)?"TXINT ":"",
304 (bsr & RC_BSR_MOINT)?"MOINT":"");
305#endif
306 if (bsr & RC_BSR_TOUT) {
307 printf("rc%d: hardware failure, reset board\n", unit);
308 rcout(RC_CTOUT, 0);
309 rc_reinit(rcb);
310 return;
311 }
312 if (bsr & RC_BSR_RXINT) {
313 iack = rcin(RC_PILR_RX);
314 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID));
315 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) {
316 printf("rc%d: fake rxint: %02x\n", unit, iack);
317 goto more_intrs;
318 }
319 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
320 t_state = rc->rc_tp->t_state;
321 /* Do RTS flow control stuff */
322 if ( (rc->rc_flags & RC_RTSFLOW)
323 || !(t_state & TS_ISOPEN)
324 ) {
325 if ( ( !(t_state & TS_ISOPEN)
326 || (t_state & TS_TBLOCK)
327 )
328 && (rc->rc_msvr & MSVR_RTS)
329 )
330 rcout(CD180_MSVR,
331 rc->rc_msvr &= ~MSVR_RTS);
332 else if (!(rc->rc_msvr & MSVR_RTS))
333 rcout(CD180_MSVR,
334 rc->rc_msvr |= MSVR_RTS);
335 }
336 ucnt = rcin(CD180_RDCR) & 0xF;
337 resid = 0;
338
339 if (t_state & TS_ISOPEN) {
340 /* check for input buffer overflow */
341 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) {
342 resid = ucnt;
343 ucnt = rc->rc_bufend - rc->rc_iptr;
344 resid -= ucnt;
345 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) {
346 rc->rc_flags |= RC_WAS_BUFOVFL;
347 rc_scheduled_event++;
348 }
349 }
350 optr = rc->rc_iptr;
351 /* check foor good data */
352 if (good_data) {
353 while (ucnt-- > 0) {
354 val = rcin(CD180_RDR);
355 optr[0] = val;
356 optr[INPUT_FLAGS_SHIFT] = 0;
357 optr++;
358 rc_scheduled_event++;
359 if (val != 0 && val == rc->rc_hotchar)
360 setsofttty();
361 }
362 } else {
363 /* Store also status data */
364 while (ucnt-- > 0) {
365 iack = rcin(CD180_RCSR);
366 if (iack & RCSR_Timeout)
367 break;
368 if ( (iack & RCSR_OE)
369 && !(rc->rc_flags & RC_WAS_SILOVFL)) {
370 rc->rc_flags |= RC_WAS_SILOVFL;
371 rc_scheduled_event++;
372 }
373 val = rcin(CD180_RDR);
374 /*
375 Don't store PE if IGNPAR and BREAK if IGNBRK,
376 this hack allows "raw" tty optimization
377 works even if IGN* is set.
378 */
379 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break))
380 || ((!(iack & (RCSR_PE|RCSR_FE))
381 || !(rc->rc_tp->t_iflag & IGNPAR))
382 && (!(iack & RCSR_Break)
383 || !(rc->rc_tp->t_iflag & IGNBRK)))) {
384 if ( (iack & (RCSR_PE|RCSR_FE))
385 && (t_state & TS_CAN_BYPASS_L_RINT)
386 && ((iack & RCSR_FE)
387 || ((iack & RCSR_PE)
388 && (rc->rc_tp->t_iflag & INPCK))))
389 val = 0;
390 else if (val != 0 && val == rc->rc_hotchar)
391 setsofttty();
392 optr[0] = val;
393 optr[INPUT_FLAGS_SHIFT] = iack;
394 optr++;
395 rc_scheduled_event++;
396 }
397 }
398 }
399 rc->rc_iptr = optr;
400 rc->rc_flags |= RC_DORXFER;
401 } else
402 resid = ucnt;
403 /* Clear FIFO if necessary */
404 while (resid-- > 0) {
405 if (!good_data)
406 iack = rcin(CD180_RCSR);
407 else
408 iack = 0;
409 if (iack & RCSR_Timeout)
410 break;
411 (void) rcin(CD180_RDR);
412 }
413 goto more_intrs;
414 }
415 if (bsr & RC_BSR_MOINT) {
416 iack = rcin(RC_PILR_MODEM);
417 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) {
418 printf("rc%d: fake moint: %02x\n", unit, iack);
419 goto more_intrs;
420 }
421 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
422 iack = rcin(CD180_MCR);
423 rc->rc_msvr = rcin(CD180_MSVR);
424 rcout(CD180_MCR, 0);
425#ifdef RCDEBUG
426 printrcflags(rc, "moint");
427#endif
428 if (rc->rc_flags & RC_CTSFLOW) {
429 if (rc->rc_msvr & MSVR_CTS)
430 rc->rc_flags |= RC_SEND_RDY;
431 else
432 rc->rc_flags &= ~RC_SEND_RDY;
433 } else
434 rc->rc_flags |= RC_SEND_RDY;
435 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) {
436 rc_scheduled_event += LOTS_OF_EVENTS;
437 rc->rc_flags |= RC_MODCHG;
438 setsofttty();
439 }
440 goto more_intrs;
441 }
442 if (bsr & RC_BSR_TXINT) {
443 iack = rcin(RC_PILR_TX);
444 if (iack != (GIVR_IT_TDI | RC_FAKEID)) {
445 printf("rc%d: fake txint: %02x\n", unit, iack);
446 goto more_intrs;
447 }
448 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
449 if ( (rc->rc_flags & RC_OSUSP)
450 || !(rc->rc_flags & RC_SEND_RDY)
451 )
452 goto more_intrs;
453 /* Handle breaks and other stuff */
454 if (rc->rc_pendcmd) {
455 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC);
456 rcout(CD180_TDR, CD180_C_ESC);
457 rcout(CD180_TDR, rc->rc_pendcmd);
458 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC);
459 rc->rc_pendcmd = 0;
460 goto more_intrs;
461 }
462 optr = rc->rc_optr;
463 resid = rc->rc_obufend - optr;
464 if (resid > CD180_NFIFO)
465 resid = CD180_NFIFO;
466 while (resid-- > 0)
467 rcout(CD180_TDR, *optr++);
468 rc->rc_optr = optr;
469
470 /* output completed? */
471 if (optr >= rc->rc_obufend) {
472 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy);
473#ifdef RCDEBUG
474 printf("rc%d/%d: output completed\n", unit, rc->rc_chan);
475#endif
476 if (!(rc->rc_flags & RC_DOXXFER)) {
477 rc_scheduled_event += LOTS_OF_EVENTS;
478 rc->rc_flags |= RC_DOXXFER;
479 setsofttty();
480 }
481 }
482 }
483 more_intrs:
484 rcout(CD180_EOIR, 0); /* end of interrupt */
485 rcout(RC_CTOUT, 0);
486 bsr = ~(rcin(RC_BSR));
487 }
488}
489
490/* Feed characters to output buffer */
491static void rc_start(tp)
c9faf524 492struct tty *tp;
984263bc 493{
c9faf524 494 struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
8d77660e 495 int nec = rc->rc_rcb->rcb_addr;
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MD
496
497 if (rc->rc_flags & RC_OSBUSY)
498 return;
8d77660e 499 crit_enter();
984263bc 500 rc->rc_flags |= RC_OSBUSY;
7b95be2a 501 cpu_disable_intr();
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MD
502 if (tp->t_state & TS_TTSTOP)
503 rc->rc_flags |= RC_OSUSP;
504 else
505 rc->rc_flags &= ~RC_OSUSP;
506 /* Do RTS flow control stuff */
507 if ( (rc->rc_flags & RC_RTSFLOW)
508 && (tp->t_state & TS_TBLOCK)
509 && (rc->rc_msvr & MSVR_RTS)
510 ) {
511 rcout(CD180_CAR, rc->rc_chan);
512 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS);
513 } else if (!(rc->rc_msvr & MSVR_RTS)) {
514 rcout(CD180_CAR, rc->rc_chan);
515 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS);
516 }
7b95be2a 517 cpu_enable_intr();
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MD
518 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP))
519 goto out;
520#ifdef RCDEBUG
521 printrcflags(rc, "rcstart");
522#endif
523 ttwwakeup(tp);
524#ifdef RCDEBUG
525 printf("rcstart: outq = %d obuf = %d\n",
526 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr);
527#endif
528 if (tp->t_state & TS_BUSY)
529 goto out; /* output still in progress ... */
530
531 if (tp->t_outq.c_cc > 0) {
532 u_int ocnt;
533
534 tp->t_state |= TS_BUSY;
535 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf);
7b95be2a 536 cpu_disable_intr();
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MD
537 rc->rc_optr = rc->rc_obuf;
538 rc->rc_obufend = rc->rc_optr + ocnt;
7b95be2a 539 cpu_enable_intr();
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MD
540 if (!(rc->rc_ier & IER_TxRdy)) {
541#ifdef RCDEBUG
542 printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan);
543#endif
544 rcout(CD180_CAR, rc->rc_chan);
545 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy);
546 }
547 }
548out:
549 rc->rc_flags &= ~RC_OSBUSY;
8d77660e 550 crit_exit();
984263bc
MD
551}
552
553/* Handle delayed events. */
7b95be2a 554void
477d3c1c 555rcpoll(void *dummy, void *frame)
984263bc 556{
c9faf524
RG
557 struct rc_chans *rc;
558 struct rc_softc *rcb;
559 u_char *tptr, *eptr;
560 struct tty *tp;
561 int chan, icnt, nec, unit;
984263bc
MD
562
563 if (rc_scheduled_event == 0)
564 return;
565repeat:
566 for (unit = 0; unit < NRC; unit++) {
567 rcb = &rc_softc[unit];
568 rc = rcb->rcb_baserc;
569 nec = rc->rc_rcb->rcb_addr;
570 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) {
571 tp = rc->rc_tp;
572#ifdef RCDEBUG
573 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG|
574 RC_WAS_BUFOVFL|RC_WAS_SILOVFL))
575 printrcflags(rc, "rcevent");
576#endif
577 if (rc->rc_flags & RC_WAS_BUFOVFL) {
7b95be2a 578 cpu_disable_intr();
984263bc
MD
579 rc->rc_flags &= ~RC_WAS_BUFOVFL;
580 rc_scheduled_event--;
7b95be2a 581 cpu_enable_intr();
984263bc
MD
582 printf("rc%d/%d: interrupt-level buffer overflow\n",
583 unit, chan);
584 }
585 if (rc->rc_flags & RC_WAS_SILOVFL) {
7b95be2a 586 cpu_disable_intr();
984263bc
MD
587 rc->rc_flags &= ~RC_WAS_SILOVFL;
588 rc_scheduled_event--;
7b95be2a 589 cpu_enable_intr();
984263bc
MD
590 printf("rc%d/%d: silo overflow\n",
591 unit, chan);
592 }
593 if (rc->rc_flags & RC_MODCHG) {
7b95be2a 594 cpu_disable_intr();
984263bc
MD
595 rc->rc_flags &= ~RC_MODCHG;
596 rc_scheduled_event -= LOTS_OF_EVENTS;
7b95be2a 597 cpu_enable_intr();
984263bc
MD
598 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD));
599 }
600 if (rc->rc_flags & RC_DORXFER) {
7b95be2a 601 cpu_disable_intr();
984263bc
MD
602 rc->rc_flags &= ~RC_DORXFER;
603 eptr = rc->rc_iptr;
604 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE])
605 tptr = &rc->rc_ibuf[RC_IBUFSIZE];
606 else
607 tptr = rc->rc_ibuf;
608 icnt = eptr - tptr;
609 if (icnt > 0) {
610 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
611 rc->rc_iptr = rc->rc_ibuf;
612 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
613 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER];
614 } else {
615 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
616 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE];
617 rc->rc_hiwat =
618 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER];
619 }
620 if ( (rc->rc_flags & RC_RTSFLOW)
621 && (tp->t_state & TS_ISOPEN)
622 && !(tp->t_state & TS_TBLOCK)
623 && !(rc->rc_msvr & MSVR_RTS)
624 ) {
625 rcout(CD180_CAR, chan);
626 rcout(CD180_MSVR,
627 rc->rc_msvr |= MSVR_RTS);
628 }
629 rc_scheduled_event -= icnt;
630 }
7b95be2a 631 cpu_enable_intr();
984263bc
MD
632
633 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN))
634 goto done1;
635
636 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT)
637 && !(tp->t_state & TS_LOCAL)) {
638 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER
639 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF))
640 && !(tp->t_state & TS_TBLOCK))
641 ttyblock(tp);
642 tk_nin += icnt;
643 tk_rawcc += icnt;
644 tp->t_rawcc += icnt;
645 if (b_to_q(tptr, icnt, &tp->t_rawq))
646 printf("rc%d/%d: tty-level buffer overflow\n",
647 unit, chan);
648 ttwakeup(tp);
649 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY)
650 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) {
651 tp->t_state &= ~TS_TTSTOP;
652 tp->t_lflag &= ~FLUSHO;
653 rc_start(tp);
654 }
655 } else {
656 for (; tptr < eptr; tptr++)
657 (*linesw[tp->t_line].l_rint)
658 (tptr[0] |
659 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp);
660 }
661done1: ;
662 }
663 if (rc->rc_flags & RC_DOXXFER) {
7b95be2a 664 cpu_disable_intr();
984263bc
MD
665 rc_scheduled_event -= LOTS_OF_EVENTS;
666 rc->rc_flags &= ~RC_DOXXFER;
667 rc->rc_tp->t_state &= ~TS_BUSY;
7b95be2a 668 cpu_enable_intr();
984263bc
MD
669 (*linesw[tp->t_line].l_start)(tp);
670 }
671 }
672 if (rc_scheduled_event == 0)
673 break;
674 }
675 if (rc_scheduled_event >= LOTS_OF_EVENTS)
676 goto repeat;
677}
678
679static void
680rc_stop(tp, rw)
c9faf524 681 struct tty *tp;
984263bc
MD
682 int rw;
683{
c9faf524 684 struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
984263bc
MD
685 u_char *tptr, *eptr;
686
687#ifdef RCDEBUG
688 printf("rc%d/%d: rc_stop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan,
689 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":"");
690#endif
691 if (rw & FWRITE)
692 rc_discard_output(rc);
7b95be2a 693 cpu_disable_intr();
984263bc
MD
694 if (rw & FREAD) {
695 rc->rc_flags &= ~RC_DORXFER;
696 eptr = rc->rc_iptr;
697 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
698 tptr = &rc->rc_ibuf[RC_IBUFSIZE];
699 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
700 } else {
701 tptr = rc->rc_ibuf;
702 rc->rc_iptr = rc->rc_ibuf;
703 }
704 rc_scheduled_event -= eptr - tptr;
705 }
706 if (tp->t_state & TS_TTSTOP)
707 rc->rc_flags |= RC_OSUSP;
708 else
709 rc->rc_flags &= ~RC_OSUSP;
7b95be2a 710 cpu_enable_intr();
984263bc
MD
711}
712
713static int
fef8985e 714rcopen(struct dev_open_args *ap)
984263bc 715{
fef8985e 716 dev_t dev = ap->a_head.a_dev;
c9faf524
RG
717 struct rc_chans *rc;
718 struct tty *tp;
8d77660e 719 int unit, nec, error = 0;
984263bc
MD
720
721 unit = GET_UNIT(dev);
722 if (unit >= NRC * CD180_NCHAN)
723 return ENXIO;
724 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED)
725 return ENXIO;
726 rc = &rc_chans[unit];
727 tp = rc->rc_tp;
728 dev->si_tty = tp;
729 nec = rc->rc_rcb->rcb_addr;
730#ifdef RCDEBUG
731 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
732#endif
8d77660e 733 crit_enter();
984263bc
MD
734
735again:
736 while (rc->rc_flags & RC_DTR_OFF) {
377d4740 737 error = tsleep(&(rc->rc_dtrwait), PCATCH, "rcdtr", 0);
984263bc
MD
738 if (error != 0)
739 goto out;
740 }
741 if (tp->t_state & TS_ISOPEN) {
742 if (CALLOUT(dev)) {
743 if (!(rc->rc_flags & RC_ACTOUT)) {
744 error = EBUSY;
745 goto out;
746 }
747 } else {
748 if (rc->rc_flags & RC_ACTOUT) {
fef8985e 749 if (ap->a_oflags & O_NONBLOCK) {
984263bc
MD
750 error = EBUSY;
751 goto out;
752 }
377d4740 753 error = tsleep(&rc->rc_rcb, PCATCH, "rcbi", 0);
984263bc
MD
754 if (error)
755 goto out;
756 goto again;
757 }
758 }
759 if (tp->t_state & TS_XCLUDE &&
fef8985e 760 suser_cred(ap->a_cred, 0)) {
984263bc
MD
761 error = EBUSY;
762 goto out;
763 }
764 } else {
765 tp->t_oproc = rc_start;
766 tp->t_param = rc_param;
767 tp->t_stop = rc_stop;
768 tp->t_dev = dev;
769
770 if (CALLOUT(dev))
771 tp->t_cflag |= CLOCAL;
772 else
773 tp->t_cflag &= ~CLOCAL;
774
775 error = rc_param(tp, &tp->t_termios);
776 if (error)
777 goto out;
778 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET);
779
780 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev))
781 (*linesw[tp->t_line].l_modem)(tp, 1);
782 }
783 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev)
fef8985e 784 && !(tp->t_cflag & CLOCAL) && !(ap->a_oflags & O_NONBLOCK)) {
984263bc 785 rc->rc_dcdwaits++;
377d4740 786 error = tsleep(TSA_CARR_ON(tp), PCATCH, "rcdcd", 0);
984263bc
MD
787 rc->rc_dcdwaits--;
788 if (error != 0)
789 goto out;
790 goto again;
791 }
792 error = (*linesw[tp->t_line].l_open)(dev, tp);
793 disc_optim(tp, &tp->t_termios, rc);
794 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev))
795 rc->rc_flags |= RC_ACTOUT;
796out:
8d77660e 797 crit_exit();
984263bc
MD
798
799 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN))
800 rc_hardclose(rc);
801
802 return error;
803}
804
805static int
fef8985e 806rcclose(struct dev_close_args *ap)
984263bc 807{
fef8985e 808 dev_t dev = ap->a_head.a_dev;
c9faf524
RG
809 struct rc_chans *rc;
810 struct tty *tp;
8d77660e 811 int unit = GET_UNIT(dev);
984263bc
MD
812
813 if (unit >= NRC * CD180_NCHAN)
814 return ENXIO;
815 rc = &rc_chans[unit];
816 tp = rc->rc_tp;
817#ifdef RCDEBUG
818 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
819#endif
8d77660e 820 crit_enter();
fef8985e 821 (*linesw[tp->t_line].l_close)(tp, ap->a_fflag);
984263bc
MD
822 disc_optim(tp, &tp->t_termios, rc);
823 rc_stop(tp, FREAD | FWRITE);
824 rc_hardclose(rc);
825 ttyclose(tp);
8d77660e 826 crit_exit();
984263bc
MD
827 return 0;
828}
829
830static void rc_hardclose(rc)
c9faf524 831struct rc_chans *rc;
984263bc 832{
8d77660e 833 int nec = rc->rc_rcb->rcb_addr;
c9faf524 834 struct tty *tp = rc->rc_tp;
984263bc 835
8d77660e 836 crit_enter();
984263bc
MD
837 rcout(CD180_CAR, rc->rc_chan);
838
839 /* Disable rx/tx intrs */
840 rcout(CD180_IER, rc->rc_ier = 0);
841 if ( (tp->t_cflag & HUPCL)
842 || (!(rc->rc_flags & RC_ACTOUT)
843 && !(rc->rc_msvr & MSVR_CD)
844 && !(tp->t_cflag & CLOCAL))
845 || !(tp->t_state & TS_ISOPEN)
846 ) {
847 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
848 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
849 (void) rc_modctl(rc, TIOCM_RTS, DMSET);
850 if (rc->rc_dtrwait) {
7a08a71e
MD
851 callout_reset(&rc->rc_dtr_ch, rc->rc_dtrwait,
852 rc_dtrwakeup, rc);
984263bc
MD
853 rc->rc_flags |= RC_DTR_OFF;
854 }
855 }
856 rc->rc_flags &= ~RC_ACTOUT;
857 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */
858 wakeup(TSA_CARR_ON(tp));
8d77660e 859 crit_exit();
984263bc
MD
860}
861
862/* Reset the bastard */
863static void rc_hwreset(unit, nec, chipid)
c9faf524 864 int unit, nec;
984263bc
MD
865 unsigned int chipid;
866{
867 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */
868 DELAY(20000);
869 WAITFORCCR(unit, -1);
870
871 rcout(RC_CTOUT, 0); /* Clear timeout */
872 rcout(CD180_GIVR, chipid);
873 rcout(CD180_GICR, 0);
874
875 /* Set Prescaler Registers (1 msec) */
876 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF);
877 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8);
878
879 /* Initialize Priority Interrupt Level Registers */
880 rcout(CD180_PILR1, RC_PILR_MODEM);
881 rcout(CD180_PILR2, RC_PILR_TX);
882 rcout(CD180_PILR3, RC_PILR_RX);
883
884 /* Reset DTR */
885 rcout(RC_DTREG, ~0);
886}
887
888/* Set channel parameters */
889static int rc_param(tp, ts)
c9faf524 890 struct tty *tp;
984263bc
MD
891 struct termios *ts;
892{
c9faf524
RG
893 struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
894 int nec = rc->rc_rcb->rcb_addr;
8d77660e 895 int idivs, odivs, val, cflag, iflag, lflag, inpflow;
984263bc
MD
896
897 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800
898 || ts->c_ispeed < 0 || ts->c_ispeed > 76800
899 )
900 return (EINVAL);
901 if (ts->c_ispeed == 0)
902 ts->c_ispeed = ts->c_ospeed;
903 odivs = RC_BRD(ts->c_ospeed);
904 idivs = RC_BRD(ts->c_ispeed);
905
8d77660e 906 crit_enter();
984263bc
MD
907
908 /* Select channel */
909 rcout(CD180_CAR, rc->rc_chan);
910
911 /* If speed == 0, hangup line */
912 if (ts->c_ospeed == 0) {
913 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
914 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
915 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
916 }
917
918 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
919 cflag = ts->c_cflag;
920 iflag = ts->c_iflag;
921 lflag = ts->c_lflag;
922
923 if (idivs > 0) {
924 rcout(CD180_RBPRL, idivs & 0xFF);
925 rcout(CD180_RBPRH, idivs >> 8);
926 }
927 if (odivs > 0) {
928 rcout(CD180_TBPRL, odivs & 0xFF);
929 rcout(CD180_TBPRH, odivs >> 8);
930 }
931
932 /* set timeout value */
933 if (ts->c_ispeed > 0) {
934 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1;
935
936 if ( !(lflag & ICANON)
937 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0
938 && ts->c_cc[VTIME] * 10 > itm)
939 itm = ts->c_cc[VTIME] * 10;
940
941 rcout(CD180_RTPR, itm <= 255 ? itm : 255);
942 }
943
944 switch (cflag & CSIZE) {
945 case CS5: val = COR1_5BITS; break;
946 case CS6: val = COR1_6BITS; break;
947 case CS7: val = COR1_7BITS; break;
948 default:
949 case CS8: val = COR1_8BITS; break;
950 }
951 if (cflag & PARENB) {
952 val |= COR1_NORMPAR;
953 if (cflag & PARODD)
954 val |= COR1_ODDP;
955 if (!(cflag & INPCK))
956 val |= COR1_Ignore;
957 } else
958 val |= COR1_Ignore;
959 if (cflag & CSTOPB)
960 val |= COR1_2SB;
961 rcout(CD180_COR1, val);
962
963 /* Set FIFO threshold */
964 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2;
965 inpflow = 0;
966 if ( (iflag & IXOFF)
967 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE
968 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE
969 || (iflag & IXANY)
970 )
971 )
972 ) {
973 inpflow = 1;
974 val |= COR3_SCDE|COR3_FCT;
975 }
976 rcout(CD180_COR3, val);
977
978 /* Initialize on-chip automatic flow control */
979 val = 0;
980 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY);
981 if (cflag & CCTS_OFLOW) {
982 rc->rc_flags |= RC_CTSFLOW;
983 val |= COR2_CtsAE;
984 } else
985 rc->rc_flags |= RC_SEND_RDY;
986 if (tp->t_state & TS_TTSTOP)
987 rc->rc_flags |= RC_OSUSP;
988 else
989 rc->rc_flags &= ~RC_OSUSP;
990 if (cflag & CRTS_IFLOW)
991 rc->rc_flags |= RC_RTSFLOW;
992 else
993 rc->rc_flags &= ~RC_RTSFLOW;
994
995 if (inpflow) {
996 if (ts->c_cc[VSTART] != _POSIX_VDISABLE)
997 rcout(CD180_SCHR1, ts->c_cc[VSTART]);
998 rcout(CD180_SCHR2, ts->c_cc[VSTOP]);
999 val |= COR2_TxIBE;
1000 if (iflag & IXANY)
1001 val |= COR2_IXM;
1002 }
1003
1004 rcout(CD180_COR2, rc->rc_cor2 = val);
1005
1006 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1007 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1008
1009 disc_optim(tp, ts, rc);
1010
1011 /* modem ctl */
1012 val = cflag & CLOCAL ? 0 : MCOR1_CDzd;
1013 if (cflag & CCTS_OFLOW)
1014 val |= MCOR1_CTSzd;
1015 rcout(CD180_MCOR1, val);
1016
1017 val = cflag & CLOCAL ? 0 : MCOR2_CDod;
1018 if (cflag & CCTS_OFLOW)
1019 val |= MCOR2_CTSod;
1020 rcout(CD180_MCOR2, val);
1021
1022 /* enable i/o and interrupts */
1023 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1024 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS));
1025 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
1026
1027 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD;
1028 if (cflag & CCTS_OFLOW)
1029 rc->rc_ier |= IER_CTS;
1030 if (cflag & CREAD)
1031 rc->rc_ier |= IER_RxData;
1032 if (tp->t_state & TS_BUSY)
1033 rc->rc_ier |= IER_TxRdy;
1034 if (ts->c_ospeed != 0)
1035 rc_modctl(rc, TIOCM_DTR, DMBIS);
1036 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS))
1037 rc->rc_flags |= RC_SEND_RDY;
1038 rcout(CD180_IER, rc->rc_ier);
8d77660e 1039 crit_exit();
984263bc
MD
1040 return 0;
1041}
1042
1043/* Re-initialize board after bogus interrupts */
1044static void rc_reinit(rcb)
1045struct rc_softc *rcb;
1046{
c9faf524
RG
1047 struct rc_chans *rc, *rce;
1048 int nec;
984263bc
MD
1049
1050 nec = rcb->rcb_addr;
1051 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID);
1052 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN];
1053 rce = rc + CD180_NCHAN;
1054 for (; rc < rce; rc++)
1055 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios);
1056}
1057
1058static int
fef8985e 1059rcioctl(struct dev_ioctl_args *ap)
984263bc 1060{
fef8985e 1061 dev_t dev = ap->a_head.a_dev;
c9faf524 1062 struct rc_chans *rc = &rc_chans[GET_UNIT(dev)];
8d77660e 1063 int error;
984263bc
MD
1064 struct tty *tp = rc->rc_tp;
1065
fef8985e
MD
1066 error = (*linesw[tp->t_line].l_ioctl)(tp, ap->a_cmd, ap->a_data,
1067 ap->a_fflag, ap->a_cred);
984263bc
MD
1068 if (error != ENOIOCTL)
1069 return (error);
fef8985e 1070 error = ttioctl(tp, ap->a_cmd, ap->a_data, ap->a_fflag);
984263bc
MD
1071 disc_optim(tp, &tp->t_termios, rc);
1072 if (error != ENOIOCTL)
1073 return (error);
8d77660e 1074 crit_enter();
984263bc 1075
fef8985e 1076 switch (ap->a_cmd) {
984263bc
MD
1077 case TIOCSBRK:
1078 rc->rc_pendcmd = CD180_C_SBRK;
1079 break;
1080
1081 case TIOCCBRK:
1082 rc->rc_pendcmd = CD180_C_EBRK;
1083 break;
1084
1085 case TIOCSDTR:
1086 (void) rc_modctl(rc, TIOCM_DTR, DMBIS);
1087 break;
1088
1089 case TIOCCDTR:
1090 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
1091 break;
1092
1093 case TIOCMGET:
fef8985e 1094 *(int *) ap->a_data = rc_modctl(rc, 0, DMGET);
984263bc
MD
1095 break;
1096
1097 case TIOCMSET:
fef8985e 1098 (void) rc_modctl(rc, *(int *) ap->a_data, DMSET);
984263bc
MD
1099 break;
1100
1101 case TIOCMBIC:
fef8985e 1102 (void) rc_modctl(rc, *(int *) ap->a_data, DMBIC);
984263bc
MD
1103 break;
1104
1105 case TIOCMBIS:
fef8985e 1106 (void) rc_modctl(rc, *(int *) ap->a_data, DMBIS);
984263bc
MD
1107 break;
1108
1109 case TIOCMSDTRWAIT:
fef8985e 1110 error = suser_cred(ap->a_cred, 0);
984263bc 1111 if (error != 0) {
8d77660e 1112 crit_exit();
984263bc
MD
1113 return (error);
1114 }
fef8985e 1115 rc->rc_dtrwait = *(int *)ap->a_data * hz / 100;
984263bc
MD
1116 break;
1117
1118 case TIOCMGDTRWAIT:
fef8985e 1119 *(int *)ap->a_data = rc->rc_dtrwait * 100 / hz;
984263bc
MD
1120 break;
1121
1122 default:
8d77660e 1123 crit_exit();
984263bc
MD
1124 return ENOTTY;
1125 }
8d77660e 1126 crit_exit();
984263bc
MD
1127 return 0;
1128}
1129
1130
1131/* Modem control routines */
1132
1133static int rc_modctl(rc, bits, cmd)
c9faf524 1134struct rc_chans *rc;
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1135int bits, cmd;
1136{
c9faf524 1137 int nec = rc->rc_rcb->rcb_addr;
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1138 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr;
1139
1140 rcout(CD180_CAR, rc->rc_chan);
1141
1142 switch (cmd) {
1143 case DMSET:
1144 rcout(RC_DTREG, (bits & TIOCM_DTR) ?
1145 ~(*dtr |= 1 << rc->rc_chan) :
1146 ~(*dtr &= ~(1 << rc->rc_chan)));
1147 msvr = rcin(CD180_MSVR);
1148 if (bits & TIOCM_RTS)
1149 msvr |= MSVR_RTS;
1150 else
1151 msvr &= ~MSVR_RTS;
1152 if (bits & TIOCM_DTR)
1153 msvr |= MSVR_DTR;
1154 else
1155 msvr &= ~MSVR_DTR;
1156 rcout(CD180_MSVR, msvr);
1157 break;
1158
1159 case DMBIS:
1160 if (bits & TIOCM_DTR)
1161 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan));
1162 msvr = rcin(CD180_MSVR);
1163 if (bits & TIOCM_RTS)
1164 msvr |= MSVR_RTS;
1165 if (bits & TIOCM_DTR)
1166 msvr |= MSVR_DTR;
1167 rcout(CD180_MSVR, msvr);
1168 break;
1169
1170 case DMGET:
1171 bits = TIOCM_LE;
1172 msvr = rc->rc_msvr = rcin(CD180_MSVR);
1173
1174 if (msvr & MSVR_RTS)
1175 bits |= TIOCM_RTS;
1176 if (msvr & MSVR_CTS)
1177 bits |= TIOCM_CTS;
1178 if (msvr & MSVR_DSR)
1179 bits |= TIOCM_DSR;
1180 if (msvr & MSVR_DTR)
1181 bits |= TIOCM_DTR;
1182 if (msvr & MSVR_CD)
1183 bits |= TIOCM_CD;
1184 if (~rcin(RC_RIREG) & (1 << rc->rc_chan))
1185 bits |= TIOCM_RI;
1186 return bits;
1187
1188 case DMBIC:
1189 if (bits & TIOCM_DTR)
1190 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan)));
1191 msvr = rcin(CD180_MSVR);
1192 if (bits & TIOCM_RTS)
1193 msvr &= ~MSVR_RTS;
1194 if (bits & TIOCM_DTR)
1195 msvr &= ~MSVR_DTR;
1196 rcout(CD180_MSVR, msvr);
1197 break;
1198 }
1199 rc->rc_msvr = rcin(CD180_MSVR);
1200 return 0;
1201}
1202
1203/* Test the board. */
1204int rc_test(nec, unit)
c9faf524 1205 int nec;
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MD
1206 int unit;
1207{
1208 int chan = 0;
8d77660e 1209 int i = 0, rcnt;
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1210 unsigned int iack, chipid;
1211 unsigned short divs;
1212 static u_char ctest[] = "\377\125\252\045\244\0\377";
1213#define CTLEN 8
1214#define ERR(s) { \
1215 printf("rc%d: ", unit); printf s ; printf("\n"); \
8d77660e 1216 crit_exit(); return 1; }
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MD
1217
1218 struct rtest {
1219 u_char txbuf[CD180_NFIFO]; /* TX buffer */
1220 u_char rxbuf[CD180_NFIFO]; /* RX buffer */
1221 int rxptr; /* RX pointer */
1222 int txptr; /* TX pointer */
1223 } tchans[CD180_NCHAN];
1224
8d77660e 1225 crit_enter();
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MD
1226
1227 chipid = RC_FAKEID;
1228
1229 /* First, reset board to inital state */
1230 rc_hwreset(unit, nec, chipid);
1231
1232 divs = RC_BRD(19200);
1233
1234 /* Initialize channels */
1235 for (chan = 0; chan < CD180_NCHAN; chan++) {
1236
1237 /* Select and reset channel */
1238 rcout(CD180_CAR, chan);
1239 CCRCMD(unit, chan, CCR_ResetChan);
1240 WAITFORCCR(unit, chan);
1241
1242 /* Set speed */
1243 rcout(CD180_RBPRL, divs & 0xFF);
1244 rcout(CD180_RBPRH, divs >> 8);
1245 rcout(CD180_TBPRL, divs & 0xFF);
1246 rcout(CD180_TBPRH, divs >> 8);
1247
1248 /* set timeout value */
1249 rcout(CD180_RTPR, 0);
1250
1251 /* Establish local loopback */
1252 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB);
1253 rcout(CD180_COR2, COR2_LLM);
1254 rcout(CD180_COR3, CD180_NFIFO);
1255 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1256 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN);
1257 WAITFORCCR(unit, chan);
1258 rcout(CD180_MSVR, MSVR_RTS);
1259
1260 /* Fill TXBUF with test data */
1261 for (i = 0; i < CD180_NFIFO; i++) {
1262 tchans[chan].txbuf[i] = ctest[i];
1263 tchans[chan].rxbuf[i] = 0;
1264 }
1265 tchans[chan].txptr = tchans[chan].rxptr = 0;
1266
1267 /* Now, start transmit */
1268 rcout(CD180_IER, IER_TxMpty|IER_RxData);
1269 }
1270 /* Pseudo-interrupt poll stuff */
1271 for (rcnt = 10000; rcnt-- > 0; rcnt--) {
1272 i = ~(rcin(RC_BSR));
1273 if (i & RC_BSR_TOUT)
1274 ERR(("BSR timeout bit set\n"))
1275 else if (i & RC_BSR_TXINT) {
1276 iack = rcin(RC_PILR_TX);
1277 if (iack != (GIVR_IT_TDI | chipid))
1278 ERR(("Bad TX intr ack (%02x != %02x)\n",
1279 iack, GIVR_IT_TDI | chipid));
1280 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1281 /* If no more data to transmit, disable TX intr */
1282 if (tchans[chan].txptr >= CD180_NFIFO) {
1283 iack = rcin(CD180_IER);
1284 rcout(CD180_IER, iack & ~IER_TxMpty);
1285 } else {
1286 for (iack = tchans[chan].txptr;
1287 iack < CD180_NFIFO; iack++)
1288 rcout(CD180_TDR,
1289 tchans[chan].txbuf[iack]);
1290 tchans[chan].txptr = iack;
1291 }
1292 rcout(CD180_EOIR, 0);
1293 } else if (i & RC_BSR_RXINT) {
1294 u_char ucnt;
1295
1296 iack = rcin(RC_PILR_RX);
1297 if (iack != (GIVR_IT_RGDI | chipid) &&
1298 iack != (GIVR_IT_REI | chipid))
1299 ERR(("Bad RX intr ack (%02x != %02x)\n",
1300 iack, GIVR_IT_RGDI | chipid))
1301 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1302 ucnt = rcin(CD180_RDCR) & 0xF;
1303 while (ucnt-- > 0) {
1304 iack = rcin(CD180_RCSR);
1305 if (iack & RCSR_Timeout)
1306 break;
1307 if (iack & 0xF)
1308 ERR(("Bad char chan %d (RCSR = %02X)\n",
1309 chan, iack))
1310 if (tchans[chan].rxptr > CD180_NFIFO)
1311 ERR(("Got extra chars chan %d\n",
1312 chan))
1313 tchans[chan].rxbuf[tchans[chan].rxptr++] =
1314 rcin(CD180_RDR);
1315 }
1316 rcout(CD180_EOIR, 0);
1317 }
1318 rcout(RC_CTOUT, 0);
1319 for (iack = chan = 0; chan < CD180_NCHAN; chan++)
1320 if (tchans[chan].rxptr >= CD180_NFIFO)
1321 iack++;
1322 if (iack == CD180_NCHAN)
1323 break;
1324 }
1325 for (chan = 0; chan < CD180_NCHAN; chan++) {
1326 /* Select and reset channel */
1327 rcout(CD180_CAR, chan);
1328 CCRCMD(unit, chan, CCR_ResetChan);
1329 }
1330
1331 if (!rcnt)
1332 ERR(("looses characters during local loopback\n"))
1333 /* Now, check data */
1334 for (chan = 0; chan < CD180_NCHAN; chan++)
1335 for (i = 0; i < CD180_NFIFO; i++)
1336 if (ctest[i] != tchans[chan].rxbuf[i])
1337 ERR(("data mismatch chan %d ptr %d (%d != %d)\n",
1338 chan, i, ctest[i], tchans[chan].rxbuf[i]))
8d77660e 1339 crit_exit();
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MD
1340 return 0;
1341}
1342
1343#ifdef RCDEBUG
1344static void printrcflags(rc, comment)
1345struct rc_chans *rc;
1346char *comment;
1347{
1348 u_short f = rc->rc_flags;
c9faf524 1349 int nec = rc->rc_rcb->rcb_addr;
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1350
1351 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n",
1352 rc->rc_rcb->rcb_unit, rc->rc_chan, comment,
1353 (f & RC_DTR_OFF)?"DTR_OFF " :"",
1354 (f & RC_ACTOUT) ?"ACTOUT " :"",
1355 (f & RC_RTSFLOW)?"RTSFLOW " :"",
1356 (f & RC_CTSFLOW)?"CTSFLOW " :"",
1357 (f & RC_DORXFER)?"DORXFER " :"",
1358 (f & RC_DOXXFER)?"DOXXFER " :"",
1359 (f & RC_MODCHG) ?"MODCHG " :"",
1360 (f & RC_OSUSP) ?"OSUSP " :"",
1361 (f & RC_OSBUSY) ?"OSBUSY " :"",
1362 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"",
1363 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"",
1364 (f & RC_SEND_RDY) ?"SEND_RDY":"");
1365
1366 rcout(CD180_CAR, rc->rc_chan);
1367
1368 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n",
1369 rc->rc_rcb->rcb_unit, rc->rc_chan,
1370 rcin(CD180_MSVR),
1371 rcin(CD180_IER),
1372 rcin(CD180_CCSR));
1373}
1374#endif /* RCDEBUG */
1375
1376static void
1377rc_dtrwakeup(chan)
1378 void *chan;
1379{
1380 struct rc_chans *rc;
1381
1382 rc = (struct rc_chans *)chan;
1383 rc->rc_flags &= ~RC_DTR_OFF;
1384 wakeup(&rc->rc_dtrwait);
1385}
1386
1387static void
1388rc_discard_output(rc)
1389 struct rc_chans *rc;
1390{
7b95be2a 1391 cpu_disable_intr();
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MD
1392 if (rc->rc_flags & RC_DOXXFER) {
1393 rc_scheduled_event -= LOTS_OF_EVENTS;
1394 rc->rc_flags &= ~RC_DOXXFER;
1395 }
1396 rc->rc_optr = rc->rc_obufend;
1397 rc->rc_tp->t_state &= ~TS_BUSY;
7b95be2a 1398 cpu_enable_intr();
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MD
1399 ttwwakeup(rc->rc_tp);
1400}
1401
1402static void
1403rc_wakeup(chan)
1404 void *chan;
1405{
984263bc 1406 if (rc_scheduled_event != 0) {
8d77660e 1407 crit_enter();
477d3c1c 1408 rcpoll(NULL, NULL);
8d77660e 1409 crit_exit();
984263bc 1410 }
7a08a71e 1411 callout_reset(&rc_wakeup_ch, 1, rc_wakeup, NULL);
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MD
1412}
1413
1414static void
1415disc_optim(tp, t, rc)
1416 struct tty *tp;
1417 struct termios *t;
1418 struct rc_chans *rc;
1419{
1420
1421 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
1422 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
1423 && (!(t->c_iflag & PARMRK)
1424 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
1425 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
1426 && linesw[tp->t_line].l_rint == ttyinput)
1427 tp->t_state |= TS_CAN_BYPASS_L_RINT;
1428 else
1429 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
1430 rc->rc_hotchar = linesw[tp->t_line].l_hotchar;
1431}
1432
1433static void
1434rc_wait0(nec, unit, chan, line)
1435 int nec, unit, chan, line;
1436{
1437 int rcnt;
1438
1439 for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--)
1440 DELAY(30);
1441 if (rcnt == 0)
1442 printf("rc%d/%d: channel command timeout, rc.c line: %d\n",
1443 unit, chan, line);
1444}