Add comment for nexus_pcib_write_config.
[dragonfly.git] / sys / bus / pci / pci.c
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1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
0beece56 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.11 2004/01/15 20:35:06 joerg Exp $
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28 *
29 */
30
31#include "opt_bus.h"
32#include "opt_pci.h"
33
34#include "opt_simos.h"
dc5a7bd2 35#include "opt_compat_oldpci.h"
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36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/malloc.h>
40#include <sys/module.h>
41#include <sys/fcntl.h>
42#include <sys/conf.h>
43#include <sys/kernel.h>
44#include <sys/queue.h>
45#include <sys/types.h>
46#include <sys/buf.h>
47
48#include <vm/vm.h>
49#include <vm/pmap.h>
50#include <vm/vm_extern.h>
51
52#include <sys/bus.h>
53#include <machine/bus.h>
54#include <sys/rman.h>
55#include <machine/resource.h>
56#include <machine/md_var.h> /* For the Alpha */
57#ifdef __i386__
bbca97bc 58#include <bus/pci/i386/pci_cfgreg.h>
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59#endif
60
dc5a7bd2 61#include <sys/pciio.h>
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62#include "pcireg.h"
63#include "pcivar.h"
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64
65#ifdef __alpha__
66#include <machine/rpb.h>
67#endif
68
69#ifdef APIC_IO
70#include <machine/smp.h>
71#endif /* APIC_IO */
72
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73static devclass_t pci_devclass;
74
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75static void pci_read_extcap(pcicfgregs *cfg);
76
77struct pci_quirk {
78 u_int32_t devid; /* Vendor/device of the card */
79 int type;
3e4db402 80#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
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81 int arg1;
82 int arg2;
83};
84
85struct pci_quirk pci_quirks[] = {
86 /*
87 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
88 */
89 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
90 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
91
92 { 0 }
93};
94
95/* map register information */
96#define PCI_MAPMEM 0x01 /* memory map */
97#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
98#define PCI_MAPPORT 0x04 /* port map */
99
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100static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
101u_int32_t pci_numdevs = 0;
102static u_int32_t pci_generation = 0;
103
104device_t
105pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func)
106{
107 struct pci_devinfo *dinfo;
108
109 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
110 if ((dinfo->cfg.bus == bus) &&
111 (dinfo->cfg.slot == slot) &&
112 (dinfo->cfg.func == func)) {
113 return (dinfo->cfg.dev);
114 }
115 }
116
117 return (NULL);
118}
119
120device_t
121pci_find_device (u_int16_t vendor, u_int16_t device)
122{
123 struct pci_devinfo *dinfo;
124
125 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
126 if ((dinfo->cfg.vendor == vendor) &&
127 (dinfo->cfg.device == device)) {
128 return (dinfo->cfg.dev);
129 }
130 }
131
132 return (NULL);
133}
134
135/* return base address of memory or port map */
136
137static u_int32_t
138pci_mapbase(unsigned mapreg)
139{
140 int mask = 0x03;
141 if ((mapreg & 0x01) == 0)
142 mask = 0x0f;
143 return (mapreg & ~mask);
144}
145
146/* return map type of memory or port map */
147
148static int
149pci_maptype(unsigned mapreg)
150{
151 static u_int8_t maptype[0x10] = {
152 PCI_MAPMEM, PCI_MAPPORT,
153 PCI_MAPMEM, 0,
154 PCI_MAPMEM, PCI_MAPPORT,
155 0, 0,
156 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
157 PCI_MAPMEM|PCI_MAPMEMP, 0,
158 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
159 0, 0,
160 };
161
162 return maptype[mapreg & 0x0f];
163}
164
165/* return log2 of map size decoded for memory or port map */
166
167static int
168pci_mapsize(unsigned testval)
169{
170 int ln2size;
171
172 testval = pci_mapbase(testval);
173 ln2size = 0;
174 if (testval != 0) {
175 while ((testval & 1) == 0)
176 {
177 ln2size++;
178 testval >>= 1;
179 }
180 }
181 return (ln2size);
182}
183
184/* return log2 of address range supported by map register */
185
186static int
187pci_maprange(unsigned mapreg)
188{
189 int ln2range = 0;
190 switch (mapreg & 0x07) {
191 case 0x00:
192 case 0x01:
193 case 0x05:
194 ln2range = 32;
195 break;
196 case 0x02:
197 ln2range = 20;
198 break;
199 case 0x04:
200 ln2range = 64;
201 break;
202 }
203 return (ln2range);
204}
205
206/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
207
208static void
209pci_fixancient(pcicfgregs *cfg)
210{
211 if (cfg->hdrtype != 0)
212 return;
213
214 /* PCI to PCI bridges use header type 1 */
215 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
216 cfg->hdrtype = 1;
217}
218
219/* read config data specific to header type 1 device (PCI to PCI bridge) */
220
221static void *
222pci_readppb(pcicfgregs *cfg)
223{
224 pcih1cfgregs *p;
225
226 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK);
227 if (p == NULL)
228 return (NULL);
229
230 bzero(p, sizeof *p);
231
232 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_1, 2);
233 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_1, 2);
234
235 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_1, 1);
236
237 p->iobase = PCI_PPBIOBASE (pci_cfgread(cfg, PCIR_IOBASEH_1, 2),
238 pci_cfgread(cfg, PCIR_IOBASEL_1, 1));
239 p->iolimit = PCI_PPBIOLIMIT (pci_cfgread(cfg, PCIR_IOLIMITH_1, 2),
240 pci_cfgread(cfg, PCIR_IOLIMITL_1, 1));
241
242 p->membase = PCI_PPBMEMBASE (0,
243 pci_cfgread(cfg, PCIR_MEMBASE_1, 2));
244 p->memlimit = PCI_PPBMEMLIMIT (0,
245 pci_cfgread(cfg, PCIR_MEMLIMIT_1, 2));
246
247 p->pmembase = PCI_PPBMEMBASE (
248 (pci_addr_t)pci_cfgread(cfg, PCIR_PMBASEH_1, 4),
249 pci_cfgread(cfg, PCIR_PMBASEL_1, 2));
250
251 p->pmemlimit = PCI_PPBMEMLIMIT (
252 (pci_addr_t)pci_cfgread(cfg, PCIR_PMLIMITH_1, 4),
253 pci_cfgread(cfg, PCIR_PMLIMITL_1, 2));
254 return (p);
255}
256
257/* read config data specific to header type 2 device (PCI to CardBus bridge) */
258
259static void *
260pci_readpcb(pcicfgregs *cfg)
261{
262 pcih2cfgregs *p;
263
264 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK);
265 if (p == NULL)
266 return (NULL);
267
268 bzero(p, sizeof *p);
269
270 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_2, 2);
271 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_2, 2);
272
273 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_2, 1);
274
275 p->membase0 = pci_cfgread(cfg, PCIR_MEMBASE0_2, 4);
276 p->memlimit0 = pci_cfgread(cfg, PCIR_MEMLIMIT0_2, 4);
277 p->membase1 = pci_cfgread(cfg, PCIR_MEMBASE1_2, 4);
278 p->memlimit1 = pci_cfgread(cfg, PCIR_MEMLIMIT1_2, 4);
279
280 p->iobase0 = pci_cfgread(cfg, PCIR_IOBASE0_2, 4);
281 p->iolimit0 = pci_cfgread(cfg, PCIR_IOLIMIT0_2, 4);
282 p->iobase1 = pci_cfgread(cfg, PCIR_IOBASE1_2, 4);
283 p->iolimit1 = pci_cfgread(cfg, PCIR_IOLIMIT1_2, 4);
284
285 p->pccardif = pci_cfgread(cfg, PCIR_PCCARDIF_2, 4);
286 return p;
287}
288
289/* extract header type specific config data */
290
291static void
292pci_hdrtypedata(pcicfgregs *cfg)
293{
294 switch (cfg->hdrtype) {
295 case 0:
296 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_0, 2);
297 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_0, 2);
298 cfg->nummaps = PCI_MAXMAPS_0;
299 break;
300 case 1:
301 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_1, 2);
302 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_1, 2);
303 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_1, 1);
304 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_1, 1);
305 cfg->nummaps = PCI_MAXMAPS_1;
306 cfg->hdrspec = pci_readppb(cfg);
307 break;
308 case 2:
309 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_2, 2);
310 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_2, 2);
311 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_2, 1);
312 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_2, 1);
313 cfg->nummaps = PCI_MAXMAPS_2;
314 cfg->hdrspec = pci_readpcb(cfg);
315 break;
316 }
317}
318
319/* read configuration header into pcicfgrect structure */
320
321static struct pci_devinfo *
322pci_readcfg(pcicfgregs *probe)
323{
324#define REG(n, w) pci_cfgread(probe, n, w)
325
326 pcicfgregs *cfg = NULL;
327 struct pci_devinfo *devlist_entry;
328 struct devlist *devlist_head;
329
330 devlist_head = &pci_devq;
331
332 devlist_entry = NULL;
333
334 if (pci_cfgread(probe, PCIR_DEVVENDOR, 4) != -1) {
335
336 devlist_entry = malloc(sizeof(struct pci_devinfo),
337 M_DEVBUF, M_WAITOK);
338 if (devlist_entry == NULL)
339 return (NULL);
340 bzero(devlist_entry, sizeof *devlist_entry);
341
342 cfg = &devlist_entry->cfg;
343
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344 cfg->bus = probe->bus;
345 cfg->slot = probe->slot;
346 cfg->func = probe->func;
347 cfg->vendor = pci_cfgread(cfg, PCIR_VENDOR, 2);
348 cfg->device = pci_cfgread(cfg, PCIR_DEVICE, 2);
349 cfg->cmdreg = pci_cfgread(cfg, PCIR_COMMAND, 2);
350 cfg->statreg = pci_cfgread(cfg, PCIR_STATUS, 2);
351 cfg->baseclass = pci_cfgread(cfg, PCIR_CLASS, 1);
352 cfg->subclass = pci_cfgread(cfg, PCIR_SUBCLASS, 1);
353 cfg->progif = pci_cfgread(cfg, PCIR_PROGIF, 1);
354 cfg->revid = pci_cfgread(cfg, PCIR_REVID, 1);
355 cfg->hdrtype = pci_cfgread(cfg, PCIR_HEADERTYPE, 1);
356 cfg->cachelnsz = pci_cfgread(cfg, PCIR_CACHELNSZ, 1);
357 cfg->lattimer = pci_cfgread(cfg, PCIR_LATTIMER, 1);
358 cfg->intpin = pci_cfgread(cfg, PCIR_INTPIN, 1);
359 cfg->intline = pci_cfgread(cfg, PCIR_INTLINE, 1);
360#ifdef __alpha__
361 alpha_platform_assign_pciintr(cfg);
362#endif
363
364#ifdef APIC_IO
365 if (cfg->intpin != 0) {
366 int airq;
367
368 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
369 if (airq >= 0) {
370 /* PCI specific entry found in MP table */
371 if (airq != cfg->intline) {
372 undirect_pci_irq(cfg->intline);
373 cfg->intline = airq;
374 }
375 } else {
376 /*
377 * PCI interrupts might be redirected to the
378 * ISA bus according to some MP tables. Use the
379 * same methods as used by the ISA devices
380 * devices to find the proper IOAPIC int pin.
381 */
382 airq = isa_apic_irq(cfg->intline);
383 if ((airq >= 0) && (airq != cfg->intline)) {
384 /* XXX: undirect_pci_irq() ? */
385 undirect_isa_irq(cfg->intline);
386 cfg->intline = airq;
387 }
388 }
389 }
390#endif /* APIC_IO */
391
392 cfg->mingnt = pci_cfgread(cfg, PCIR_MINGNT, 1);
393 cfg->maxlat = pci_cfgread(cfg, PCIR_MAXLAT, 1);
394
395 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
396 cfg->hdrtype &= ~PCIM_MFDEV;
397
398 pci_fixancient(cfg);
399 pci_hdrtypedata(cfg);
400
401 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
402 pci_read_extcap(cfg);
403
404 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
405
406 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
407 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
408 devlist_entry->conf.pc_sel.pc_func = cfg->func;
409 devlist_entry->conf.pc_hdr = cfg->hdrtype;
410
411 devlist_entry->conf.pc_subvendor = cfg->subvendor;
412 devlist_entry->conf.pc_subdevice = cfg->subdevice;
413 devlist_entry->conf.pc_vendor = cfg->vendor;
414 devlist_entry->conf.pc_device = cfg->device;
415
416 devlist_entry->conf.pc_class = cfg->baseclass;
417 devlist_entry->conf.pc_subclass = cfg->subclass;
418 devlist_entry->conf.pc_progif = cfg->progif;
419 devlist_entry->conf.pc_revid = cfg->revid;
420
421 pci_numdevs++;
422 pci_generation++;
423 }
424 return (devlist_entry);
425#undef REG
426}
427
428static void
429pci_read_extcap(pcicfgregs *cfg)
430{
431#define REG(n, w) pci_cfgread(cfg, n, w)
432 int ptr, nextptr, ptrptr;
433
434 switch (cfg->hdrtype) {
435 case 0:
436 ptrptr = 0x34;
437 break;
438 case 2:
439 ptrptr = 0x14;
440 break;
441 default:
442 return; /* no extended capabilities support */
443 }
444 nextptr = REG(ptrptr, 1); /* sanity check? */
445
446 /*
447 * Read capability entries.
448 */
449 while (nextptr != 0) {
450 /* Sanity check */
451 if (nextptr > 255) {
452 printf("illegal PCI extended capability offset %d\n",
453 nextptr);
454 return;
455 }
456 /* Find the next entry */
457 ptr = nextptr;
458 nextptr = REG(ptr + 1, 1);
459
460 /* Process this entry */
461 switch (REG(ptr, 1)) {
462 case 0x01: /* PCI power management */
463 if (cfg->pp_cap == 0) {
464 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
465 cfg->pp_status = ptr + PCIR_POWER_STATUS;
466 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
467 if ((nextptr - ptr) > PCIR_POWER_DATA)
468 cfg->pp_data = ptr + PCIR_POWER_DATA;
469 }
470 break;
471 default:
472 break;
473 }
474 }
475#undef REG
476}
477
478#if 0
479/* free pcicfgregs structure and all depending data structures */
480
481static int
482pci_freecfg(struct pci_devinfo *dinfo)
483{
484 struct devlist *devlist_head;
485
486 devlist_head = &pci_devq;
487
488 if (dinfo->cfg.hdrspec != NULL)
489 free(dinfo->cfg.hdrspec, M_DEVBUF);
490 if (dinfo->cfg.map != NULL)
491 free(dinfo->cfg.map, M_DEVBUF);
492 /* XXX this hasn't been tested */
493 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
494 free(dinfo, M_DEVBUF);
495
496 /* increment the generation count */
497 pci_generation++;
498
499 /* we're losing one device */
500 pci_numdevs--;
501 return (0);
502}
503#endif
504
505
506/*
507 * PCI power manangement
508 */
509static int
510pci_set_powerstate_method(device_t dev, device_t child, int state)
511{
512 struct pci_devinfo *dinfo = device_get_ivars(child);
513 pcicfgregs *cfg = &dinfo->cfg;
514 u_int16_t status;
515 int result;
516
517 if (cfg->pp_cap != 0) {
518 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK;
519 result = 0;
520 switch (state) {
521 case PCI_POWERSTATE_D0:
522 status |= PCIM_PSTAT_D0;
523 break;
524 case PCI_POWERSTATE_D1:
525 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) {
526 status |= PCIM_PSTAT_D1;
527 } else {
528 result = EOPNOTSUPP;
529 }
530 break;
531 case PCI_POWERSTATE_D2:
532 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) {
533 status |= PCIM_PSTAT_D2;
534 } else {
535 result = EOPNOTSUPP;
536 }
537 break;
538 case PCI_POWERSTATE_D3:
539 status |= PCIM_PSTAT_D3;
540 break;
541 default:
542 result = EINVAL;
543 }
544 if (result == 0)
545 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2);
546 } else {
547 result = ENXIO;
548 }
549 return(result);
550}
551
552static int
553pci_get_powerstate_method(device_t dev, device_t child)
554{
555 struct pci_devinfo *dinfo = device_get_ivars(child);
556 pcicfgregs *cfg = &dinfo->cfg;
557 u_int16_t status;
558 int result;
559
560 if (cfg->pp_cap != 0) {
561 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2);
562 switch (status & PCIM_PSTAT_DMASK) {
563 case PCIM_PSTAT_D0:
564 result = PCI_POWERSTATE_D0;
565 break;
566 case PCIM_PSTAT_D1:
567 result = PCI_POWERSTATE_D1;
568 break;
569 case PCIM_PSTAT_D2:
570 result = PCI_POWERSTATE_D2;
571 break;
572 case PCIM_PSTAT_D3:
573 result = PCI_POWERSTATE_D3;
574 break;
575 default:
576 result = PCI_POWERSTATE_UNKNOWN;
577 break;
578 }
579 } else {
580 /* No support, device is always at D0 */
581 result = PCI_POWERSTATE_D0;
582 }
583 return(result);
584}
585
586/*
587 * Some convenience functions for PCI device drivers.
588 */
589
590static __inline void
591pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
592{
593 u_int16_t command;
594
595 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
596 command |= bit;
597 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
598}
599
600static __inline void
601pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
602{
603 u_int16_t command;
604
605 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
606 command &= ~bit;
607 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
608}
609
610static void
611pci_enable_busmaster_method(device_t dev, device_t child)
612{
613 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
614}
615
616static void
617pci_disable_busmaster_method(device_t dev, device_t child)
618{
619 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
620}
621
622static void
623pci_enable_io_method(device_t dev, device_t child, int space)
624{
625 switch(space) {
626 case SYS_RES_IOPORT:
627 pci_set_command_bit(dev, child, PCIM_CMD_PORTEN);
628 break;
629 case SYS_RES_MEMORY:
630 pci_set_command_bit(dev, child, PCIM_CMD_MEMEN);
631 break;
632 }
633}
634
635static void
636pci_disable_io_method(device_t dev, device_t child, int space)
637{
638 switch(space) {
639 case SYS_RES_IOPORT:
640 pci_clear_command_bit(dev, child, PCIM_CMD_PORTEN);
641 break;
642 case SYS_RES_MEMORY:
643 pci_clear_command_bit(dev, child, PCIM_CMD_MEMEN);
644 break;
645 }
646}
647
648/*
649 * This is the user interface to PCI configuration space.
650 */
651
652static int
41c20dac 653pci_open(dev_t dev, int oflags, int devtype, struct thread *td)
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654{
655 if ((oflags & FWRITE) && securelevel > 0) {
656 return EPERM;
657 }
658 return 0;
659}
660
661static int
41c20dac 662pci_close(dev_t dev, int flag, int devtype, struct thread *td)
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663{
664 return 0;
665}
666
667/*
668 * Match a single pci_conf structure against an array of pci_match_conf
669 * structures. The first argument, 'matches', is an array of num_matches
670 * pci_match_conf structures. match_buf is a pointer to the pci_conf
671 * structure that will be compared to every entry in the matches array.
672 * This function returns 1 on failure, 0 on success.
673 */
674static int
675pci_conf_match(struct pci_match_conf *matches, int num_matches,
676 struct pci_conf *match_buf)
677{
678 int i;
679
680 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
681 return(1);
682
683 for (i = 0; i < num_matches; i++) {
684 /*
685 * I'm not sure why someone would do this...but...
686 */
687 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
688 continue;
689
690 /*
691 * Look at each of the match flags. If it's set, do the
692 * comparison. If the comparison fails, we don't have a
693 * match, go on to the next item if there is one.
694 */
695 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
696 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
697 continue;
698
699 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
700 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
701 continue;
702
703 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
704 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
705 continue;
706
707 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
708 && (match_buf->pc_vendor != matches[i].pc_vendor))
709 continue;
710
711 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
712 && (match_buf->pc_device != matches[i].pc_device))
713 continue;
714
715 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
716 && (match_buf->pc_class != matches[i].pc_class))
717 continue;
718
719 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
720 && (match_buf->pd_unit != matches[i].pd_unit))
721 continue;
722
723 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
724 && (strncmp(matches[i].pd_name, match_buf->pd_name,
725 sizeof(match_buf->pd_name)) != 0))
726 continue;
727
728 return(0);
729 }
730
731 return(1);
732}
733
734/*
735 * Locate the parent of a PCI device by scanning the PCI devlist
736 * and return the entry for the parent.
737 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
738 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
739 */
740
741pcicfgregs *
742pci_devlist_get_parent(pcicfgregs *cfg)
743{
744 struct devlist *devlist_head;
745 struct pci_devinfo *dinfo;
746 pcicfgregs *bridge_cfg;
747 int i;
748
749 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
750
751 /* If the device is on PCI bus 0, look for the host */
752 if (cfg->bus == 0) {
753 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
754 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
755 bridge_cfg = &dinfo->cfg;
756 if (bridge_cfg->baseclass == PCIC_BRIDGE
757 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
758 && bridge_cfg->bus == cfg->bus) {
759 return bridge_cfg;
760 }
761 }
762 }
763
764 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
765 if (cfg->bus > 0) {
766 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
767 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
768 bridge_cfg = &dinfo->cfg;
769 if (bridge_cfg->baseclass == PCIC_BRIDGE
770 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
771 && bridge_cfg->secondarybus == cfg->bus) {
772 return bridge_cfg;
773 }
774 }
775 }
776
777 return NULL;
778}
779
780static int
41c20dac 781pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td)
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782{
783 struct pci_io *io;
784 const char *name;
785 int error;
786
787 if (!(flag & FWRITE))
788 return EPERM;
789
790
791 switch(cmd) {
792 case PCIOCGETCONF:
793 {
794 struct pci_devinfo *dinfo;
795 struct pci_conf_io *cio;
796 struct devlist *devlist_head;
797 struct pci_match_conf *pattern_buf;
798 int num_patterns;
799 size_t iolen;
800 int ionum, i;
801
802 cio = (struct pci_conf_io *)data;
803
804 num_patterns = 0;
805 dinfo = NULL;
806
807 /*
808 * Hopefully the user won't pass in a null pointer, but it
809 * can't hurt to check.
810 */
811 if (cio == NULL) {
812 error = EINVAL;
813 break;
814 }
815
816 /*
817 * If the user specified an offset into the device list,
818 * but the list has changed since they last called this
819 * ioctl, tell them that the list has changed. They will
820 * have to get the list from the beginning.
821 */
822 if ((cio->offset != 0)
823 && (cio->generation != pci_generation)){
824 cio->num_matches = 0;
825 cio->status = PCI_GETCONF_LIST_CHANGED;
826 error = 0;
827 break;
828 }
829
830 /*
831 * Check to see whether the user has asked for an offset
832 * past the end of our list.
833 */
834 if (cio->offset >= pci_numdevs) {
835 cio->num_matches = 0;
836 cio->status = PCI_GETCONF_LAST_DEVICE;
837 error = 0;
838 break;
839 }
840
841 /* get the head of the device queue */
842 devlist_head = &pci_devq;
843
844 /*
845 * Determine how much room we have for pci_conf structures.
846 * Round the user's buffer size down to the nearest
847 * multiple of sizeof(struct pci_conf) in case the user
848 * didn't specify a multiple of that size.
849 */
850 iolen = min(cio->match_buf_len -
851 (cio->match_buf_len % sizeof(struct pci_conf)),
852 pci_numdevs * sizeof(struct pci_conf));
853
854 /*
855 * Since we know that iolen is a multiple of the size of
856 * the pciconf union, it's okay to do this.
857 */
858 ionum = iolen / sizeof(struct pci_conf);
859
860 /*
861 * If this test is true, the user wants the pci_conf
862 * structures returned to match the supplied entries.
863 */
864 if ((cio->num_patterns > 0)
865 && (cio->pat_buf_len > 0)) {
866 /*
867 * pat_buf_len needs to be:
868 * num_patterns * sizeof(struct pci_match_conf)
869 * While it is certainly possible the user just
870 * allocated a large buffer, but set the number of
871 * matches correctly, it is far more likely that
872 * their kernel doesn't match the userland utility
873 * they're using. It's also possible that the user
874 * forgot to initialize some variables. Yes, this
875 * may be overly picky, but I hazard to guess that
876 * it's far more likely to just catch folks that
877 * updated their kernel but not their userland.
878 */
879 if ((cio->num_patterns *
880 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
881 /* The user made a mistake, return an error*/
882 cio->status = PCI_GETCONF_ERROR;
883 printf("pci_ioctl: pat_buf_len %d != "
884 "num_patterns (%d) * sizeof(struct "
885 "pci_match_conf) (%d)\npci_ioctl: "
886 "pat_buf_len should be = %d\n",
887 cio->pat_buf_len, cio->num_patterns,
888 (int)sizeof(struct pci_match_conf),
889 (int)sizeof(struct pci_match_conf) *
890 cio->num_patterns);
891 printf("pci_ioctl: do your headers match your "
892 "kernel?\n");
893 cio->num_matches = 0;
894 error = EINVAL;
895 break;
896 }
897
898 /*
899 * Check the user's buffer to make sure it's readable.
900 */
901 if (!useracc((caddr_t)cio->patterns,
902 cio->pat_buf_len, VM_PROT_READ)) {
903 printf("pci_ioctl: pattern buffer %p, "
904 "length %u isn't user accessible for"
905 " READ\n", cio->patterns,
906 cio->pat_buf_len);
907 error = EACCES;
908 break;
909 }
910 /*
911 * Allocate a buffer to hold the patterns.
912 */
913 pattern_buf = malloc(cio->pat_buf_len, M_TEMP,
914 M_WAITOK);
915 error = copyin(cio->patterns, pattern_buf,
916 cio->pat_buf_len);
917 if (error != 0)
918 break;
919 num_patterns = cio->num_patterns;
920
921 } else if ((cio->num_patterns > 0)
922 || (cio->pat_buf_len > 0)) {
923 /*
924 * The user made a mistake, spit out an error.
925 */
926 cio->status = PCI_GETCONF_ERROR;
927 cio->num_matches = 0;
928 printf("pci_ioctl: invalid GETCONF arguments\n");
929 error = EINVAL;
930 break;
931 } else
932 pattern_buf = NULL;
933
934 /*
935 * Make sure we can write to the match buffer.
936 */
937 if (!useracc((caddr_t)cio->matches,
938 cio->match_buf_len, VM_PROT_WRITE)) {
939 printf("pci_ioctl: match buffer %p, length %u "
940 "isn't user accessible for WRITE\n",
941 cio->matches, cio->match_buf_len);
942 error = EACCES;
943 break;
944 }
945
946 /*
947 * Go through the list of devices and copy out the devices
948 * that match the user's criteria.
949 */
950 for (cio->num_matches = 0, error = 0, i = 0,
951 dinfo = STAILQ_FIRST(devlist_head);
952 (dinfo != NULL) && (cio->num_matches < ionum)
953 && (error == 0) && (i < pci_numdevs);
954 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
955
956 if (i < cio->offset)
957 continue;
958
959 /* Populate pd_name and pd_unit */
960 name = NULL;
961 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
962 name = device_get_name(dinfo->cfg.dev);
963 if (name) {
964 strncpy(dinfo->conf.pd_name, name,
965 sizeof(dinfo->conf.pd_name));
966 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
967 dinfo->conf.pd_unit =
968 device_get_unit(dinfo->cfg.dev);
969 }
970
971 if ((pattern_buf == NULL) ||
972 (pci_conf_match(pattern_buf, num_patterns,
973 &dinfo->conf) == 0)) {
974
975 /*
976 * If we've filled up the user's buffer,
977 * break out at this point. Since we've
978 * got a match here, we'll pick right back
979 * up at the matching entry. We can also
980 * tell the user that there are more matches
981 * left.
982 */
983 if (cio->num_matches >= ionum)
984 break;
985
986 error = copyout(&dinfo->conf,
987 &cio->matches[cio->num_matches],
988 sizeof(struct pci_conf));
989 cio->num_matches++;
990 }
991 }
992
993 /*
994 * Set the pointer into the list, so if the user is getting
995 * n records at a time, where n < pci_numdevs,
996 */
997 cio->offset = i;
998
999 /*
1000 * Set the generation, the user will need this if they make
1001 * another ioctl call with offset != 0.
1002 */
1003 cio->generation = pci_generation;
1004
1005 /*
1006 * If this is the last device, inform the user so he won't
1007 * bother asking for more devices. If dinfo isn't NULL, we
1008 * know that there are more matches in the list because of
1009 * the way the traversal is done.
1010 */
1011 if (dinfo == NULL)
1012 cio->status = PCI_GETCONF_LAST_DEVICE;
1013 else
1014 cio->status = PCI_GETCONF_MORE_DEVS;
1015
1016 if (pattern_buf != NULL)
1017 free(pattern_buf, M_TEMP);
1018
1019 break;
1020 }
1021 case PCIOCREAD:
1022 io = (struct pci_io *)data;
1023 switch(io->pi_width) {
1024 pcicfgregs probe;
1025 case 4:
1026 case 2:
1027 case 1:
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1028 probe.bus = io->pi_sel.pc_bus;
1029 probe.slot = io->pi_sel.pc_dev;
1030 probe.func = io->pi_sel.pc_func;
1031 io->pi_data = pci_cfgread(&probe,
1032 io->pi_reg, io->pi_width);
1033 error = 0;
1034 break;
1035 default:
1036 error = ENODEV;
1037 break;
1038 }
1039 break;
1040
1041 case PCIOCWRITE:
1042 io = (struct pci_io *)data;
1043 switch(io->pi_width) {
1044 pcicfgregs probe;
1045 case 4:
1046 case 2:
1047 case 1:
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MD
1048 probe.bus = io->pi_sel.pc_bus;
1049 probe.slot = io->pi_sel.pc_dev;
1050 probe.func = io->pi_sel.pc_func;
1051 pci_cfgwrite(&probe,
1052 io->pi_reg, io->pi_data, io->pi_width);
1053 error = 0;
1054 break;
1055 default:
1056 error = ENODEV;
1057 break;
1058 }
1059 break;
1060
1061 default:
1062 error = ENOTTY;
1063 break;
1064 }
1065
1066 return (error);
1067}
1068
1069#define PCI_CDEV 78
1070
1071static struct cdevsw pcicdev = {
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MD
1072 /* name */ "pci",
1073 /* maj */ PCI_CDEV,
1074 /* flags */ 0,
1075 /* port */ NULL,
1076 /* autoq */ 0,
1077
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MD
1078 /* open */ pci_open,
1079 /* close */ pci_close,
1080 /* read */ noread,
1081 /* write */ nowrite,
1082 /* ioctl */ pci_ioctl,
1083 /* poll */ nopoll,
1084 /* mmap */ nommap,
1085 /* strategy */ nostrategy,
984263bc 1086 /* dump */ nodump,
fabb8ceb 1087 /* psize */ nopsize
984263bc
MD
1088};
1089
1090#include "pci_if.h"
1091
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1092/*
1093 * New style pci driver. Parent device is either a pci-host-bridge or a
1094 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1095 */
1096
1097static void
1098pci_print_verbose(struct pci_devinfo *dinfo)
1099{
1100 if (bootverbose) {
1101 pcicfgregs *cfg = &dinfo->cfg;
1102
1103 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
1104 cfg->vendor, cfg->device, cfg->revid);
1105 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
1106 cfg->baseclass, cfg->subclass, cfg->progif,
1107 cfg->hdrtype, cfg->mfdev);
1108 printf("\tsubordinatebus=%x \tsecondarybus=%x\n",
1109 cfg->subordinatebus, cfg->secondarybus);
1110#ifdef PCI_DEBUG
1111 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
1112 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
1113 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
1114 cfg->lattimer, cfg->lattimer * 30,
1115 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1116#endif /* PCI_DEBUG */
1117 if (cfg->intpin > 0)
1118 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
1119 }
1120}
1121
1122static int
1123pci_porten(pcicfgregs *cfg)
1124{
1125 return ((cfg->cmdreg & PCIM_CMD_PORTEN) != 0);
1126}
1127
1128static int
1129pci_memen(pcicfgregs *cfg)
1130{
1131 return ((cfg->cmdreg & PCIM_CMD_MEMEN) != 0);
1132}
1133
1134/*
1135 * Add a resource based on a pci map register. Return 1 if the map
1136 * register is a 32bit map register or 2 if it is a 64bit register.
1137 */
1138static int
1139pci_add_map(device_t dev, pcicfgregs* cfg, int reg)
1140{
1141 struct pci_devinfo *dinfo = device_get_ivars(dev);
1142 struct resource_list *rl = &dinfo->resources;
1143 u_int32_t map;
1144 u_int64_t base;
1145 u_int8_t ln2size;
1146 u_int8_t ln2range;
1147 u_int32_t testval;
1148
1149 int type;
1150
1151 map = pci_cfgread(cfg, reg, 4);
1152
1153 if (map == 0 || map == 0xffffffff)
1154 return 1; /* skip invalid entry */
1155
1156 pci_cfgwrite(cfg, reg, 0xffffffff, 4);
1157 testval = pci_cfgread(cfg, reg, 4);
1158 pci_cfgwrite(cfg, reg, map, 4);
1159
1160 base = pci_mapbase(map);
1161 if (pci_maptype(map) & PCI_MAPMEM)
1162 type = SYS_RES_MEMORY;
1163 else
1164 type = SYS_RES_IOPORT;
1165 ln2size = pci_mapsize(testval);
1166 ln2range = pci_maprange(testval);
1167 if (ln2range == 64) {
1168 /* Read the other half of a 64bit map register */
1169 base |= (u_int64_t) pci_cfgread(cfg, reg + 4, 4) << 32;
1170 }
1171
1172#ifdef __alpha__
1173 /*
1174 * XXX: encode hose number in the base addr,
1175 * This will go away once the bus_space functions
1176 * can deal with multiple hoses
1177 */
1178
1179 if (cfg->hose) {
1180 u_int32_t mask, shift, maxh;
1181
1182 switch (hwrpb->rpb_type) {
1183 case ST_DEC_4100:
1184 case -ST_DEC_4100:
1185 mask = 0xc0000000;
1186 shift = 30;
1187 maxh = 4; /* not a hose. MCPCIA instance # */
1188 break;
1189 case ST_DEC_21000:
1190 mask = 0xf8000000;
1191 shift = 27;
1192 maxh = 32;
1193 break;
1194 case ST_DEC_6600:
1195 mask = 0x80000000;
1196 shift = 31;
1197 maxh = 2;
1198 break;
1199 default:
1200 mask = 0;
1201 shift = 0;
1202 maxh = 0;
1203 break;
1204 }
1205 if (base & mask) {
1206 printf("base addr = 0x%llx\n", (long long) base);
1207 printf("mask addr = 0x%lx\n", (long) mask);
1208 printf("hacked addr = 0x%llx\n", (long long)
1209 (base | ((u_int64_t)cfg->hose << shift)));
1210 panic("hose encoding hack would clobber base addr");
1211 /* NOTREACHED */
1212 }
1213 if (cfg->hose >= maxh) {
1214 panic("Hose %d - can only encode %d hose(s)",
1215 cfg->hose, maxh);
1216 /* NOTREACHED */
1217 }
1218 base |= ((u_int64_t)cfg->hose << shift);
1219 }
1220#endif
1221
1222 /*
1223 * This code theoretically does the right thing, but has
1224 * undesirable side effects in some cases where
1225 * peripherals respond oddly to having these bits
1226 * enabled. Leave them alone by default.
1227 */
1228#ifdef PCI_ENABLE_IO_MODES
1229 if (type == SYS_RES_IOPORT && !pci_porten(cfg)) {
1230 cfg->cmdreg |= PCIM_CMD_PORTEN;
1231 pci_cfgwrite(cfg, PCIR_COMMAND, cfg->cmdreg, 2);
1232 }
1233 if (type == SYS_RES_MEMORY && !pci_memen(cfg)) {
1234 cfg->cmdreg |= PCIM_CMD_MEMEN;
1235 pci_cfgwrite(cfg, PCIR_COMMAND, cfg->cmdreg, 2);
1236 }
1237#else
1238 if (type == SYS_RES_IOPORT && !pci_porten(cfg))
1239 return 1;
1240 if (type == SYS_RES_MEMORY && !pci_memen(cfg))
1241 return 1;
1242#endif
1243
1244 resource_list_add(rl, type, reg,
1245 base, base + (1 << ln2size) - 1,
1246 (1 << ln2size));
1247
1248 if (bootverbose) {
1249 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
1250 reg, pci_maptype(base), ln2range,
1251 (unsigned int) base, ln2size);
1252 }
1253
1254 return (ln2range == 64) ? 2 : 1;
1255}
1256
1257static void
1258pci_add_resources(device_t dev, pcicfgregs* cfg)
1259{
1260 struct pci_devinfo *dinfo = device_get_ivars(dev);
1261 struct resource_list *rl = &dinfo->resources;
1262 struct pci_quirk *q;
1263 int i;
1264
1265 for (i = 0; i < cfg->nummaps;) {
1266 i += pci_add_map(dev, cfg, PCIR_MAPS + i*4);
1267 }
1268
1269 for (q = &pci_quirks[0]; q->devid; q++) {
1270 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1271 && q->type == PCI_QUIRK_MAP_REG)
1272 pci_add_map(dev, cfg, q->arg1);
1273 }
1274
1275 if (cfg->intpin > 0 && cfg->intline != 255)
1276 resource_list_add(rl, SYS_RES_IRQ, 0,
1277 cfg->intline, cfg->intline, 1);
1278}
1279
1280static void
1281pci_add_children(device_t dev, int busno)
1282{
1283 pcicfgregs probe;
1284
1285#ifdef SIMOS
1286#undef PCI_SLOTMAX
1287#define PCI_SLOTMAX 0
1288#endif
1289
1290 bzero(&probe, sizeof probe);
984263bc
MD
1291 probe.bus = busno;
1292
1293 for (probe.slot = 0; probe.slot <= PCI_SLOTMAX; probe.slot++) {
1294 int pcifunchigh = 0;
1295 for (probe.func = 0; probe.func <= pcifunchigh; probe.func++) {
1296 struct pci_devinfo *dinfo = pci_readcfg(&probe);
1297 if (dinfo != NULL) {
1298 if (dinfo->cfg.mfdev)
1299 pcifunchigh = 7;
1300
1301 pci_print_verbose(dinfo);
1302 dinfo->cfg.dev = device_add_child(dev, NULL, -1);
1303 device_set_ivars(dinfo->cfg.dev, dinfo);
1304 pci_add_resources(dinfo->cfg.dev, &dinfo->cfg);
1305 }
1306 }
1307 }
1308}
1309
1310static int
1311pci_new_probe(device_t dev)
1312{
1313 static int once;
1314
1315 device_set_desc(dev, "PCI bus");
1316 pci_add_children(dev, device_get_unit(dev));
1317 if (!once) {
1318 make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci");
1319 once++;
1320 }
1321
1322 return 0;
1323}
1324
1325static int
1326pci_print_resources(struct resource_list *rl, const char *name, int type,
1327 const char *format)
1328{
1329 struct resource_list_entry *rle;
1330 int printed, retval;
1331
1332 printed = 0;
1333 retval = 0;
1334 /* Yes, this is kinda cheating */
1335 SLIST_FOREACH(rle, rl, link) {
1336 if (rle->type == type) {
1337 if (printed == 0)
1338 retval += printf(" %s ", name);
1339 else if (printed > 0)
1340 retval += printf(",");
1341 printed++;
1342 retval += printf(format, rle->start);
1343 if (rle->count > 1) {
1344 retval += printf("-");
1345 retval += printf(format, rle->start +
1346 rle->count - 1);
1347 }
1348 }
1349 }
1350 return retval;
1351}
1352
1353static int
1354pci_print_child(device_t dev, device_t child)
1355{
1356 struct pci_devinfo *dinfo;
1357 struct resource_list *rl;
1358 pcicfgregs *cfg;
1359 int retval = 0;
1360
1361 dinfo = device_get_ivars(child);
1362 cfg = &dinfo->cfg;
1363 rl = &dinfo->resources;
1364
1365 retval += bus_print_child_header(dev, child);
1366
1367 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1368 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1369 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1370 if (device_get_flags(dev))
1371 retval += printf(" flags %#x", device_get_flags(dev));
1372
1373 retval += printf(" at device %d.%d", pci_get_slot(child),
1374 pci_get_function(child));
1375
1376 retval += bus_print_child_footer(dev, child);
1377
1378 return (retval);
1379}
1380
1381static void
1382pci_probe_nomatch(device_t dev, device_t child)
1383{
1384 struct pci_devinfo *dinfo;
1385 pcicfgregs *cfg;
1386 const char *desc;
1387 int unknown;
1388
1389 unknown = 0;
1390 dinfo = device_get_ivars(child);
1391 cfg = &dinfo->cfg;
1392 desc = pci_ata_match(child);
1393 if (!desc) desc = pci_usb_match(child);
1394 if (!desc) desc = pci_vga_match(child);
27c23c6b 1395 if (!desc) desc = pci_chip_match(child);
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1396 if (!desc) {
1397 desc = "unknown card";
1398 unknown++;
1399 }
1400 device_printf(dev, "<%s>", desc);
1401 if (bootverbose || unknown) {
1402 printf(" (vendor=0x%04x, dev=0x%04x)",
1403 cfg->vendor,
1404 cfg->device);
1405 }
1406 printf(" at %d.%d",
1407 pci_get_slot(child),
1408 pci_get_function(child));
1409 if (cfg->intpin > 0 && cfg->intline != 255) {
1410 printf(" irq %d", cfg->intline);
1411 }
1412 printf("\n");
1413
1414 return;
1415}
1416
1417static int
1418pci_read_ivar(device_t dev, device_t child, int which, u_long *result)
1419{
1420 struct pci_devinfo *dinfo;
1421 pcicfgregs *cfg;
1422
1423 dinfo = device_get_ivars(child);
1424 cfg = &dinfo->cfg;
1425
1426 switch (which) {
1427 case PCI_IVAR_SUBVENDOR:
1428 *result = cfg->subvendor;
1429 break;
1430 case PCI_IVAR_SUBDEVICE:
1431 *result = cfg->subdevice;
1432 break;
1433 case PCI_IVAR_VENDOR:
1434 *result = cfg->vendor;
1435 break;
1436 case PCI_IVAR_DEVICE:
1437 *result = cfg->device;
1438 break;
1439 case PCI_IVAR_DEVID:
1440 *result = (cfg->device << 16) | cfg->vendor;
1441 break;
1442 case PCI_IVAR_CLASS:
1443 *result = cfg->baseclass;
1444 break;
1445 case PCI_IVAR_SUBCLASS:
1446 *result = cfg->subclass;
1447 break;
1448 case PCI_IVAR_PROGIF:
1449 *result = cfg->progif;
1450 break;
1451 case PCI_IVAR_REVID:
1452 *result = cfg->revid;
1453 break;
1454 case PCI_IVAR_INTPIN:
1455 *result = cfg->intpin;
1456 break;
1457 case PCI_IVAR_IRQ:
1458 *result = cfg->intline;
1459 break;
1460 case PCI_IVAR_BUS:
1461 *result = cfg->bus;
1462 break;
1463 case PCI_IVAR_SLOT:
1464 *result = cfg->slot;
1465 break;
1466 case PCI_IVAR_FUNCTION:
1467 *result = cfg->func;
1468 break;
1469 case PCI_IVAR_SECONDARYBUS:
1470 *result = cfg->secondarybus;
1471 break;
1472 case PCI_IVAR_SUBORDINATEBUS:
1473 *result = cfg->subordinatebus;
1474 break;
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1475 default:
1476 return ENOENT;
1477 }
1478 return 0;
1479}
1480
1481static int
1482pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1483{
1484 struct pci_devinfo *dinfo;
1485 pcicfgregs *cfg;
1486
1487 dinfo = device_get_ivars(child);
1488 cfg = &dinfo->cfg;
1489
1490 switch (which) {
1491 case PCI_IVAR_SUBVENDOR:
1492 case PCI_IVAR_SUBDEVICE:
1493 case PCI_IVAR_VENDOR:
1494 case PCI_IVAR_DEVICE:
1495 case PCI_IVAR_DEVID:
1496 case PCI_IVAR_CLASS:
1497 case PCI_IVAR_SUBCLASS:
1498 case PCI_IVAR_PROGIF:
1499 case PCI_IVAR_REVID:
1500 case PCI_IVAR_INTPIN:
1501 case PCI_IVAR_IRQ:
1502 case PCI_IVAR_BUS:
1503 case PCI_IVAR_SLOT:
1504 case PCI_IVAR_FUNCTION:
1505 return EINVAL; /* disallow for now */
1506
1507 case PCI_IVAR_SECONDARYBUS:
1508 cfg->secondarybus = value;
1509 break;
1510 case PCI_IVAR_SUBORDINATEBUS:
1511 cfg->subordinatebus = value;
1512 break;
1513 default:
1514 return ENOENT;
1515 }
1516 return 0;
1517}
1518
1519static struct resource *
1520pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1521 u_long start, u_long end, u_long count, u_int flags)
1522{
1523 struct pci_devinfo *dinfo = device_get_ivars(child);
1524 struct resource_list *rl = &dinfo->resources;
1525
1526#ifdef __i386__ /* Only supported on x86 in stable */
1527 pcicfgregs *cfg = &dinfo->cfg;
1528 /*
1529 * Perform lazy resource allocation
1530 *
1531 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY
1532 */
1533 if (device_get_parent(child) == dev) {
1534 /*
1535 * If device doesn't have an interrupt routed, and is
1536 * deserving of an interrupt, try to assign it one.
1537 */
1538 if ((type == SYS_RES_IRQ) &&
1539 (cfg->intline == 255 || cfg->intline == 0) &&
1540 (cfg->intpin != 0) && (start == 0) && (end == ~0UL)) {
1541 cfg->intline = pci_cfgintr(pci_get_bus(child),
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1542 pci_get_slot(child), cfg->intpin,
1543 pci_get_irq(child));
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1544 if (cfg->intline != 255) {
1545 pci_write_config(child, PCIR_INTLINE,
1546 cfg->intline, 1);
1547 resource_list_add(rl, SYS_RES_IRQ, 0,
1548 cfg->intline, cfg->intline, 1);
1549 }
1550 }
1551 }
1552#endif
1553 return resource_list_alloc(rl, dev, child, type, rid,
1554 start, end, count, flags);
1555}
1556
1557static int
1558pci_release_resource(device_t dev, device_t child, int type, int rid,
1559 struct resource *r)
1560{
1561 struct pci_devinfo *dinfo = device_get_ivars(child);
1562 struct resource_list *rl = &dinfo->resources;
1563
1564 return resource_list_release(rl, dev, child, type, rid, r);
1565}
1566
1567static int
1568pci_set_resource(device_t dev, device_t child, int type, int rid,
1569 u_long start, u_long count)
1570{
1571 struct pci_devinfo *dinfo = device_get_ivars(child);
1572 struct resource_list *rl = &dinfo->resources;
1573
1574 resource_list_add(rl, type, rid, start, start + count - 1, count);
1575 return 0;
1576}
1577
1578static int
1579pci_get_resource(device_t dev, device_t child, int type, int rid,
1580 u_long *startp, u_long *countp)
1581{
1582 struct pci_devinfo *dinfo = device_get_ivars(child);
1583 struct resource_list *rl = &dinfo->resources;
1584 struct resource_list_entry *rle;
1585
1586 rle = resource_list_find(rl, type, rid);
1587 if (!rle)
1588 return ENOENT;
1589
1590 if (startp)
1591 *startp = rle->start;
1592 if (countp)
1593 *countp = rle->count;
1594
1595 return 0;
1596}
1597
1598static void
1599pci_delete_resource(device_t dev, device_t child, int type, int rid)
1600{
1601 printf("pci_delete_resource: PCI resources can not be deleted\n");
1602}
1603
1604static u_int32_t
1605pci_read_config_method(device_t dev, device_t child, int reg, int width)
1606{
1607 struct pci_devinfo *dinfo = device_get_ivars(child);
1608 pcicfgregs *cfg = &dinfo->cfg;
1609 return pci_cfgread(cfg, reg, width);
1610}
1611
1612static void
1613pci_write_config_method(device_t dev, device_t child, int reg,
1614 u_int32_t val, int width)
1615{
1616 struct pci_devinfo *dinfo = device_get_ivars(child);
1617 pcicfgregs *cfg = &dinfo->cfg;
1618 pci_cfgwrite(cfg, reg, val, width);
1619}
1620
1621static int
1622pci_modevent(module_t mod, int what, void *arg)
1623{
1624 switch (what) {
1625 case MOD_LOAD:
1626 STAILQ_INIT(&pci_devq);
1627 break;
1628
1629 case MOD_UNLOAD:
1630 break;
1631 }
1632
1633 return 0;
1634}
1635
1636static device_method_t pci_methods[] = {
1637 /* Device interface */
1638 DEVMETHOD(device_probe, pci_new_probe),
1639 DEVMETHOD(device_attach, bus_generic_attach),
1640 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1641 DEVMETHOD(device_suspend, bus_generic_suspend),
1642 DEVMETHOD(device_resume, bus_generic_resume),
1643
1644 /* Bus interface */
1645 DEVMETHOD(bus_print_child, pci_print_child),
1646 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
1647 DEVMETHOD(bus_read_ivar, pci_read_ivar),
1648 DEVMETHOD(bus_write_ivar, pci_write_ivar),
1649 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1650 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
1651 DEVMETHOD(bus_release_resource, pci_release_resource),
1652 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1653 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1654 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1655 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1656 DEVMETHOD(bus_set_resource, pci_set_resource),
1657 DEVMETHOD(bus_get_resource, pci_get_resource),
1658 DEVMETHOD(bus_delete_resource, pci_delete_resource),
1659
1660 /* PCI interface */
1661 DEVMETHOD(pci_read_config, pci_read_config_method),
1662 DEVMETHOD(pci_write_config, pci_write_config_method),
1663 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
1664 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
1665 DEVMETHOD(pci_enable_io, pci_enable_io_method),
1666 DEVMETHOD(pci_disable_io, pci_disable_io_method),
1667 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
1668 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
1669
1670 { 0, 0 }
1671};
1672
1673static driver_t pci_driver = {
1674 "pci",
1675 pci_methods,
1676 1, /* no softc */
1677};
1678
1679DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);