Spell 'separate' and its siblings the way it is supposed to.
[dragonfly.git] / sys / bus / pci / pci.c
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1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
dc5a7bd2 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.7 2004/01/07 18:13:19 joerg Exp $
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28 *
29 */
30
31#include "opt_bus.h"
32#include "opt_pci.h"
33
34#include "opt_simos.h"
dc5a7bd2 35#include "opt_compat_oldpci.h"
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36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/malloc.h>
40#include <sys/module.h>
41#include <sys/fcntl.h>
42#include <sys/conf.h>
43#include <sys/kernel.h>
44#include <sys/queue.h>
45#include <sys/types.h>
46#include <sys/buf.h>
47
48#include <vm/vm.h>
49#include <vm/pmap.h>
50#include <vm/vm_extern.h>
51
52#include <sys/bus.h>
53#include <machine/bus.h>
54#include <sys/rman.h>
55#include <machine/resource.h>
56#include <machine/md_var.h> /* For the Alpha */
57#ifdef __i386__
58#include <machine/pci_cfgreg.h>
59#endif
60
dc5a7bd2 61#include <sys/pciio.h>
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62#include "pcireg.h"
63#include "pcivar.h"
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64
65#ifdef __alpha__
66#include <machine/rpb.h>
67#endif
68
69#ifdef APIC_IO
70#include <machine/smp.h>
71#endif /* APIC_IO */
72
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73static devclass_t pci_devclass;
74
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75static void pci_read_extcap(pcicfgregs *cfg);
76
77struct pci_quirk {
78 u_int32_t devid; /* Vendor/device of the card */
79 int type;
80#define PCI_QUIRK_MAP_REG 1 /* PCI map register in wierd place */
81 int arg1;
82 int arg2;
83};
84
85struct pci_quirk pci_quirks[] = {
86 /*
87 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
88 */
89 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
90 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
91
92 { 0 }
93};
94
95/* map register information */
96#define PCI_MAPMEM 0x01 /* memory map */
97#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
98#define PCI_MAPPORT 0x04 /* port map */
99
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100static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
101u_int32_t pci_numdevs = 0;
102static u_int32_t pci_generation = 0;
103
104device_t
105pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func)
106{
107 struct pci_devinfo *dinfo;
108
109 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
110 if ((dinfo->cfg.bus == bus) &&
111 (dinfo->cfg.slot == slot) &&
112 (dinfo->cfg.func == func)) {
113 return (dinfo->cfg.dev);
114 }
115 }
116
117 return (NULL);
118}
119
120device_t
121pci_find_device (u_int16_t vendor, u_int16_t device)
122{
123 struct pci_devinfo *dinfo;
124
125 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
126 if ((dinfo->cfg.vendor == vendor) &&
127 (dinfo->cfg.device == device)) {
128 return (dinfo->cfg.dev);
129 }
130 }
131
132 return (NULL);
133}
134
135/* return base address of memory or port map */
136
137static u_int32_t
138pci_mapbase(unsigned mapreg)
139{
140 int mask = 0x03;
141 if ((mapreg & 0x01) == 0)
142 mask = 0x0f;
143 return (mapreg & ~mask);
144}
145
146/* return map type of memory or port map */
147
148static int
149pci_maptype(unsigned mapreg)
150{
151 static u_int8_t maptype[0x10] = {
152 PCI_MAPMEM, PCI_MAPPORT,
153 PCI_MAPMEM, 0,
154 PCI_MAPMEM, PCI_MAPPORT,
155 0, 0,
156 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
157 PCI_MAPMEM|PCI_MAPMEMP, 0,
158 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
159 0, 0,
160 };
161
162 return maptype[mapreg & 0x0f];
163}
164
165/* return log2 of map size decoded for memory or port map */
166
167static int
168pci_mapsize(unsigned testval)
169{
170 int ln2size;
171
172 testval = pci_mapbase(testval);
173 ln2size = 0;
174 if (testval != 0) {
175 while ((testval & 1) == 0)
176 {
177 ln2size++;
178 testval >>= 1;
179 }
180 }
181 return (ln2size);
182}
183
184/* return log2 of address range supported by map register */
185
186static int
187pci_maprange(unsigned mapreg)
188{
189 int ln2range = 0;
190 switch (mapreg & 0x07) {
191 case 0x00:
192 case 0x01:
193 case 0x05:
194 ln2range = 32;
195 break;
196 case 0x02:
197 ln2range = 20;
198 break;
199 case 0x04:
200 ln2range = 64;
201 break;
202 }
203 return (ln2range);
204}
205
206/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
207
208static void
209pci_fixancient(pcicfgregs *cfg)
210{
211 if (cfg->hdrtype != 0)
212 return;
213
214 /* PCI to PCI bridges use header type 1 */
215 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
216 cfg->hdrtype = 1;
217}
218
219/* read config data specific to header type 1 device (PCI to PCI bridge) */
220
221static void *
222pci_readppb(pcicfgregs *cfg)
223{
224 pcih1cfgregs *p;
225
226 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK);
227 if (p == NULL)
228 return (NULL);
229
230 bzero(p, sizeof *p);
231
232 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_1, 2);
233 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_1, 2);
234
235 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_1, 1);
236
237 p->iobase = PCI_PPBIOBASE (pci_cfgread(cfg, PCIR_IOBASEH_1, 2),
238 pci_cfgread(cfg, PCIR_IOBASEL_1, 1));
239 p->iolimit = PCI_PPBIOLIMIT (pci_cfgread(cfg, PCIR_IOLIMITH_1, 2),
240 pci_cfgread(cfg, PCIR_IOLIMITL_1, 1));
241
242 p->membase = PCI_PPBMEMBASE (0,
243 pci_cfgread(cfg, PCIR_MEMBASE_1, 2));
244 p->memlimit = PCI_PPBMEMLIMIT (0,
245 pci_cfgread(cfg, PCIR_MEMLIMIT_1, 2));
246
247 p->pmembase = PCI_PPBMEMBASE (
248 (pci_addr_t)pci_cfgread(cfg, PCIR_PMBASEH_1, 4),
249 pci_cfgread(cfg, PCIR_PMBASEL_1, 2));
250
251 p->pmemlimit = PCI_PPBMEMLIMIT (
252 (pci_addr_t)pci_cfgread(cfg, PCIR_PMLIMITH_1, 4),
253 pci_cfgread(cfg, PCIR_PMLIMITL_1, 2));
254 return (p);
255}
256
257/* read config data specific to header type 2 device (PCI to CardBus bridge) */
258
259static void *
260pci_readpcb(pcicfgregs *cfg)
261{
262 pcih2cfgregs *p;
263
264 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK);
265 if (p == NULL)
266 return (NULL);
267
268 bzero(p, sizeof *p);
269
270 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_2, 2);
271 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_2, 2);
272
273 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_2, 1);
274
275 p->membase0 = pci_cfgread(cfg, PCIR_MEMBASE0_2, 4);
276 p->memlimit0 = pci_cfgread(cfg, PCIR_MEMLIMIT0_2, 4);
277 p->membase1 = pci_cfgread(cfg, PCIR_MEMBASE1_2, 4);
278 p->memlimit1 = pci_cfgread(cfg, PCIR_MEMLIMIT1_2, 4);
279
280 p->iobase0 = pci_cfgread(cfg, PCIR_IOBASE0_2, 4);
281 p->iolimit0 = pci_cfgread(cfg, PCIR_IOLIMIT0_2, 4);
282 p->iobase1 = pci_cfgread(cfg, PCIR_IOBASE1_2, 4);
283 p->iolimit1 = pci_cfgread(cfg, PCIR_IOLIMIT1_2, 4);
284
285 p->pccardif = pci_cfgread(cfg, PCIR_PCCARDIF_2, 4);
286 return p;
287}
288
289/* extract header type specific config data */
290
291static void
292pci_hdrtypedata(pcicfgregs *cfg)
293{
294 switch (cfg->hdrtype) {
295 case 0:
296 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_0, 2);
297 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_0, 2);
298 cfg->nummaps = PCI_MAXMAPS_0;
299 break;
300 case 1:
301 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_1, 2);
302 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_1, 2);
303 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_1, 1);
304 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_1, 1);
305 cfg->nummaps = PCI_MAXMAPS_1;
306 cfg->hdrspec = pci_readppb(cfg);
307 break;
308 case 2:
309 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_2, 2);
310 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_2, 2);
311 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_2, 1);
312 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_2, 1);
313 cfg->nummaps = PCI_MAXMAPS_2;
314 cfg->hdrspec = pci_readpcb(cfg);
315 break;
316 }
317}
318
319/* read configuration header into pcicfgrect structure */
320
321static struct pci_devinfo *
322pci_readcfg(pcicfgregs *probe)
323{
324#define REG(n, w) pci_cfgread(probe, n, w)
325
326 pcicfgregs *cfg = NULL;
327 struct pci_devinfo *devlist_entry;
328 struct devlist *devlist_head;
329
330 devlist_head = &pci_devq;
331
332 devlist_entry = NULL;
333
334 if (pci_cfgread(probe, PCIR_DEVVENDOR, 4) != -1) {
335
336 devlist_entry = malloc(sizeof(struct pci_devinfo),
337 M_DEVBUF, M_WAITOK);
338 if (devlist_entry == NULL)
339 return (NULL);
340 bzero(devlist_entry, sizeof *devlist_entry);
341
342 cfg = &devlist_entry->cfg;
343
344 cfg->hose = probe->hose;
345 cfg->bus = probe->bus;
346 cfg->slot = probe->slot;
347 cfg->func = probe->func;
348 cfg->vendor = pci_cfgread(cfg, PCIR_VENDOR, 2);
349 cfg->device = pci_cfgread(cfg, PCIR_DEVICE, 2);
350 cfg->cmdreg = pci_cfgread(cfg, PCIR_COMMAND, 2);
351 cfg->statreg = pci_cfgread(cfg, PCIR_STATUS, 2);
352 cfg->baseclass = pci_cfgread(cfg, PCIR_CLASS, 1);
353 cfg->subclass = pci_cfgread(cfg, PCIR_SUBCLASS, 1);
354 cfg->progif = pci_cfgread(cfg, PCIR_PROGIF, 1);
355 cfg->revid = pci_cfgread(cfg, PCIR_REVID, 1);
356 cfg->hdrtype = pci_cfgread(cfg, PCIR_HEADERTYPE, 1);
357 cfg->cachelnsz = pci_cfgread(cfg, PCIR_CACHELNSZ, 1);
358 cfg->lattimer = pci_cfgread(cfg, PCIR_LATTIMER, 1);
359 cfg->intpin = pci_cfgread(cfg, PCIR_INTPIN, 1);
360 cfg->intline = pci_cfgread(cfg, PCIR_INTLINE, 1);
361#ifdef __alpha__
362 alpha_platform_assign_pciintr(cfg);
363#endif
364
365#ifdef APIC_IO
366 if (cfg->intpin != 0) {
367 int airq;
368
369 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
370 if (airq >= 0) {
371 /* PCI specific entry found in MP table */
372 if (airq != cfg->intline) {
373 undirect_pci_irq(cfg->intline);
374 cfg->intline = airq;
375 }
376 } else {
377 /*
378 * PCI interrupts might be redirected to the
379 * ISA bus according to some MP tables. Use the
380 * same methods as used by the ISA devices
381 * devices to find the proper IOAPIC int pin.
382 */
383 airq = isa_apic_irq(cfg->intline);
384 if ((airq >= 0) && (airq != cfg->intline)) {
385 /* XXX: undirect_pci_irq() ? */
386 undirect_isa_irq(cfg->intline);
387 cfg->intline = airq;
388 }
389 }
390 }
391#endif /* APIC_IO */
392
393 cfg->mingnt = pci_cfgread(cfg, PCIR_MINGNT, 1);
394 cfg->maxlat = pci_cfgread(cfg, PCIR_MAXLAT, 1);
395
396 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
397 cfg->hdrtype &= ~PCIM_MFDEV;
398
399 pci_fixancient(cfg);
400 pci_hdrtypedata(cfg);
401
402 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
403 pci_read_extcap(cfg);
404
405 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
406
407 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
408 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
409 devlist_entry->conf.pc_sel.pc_func = cfg->func;
410 devlist_entry->conf.pc_hdr = cfg->hdrtype;
411
412 devlist_entry->conf.pc_subvendor = cfg->subvendor;
413 devlist_entry->conf.pc_subdevice = cfg->subdevice;
414 devlist_entry->conf.pc_vendor = cfg->vendor;
415 devlist_entry->conf.pc_device = cfg->device;
416
417 devlist_entry->conf.pc_class = cfg->baseclass;
418 devlist_entry->conf.pc_subclass = cfg->subclass;
419 devlist_entry->conf.pc_progif = cfg->progif;
420 devlist_entry->conf.pc_revid = cfg->revid;
421
422 pci_numdevs++;
423 pci_generation++;
424 }
425 return (devlist_entry);
426#undef REG
427}
428
429static void
430pci_read_extcap(pcicfgregs *cfg)
431{
432#define REG(n, w) pci_cfgread(cfg, n, w)
433 int ptr, nextptr, ptrptr;
434
435 switch (cfg->hdrtype) {
436 case 0:
437 ptrptr = 0x34;
438 break;
439 case 2:
440 ptrptr = 0x14;
441 break;
442 default:
443 return; /* no extended capabilities support */
444 }
445 nextptr = REG(ptrptr, 1); /* sanity check? */
446
447 /*
448 * Read capability entries.
449 */
450 while (nextptr != 0) {
451 /* Sanity check */
452 if (nextptr > 255) {
453 printf("illegal PCI extended capability offset %d\n",
454 nextptr);
455 return;
456 }
457 /* Find the next entry */
458 ptr = nextptr;
459 nextptr = REG(ptr + 1, 1);
460
461 /* Process this entry */
462 switch (REG(ptr, 1)) {
463 case 0x01: /* PCI power management */
464 if (cfg->pp_cap == 0) {
465 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
466 cfg->pp_status = ptr + PCIR_POWER_STATUS;
467 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
468 if ((nextptr - ptr) > PCIR_POWER_DATA)
469 cfg->pp_data = ptr + PCIR_POWER_DATA;
470 }
471 break;
472 default:
473 break;
474 }
475 }
476#undef REG
477}
478
479#if 0
480/* free pcicfgregs structure and all depending data structures */
481
482static int
483pci_freecfg(struct pci_devinfo *dinfo)
484{
485 struct devlist *devlist_head;
486
487 devlist_head = &pci_devq;
488
489 if (dinfo->cfg.hdrspec != NULL)
490 free(dinfo->cfg.hdrspec, M_DEVBUF);
491 if (dinfo->cfg.map != NULL)
492 free(dinfo->cfg.map, M_DEVBUF);
493 /* XXX this hasn't been tested */
494 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
495 free(dinfo, M_DEVBUF);
496
497 /* increment the generation count */
498 pci_generation++;
499
500 /* we're losing one device */
501 pci_numdevs--;
502 return (0);
503}
504#endif
505
506
507/*
508 * PCI power manangement
509 */
510static int
511pci_set_powerstate_method(device_t dev, device_t child, int state)
512{
513 struct pci_devinfo *dinfo = device_get_ivars(child);
514 pcicfgregs *cfg = &dinfo->cfg;
515 u_int16_t status;
516 int result;
517
518 if (cfg->pp_cap != 0) {
519 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK;
520 result = 0;
521 switch (state) {
522 case PCI_POWERSTATE_D0:
523 status |= PCIM_PSTAT_D0;
524 break;
525 case PCI_POWERSTATE_D1:
526 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) {
527 status |= PCIM_PSTAT_D1;
528 } else {
529 result = EOPNOTSUPP;
530 }
531 break;
532 case PCI_POWERSTATE_D2:
533 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) {
534 status |= PCIM_PSTAT_D2;
535 } else {
536 result = EOPNOTSUPP;
537 }
538 break;
539 case PCI_POWERSTATE_D3:
540 status |= PCIM_PSTAT_D3;
541 break;
542 default:
543 result = EINVAL;
544 }
545 if (result == 0)
546 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2);
547 } else {
548 result = ENXIO;
549 }
550 return(result);
551}
552
553static int
554pci_get_powerstate_method(device_t dev, device_t child)
555{
556 struct pci_devinfo *dinfo = device_get_ivars(child);
557 pcicfgregs *cfg = &dinfo->cfg;
558 u_int16_t status;
559 int result;
560
561 if (cfg->pp_cap != 0) {
562 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2);
563 switch (status & PCIM_PSTAT_DMASK) {
564 case PCIM_PSTAT_D0:
565 result = PCI_POWERSTATE_D0;
566 break;
567 case PCIM_PSTAT_D1:
568 result = PCI_POWERSTATE_D1;
569 break;
570 case PCIM_PSTAT_D2:
571 result = PCI_POWERSTATE_D2;
572 break;
573 case PCIM_PSTAT_D3:
574 result = PCI_POWERSTATE_D3;
575 break;
576 default:
577 result = PCI_POWERSTATE_UNKNOWN;
578 break;
579 }
580 } else {
581 /* No support, device is always at D0 */
582 result = PCI_POWERSTATE_D0;
583 }
584 return(result);
585}
586
587/*
588 * Some convenience functions for PCI device drivers.
589 */
590
591static __inline void
592pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
593{
594 u_int16_t command;
595
596 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
597 command |= bit;
598 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
599}
600
601static __inline void
602pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
603{
604 u_int16_t command;
605
606 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
607 command &= ~bit;
608 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
609}
610
611static void
612pci_enable_busmaster_method(device_t dev, device_t child)
613{
614 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
615}
616
617static void
618pci_disable_busmaster_method(device_t dev, device_t child)
619{
620 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
621}
622
623static void
624pci_enable_io_method(device_t dev, device_t child, int space)
625{
626 switch(space) {
627 case SYS_RES_IOPORT:
628 pci_set_command_bit(dev, child, PCIM_CMD_PORTEN);
629 break;
630 case SYS_RES_MEMORY:
631 pci_set_command_bit(dev, child, PCIM_CMD_MEMEN);
632 break;
633 }
634}
635
636static void
637pci_disable_io_method(device_t dev, device_t child, int space)
638{
639 switch(space) {
640 case SYS_RES_IOPORT:
641 pci_clear_command_bit(dev, child, PCIM_CMD_PORTEN);
642 break;
643 case SYS_RES_MEMORY:
644 pci_clear_command_bit(dev, child, PCIM_CMD_MEMEN);
645 break;
646 }
647}
648
649/*
650 * This is the user interface to PCI configuration space.
651 */
652
653static int
41c20dac 654pci_open(dev_t dev, int oflags, int devtype, struct thread *td)
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655{
656 if ((oflags & FWRITE) && securelevel > 0) {
657 return EPERM;
658 }
659 return 0;
660}
661
662static int
41c20dac 663pci_close(dev_t dev, int flag, int devtype, struct thread *td)
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664{
665 return 0;
666}
667
668/*
669 * Match a single pci_conf structure against an array of pci_match_conf
670 * structures. The first argument, 'matches', is an array of num_matches
671 * pci_match_conf structures. match_buf is a pointer to the pci_conf
672 * structure that will be compared to every entry in the matches array.
673 * This function returns 1 on failure, 0 on success.
674 */
675static int
676pci_conf_match(struct pci_match_conf *matches, int num_matches,
677 struct pci_conf *match_buf)
678{
679 int i;
680
681 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
682 return(1);
683
684 for (i = 0; i < num_matches; i++) {
685 /*
686 * I'm not sure why someone would do this...but...
687 */
688 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
689 continue;
690
691 /*
692 * Look at each of the match flags. If it's set, do the
693 * comparison. If the comparison fails, we don't have a
694 * match, go on to the next item if there is one.
695 */
696 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
697 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
698 continue;
699
700 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
701 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
702 continue;
703
704 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
705 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
706 continue;
707
708 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
709 && (match_buf->pc_vendor != matches[i].pc_vendor))
710 continue;
711
712 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
713 && (match_buf->pc_device != matches[i].pc_device))
714 continue;
715
716 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
717 && (match_buf->pc_class != matches[i].pc_class))
718 continue;
719
720 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
721 && (match_buf->pd_unit != matches[i].pd_unit))
722 continue;
723
724 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
725 && (strncmp(matches[i].pd_name, match_buf->pd_name,
726 sizeof(match_buf->pd_name)) != 0))
727 continue;
728
729 return(0);
730 }
731
732 return(1);
733}
734
735/*
736 * Locate the parent of a PCI device by scanning the PCI devlist
737 * and return the entry for the parent.
738 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
739 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
740 */
741
742pcicfgregs *
743pci_devlist_get_parent(pcicfgregs *cfg)
744{
745 struct devlist *devlist_head;
746 struct pci_devinfo *dinfo;
747 pcicfgregs *bridge_cfg;
748 int i;
749
750 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
751
752 /* If the device is on PCI bus 0, look for the host */
753 if (cfg->bus == 0) {
754 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
755 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
756 bridge_cfg = &dinfo->cfg;
757 if (bridge_cfg->baseclass == PCIC_BRIDGE
758 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
759 && bridge_cfg->bus == cfg->bus) {
760 return bridge_cfg;
761 }
762 }
763 }
764
765 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
766 if (cfg->bus > 0) {
767 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
768 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
769 bridge_cfg = &dinfo->cfg;
770 if (bridge_cfg->baseclass == PCIC_BRIDGE
771 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
772 && bridge_cfg->secondarybus == cfg->bus) {
773 return bridge_cfg;
774 }
775 }
776 }
777
778 return NULL;
779}
780
781static int
41c20dac 782pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td)
984263bc
MD
783{
784 struct pci_io *io;
785 const char *name;
786 int error;
787
788 if (!(flag & FWRITE))
789 return EPERM;
790
791
792 switch(cmd) {
793 case PCIOCGETCONF:
794 {
795 struct pci_devinfo *dinfo;
796 struct pci_conf_io *cio;
797 struct devlist *devlist_head;
798 struct pci_match_conf *pattern_buf;
799 int num_patterns;
800 size_t iolen;
801 int ionum, i;
802
803 cio = (struct pci_conf_io *)data;
804
805 num_patterns = 0;
806 dinfo = NULL;
807
808 /*
809 * Hopefully the user won't pass in a null pointer, but it
810 * can't hurt to check.
811 */
812 if (cio == NULL) {
813 error = EINVAL;
814 break;
815 }
816
817 /*
818 * If the user specified an offset into the device list,
819 * but the list has changed since they last called this
820 * ioctl, tell them that the list has changed. They will
821 * have to get the list from the beginning.
822 */
823 if ((cio->offset != 0)
824 && (cio->generation != pci_generation)){
825 cio->num_matches = 0;
826 cio->status = PCI_GETCONF_LIST_CHANGED;
827 error = 0;
828 break;
829 }
830
831 /*
832 * Check to see whether the user has asked for an offset
833 * past the end of our list.
834 */
835 if (cio->offset >= pci_numdevs) {
836 cio->num_matches = 0;
837 cio->status = PCI_GETCONF_LAST_DEVICE;
838 error = 0;
839 break;
840 }
841
842 /* get the head of the device queue */
843 devlist_head = &pci_devq;
844
845 /*
846 * Determine how much room we have for pci_conf structures.
847 * Round the user's buffer size down to the nearest
848 * multiple of sizeof(struct pci_conf) in case the user
849 * didn't specify a multiple of that size.
850 */
851 iolen = min(cio->match_buf_len -
852 (cio->match_buf_len % sizeof(struct pci_conf)),
853 pci_numdevs * sizeof(struct pci_conf));
854
855 /*
856 * Since we know that iolen is a multiple of the size of
857 * the pciconf union, it's okay to do this.
858 */
859 ionum = iolen / sizeof(struct pci_conf);
860
861 /*
862 * If this test is true, the user wants the pci_conf
863 * structures returned to match the supplied entries.
864 */
865 if ((cio->num_patterns > 0)
866 && (cio->pat_buf_len > 0)) {
867 /*
868 * pat_buf_len needs to be:
869 * num_patterns * sizeof(struct pci_match_conf)
870 * While it is certainly possible the user just
871 * allocated a large buffer, but set the number of
872 * matches correctly, it is far more likely that
873 * their kernel doesn't match the userland utility
874 * they're using. It's also possible that the user
875 * forgot to initialize some variables. Yes, this
876 * may be overly picky, but I hazard to guess that
877 * it's far more likely to just catch folks that
878 * updated their kernel but not their userland.
879 */
880 if ((cio->num_patterns *
881 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
882 /* The user made a mistake, return an error*/
883 cio->status = PCI_GETCONF_ERROR;
884 printf("pci_ioctl: pat_buf_len %d != "
885 "num_patterns (%d) * sizeof(struct "
886 "pci_match_conf) (%d)\npci_ioctl: "
887 "pat_buf_len should be = %d\n",
888 cio->pat_buf_len, cio->num_patterns,
889 (int)sizeof(struct pci_match_conf),
890 (int)sizeof(struct pci_match_conf) *
891 cio->num_patterns);
892 printf("pci_ioctl: do your headers match your "
893 "kernel?\n");
894 cio->num_matches = 0;
895 error = EINVAL;
896 break;
897 }
898
899 /*
900 * Check the user's buffer to make sure it's readable.
901 */
902 if (!useracc((caddr_t)cio->patterns,
903 cio->pat_buf_len, VM_PROT_READ)) {
904 printf("pci_ioctl: pattern buffer %p, "
905 "length %u isn't user accessible for"
906 " READ\n", cio->patterns,
907 cio->pat_buf_len);
908 error = EACCES;
909 break;
910 }
911 /*
912 * Allocate a buffer to hold the patterns.
913 */
914 pattern_buf = malloc(cio->pat_buf_len, M_TEMP,
915 M_WAITOK);
916 error = copyin(cio->patterns, pattern_buf,
917 cio->pat_buf_len);
918 if (error != 0)
919 break;
920 num_patterns = cio->num_patterns;
921
922 } else if ((cio->num_patterns > 0)
923 || (cio->pat_buf_len > 0)) {
924 /*
925 * The user made a mistake, spit out an error.
926 */
927 cio->status = PCI_GETCONF_ERROR;
928 cio->num_matches = 0;
929 printf("pci_ioctl: invalid GETCONF arguments\n");
930 error = EINVAL;
931 break;
932 } else
933 pattern_buf = NULL;
934
935 /*
936 * Make sure we can write to the match buffer.
937 */
938 if (!useracc((caddr_t)cio->matches,
939 cio->match_buf_len, VM_PROT_WRITE)) {
940 printf("pci_ioctl: match buffer %p, length %u "
941 "isn't user accessible for WRITE\n",
942 cio->matches, cio->match_buf_len);
943 error = EACCES;
944 break;
945 }
946
947 /*
948 * Go through the list of devices and copy out the devices
949 * that match the user's criteria.
950 */
951 for (cio->num_matches = 0, error = 0, i = 0,
952 dinfo = STAILQ_FIRST(devlist_head);
953 (dinfo != NULL) && (cio->num_matches < ionum)
954 && (error == 0) && (i < pci_numdevs);
955 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
956
957 if (i < cio->offset)
958 continue;
959
960 /* Populate pd_name and pd_unit */
961 name = NULL;
962 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
963 name = device_get_name(dinfo->cfg.dev);
964 if (name) {
965 strncpy(dinfo->conf.pd_name, name,
966 sizeof(dinfo->conf.pd_name));
967 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
968 dinfo->conf.pd_unit =
969 device_get_unit(dinfo->cfg.dev);
970 }
971
972 if ((pattern_buf == NULL) ||
973 (pci_conf_match(pattern_buf, num_patterns,
974 &dinfo->conf) == 0)) {
975
976 /*
977 * If we've filled up the user's buffer,
978 * break out at this point. Since we've
979 * got a match here, we'll pick right back
980 * up at the matching entry. We can also
981 * tell the user that there are more matches
982 * left.
983 */
984 if (cio->num_matches >= ionum)
985 break;
986
987 error = copyout(&dinfo->conf,
988 &cio->matches[cio->num_matches],
989 sizeof(struct pci_conf));
990 cio->num_matches++;
991 }
992 }
993
994 /*
995 * Set the pointer into the list, so if the user is getting
996 * n records at a time, where n < pci_numdevs,
997 */
998 cio->offset = i;
999
1000 /*
1001 * Set the generation, the user will need this if they make
1002 * another ioctl call with offset != 0.
1003 */
1004 cio->generation = pci_generation;
1005
1006 /*
1007 * If this is the last device, inform the user so he won't
1008 * bother asking for more devices. If dinfo isn't NULL, we
1009 * know that there are more matches in the list because of
1010 * the way the traversal is done.
1011 */
1012 if (dinfo == NULL)
1013 cio->status = PCI_GETCONF_LAST_DEVICE;
1014 else
1015 cio->status = PCI_GETCONF_MORE_DEVS;
1016
1017 if (pattern_buf != NULL)
1018 free(pattern_buf, M_TEMP);
1019
1020 break;
1021 }
1022 case PCIOCREAD:
1023 io = (struct pci_io *)data;
1024 switch(io->pi_width) {
1025 pcicfgregs probe;
1026 case 4:
1027 case 2:
1028 case 1:
1029 probe.hose = -1;
1030 probe.bus = io->pi_sel.pc_bus;
1031 probe.slot = io->pi_sel.pc_dev;
1032 probe.func = io->pi_sel.pc_func;
1033 io->pi_data = pci_cfgread(&probe,
1034 io->pi_reg, io->pi_width);
1035 error = 0;
1036 break;
1037 default:
1038 error = ENODEV;
1039 break;
1040 }
1041 break;
1042
1043 case PCIOCWRITE:
1044 io = (struct pci_io *)data;
1045 switch(io->pi_width) {
1046 pcicfgregs probe;
1047 case 4:
1048 case 2:
1049 case 1:
1050 probe.hose = -1;
1051 probe.bus = io->pi_sel.pc_bus;
1052 probe.slot = io->pi_sel.pc_dev;
1053 probe.func = io->pi_sel.pc_func;
1054 pci_cfgwrite(&probe,
1055 io->pi_reg, io->pi_data, io->pi_width);
1056 error = 0;
1057 break;
1058 default:
1059 error = ENODEV;
1060 break;
1061 }
1062 break;
1063
1064 default:
1065 error = ENOTTY;
1066 break;
1067 }
1068
1069 return (error);
1070}
1071
1072#define PCI_CDEV 78
1073
1074static struct cdevsw pcicdev = {
fabb8ceb
MD
1075 /* name */ "pci",
1076 /* maj */ PCI_CDEV,
1077 /* flags */ 0,
1078 /* port */ NULL,
1079 /* autoq */ 0,
1080
984263bc
MD
1081 /* open */ pci_open,
1082 /* close */ pci_close,
1083 /* read */ noread,
1084 /* write */ nowrite,
1085 /* ioctl */ pci_ioctl,
1086 /* poll */ nopoll,
1087 /* mmap */ nommap,
1088 /* strategy */ nostrategy,
984263bc 1089 /* dump */ nodump,
fabb8ceb 1090 /* psize */ nopsize
984263bc
MD
1091};
1092
1093#include "pci_if.h"
1094
984263bc
MD
1095/*
1096 * New style pci driver. Parent device is either a pci-host-bridge or a
1097 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1098 */
1099
1100static void
1101pci_print_verbose(struct pci_devinfo *dinfo)
1102{
1103 if (bootverbose) {
1104 pcicfgregs *cfg = &dinfo->cfg;
1105
1106 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
1107 cfg->vendor, cfg->device, cfg->revid);
1108 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
1109 cfg->baseclass, cfg->subclass, cfg->progif,
1110 cfg->hdrtype, cfg->mfdev);
1111 printf("\tsubordinatebus=%x \tsecondarybus=%x\n",
1112 cfg->subordinatebus, cfg->secondarybus);
1113#ifdef PCI_DEBUG
1114 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
1115 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
1116 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
1117 cfg->lattimer, cfg->lattimer * 30,
1118 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1119#endif /* PCI_DEBUG */
1120 if (cfg->intpin > 0)
1121 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
1122 }
1123}
1124
1125static int
1126pci_porten(pcicfgregs *cfg)
1127{
1128 return ((cfg->cmdreg & PCIM_CMD_PORTEN) != 0);
1129}
1130
1131static int
1132pci_memen(pcicfgregs *cfg)
1133{
1134 return ((cfg->cmdreg & PCIM_CMD_MEMEN) != 0);
1135}
1136
1137/*
1138 * Add a resource based on a pci map register. Return 1 if the map
1139 * register is a 32bit map register or 2 if it is a 64bit register.
1140 */
1141static int
1142pci_add_map(device_t dev, pcicfgregs* cfg, int reg)
1143{
1144 struct pci_devinfo *dinfo = device_get_ivars(dev);
1145 struct resource_list *rl = &dinfo->resources;
1146 u_int32_t map;
1147 u_int64_t base;
1148 u_int8_t ln2size;
1149 u_int8_t ln2range;
1150 u_int32_t testval;
1151
1152 int type;
1153
1154 map = pci_cfgread(cfg, reg, 4);
1155
1156 if (map == 0 || map == 0xffffffff)
1157 return 1; /* skip invalid entry */
1158
1159 pci_cfgwrite(cfg, reg, 0xffffffff, 4);
1160 testval = pci_cfgread(cfg, reg, 4);
1161 pci_cfgwrite(cfg, reg, map, 4);
1162
1163 base = pci_mapbase(map);
1164 if (pci_maptype(map) & PCI_MAPMEM)
1165 type = SYS_RES_MEMORY;
1166 else
1167 type = SYS_RES_IOPORT;
1168 ln2size = pci_mapsize(testval);
1169 ln2range = pci_maprange(testval);
1170 if (ln2range == 64) {
1171 /* Read the other half of a 64bit map register */
1172 base |= (u_int64_t) pci_cfgread(cfg, reg + 4, 4) << 32;
1173 }
1174
1175#ifdef __alpha__
1176 /*
1177 * XXX: encode hose number in the base addr,
1178 * This will go away once the bus_space functions
1179 * can deal with multiple hoses
1180 */
1181
1182 if (cfg->hose) {
1183 u_int32_t mask, shift, maxh;
1184
1185 switch (hwrpb->rpb_type) {
1186 case ST_DEC_4100:
1187 case -ST_DEC_4100:
1188 mask = 0xc0000000;
1189 shift = 30;
1190 maxh = 4; /* not a hose. MCPCIA instance # */
1191 break;
1192 case ST_DEC_21000:
1193 mask = 0xf8000000;
1194 shift = 27;
1195 maxh = 32;
1196 break;
1197 case ST_DEC_6600:
1198 mask = 0x80000000;
1199 shift = 31;
1200 maxh = 2;
1201 break;
1202 default:
1203 mask = 0;
1204 shift = 0;
1205 maxh = 0;
1206 break;
1207 }
1208 if (base & mask) {
1209 printf("base addr = 0x%llx\n", (long long) base);
1210 printf("mask addr = 0x%lx\n", (long) mask);
1211 printf("hacked addr = 0x%llx\n", (long long)
1212 (base | ((u_int64_t)cfg->hose << shift)));
1213 panic("hose encoding hack would clobber base addr");
1214 /* NOTREACHED */
1215 }
1216 if (cfg->hose >= maxh) {
1217 panic("Hose %d - can only encode %d hose(s)",
1218 cfg->hose, maxh);
1219 /* NOTREACHED */
1220 }
1221 base |= ((u_int64_t)cfg->hose << shift);
1222 }
1223#endif
1224
1225 /*
1226 * This code theoretically does the right thing, but has
1227 * undesirable side effects in some cases where
1228 * peripherals respond oddly to having these bits
1229 * enabled. Leave them alone by default.
1230 */
1231#ifdef PCI_ENABLE_IO_MODES
1232 if (type == SYS_RES_IOPORT && !pci_porten(cfg)) {
1233 cfg->cmdreg |= PCIM_CMD_PORTEN;
1234 pci_cfgwrite(cfg, PCIR_COMMAND, cfg->cmdreg, 2);
1235 }
1236 if (type == SYS_RES_MEMORY && !pci_memen(cfg)) {
1237 cfg->cmdreg |= PCIM_CMD_MEMEN;
1238 pci_cfgwrite(cfg, PCIR_COMMAND, cfg->cmdreg, 2);
1239 }
1240#else
1241 if (type == SYS_RES_IOPORT && !pci_porten(cfg))
1242 return 1;
1243 if (type == SYS_RES_MEMORY && !pci_memen(cfg))
1244 return 1;
1245#endif
1246
1247 resource_list_add(rl, type, reg,
1248 base, base + (1 << ln2size) - 1,
1249 (1 << ln2size));
1250
1251 if (bootverbose) {
1252 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
1253 reg, pci_maptype(base), ln2range,
1254 (unsigned int) base, ln2size);
1255 }
1256
1257 return (ln2range == 64) ? 2 : 1;
1258}
1259
1260static void
1261pci_add_resources(device_t dev, pcicfgregs* cfg)
1262{
1263 struct pci_devinfo *dinfo = device_get_ivars(dev);
1264 struct resource_list *rl = &dinfo->resources;
1265 struct pci_quirk *q;
1266 int i;
1267
1268 for (i = 0; i < cfg->nummaps;) {
1269 i += pci_add_map(dev, cfg, PCIR_MAPS + i*4);
1270 }
1271
1272 for (q = &pci_quirks[0]; q->devid; q++) {
1273 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1274 && q->type == PCI_QUIRK_MAP_REG)
1275 pci_add_map(dev, cfg, q->arg1);
1276 }
1277
1278 if (cfg->intpin > 0 && cfg->intline != 255)
1279 resource_list_add(rl, SYS_RES_IRQ, 0,
1280 cfg->intline, cfg->intline, 1);
1281}
1282
1283static void
1284pci_add_children(device_t dev, int busno)
1285{
1286 pcicfgregs probe;
1287
1288#ifdef SIMOS
1289#undef PCI_SLOTMAX
1290#define PCI_SLOTMAX 0
1291#endif
1292
1293 bzero(&probe, sizeof probe);
1294#ifdef __alpha__
1295 probe.hose = pcib_get_hose(dev);
1296#endif
1297#ifdef __i386__
1298 probe.hose = 0;
1299#endif
1300 probe.bus = busno;
1301
1302 for (probe.slot = 0; probe.slot <= PCI_SLOTMAX; probe.slot++) {
1303 int pcifunchigh = 0;
1304 for (probe.func = 0; probe.func <= pcifunchigh; probe.func++) {
1305 struct pci_devinfo *dinfo = pci_readcfg(&probe);
1306 if (dinfo != NULL) {
1307 if (dinfo->cfg.mfdev)
1308 pcifunchigh = 7;
1309
1310 pci_print_verbose(dinfo);
1311 dinfo->cfg.dev = device_add_child(dev, NULL, -1);
1312 device_set_ivars(dinfo->cfg.dev, dinfo);
1313 pci_add_resources(dinfo->cfg.dev, &dinfo->cfg);
1314 }
1315 }
1316 }
1317}
1318
1319static int
1320pci_new_probe(device_t dev)
1321{
1322 static int once;
1323
1324 device_set_desc(dev, "PCI bus");
1325 pci_add_children(dev, device_get_unit(dev));
1326 if (!once) {
1327 make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci");
1328 once++;
1329 }
1330
1331 return 0;
1332}
1333
1334static int
1335pci_print_resources(struct resource_list *rl, const char *name, int type,
1336 const char *format)
1337{
1338 struct resource_list_entry *rle;
1339 int printed, retval;
1340
1341 printed = 0;
1342 retval = 0;
1343 /* Yes, this is kinda cheating */
1344 SLIST_FOREACH(rle, rl, link) {
1345 if (rle->type == type) {
1346 if (printed == 0)
1347 retval += printf(" %s ", name);
1348 else if (printed > 0)
1349 retval += printf(",");
1350 printed++;
1351 retval += printf(format, rle->start);
1352 if (rle->count > 1) {
1353 retval += printf("-");
1354 retval += printf(format, rle->start +
1355 rle->count - 1);
1356 }
1357 }
1358 }
1359 return retval;
1360}
1361
1362static int
1363pci_print_child(device_t dev, device_t child)
1364{
1365 struct pci_devinfo *dinfo;
1366 struct resource_list *rl;
1367 pcicfgregs *cfg;
1368 int retval = 0;
1369
1370 dinfo = device_get_ivars(child);
1371 cfg = &dinfo->cfg;
1372 rl = &dinfo->resources;
1373
1374 retval += bus_print_child_header(dev, child);
1375
1376 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1377 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1378 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1379 if (device_get_flags(dev))
1380 retval += printf(" flags %#x", device_get_flags(dev));
1381
1382 retval += printf(" at device %d.%d", pci_get_slot(child),
1383 pci_get_function(child));
1384
1385 retval += bus_print_child_footer(dev, child);
1386
1387 return (retval);
1388}
1389
1390static void
1391pci_probe_nomatch(device_t dev, device_t child)
1392{
1393 struct pci_devinfo *dinfo;
1394 pcicfgregs *cfg;
1395 const char *desc;
1396 int unknown;
1397
1398 unknown = 0;
1399 dinfo = device_get_ivars(child);
1400 cfg = &dinfo->cfg;
1401 desc = pci_ata_match(child);
1402 if (!desc) desc = pci_usb_match(child);
1403 if (!desc) desc = pci_vga_match(child);
1404 if (!desc) {
1405 desc = "unknown card";
1406 unknown++;
1407 }
1408 device_printf(dev, "<%s>", desc);
1409 if (bootverbose || unknown) {
1410 printf(" (vendor=0x%04x, dev=0x%04x)",
1411 cfg->vendor,
1412 cfg->device);
1413 }
1414 printf(" at %d.%d",
1415 pci_get_slot(child),
1416 pci_get_function(child));
1417 if (cfg->intpin > 0 && cfg->intline != 255) {
1418 printf(" irq %d", cfg->intline);
1419 }
1420 printf("\n");
1421
1422 return;
1423}
1424
1425static int
1426pci_read_ivar(device_t dev, device_t child, int which, u_long *result)
1427{
1428 struct pci_devinfo *dinfo;
1429 pcicfgregs *cfg;
1430
1431 dinfo = device_get_ivars(child);
1432 cfg = &dinfo->cfg;
1433
1434 switch (which) {
1435 case PCI_IVAR_SUBVENDOR:
1436 *result = cfg->subvendor;
1437 break;
1438 case PCI_IVAR_SUBDEVICE:
1439 *result = cfg->subdevice;
1440 break;
1441 case PCI_IVAR_VENDOR:
1442 *result = cfg->vendor;
1443 break;
1444 case PCI_IVAR_DEVICE:
1445 *result = cfg->device;
1446 break;
1447 case PCI_IVAR_DEVID:
1448 *result = (cfg->device << 16) | cfg->vendor;
1449 break;
1450 case PCI_IVAR_CLASS:
1451 *result = cfg->baseclass;
1452 break;
1453 case PCI_IVAR_SUBCLASS:
1454 *result = cfg->subclass;
1455 break;
1456 case PCI_IVAR_PROGIF:
1457 *result = cfg->progif;
1458 break;
1459 case PCI_IVAR_REVID:
1460 *result = cfg->revid;
1461 break;
1462 case PCI_IVAR_INTPIN:
1463 *result = cfg->intpin;
1464 break;
1465 case PCI_IVAR_IRQ:
1466 *result = cfg->intline;
1467 break;
1468 case PCI_IVAR_BUS:
1469 *result = cfg->bus;
1470 break;
1471 case PCI_IVAR_SLOT:
1472 *result = cfg->slot;
1473 break;
1474 case PCI_IVAR_FUNCTION:
1475 *result = cfg->func;
1476 break;
1477 case PCI_IVAR_SECONDARYBUS:
1478 *result = cfg->secondarybus;
1479 break;
1480 case PCI_IVAR_SUBORDINATEBUS:
1481 *result = cfg->subordinatebus;
1482 break;
1483 case PCI_IVAR_HOSE:
1484 /*
1485 * Pass up to parent bridge.
1486 */
1487 *result = pcib_get_hose(dev);
1488 break;
1489 default:
1490 return ENOENT;
1491 }
1492 return 0;
1493}
1494
1495static int
1496pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1497{
1498 struct pci_devinfo *dinfo;
1499 pcicfgregs *cfg;
1500
1501 dinfo = device_get_ivars(child);
1502 cfg = &dinfo->cfg;
1503
1504 switch (which) {
1505 case PCI_IVAR_SUBVENDOR:
1506 case PCI_IVAR_SUBDEVICE:
1507 case PCI_IVAR_VENDOR:
1508 case PCI_IVAR_DEVICE:
1509 case PCI_IVAR_DEVID:
1510 case PCI_IVAR_CLASS:
1511 case PCI_IVAR_SUBCLASS:
1512 case PCI_IVAR_PROGIF:
1513 case PCI_IVAR_REVID:
1514 case PCI_IVAR_INTPIN:
1515 case PCI_IVAR_IRQ:
1516 case PCI_IVAR_BUS:
1517 case PCI_IVAR_SLOT:
1518 case PCI_IVAR_FUNCTION:
1519 return EINVAL; /* disallow for now */
1520
1521 case PCI_IVAR_SECONDARYBUS:
1522 cfg->secondarybus = value;
1523 break;
1524 case PCI_IVAR_SUBORDINATEBUS:
1525 cfg->subordinatebus = value;
1526 break;
1527 default:
1528 return ENOENT;
1529 }
1530 return 0;
1531}
1532
1533static struct resource *
1534pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1535 u_long start, u_long end, u_long count, u_int flags)
1536{
1537 struct pci_devinfo *dinfo = device_get_ivars(child);
1538 struct resource_list *rl = &dinfo->resources;
1539
1540#ifdef __i386__ /* Only supported on x86 in stable */
1541 pcicfgregs *cfg = &dinfo->cfg;
1542 /*
1543 * Perform lazy resource allocation
1544 *
1545 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY
1546 */
1547 if (device_get_parent(child) == dev) {
1548 /*
1549 * If device doesn't have an interrupt routed, and is
1550 * deserving of an interrupt, try to assign it one.
1551 */
1552 if ((type == SYS_RES_IRQ) &&
1553 (cfg->intline == 255 || cfg->intline == 0) &&
1554 (cfg->intpin != 0) && (start == 0) && (end == ~0UL)) {
1555 cfg->intline = pci_cfgintr(pci_get_bus(child),
1556 pci_get_slot(child), cfg->intpin);
1557 if (cfg->intline != 255) {
1558 pci_write_config(child, PCIR_INTLINE,
1559 cfg->intline, 1);
1560 resource_list_add(rl, SYS_RES_IRQ, 0,
1561 cfg->intline, cfg->intline, 1);
1562 }
1563 }
1564 }
1565#endif
1566 return resource_list_alloc(rl, dev, child, type, rid,
1567 start, end, count, flags);
1568}
1569
1570static int
1571pci_release_resource(device_t dev, device_t child, int type, int rid,
1572 struct resource *r)
1573{
1574 struct pci_devinfo *dinfo = device_get_ivars(child);
1575 struct resource_list *rl = &dinfo->resources;
1576
1577 return resource_list_release(rl, dev, child, type, rid, r);
1578}
1579
1580static int
1581pci_set_resource(device_t dev, device_t child, int type, int rid,
1582 u_long start, u_long count)
1583{
1584 struct pci_devinfo *dinfo = device_get_ivars(child);
1585 struct resource_list *rl = &dinfo->resources;
1586
1587 resource_list_add(rl, type, rid, start, start + count - 1, count);
1588 return 0;
1589}
1590
1591static int
1592pci_get_resource(device_t dev, device_t child, int type, int rid,
1593 u_long *startp, u_long *countp)
1594{
1595 struct pci_devinfo *dinfo = device_get_ivars(child);
1596 struct resource_list *rl = &dinfo->resources;
1597 struct resource_list_entry *rle;
1598
1599 rle = resource_list_find(rl, type, rid);
1600 if (!rle)
1601 return ENOENT;
1602
1603 if (startp)
1604 *startp = rle->start;
1605 if (countp)
1606 *countp = rle->count;
1607
1608 return 0;
1609}
1610
1611static void
1612pci_delete_resource(device_t dev, device_t child, int type, int rid)
1613{
1614 printf("pci_delete_resource: PCI resources can not be deleted\n");
1615}
1616
1617static u_int32_t
1618pci_read_config_method(device_t dev, device_t child, int reg, int width)
1619{
1620 struct pci_devinfo *dinfo = device_get_ivars(child);
1621 pcicfgregs *cfg = &dinfo->cfg;
1622 return pci_cfgread(cfg, reg, width);
1623}
1624
1625static void
1626pci_write_config_method(device_t dev, device_t child, int reg,
1627 u_int32_t val, int width)
1628{
1629 struct pci_devinfo *dinfo = device_get_ivars(child);
1630 pcicfgregs *cfg = &dinfo->cfg;
1631 pci_cfgwrite(cfg, reg, val, width);
1632}
1633
1634static int
1635pci_modevent(module_t mod, int what, void *arg)
1636{
1637 switch (what) {
1638 case MOD_LOAD:
1639 STAILQ_INIT(&pci_devq);
1640 break;
1641
1642 case MOD_UNLOAD:
1643 break;
1644 }
1645
1646 return 0;
1647}
1648
1649static device_method_t pci_methods[] = {
1650 /* Device interface */
1651 DEVMETHOD(device_probe, pci_new_probe),
1652 DEVMETHOD(device_attach, bus_generic_attach),
1653 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1654 DEVMETHOD(device_suspend, bus_generic_suspend),
1655 DEVMETHOD(device_resume, bus_generic_resume),
1656
1657 /* Bus interface */
1658 DEVMETHOD(bus_print_child, pci_print_child),
1659 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
1660 DEVMETHOD(bus_read_ivar, pci_read_ivar),
1661 DEVMETHOD(bus_write_ivar, pci_write_ivar),
1662 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1663 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
1664 DEVMETHOD(bus_release_resource, pci_release_resource),
1665 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1666 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1667 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1668 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1669 DEVMETHOD(bus_set_resource, pci_set_resource),
1670 DEVMETHOD(bus_get_resource, pci_get_resource),
1671 DEVMETHOD(bus_delete_resource, pci_delete_resource),
1672
1673 /* PCI interface */
1674 DEVMETHOD(pci_read_config, pci_read_config_method),
1675 DEVMETHOD(pci_write_config, pci_write_config_method),
1676 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
1677 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
1678 DEVMETHOD(pci_enable_io, pci_enable_io_method),
1679 DEVMETHOD(pci_disable_io, pci_disable_io_method),
1680 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
1681 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
1682
1683 { 0, 0 }
1684};
1685
1686static driver_t pci_driver = {
1687 "pci",
1688 pci_methods,
1689 1, /* no softc */
1690};
1691
1692DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);