- Add CAP_PTR macro for type 2 devices (cardbus)
[dragonfly.git] / sys / bus / pci / pci.c
CommitLineData
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1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
81c29ce4 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.41 2007/11/23 13:40:58 sephe Exp $
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28 *
29 */
30
31#include "opt_bus.h"
32#include "opt_pci.h"
33
dc5a7bd2 34#include "opt_compat_oldpci.h"
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35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/malloc.h>
39#include <sys/module.h>
40#include <sys/fcntl.h>
41#include <sys/conf.h>
42#include <sys/kernel.h>
43#include <sys/queue.h>
44#include <sys/types.h>
45#include <sys/buf.h>
46
47#include <vm/vm.h>
48#include <vm/pmap.h>
49#include <vm/vm_extern.h>
50
51#include <sys/bus.h>
984263bc 52#include <sys/rman.h>
97359a5b 53#include <machine/smp.h>
984263bc 54#ifdef __i386__
bbca97bc 55#include <bus/pci/i386/pci_cfgreg.h>
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56#endif
57
dc5a7bd2 58#include <sys/pciio.h>
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59#include "pcireg.h"
60#include "pcivar.h"
22457186 61#include "pci_private.h"
984263bc 62
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63#include "pcib_if.h"
64
e126caf1 65devclass_t pci_devclass;
2581072f 66const char *pcib_owner;
dc5a7bd2 67
4a5a2d63 68static void pci_read_extcap(device_t dev, pcicfgregs *cfg);
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69
70struct pci_quirk {
71 u_int32_t devid; /* Vendor/device of the card */
72 int type;
3e4db402 73#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
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74 int arg1;
75 int arg2;
76};
77
78struct pci_quirk pci_quirks[] = {
79 /*
80 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
81 */
82 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
83 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
f1f0bfb2
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84 /* As does the Serverworks OSB4 (the SMBus mapping register) */
85 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
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86
87 { 0 }
88};
89
90/* map register information */
91#define PCI_MAPMEM 0x01 /* memory map */
92#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
93#define PCI_MAPPORT 0x04 /* port map */
94
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95static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
96u_int32_t pci_numdevs = 0;
97static u_int32_t pci_generation = 0;
98
99device_t
100pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func)
101{
102 struct pci_devinfo *dinfo;
103
104 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
105 if ((dinfo->cfg.bus == bus) &&
106 (dinfo->cfg.slot == slot) &&
107 (dinfo->cfg.func == func)) {
108 return (dinfo->cfg.dev);
109 }
110 }
111
112 return (NULL);
113}
114
115device_t
116pci_find_device (u_int16_t vendor, u_int16_t device)
117{
118 struct pci_devinfo *dinfo;
119
120 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
121 if ((dinfo->cfg.vendor == vendor) &&
122 (dinfo->cfg.device == device)) {
123 return (dinfo->cfg.dev);
124 }
125 }
126
127 return (NULL);
128}
129
130/* return base address of memory or port map */
131
132static u_int32_t
133pci_mapbase(unsigned mapreg)
134{
135 int mask = 0x03;
136 if ((mapreg & 0x01) == 0)
137 mask = 0x0f;
138 return (mapreg & ~mask);
139}
140
141/* return map type of memory or port map */
142
143static int
144pci_maptype(unsigned mapreg)
145{
146 static u_int8_t maptype[0x10] = {
147 PCI_MAPMEM, PCI_MAPPORT,
148 PCI_MAPMEM, 0,
149 PCI_MAPMEM, PCI_MAPPORT,
150 0, 0,
151 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
152 PCI_MAPMEM|PCI_MAPMEMP, 0,
153 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
154 0, 0,
155 };
156
157 return maptype[mapreg & 0x0f];
158}
159
160/* return log2 of map size decoded for memory or port map */
161
162static int
163pci_mapsize(unsigned testval)
164{
165 int ln2size;
166
167 testval = pci_mapbase(testval);
168 ln2size = 0;
169 if (testval != 0) {
170 while ((testval & 1) == 0)
171 {
172 ln2size++;
173 testval >>= 1;
174 }
175 }
176 return (ln2size);
177}
178
179/* return log2 of address range supported by map register */
180
181static int
182pci_maprange(unsigned mapreg)
183{
184 int ln2range = 0;
185 switch (mapreg & 0x07) {
186 case 0x00:
187 case 0x01:
188 case 0x05:
189 ln2range = 32;
190 break;
191 case 0x02:
192 ln2range = 20;
193 break;
194 case 0x04:
195 ln2range = 64;
196 break;
197 }
198 return (ln2range);
199}
200
201/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
202
203static void
204pci_fixancient(pcicfgregs *cfg)
205{
206 if (cfg->hdrtype != 0)
207 return;
208
209 /* PCI to PCI bridges use header type 1 */
210 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
211 cfg->hdrtype = 1;
212}
213
214/* read config data specific to header type 1 device (PCI to PCI bridge) */
215
216static void *
4a5a2d63 217pci_readppb(device_t pcib, int b, int s, int f)
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218{
219 pcih1cfgregs *p;
220
efda3bd0 221 p = kmalloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
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222 if (p == NULL)
223 return (NULL);
224
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225 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
226 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
984263bc 227
4a5a2d63 228 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
984263bc 229
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230 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
231 PCIR_IOBASEH_1, 2),
232 PCIB_READ_CONFIG(pcib, b, s, f,
233 PCIR_IOBASEL_1, 1));
234 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
235 PCIR_IOLIMITH_1, 2),
236 PCIB_READ_CONFIG(pcib, b, s, f,
237 PCIR_IOLIMITL_1, 1));
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238
239 p->membase = PCI_PPBMEMBASE (0,
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240 PCIB_READ_CONFIG(pcib, b, s, f,
241 PCIR_MEMBASE_1, 2));
984263bc 242 p->memlimit = PCI_PPBMEMLIMIT (0,
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243 PCIB_READ_CONFIG(pcib, b, s, f,
244 PCIR_MEMLIMIT_1, 2));
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245
246 p->pmembase = PCI_PPBMEMBASE (
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247 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
248 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
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249
250 p->pmemlimit = PCI_PPBMEMLIMIT (
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251 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
252 PCIR_PMLIMITH_1, 4),
253 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
254
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255 return (p);
256}
257
258/* read config data specific to header type 2 device (PCI to CardBus bridge) */
259
260static void *
4a5a2d63 261pci_readpcb(device_t pcib, int b, int s, int f)
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262{
263 pcih2cfgregs *p;
264
efda3bd0 265 p = kmalloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
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266 if (p == NULL)
267 return (NULL);
268
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269 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
270 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
984263bc 271
4a5a2d63 272 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
984263bc 273
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274 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
275 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
276 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
277 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
984263bc 278
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279 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
280 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
281 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
282 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
984263bc 283
4a5a2d63 284 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
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285 return p;
286}
287
288/* extract header type specific config data */
289
290static void
4a5a2d63 291pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
984263bc 292{
4a5a2d63 293#define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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294 switch (cfg->hdrtype) {
295 case 0:
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296 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
297 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
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298 cfg->nummaps = PCI_MAXMAPS_0;
299 break;
300 case 1:
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301 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
302 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
303 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
304 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
984263bc 305 cfg->nummaps = PCI_MAXMAPS_1;
4a5a2d63 306 cfg->hdrspec = pci_readppb(pcib, b, s, f);
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307 break;
308 case 2:
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309 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
310 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
311 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
312 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
984263bc 313 cfg->nummaps = PCI_MAXMAPS_2;
4a5a2d63 314 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
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315 break;
316 }
4a5a2d63 317#undef REG
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318}
319
320/* read configuration header into pcicfgrect structure */
321
22457186 322struct pci_devinfo *
c01b8d84 323pci_read_device(device_t pcib, int b, int s, int f, size_t size)
984263bc 324{
4a5a2d63 325#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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326
327 pcicfgregs *cfg = NULL;
328 struct pci_devinfo *devlist_entry;
329 struct devlist *devlist_head;
330
331 devlist_head = &pci_devq;
332
333 devlist_entry = NULL;
334
4a5a2d63 335 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
984263bc 336
efda3bd0 337 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
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338 if (devlist_entry == NULL)
339 return (NULL);
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340
341 cfg = &devlist_entry->cfg;
342
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343 cfg->bus = b;
344 cfg->slot = s;
345 cfg->func = f;
346 cfg->vendor = REG(PCIR_VENDOR, 2);
347 cfg->device = REG(PCIR_DEVICE, 2);
348 cfg->cmdreg = REG(PCIR_COMMAND, 2);
349 cfg->statreg = REG(PCIR_STATUS, 2);
350 cfg->baseclass = REG(PCIR_CLASS, 1);
351 cfg->subclass = REG(PCIR_SUBCLASS, 1);
352 cfg->progif = REG(PCIR_PROGIF, 1);
353 cfg->revid = REG(PCIR_REVID, 1);
e126caf1 354 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
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355 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
356 cfg->lattimer = REG(PCIR_LATTIMER, 1);
357 cfg->intpin = REG(PCIR_INTPIN, 1);
358 cfg->intline = REG(PCIR_INTLINE, 1);
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359
360#ifdef APIC_IO
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361 /*
362 * If using the APIC the intpin is probably wrong, since it
363 * is often setup by the BIOS with the PIC in mind.
364 */
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365 if (cfg->intpin != 0) {
366 int airq;
367
368 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
369 if (airq >= 0) {
370 /* PCI specific entry found in MP table */
371 if (airq != cfg->intline) {
372 undirect_pci_irq(cfg->intline);
373 cfg->intline = airq;
374 }
375 } else {
376 /*
377 * PCI interrupts might be redirected to the
378 * ISA bus according to some MP tables. Use the
379 * same methods as used by the ISA devices
380 * devices to find the proper IOAPIC int pin.
381 */
382 airq = isa_apic_irq(cfg->intline);
383 if ((airq >= 0) && (airq != cfg->intline)) {
384 /* XXX: undirect_pci_irq() ? */
385 undirect_isa_irq(cfg->intline);
386 cfg->intline = airq;
387 }
388 }
389 }
390#endif /* APIC_IO */
391
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392 cfg->mingnt = REG(PCIR_MINGNT, 1);
393 cfg->maxlat = REG(PCIR_MAXLAT, 1);
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394
395 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
396 cfg->hdrtype &= ~PCIM_MFDEV;
397
398 pci_fixancient(cfg);
4a5a2d63 399 pci_hdrtypedata(pcib, b, s, f, cfg);
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400
401 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
4a5a2d63 402 pci_read_extcap(pcib, cfg);
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403
404 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
405
406 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
407 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
408 devlist_entry->conf.pc_sel.pc_func = cfg->func;
409 devlist_entry->conf.pc_hdr = cfg->hdrtype;
410
411 devlist_entry->conf.pc_subvendor = cfg->subvendor;
412 devlist_entry->conf.pc_subdevice = cfg->subdevice;
413 devlist_entry->conf.pc_vendor = cfg->vendor;
414 devlist_entry->conf.pc_device = cfg->device;
415
416 devlist_entry->conf.pc_class = cfg->baseclass;
417 devlist_entry->conf.pc_subclass = cfg->subclass;
418 devlist_entry->conf.pc_progif = cfg->progif;
419 devlist_entry->conf.pc_revid = cfg->revid;
420
421 pci_numdevs++;
422 pci_generation++;
423 }
424 return (devlist_entry);
425#undef REG
426}
427
428static void
4a5a2d63 429pci_read_extcap(device_t pcib, pcicfgregs *cfg)
984263bc 430{
4a5a2d63 431#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
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432 int ptr, nextptr, ptrptr;
433
434 switch (cfg->hdrtype) {
435 case 0:
81c29ce4
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436 case 1:
437 ptrptr = PCIR_CAP_PTR;
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438 break;
439 case 2:
81c29ce4 440 ptrptr = PCIR_CAP_PTR_2;
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441 break;
442 default:
443 return; /* no extended capabilities support */
444 }
445 nextptr = REG(ptrptr, 1); /* sanity check? */
446
447 /*
448 * Read capability entries.
449 */
450 while (nextptr != 0) {
451 /* Sanity check */
452 if (nextptr > 255) {
85f8e2ea 453 kprintf("illegal PCI extended capability offset %d\n",
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454 nextptr);
455 return;
456 }
457 /* Find the next entry */
458 ptr = nextptr;
459 nextptr = REG(ptr + 1, 1);
460
461 /* Process this entry */
462 switch (REG(ptr, 1)) {
81c29ce4 463 case PCIY_PMG: /* PCI power management */
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464 if (cfg->pp_cap == 0) {
465 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
466 cfg->pp_status = ptr + PCIR_POWER_STATUS;
467 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
468 if ((nextptr - ptr) > PCIR_POWER_DATA)
469 cfg->pp_data = ptr + PCIR_POWER_DATA;
470 }
471 break;
472 default:
473 break;
474 }
475 }
476#undef REG
477}
478
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479/* free pcicfgregs structure and all depending data structures */
480
22457186 481int
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482pci_freecfg(struct pci_devinfo *dinfo)
483{
484 struct devlist *devlist_head;
485
486 devlist_head = &pci_devq;
487
488 if (dinfo->cfg.hdrspec != NULL)
efda3bd0 489 kfree(dinfo->cfg.hdrspec, M_DEVBUF);
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490 /* XXX this hasn't been tested */
491 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
efda3bd0 492 kfree(dinfo, M_DEVBUF);
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493
494 /* increment the generation count */
495 pci_generation++;
496
497 /* we're losing one device */
498 pci_numdevs--;
499 return (0);
500}
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501
502
503/*
504 * PCI power manangement
505 */
e126caf1 506int
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507pci_set_powerstate_method(device_t dev, device_t child, int state)
508{
509 struct pci_devinfo *dinfo = device_get_ivars(child);
510 pcicfgregs *cfg = &dinfo->cfg;
511 u_int16_t status;
512 int result;
513
514 if (cfg->pp_cap != 0) {
515 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK;
516 result = 0;
517 switch (state) {
518 case PCI_POWERSTATE_D0:
519 status |= PCIM_PSTAT_D0;
520 break;
521 case PCI_POWERSTATE_D1:
522 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) {
523 status |= PCIM_PSTAT_D1;
524 } else {
525 result = EOPNOTSUPP;
526 }
527 break;
528 case PCI_POWERSTATE_D2:
529 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) {
530 status |= PCIM_PSTAT_D2;
531 } else {
532 result = EOPNOTSUPP;
533 }
534 break;
535 case PCI_POWERSTATE_D3:
536 status |= PCIM_PSTAT_D3;
537 break;
538 default:
539 result = EINVAL;
540 }
541 if (result == 0)
542 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2);
543 } else {
544 result = ENXIO;
545 }
546 return(result);
547}
548
e126caf1 549int
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550pci_get_powerstate_method(device_t dev, device_t child)
551{
552 struct pci_devinfo *dinfo = device_get_ivars(child);
553 pcicfgregs *cfg = &dinfo->cfg;
554 u_int16_t status;
555 int result;
556
557 if (cfg->pp_cap != 0) {
558 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2);
559 switch (status & PCIM_PSTAT_DMASK) {
560 case PCIM_PSTAT_D0:
561 result = PCI_POWERSTATE_D0;
562 break;
563 case PCIM_PSTAT_D1:
564 result = PCI_POWERSTATE_D1;
565 break;
566 case PCIM_PSTAT_D2:
567 result = PCI_POWERSTATE_D2;
568 break;
569 case PCIM_PSTAT_D3:
570 result = PCI_POWERSTATE_D3;
571 break;
572 default:
573 result = PCI_POWERSTATE_UNKNOWN;
574 break;
575 }
576 } else {
577 /* No support, device is always at D0 */
578 result = PCI_POWERSTATE_D0;
579 }
580 return(result);
581}
582
583/*
584 * Some convenience functions for PCI device drivers.
585 */
586
587static __inline void
588pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
589{
590 u_int16_t command;
591
592 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
593 command |= bit;
594 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
595}
596
597static __inline void
598pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
599{
600 u_int16_t command;
601
602 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
603 command &= ~bit;
604 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
605}
606
e126caf1 607int
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608pci_enable_busmaster_method(device_t dev, device_t child)
609{
610 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 611 return(0);
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612}
613
e126caf1 614int
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615pci_disable_busmaster_method(device_t dev, device_t child)
616{
617 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 618 return(0);
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619}
620
e126caf1 621int
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622pci_enable_io_method(device_t dev, device_t child, int space)
623{
e126caf1
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624 uint16_t command;
625 uint16_t bit;
626 char *error;
627
628 bit = 0;
629 error = NULL;
630
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631 switch(space) {
632 case SYS_RES_IOPORT:
e126caf1
MD
633 bit = PCIM_CMD_PORTEN;
634 error = "port";
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635 break;
636 case SYS_RES_MEMORY:
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637 bit = PCIM_CMD_MEMEN;
638 error = "memory";
984263bc 639 break;
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MD
640 default:
641 return(EINVAL);
984263bc 642 }
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MD
643 pci_set_command_bit(dev, child, bit);
644 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
645 if (command & bit)
646 return(0);
647 device_printf(child, "failed to enable %s mapping!\n", error);
648 return(ENXIO);
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649}
650
e126caf1 651int
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652pci_disable_io_method(device_t dev, device_t child, int space)
653{
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MD
654 uint16_t command;
655 uint16_t bit;
656 char *error;
657
658 bit = 0;
659 error = NULL;
660
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661 switch(space) {
662 case SYS_RES_IOPORT:
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663 bit = PCIM_CMD_PORTEN;
664 error = "port";
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665 break;
666 case SYS_RES_MEMORY:
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667 bit = PCIM_CMD_MEMEN;
668 error = "memory";
984263bc 669 break;
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670 default:
671 return (EINVAL);
984263bc 672 }
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673 pci_clear_command_bit(dev, child, bit);
674 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
675 if (command & bit) {
676 device_printf(child, "failed to disable %s mapping!\n", error);
677 return (ENXIO);
678 }
679 return (0);
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680}
681
682/*
683 * This is the user interface to PCI configuration space.
684 */
685
686static int
fef8985e 687pci_open(struct dev_open_args *ap)
984263bc 688{
fef8985e 689 if ((ap->a_oflags & FWRITE) && securelevel > 0) {
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690 return EPERM;
691 }
692 return 0;
693}
694
695static int
fef8985e 696pci_close(struct dev_close_args *ap)
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697{
698 return 0;
699}
700
701/*
702 * Match a single pci_conf structure against an array of pci_match_conf
703 * structures. The first argument, 'matches', is an array of num_matches
704 * pci_match_conf structures. match_buf is a pointer to the pci_conf
705 * structure that will be compared to every entry in the matches array.
706 * This function returns 1 on failure, 0 on success.
707 */
708static int
709pci_conf_match(struct pci_match_conf *matches, int num_matches,
710 struct pci_conf *match_buf)
711{
712 int i;
713
714 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
715 return(1);
716
717 for (i = 0; i < num_matches; i++) {
718 /*
719 * I'm not sure why someone would do this...but...
720 */
721 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
722 continue;
723
724 /*
725 * Look at each of the match flags. If it's set, do the
726 * comparison. If the comparison fails, we don't have a
727 * match, go on to the next item if there is one.
728 */
729 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
730 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
731 continue;
732
733 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
734 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
735 continue;
736
737 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
738 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
739 continue;
740
741 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
742 && (match_buf->pc_vendor != matches[i].pc_vendor))
743 continue;
744
745 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
746 && (match_buf->pc_device != matches[i].pc_device))
747 continue;
748
749 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
750 && (match_buf->pc_class != matches[i].pc_class))
751 continue;
752
753 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
754 && (match_buf->pd_unit != matches[i].pd_unit))
755 continue;
756
757 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
758 && (strncmp(matches[i].pd_name, match_buf->pd_name,
759 sizeof(match_buf->pd_name)) != 0))
760 continue;
761
762 return(0);
763 }
764
765 return(1);
766}
767
768/*
769 * Locate the parent of a PCI device by scanning the PCI devlist
770 * and return the entry for the parent.
771 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
772 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
773 */
774
775pcicfgregs *
776pci_devlist_get_parent(pcicfgregs *cfg)
777{
778 struct devlist *devlist_head;
779 struct pci_devinfo *dinfo;
780 pcicfgregs *bridge_cfg;
781 int i;
782
783 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
784
785 /* If the device is on PCI bus 0, look for the host */
786 if (cfg->bus == 0) {
787 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
788 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
789 bridge_cfg = &dinfo->cfg;
790 if (bridge_cfg->baseclass == PCIC_BRIDGE
791 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
792 && bridge_cfg->bus == cfg->bus) {
793 return bridge_cfg;
794 }
795 }
796 }
797
798 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
799 if (cfg->bus > 0) {
800 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
801 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
802 bridge_cfg = &dinfo->cfg;
803 if (bridge_cfg->baseclass == PCIC_BRIDGE
804 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
805 && bridge_cfg->secondarybus == cfg->bus) {
806 return bridge_cfg;
807 }
808 }
809 }
810
811 return NULL;
812}
813
814static int
fef8985e 815pci_ioctl(struct dev_ioctl_args *ap)
984263bc 816{
4a5a2d63 817 device_t pci, pcib;
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818 struct pci_io *io;
819 const char *name;
820 int error;
821
fef8985e 822 if (!(ap->a_fflag & FWRITE))
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823 return EPERM;
824
fef8985e 825 switch(ap->a_cmd) {
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826 case PCIOCGETCONF:
827 {
828 struct pci_devinfo *dinfo;
829 struct pci_conf_io *cio;
830 struct devlist *devlist_head;
831 struct pci_match_conf *pattern_buf;
832 int num_patterns;
833 size_t iolen;
834 int ionum, i;
835
fef8985e 836 cio = (struct pci_conf_io *)ap->a_data;
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837
838 num_patterns = 0;
839 dinfo = NULL;
840
841 /*
842 * Hopefully the user won't pass in a null pointer, but it
843 * can't hurt to check.
844 */
845 if (cio == NULL) {
846 error = EINVAL;
847 break;
848 }
849
850 /*
851 * If the user specified an offset into the device list,
852 * but the list has changed since they last called this
853 * ioctl, tell them that the list has changed. They will
854 * have to get the list from the beginning.
855 */
856 if ((cio->offset != 0)
857 && (cio->generation != pci_generation)){
858 cio->num_matches = 0;
859 cio->status = PCI_GETCONF_LIST_CHANGED;
860 error = 0;
861 break;
862 }
863
864 /*
865 * Check to see whether the user has asked for an offset
866 * past the end of our list.
867 */
868 if (cio->offset >= pci_numdevs) {
869 cio->num_matches = 0;
870 cio->status = PCI_GETCONF_LAST_DEVICE;
871 error = 0;
872 break;
873 }
874
875 /* get the head of the device queue */
876 devlist_head = &pci_devq;
877
878 /*
879 * Determine how much room we have for pci_conf structures.
880 * Round the user's buffer size down to the nearest
881 * multiple of sizeof(struct pci_conf) in case the user
882 * didn't specify a multiple of that size.
883 */
884 iolen = min(cio->match_buf_len -
885 (cio->match_buf_len % sizeof(struct pci_conf)),
886 pci_numdevs * sizeof(struct pci_conf));
887
888 /*
889 * Since we know that iolen is a multiple of the size of
890 * the pciconf union, it's okay to do this.
891 */
892 ionum = iolen / sizeof(struct pci_conf);
893
894 /*
895 * If this test is true, the user wants the pci_conf
896 * structures returned to match the supplied entries.
897 */
898 if ((cio->num_patterns > 0)
899 && (cio->pat_buf_len > 0)) {
900 /*
901 * pat_buf_len needs to be:
902 * num_patterns * sizeof(struct pci_match_conf)
903 * While it is certainly possible the user just
904 * allocated a large buffer, but set the number of
905 * matches correctly, it is far more likely that
906 * their kernel doesn't match the userland utility
907 * they're using. It's also possible that the user
908 * forgot to initialize some variables. Yes, this
909 * may be overly picky, but I hazard to guess that
910 * it's far more likely to just catch folks that
911 * updated their kernel but not their userland.
912 */
913 if ((cio->num_patterns *
914 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
915 /* The user made a mistake, return an error*/
916 cio->status = PCI_GETCONF_ERROR;
85f8e2ea 917 kprintf("pci_ioctl: pat_buf_len %d != "
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918 "num_patterns (%d) * sizeof(struct "
919 "pci_match_conf) (%d)\npci_ioctl: "
920 "pat_buf_len should be = %d\n",
921 cio->pat_buf_len, cio->num_patterns,
922 (int)sizeof(struct pci_match_conf),
923 (int)sizeof(struct pci_match_conf) *
924 cio->num_patterns);
85f8e2ea 925 kprintf("pci_ioctl: do your headers match your "
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MD
926 "kernel?\n");
927 cio->num_matches = 0;
928 error = EINVAL;
929 break;
930 }
931
932 /*
933 * Check the user's buffer to make sure it's readable.
934 */
935 if (!useracc((caddr_t)cio->patterns,
936 cio->pat_buf_len, VM_PROT_READ)) {
85f8e2ea 937 kprintf("pci_ioctl: pattern buffer %p, "
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MD
938 "length %u isn't user accessible for"
939 " READ\n", cio->patterns,
940 cio->pat_buf_len);
941 error = EACCES;
942 break;
943 }
944 /*
945 * Allocate a buffer to hold the patterns.
946 */
efda3bd0 947 pattern_buf = kmalloc(cio->pat_buf_len, M_TEMP,
984263bc
MD
948 M_WAITOK);
949 error = copyin(cio->patterns, pattern_buf,
950 cio->pat_buf_len);
951 if (error != 0)
952 break;
953 num_patterns = cio->num_patterns;
954
955 } else if ((cio->num_patterns > 0)
956 || (cio->pat_buf_len > 0)) {
957 /*
958 * The user made a mistake, spit out an error.
959 */
960 cio->status = PCI_GETCONF_ERROR;
961 cio->num_matches = 0;
85f8e2ea 962 kprintf("pci_ioctl: invalid GETCONF arguments\n");
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963 error = EINVAL;
964 break;
965 } else
966 pattern_buf = NULL;
967
968 /*
969 * Make sure we can write to the match buffer.
970 */
971 if (!useracc((caddr_t)cio->matches,
972 cio->match_buf_len, VM_PROT_WRITE)) {
85f8e2ea 973 kprintf("pci_ioctl: match buffer %p, length %u "
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974 "isn't user accessible for WRITE\n",
975 cio->matches, cio->match_buf_len);
976 error = EACCES;
977 break;
978 }
979
980 /*
981 * Go through the list of devices and copy out the devices
982 * that match the user's criteria.
983 */
984 for (cio->num_matches = 0, error = 0, i = 0,
985 dinfo = STAILQ_FIRST(devlist_head);
986 (dinfo != NULL) && (cio->num_matches < ionum)
987 && (error == 0) && (i < pci_numdevs);
988 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
989
990 if (i < cio->offset)
991 continue;
992
993 /* Populate pd_name and pd_unit */
994 name = NULL;
995 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
996 name = device_get_name(dinfo->cfg.dev);
997 if (name) {
998 strncpy(dinfo->conf.pd_name, name,
999 sizeof(dinfo->conf.pd_name));
1000 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
1001 dinfo->conf.pd_unit =
1002 device_get_unit(dinfo->cfg.dev);
1003 }
1004
1005 if ((pattern_buf == NULL) ||
1006 (pci_conf_match(pattern_buf, num_patterns,
1007 &dinfo->conf) == 0)) {
1008
1009 /*
1010 * If we've filled up the user's buffer,
1011 * break out at this point. Since we've
1012 * got a match here, we'll pick right back
1013 * up at the matching entry. We can also
1014 * tell the user that there are more matches
1015 * left.
1016 */
1017 if (cio->num_matches >= ionum)
1018 break;
1019
1020 error = copyout(&dinfo->conf,
1021 &cio->matches[cio->num_matches],
1022 sizeof(struct pci_conf));
1023 cio->num_matches++;
1024 }
1025 }
1026
1027 /*
1028 * Set the pointer into the list, so if the user is getting
1029 * n records at a time, where n < pci_numdevs,
1030 */
1031 cio->offset = i;
1032
1033 /*
1034 * Set the generation, the user will need this if they make
1035 * another ioctl call with offset != 0.
1036 */
1037 cio->generation = pci_generation;
1038
1039 /*
1040 * If this is the last device, inform the user so he won't
1041 * bother asking for more devices. If dinfo isn't NULL, we
1042 * know that there are more matches in the list because of
1043 * the way the traversal is done.
1044 */
1045 if (dinfo == NULL)
1046 cio->status = PCI_GETCONF_LAST_DEVICE;
1047 else
1048 cio->status = PCI_GETCONF_MORE_DEVS;
1049
1050 if (pattern_buf != NULL)
efda3bd0 1051 kfree(pattern_buf, M_TEMP);
984263bc
MD
1052
1053 break;
1054 }
1055 case PCIOCREAD:
fef8985e 1056 io = (struct pci_io *)ap->a_data;
984263bc 1057 switch(io->pi_width) {
984263bc
MD
1058 case 4:
1059 case 2:
1060 case 1:
4a5a2d63
JS
1061 /*
1062 * Assume that the user-level bus number is
1063 * actually the pciN instance number. We map
1064 * from that to the real pcib+bus combination.
1065 */
1066 pci = devclass_get_device(pci_devclass,
1067 io->pi_sel.pc_bus);
1068 if (pci) {
2581072f
MD
1069 /*
1070 * pci is the pci device and may contain
1071 * several children (for each function code).
1072 * The governing pci bus is the parent to
1073 * the pci device.
1074 */
1075 int b;
1076
4a5a2d63 1077 pcib = device_get_parent(pci);
2581072f 1078 b = pcib_get_bus(pcib);
4a5a2d63
JS
1079 io->pi_data =
1080 PCIB_READ_CONFIG(pcib,
1081 b,
1082 io->pi_sel.pc_dev,
1083 io->pi_sel.pc_func,
1084 io->pi_reg,
1085 io->pi_width);
1086 error = 0;
1087 } else {
1088 error = ENODEV;
1089 }
984263bc
MD
1090 break;
1091 default:
1092 error = ENODEV;
1093 break;
1094 }
1095 break;
1096
1097 case PCIOCWRITE:
fef8985e 1098 io = (struct pci_io *)ap->a_data;
984263bc 1099 switch(io->pi_width) {
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MD
1100 case 4:
1101 case 2:
1102 case 1:
4a5a2d63
JS
1103 /*
1104 * Assume that the user-level bus number is
1105 * actually the pciN instance number. We map
1106 * from that to the real pcib+bus combination.
1107 */
1108 pci = devclass_get_device(pci_devclass,
1109 io->pi_sel.pc_bus);
1110 if (pci) {
2581072f
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1111 /*
1112 * pci is the pci device and may contain
1113 * several children (for each function code).
1114 * The governing pci bus is the parent to
1115 * the pci device.
1116 */
1117 int b;
1118
4a5a2d63 1119 pcib = device_get_parent(pci);
2581072f 1120 b = pcib_get_bus(pcib);
4a5a2d63
JS
1121 PCIB_WRITE_CONFIG(pcib,
1122 b,
1123 io->pi_sel.pc_dev,
1124 io->pi_sel.pc_func,
1125 io->pi_reg,
1126 io->pi_data,
1127 io->pi_width);
1128 error = 0;
1129 } else {
1130 error = ENODEV;
1131 }
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MD
1132 break;
1133 default:
1134 error = ENODEV;
1135 break;
1136 }
1137 break;
1138
1139 default:
1140 error = ENOTTY;
1141 break;
1142 }
1143
1144 return (error);
1145}
1146
1147#define PCI_CDEV 78
1148
fef8985e
MD
1149static struct dev_ops pcic_ops = {
1150 { "pci", PCI_CDEV, 0 },
1151 .d_open = pci_open,
1152 .d_close = pci_close,
1153 .d_ioctl = pci_ioctl,
984263bc
MD
1154};
1155
1156#include "pci_if.h"
1157
984263bc
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1158/*
1159 * New style pci driver. Parent device is either a pci-host-bridge or a
1160 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1161 */
ed1bd994
MD
1162const char *
1163pci_class_to_string(int baseclass)
1164{
1165 const char *name;
1166
1167 switch(baseclass) {
1168 case PCIC_OLD:
1169 name = "OLD";
1170 break;
1171 case PCIC_STORAGE:
1172 name = "STORAGE";
1173 break;
1174 case PCIC_NETWORK:
1175 name = "NETWORK";
1176 break;
1177 case PCIC_DISPLAY:
1178 name = "DISPLAY";
1179 break;
1180 case PCIC_MULTIMEDIA:
1181 name = "MULTIMEDIA";
1182 break;
1183 case PCIC_MEMORY:
1184 name = "MEMORY";
1185 break;
1186 case PCIC_BRIDGE:
1187 name = "BRIDGE";
1188 break;
1189 case PCIC_SIMPLECOMM:
1190 name = "SIMPLECOMM";
1191 break;
1192 case PCIC_BASEPERIPH:
1193 name = "BASEPERIPH";
1194 break;
1195 case PCIC_INPUTDEV:
1196 name = "INPUTDEV";
1197 break;
1198 case PCIC_DOCKING:
1199 name = "DOCKING";
1200 break;
1201 case PCIC_PROCESSOR:
1202 name = "PROCESSOR";
1203 break;
1204 case PCIC_SERIALBUS:
1205 name = "SERIALBUS";
1206 break;
1207 case PCIC_WIRELESS:
1208 name = "WIRELESS";
1209 break;
1210 case PCIC_I2O:
1211 name = "I20";
1212 break;
1213 case PCIC_SATELLITE:
1214 name = "SATELLITE";
1215 break;
1216 case PCIC_CRYPTO:
1217 name = "CRYPTO";
1218 break;
1219 case PCIC_SIGPROC:
1220 name = "SIGPROC";
1221 break;
1222 case PCIC_OTHER:
1223 name = "OTHER";
1224 break;
1225 default:
1226 name = "?";
1227 break;
1228 }
1229 return(name);
1230}
984263bc 1231
22457186 1232void
984263bc
MD
1233pci_print_verbose(struct pci_devinfo *dinfo)
1234{
1235 if (bootverbose) {
1236 pcicfgregs *cfg = &dinfo->cfg;
1237
85f8e2ea 1238 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
984263bc 1239 cfg->vendor, cfg->device, cfg->revid);
85f8e2ea 1240 kprintf("\tbus=%d, slot=%d, func=%d\n",
4a5a2d63 1241 cfg->bus, cfg->slot, cfg->func);
85f8e2ea 1242 kprintf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
ed1bd994 1243 pci_class_to_string(cfg->baseclass),
984263bc
MD
1244 cfg->baseclass, cfg->subclass, cfg->progif,
1245 cfg->hdrtype, cfg->mfdev);
85f8e2ea 1246 kprintf("\tsubordinatebus=%x \tsecondarybus=%x\n",
984263bc
MD
1247 cfg->subordinatebus, cfg->secondarybus);
1248#ifdef PCI_DEBUG
85f8e2ea 1249 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
984263bc 1250 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
85f8e2ea 1251 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
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MD
1252 cfg->lattimer, cfg->lattimer * 30,
1253 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1254#endif /* PCI_DEBUG */
1255 if (cfg->intpin > 0)
85f8e2ea 1256 kprintf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
984263bc
MD
1257 }
1258}
1259
1260static int
4a5a2d63 1261pci_porten(device_t pcib, int b, int s, int f)
984263bc 1262{
4a5a2d63
JS
1263 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1264 & PCIM_CMD_PORTEN) != 0;
984263bc
MD
1265}
1266
1267static int
4a5a2d63 1268pci_memen(device_t pcib, int b, int s, int f)
984263bc 1269{
4a5a2d63
JS
1270 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1271 & PCIM_CMD_MEMEN) != 0;
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MD
1272}
1273
1274/*
1275 * Add a resource based on a pci map register. Return 1 if the map
1276 * register is a 32bit map register or 2 if it is a 64bit register.
1277 */
1278static int
4a5a2d63
JS
1279pci_add_map(device_t pcib, int b, int s, int f, int reg,
1280 struct resource_list *rl)
984263bc 1281{
984263bc
MD
1282 u_int32_t map;
1283 u_int64_t base;
1284 u_int8_t ln2size;
1285 u_int8_t ln2range;
1286 u_int32_t testval;
4a5a2d63
JS
1287
1288
1289#ifdef PCI_ENABLE_IO_MODES
1290 u_int16_t cmd;
1291#endif
984263bc
MD
1292 int type;
1293
4a5a2d63 1294 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
984263bc
MD
1295
1296 if (map == 0 || map == 0xffffffff)
1297 return 1; /* skip invalid entry */
1298
4a5a2d63
JS
1299 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1300 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1301 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
984263bc
MD
1302
1303 base = pci_mapbase(map);
1304 if (pci_maptype(map) & PCI_MAPMEM)
1305 type = SYS_RES_MEMORY;
1306 else
1307 type = SYS_RES_IOPORT;
1308 ln2size = pci_mapsize(testval);
1309 ln2range = pci_maprange(testval);
1310 if (ln2range == 64) {
1311 /* Read the other half of a 64bit map register */
4a5a2d63 1312 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
984263bc
MD
1313 }
1314
984263bc
MD
1315 /*
1316 * This code theoretically does the right thing, but has
1317 * undesirable side effects in some cases where
1318 * peripherals respond oddly to having these bits
1319 * enabled. Leave them alone by default.
1320 */
1321#ifdef PCI_ENABLE_IO_MODES
4a5a2d63
JS
1322 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1323 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1324 cmd |= PCIM_CMD_PORTEN;
1325 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc 1326 }
4a5a2d63
JS
1327 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1328 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1329 cmd |= PCIM_CMD_MEMEN;
1330 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc
MD
1331 }
1332#else
4a5a2d63 1333 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
984263bc 1334 return 1;
4a5a2d63 1335 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
984263bc
MD
1336 return 1;
1337#endif
1338
1339 resource_list_add(rl, type, reg,
1340 base, base + (1 << ln2size) - 1,
1341 (1 << ln2size));
1342
1343 if (bootverbose) {
85f8e2ea 1344 kprintf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
984263bc
MD
1345 reg, pci_maptype(base), ln2range,
1346 (unsigned int) base, ln2size);
1347 }
1348
1349 return (ln2range == 64) ? 2 : 1;
1350}
1351
201eb0a7
TS
1352#ifdef PCI_MAP_FIXUP
1353/*
1354 * For ATA devices we need to decide early on what addressing mode to use.
1355 * Legacy demands that the primary and secondary ATA ports sits on the
1356 * same addresses that old ISA hardware did. This dictates that we use
1357 * those addresses and ignore the BARs if we cannot set PCI native
1358 * addressing mode.
1359 */
1360static void
1361pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, int s, int f,
1362 struct resource_list *rl)
1363{
1364 int rid, type, progif;
1365#if 0
1366 /* if this device supports PCI native addressing use it */
1367 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1368 if ((progif &0x8a) == 0x8a) {
1369 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
1370 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
85f8e2ea 1371 kprintf("Trying ATA native PCI addressing mode\n");
201eb0a7
TS
1372 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
1373 }
1374 }
1375#endif
1376 /*
1377 * Because we return any preallocated resources for lazy
1378 * allocation for PCI devices in pci_alloc_resource(), we can
1379 * allocate our legacy resources here.
1380 */
1381 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1382 type = SYS_RES_IOPORT;
1383 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
1384 pci_add_map(pcib, b, s, f, PCIR_BAR(0), rl);
1385 pci_add_map(pcib, b, s, f, PCIR_BAR(1), rl);
1386 } else {
1387 rid = PCIR_BAR(0);
1388 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
1389 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
1390 0);
1391 rid = PCIR_BAR(1);
1392 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
1393 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
1394 0);
1395 }
1396 if (progif & PCIP_STORAGE_IDE_MODESEC) {
1397 pci_add_map(pcib, b, s, f, PCIR_BAR(2), rl);
1398 pci_add_map(pcib, b, s, f, PCIR_BAR(3), rl);
1399 } else {
1400 rid = PCIR_BAR(2);
1401 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
1402 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
1403 0);
1404 rid = PCIR_BAR(3);
1405 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
1406 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
1407 0);
1408 }
1409 pci_add_map(pcib, b, s, f, PCIR_BAR(4), rl);
1410 pci_add_map(pcib, b, s, f, PCIR_BAR(5), rl);
1411}
1412#endif /* PCI_MAP_FIXUP */
1413
984263bc 1414static void
e126caf1 1415pci_add_resources(device_t pcib, device_t bus, device_t dev)
984263bc
MD
1416{
1417 struct pci_devinfo *dinfo = device_get_ivars(dev);
4a5a2d63 1418 pcicfgregs *cfg = &dinfo->cfg;
984263bc
MD
1419 struct resource_list *rl = &dinfo->resources;
1420 struct pci_quirk *q;
e126caf1
MD
1421 int b, i, f, s;
1422#if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */
1423 int irq;
1424#endif
984263bc 1425
e126caf1
MD
1426 b = cfg->bus;
1427 s = cfg->slot;
1428 f = cfg->func;
201eb0a7
TS
1429#ifdef PCI_MAP_FIXUP
1430 /* atapci devices in legacy mode need special map treatment */
1431 if ((pci_get_class(dev) == PCIC_STORAGE) &&
1432 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
d3d1ea7a
MD
1433 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
1434 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
1435 !pci_read_config(dev, PCIR_BAR(2), 4))) )
201eb0a7
TS
1436 pci_ata_maps(pcib, bus, dev, b, s, f, rl);
1437 else
1438#endif /* PCI_MAP_FIXUP */
1439 for (i = 0; i < cfg->nummaps;) {
1440 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl);
1441 }
984263bc
MD
1442
1443 for (q = &pci_quirks[0]; q->devid; q++) {
1444 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1445 && q->type == PCI_QUIRK_MAP_REG)
4a5a2d63 1446 pci_add_map(pcib, b, s, f, q->arg1, rl);
984263bc
MD
1447 }
1448
1449 if (cfg->intpin > 0 && cfg->intline != 255)
1450 resource_list_add(rl, SYS_RES_IRQ, 0,
1451 cfg->intline, cfg->intline, 1);
1452}
1453
e126caf1
MD
1454void
1455pci_add_children(device_t dev, int busno, size_t dinfo_size)
984263bc 1456{
e126caf1 1457#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
4a5a2d63 1458 device_t pcib = device_get_parent(dev);
e126caf1 1459 struct pci_devinfo *dinfo;
4a5a2d63 1460 int maxslots;
e126caf1
MD
1461 int s, f, pcifunchigh;
1462 uint8_t hdrtype;
1463
1464 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo));
984263bc 1465
4a5a2d63 1466 maxslots = PCIB_MAXSLOTS(pcib);
984263bc 1467
57e943f7 1468 for (s = 0; s <= maxslots; s++) {
e126caf1
MD
1469 pcifunchigh = 0;
1470 f = 0;
1471 hdrtype = REG(PCIR_HDRTYPE, 1);
1472 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1473 continue;
1474 if (hdrtype & PCIM_MFDEV)
1475 pcifunchigh = PCI_FUNCMAX;
5e658043 1476 for (f = 0; f <= pcifunchigh; f++) {
e126caf1 1477 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
984263bc 1478 if (dinfo != NULL) {
e126caf1 1479 pci_add_child(dev, dinfo);
984263bc
MD
1480 }
1481 }
1482 }
e126caf1
MD
1483#undef REG
1484}
1485
2581072f
MD
1486/*
1487 * The actual PCI child that we add has a NULL driver whos parent
1488 * device will be "pci". The child contains the ivars, not the parent.
1489 */
e126caf1
MD
1490void
1491pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1492{
1493 device_t pcib;
1494
1495 pcib = device_get_parent(bus);
1496 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1497 device_set_ivars(dinfo->cfg.dev, dinfo);
1498 pci_add_resources(pcib, bus, dinfo->cfg.dev);
1499 pci_print_verbose(dinfo);
984263bc
MD
1500}
1501
c01b8d84
MD
1502/*
1503 * Probe the PCI bus. Note: probe code is not supposed to add children
1504 * or call attach.
1505 */
984263bc 1506static int
4a5a2d63 1507pci_probe(device_t dev)
984263bc 1508{
984263bc 1509 device_set_desc(dev, "PCI bus");
4a5a2d63 1510
c01b8d84
MD
1511 /* Allow other subclasses to override this driver */
1512 return(-1000);
984263bc
MD
1513}
1514
e126caf1
MD
1515static int
1516pci_attach(device_t dev)
1517{
1518 int busno;
e4c9c0c8
MD
1519 int lunit = device_get_unit(dev);
1520
fef8985e
MD
1521 dev_ops_add(&pcic_ops, -1, lunit);
1522 make_dev(&pcic_ops, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit);
e126caf1
MD
1523
1524 /*
1525 * Since there can be multiple independantly numbered PCI
1526 * busses on some large alpha systems, we can't use the unit
1527 * number to decide what bus we are probing. We ask the parent
1528 * pcib what our bus number is.
2581072f
MD
1529 *
1530 * pcib_get_bus() must act on the pci bus device, not on the pci
1531 * device, because it uses badly hacked nexus-based ivars to
1532 * store and retrieve the physical bus number. XXX
e126caf1 1533 */
2581072f 1534 busno = pcib_get_bus(device_get_parent(dev));
e126caf1 1535 if (bootverbose)
ed1bd994 1536 device_printf(dev, "pci_attach() physical bus=%d\n", busno);
e126caf1
MD
1537
1538 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1539
1540 return (bus_generic_attach(dev));
1541}
1542
984263bc
MD
1543static int
1544pci_print_resources(struct resource_list *rl, const char *name, int type,
1545 const char *format)
1546{
1547 struct resource_list_entry *rle;
1548 int printed, retval;
1549
1550 printed = 0;
1551 retval = 0;
1552 /* Yes, this is kinda cheating */
1553 SLIST_FOREACH(rle, rl, link) {
1554 if (rle->type == type) {
1555 if (printed == 0)
85f8e2ea 1556 retval += kprintf(" %s ", name);
984263bc 1557 else if (printed > 0)
85f8e2ea 1558 retval += kprintf(",");
984263bc 1559 printed++;
85f8e2ea 1560 retval += kprintf(format, rle->start);
984263bc 1561 if (rle->count > 1) {
85f8e2ea
SW
1562 retval += kprintf("-");
1563 retval += kprintf(format, rle->start +
984263bc
MD
1564 rle->count - 1);
1565 }
1566 }
1567 }
1568 return retval;
1569}
1570
e126caf1 1571int
984263bc
MD
1572pci_print_child(device_t dev, device_t child)
1573{
1574 struct pci_devinfo *dinfo;
1575 struct resource_list *rl;
1576 pcicfgregs *cfg;
1577 int retval = 0;
1578
1579 dinfo = device_get_ivars(child);
1580 cfg = &dinfo->cfg;
1581 rl = &dinfo->resources;
1582
1583 retval += bus_print_child_header(dev, child);
1584
1585 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1586 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1587 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1588 if (device_get_flags(dev))
85f8e2ea 1589 retval += kprintf(" flags %#x", device_get_flags(dev));
984263bc 1590
85f8e2ea 1591 retval += kprintf(" at device %d.%d", pci_get_slot(child),
984263bc
MD
1592 pci_get_function(child));
1593
1594 retval += bus_print_child_footer(dev, child);
1595
1596 return (retval);
1597}
1598
e126caf1 1599void
984263bc
MD
1600pci_probe_nomatch(device_t dev, device_t child)
1601{
1602 struct pci_devinfo *dinfo;
1603 pcicfgregs *cfg;
1604 const char *desc;
1605 int unknown;
1606
1607 unknown = 0;
1608 dinfo = device_get_ivars(child);
1609 cfg = &dinfo->cfg;
1610 desc = pci_ata_match(child);
1611 if (!desc) desc = pci_usb_match(child);
1612 if (!desc) desc = pci_vga_match(child);
27c23c6b 1613 if (!desc) desc = pci_chip_match(child);
984263bc
MD
1614 if (!desc) {
1615 desc = "unknown card";
1616 unknown++;
1617 }
1618 device_printf(dev, "<%s>", desc);
1619 if (bootverbose || unknown) {
85f8e2ea 1620 kprintf(" (vendor=0x%04x, dev=0x%04x)",
984263bc
MD
1621 cfg->vendor,
1622 cfg->device);
1623 }
85f8e2ea 1624 kprintf(" at %d.%d",
984263bc
MD
1625 pci_get_slot(child),
1626 pci_get_function(child));
1627 if (cfg->intpin > 0 && cfg->intline != 255) {
85f8e2ea 1628 kprintf(" irq %d", cfg->intline);
984263bc 1629 }
85f8e2ea 1630 kprintf("\n");
984263bc
MD
1631
1632 return;
1633}
1634
22457186 1635int
4a5a2d63 1636pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
984263bc
MD
1637{
1638 struct pci_devinfo *dinfo;
1639 pcicfgregs *cfg;
1640
1641 dinfo = device_get_ivars(child);
1642 cfg = &dinfo->cfg;
1643
1644 switch (which) {
1645 case PCI_IVAR_SUBVENDOR:
1646 *result = cfg->subvendor;
1647 break;
1648 case PCI_IVAR_SUBDEVICE:
1649 *result = cfg->subdevice;
1650 break;
1651 case PCI_IVAR_VENDOR:
1652 *result = cfg->vendor;
1653 break;
1654 case PCI_IVAR_DEVICE:
1655 *result = cfg->device;
1656 break;
1657 case PCI_IVAR_DEVID:
1658 *result = (cfg->device << 16) | cfg->vendor;
1659 break;
1660 case PCI_IVAR_CLASS:
1661 *result = cfg->baseclass;
1662 break;
1663 case PCI_IVAR_SUBCLASS:
1664 *result = cfg->subclass;
1665 break;
1666 case PCI_IVAR_PROGIF:
1667 *result = cfg->progif;
1668 break;
1669 case PCI_IVAR_REVID:
1670 *result = cfg->revid;
1671 break;
1672 case PCI_IVAR_INTPIN:
1673 *result = cfg->intpin;
1674 break;
1675 case PCI_IVAR_IRQ:
1676 *result = cfg->intline;
1677 break;
1678 case PCI_IVAR_BUS:
1679 *result = cfg->bus;
1680 break;
1681 case PCI_IVAR_SLOT:
1682 *result = cfg->slot;
1683 break;
1684 case PCI_IVAR_FUNCTION:
1685 *result = cfg->func;
1686 break;
1687 case PCI_IVAR_SECONDARYBUS:
1688 *result = cfg->secondarybus;
1689 break;
1690 case PCI_IVAR_SUBORDINATEBUS:
1691 *result = cfg->subordinatebus;
1692 break;
f72d3d23
JS
1693 case PCI_IVAR_ETHADDR:
1694 /*
1695 * The generic accessor doesn't deal with failure, so
1696 * we set the return value, then return an error.
1697 */
1698 *result = NULL;
1699 return (EINVAL);
984263bc
MD
1700 default:
1701 return ENOENT;
1702 }
1703 return 0;
1704}
1705
22457186 1706int
984263bc
MD
1707pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1708{
1709 struct pci_devinfo *dinfo;
1710 pcicfgregs *cfg;
1711
1712 dinfo = device_get_ivars(child);
1713 cfg = &dinfo->cfg;
1714
1715 switch (which) {
1716 case PCI_IVAR_SUBVENDOR:
1717 case PCI_IVAR_SUBDEVICE:
1718 case PCI_IVAR_VENDOR:
1719 case PCI_IVAR_DEVICE:
1720 case PCI_IVAR_DEVID:
1721 case PCI_IVAR_CLASS:
1722 case PCI_IVAR_SUBCLASS:
1723 case PCI_IVAR_PROGIF:
1724 case PCI_IVAR_REVID:
1725 case PCI_IVAR_INTPIN:
1726 case PCI_IVAR_IRQ:
1727 case PCI_IVAR_BUS:
1728 case PCI_IVAR_SLOT:
1729 case PCI_IVAR_FUNCTION:
f72d3d23 1730 case PCI_IVAR_ETHADDR:
984263bc
MD
1731 return EINVAL; /* disallow for now */
1732
1733 case PCI_IVAR_SECONDARYBUS:
1734 cfg->secondarybus = value;
1735 break;
1736 case PCI_IVAR_SUBORDINATEBUS:
1737 cfg->subordinatebus = value;
1738 break;
1739 default:
1740 return ENOENT;
1741 }
1742 return 0;
1743}
1744
201eb0a7
TS
1745#ifdef PCI_MAP_FIXUP
1746static struct resource *
1747pci_alloc_map(device_t dev, device_t child, int type, int *rid, u_long start,
1748 u_long end, u_long count, u_int flags)
1749{
1750 struct pci_devinfo *dinfo = device_get_ivars(child);
1751 struct resource_list *rl = &dinfo->resources;
1752 struct resource_list_entry *rle;
1753 struct resource *res;
1754 uint32_t map, testval;
1755 int mapsize;
1756
1757 /*
1758 * Weed out the bogons, and figure out how large the BAR/map
1759 * is. BARs that read back 0 here are bogus and unimplemented.
1760 *
1761 * Note: atapci in legacy mode are special and handled elsewhere
1762 * in the code. If you have an atapci device in legacy mode and
1763 * it fails here, that other code is broken.
1764 */
1765 res = NULL;
1766 map = pci_read_config(child, *rid, 4);
1767 pci_write_config(child, *rid, 0xffffffff, 4);
1768 testval = pci_read_config(child, *rid, 4);
1769 if (pci_mapbase(testval) == 0)
1770 goto out;
1771 if (pci_maptype(testval) & PCI_MAPMEM) {
1772 if (type != SYS_RES_MEMORY) {
1773 if (bootverbose)
1774 device_printf(dev, "child %s requested type %d"
1775 " for rid %#x, but the BAR says "
1776 "it is a memio\n",
1777 device_get_nameunit(child), type,
1778 *rid);
1779 goto out;
1780 }
1781 } else {
1782 if (type != SYS_RES_IOPORT) {
1783 if (bootverbose)
1784 device_printf(dev, "child %s requested type %d"
1785 " for rid %#x, but the BAR says "
1786 "it is an ioport\n",
1787 device_get_nameunit(child), type,
1788 *rid);
1789 goto out;
1790 }
1791 }
1792 /*
1793 * For real BARs, we need to override the size that
1794 * the driver requests, because that's what the BAR
1795 * actually uses and we would otherwise have a
1796 * situation where we might allocate the excess to
1797 * another driver, which won't work.
1798 */
1799 mapsize = pci_mapsize(testval);
1800 count = 1 << mapsize;
1801 if (RF_ALIGNMENT(flags) < mapsize)
1802 flags = (flags & ~RF_ALIGNMENT_MASK) |
1803 RF_ALIGNMENT_LOG2(mapsize);
1804 /*
1805 * Allocate enough resource, and then write back the
1806 * appropriate BAR for that resource.
1807 */
1808 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
1809 start, end, count, flags);
1810 if (res == NULL) {
1811 device_printf(child, "%#lx bytes at rid %#x res %d failed "
1812 "(%#lx, %#lx)\n", count, *rid, type, start, end);
1813 goto out;
1814 }
1815 resource_list_add(rl, type, *rid, start, end, count);
1816 rle = resource_list_find(rl, type, *rid);
1817 if (rle == NULL)
1818 panic("pci_alloc_map: unexpectedly can't find resource.");
1819 rle->res = res;
1820 rle->start = rman_get_start(res);
1821 rle->end = rman_get_end(res);
1822 rle->count = count;
1823 if (bootverbose)
1824 device_printf(child, "lazy allocation of %#lx bytes rid %#x "
1825 "type %d at %#lx\n", count, *rid, type,
1826 rman_get_start(res));
1827 map = rman_get_start(res);
1828out:;
1829 pci_write_config(child, *rid, map, 4);
1830 return res;
1831}
1832#endif /* PCI_MAP_FIXUP */
1833
261fa16d 1834struct resource *
984263bc
MD
1835pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1836 u_long start, u_long end, u_long count, u_int flags)
1837{
1838 struct pci_devinfo *dinfo = device_get_ivars(child);
1839 struct resource_list *rl = &dinfo->resources;
201eb0a7
TS
1840#ifdef PCI_MAP_FIXUP
1841 struct resource_list_entry *rle;
1842#endif /* PCI_MAP_FIXUP */
984263bc 1843 pcicfgregs *cfg = &dinfo->cfg;
de67e43b 1844
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1845 /*
1846 * Perform lazy resource allocation
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1847 */
1848 if (device_get_parent(child) == dev) {
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JS
1849 switch (type) {
1850 case SYS_RES_IRQ:
1851#ifdef __i386__
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1852 /*
1853 * If device doesn't have an interrupt routed, and is
1854 * deserving of an interrupt, try to assign it one.
1855 */
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JS
1856 if ((cfg->intline == 255 || cfg->intline == 0) &&
1857 (cfg->intpin != 0) &&
1858 (start == 0) && (end == ~0UL)) {
1859 cfg->intline = PCIB_ROUTE_INTERRUPT(
1860 device_get_parent(dev), child,
1861 cfg->intpin);
1862 if (cfg->intline != 255) {
1863 pci_write_config(child, PCIR_INTLINE,
1864 cfg->intline, 1);
1865 resource_list_add(rl, SYS_RES_IRQ, 0,
1866 cfg->intline, cfg->intline, 1);
1867 }
1868 }
820c1612 1869 break;
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JS
1870#endif
1871 case SYS_RES_IOPORT:
201eb0a7 1872 /* FALLTHROUGH */
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JS
1873 case SYS_RES_MEMORY:
1874 if (*rid < PCIR_BAR(cfg->nummaps)) {
1875 /*
1876 * Enable the I/O mode. We should
1877 * also be assigning resources too
1878 * when none are present. The
1879 * resource_list_alloc kind of sorta does
1880 * this...
1881 */
1882 if (PCI_ENABLE_IO(dev, child, type))
1883 return (NULL);
984263bc 1884 }
201eb0a7
TS
1885#ifdef PCI_MAP_FIXUP
1886 rle = resource_list_find(rl, type, *rid);
1887 if (rle == NULL)
1888 return pci_alloc_map(dev, child, type, rid,
1889 start, end, count, flags);
1890#endif /* PCI_MAP_FIXUP */
820c1612 1891 break;
984263bc 1892 }
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TS
1893#ifdef PCI_MAP_FIXUP
1894 /*
1895 * If we've already allocated the resource, then
1896 * return it now. But first we may need to activate
1897 * it, since we don't allocate the resource as active
1898 * above. Normally this would be done down in the
1899 * nexus, but since we short-circuit that path we have
1900 * to do its job here. Not sure if we should free the
1901 * resource if it fails to activate.
1902 *
1903 * Note: this also finds and returns resources for
1904 * atapci devices in legacy mode as allocated in
1905 * pci_ata_maps().
1906 */
1907 rle = resource_list_find(rl, type, *rid);
1908 if (rle != NULL && rle->res != NULL) {
1909 if (bootverbose)
1910 device_printf(child, "reserved %#lx bytes for "
1911 "rid %#x type %d at %#lx\n",
1912 rman_get_size(rle->res), *rid,
1913 type, rman_get_start(rle->res));
1914 if ((flags & RF_ACTIVE) &&
1915 bus_generic_activate_resource(dev, child, type,
1916 *rid, rle->res) != 0)
1917 return NULL;
1918 return rle->res;
1919 }
1920#endif /* PCI_MAP_FIXUP */
984263bc 1921 }
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1922 return resource_list_alloc(rl, dev, child, type, rid,
1923 start, end, count, flags);
1924}
1925
1926static int
1927pci_release_resource(device_t dev, device_t child, int type, int rid,
1928 struct resource *r)
1929{
1930 struct pci_devinfo *dinfo = device_get_ivars(child);
1931 struct resource_list *rl = &dinfo->resources;
1932
1933 return resource_list_release(rl, dev, child, type, rid, r);
1934}
1935
1936static int
1937pci_set_resource(device_t dev, device_t child, int type, int rid,
1938 u_long start, u_long count)
1939{
1940 struct pci_devinfo *dinfo = device_get_ivars(child);
1941 struct resource_list *rl = &dinfo->resources;
1942
1943 resource_list_add(rl, type, rid, start, start + count - 1, count);
1944 return 0;
1945}
1946
1947static int
1948pci_get_resource(device_t dev, device_t child, int type, int rid,
1949 u_long *startp, u_long *countp)
1950{
1951 struct pci_devinfo *dinfo = device_get_ivars(child);
1952 struct resource_list *rl = &dinfo->resources;
1953 struct resource_list_entry *rle;
1954
1955 rle = resource_list_find(rl, type, rid);
1956 if (!rle)
1957 return ENOENT;
1958
1959 if (startp)
1960 *startp = rle->start;
1961 if (countp)
1962 *countp = rle->count;
1963
1964 return 0;
1965}
1966
e126caf1 1967void
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1968pci_delete_resource(device_t dev, device_t child, int type, int rid)
1969{
85f8e2ea 1970 kprintf("pci_delete_resource: PCI resources can not be deleted\n");
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MD
1971}
1972
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MD
1973struct resource_list *
1974pci_get_resource_list (device_t dev, device_t child)
1975{
b0486c83 1976 struct pci_devinfo *dinfo = device_get_ivars(child);
e126caf1 1977
b0486c83 1978 if (dinfo == NULL)
e126caf1 1979 return (NULL);
b0486c83 1980 return (&dinfo->resources);
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MD
1981}
1982
1983u_int32_t
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1984pci_read_config_method(device_t dev, device_t child, int reg, int width)
1985{
1986 struct pci_devinfo *dinfo = device_get_ivars(child);
1987 pcicfgregs *cfg = &dinfo->cfg;
4a5a2d63
JS
1988
1989 return PCIB_READ_CONFIG(device_get_parent(dev),
1990 cfg->bus, cfg->slot, cfg->func,
1991 reg, width);
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1992}
1993
e126caf1 1994void
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1995pci_write_config_method(device_t dev, device_t child, int reg,
1996 u_int32_t val, int width)
1997{
1998 struct pci_devinfo *dinfo = device_get_ivars(child);
1999 pcicfgregs *cfg = &dinfo->cfg;
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JS
2000
2001 PCIB_WRITE_CONFIG(device_get_parent(dev),
2002 cfg->bus, cfg->slot, cfg->func,
2003 reg, val, width);
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MD
2004}
2005
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MD
2006int
2007pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
2008 size_t buflen)
2009{
2010 struct pci_devinfo *dinfo;
2011
2012 dinfo = device_get_ivars(child);
f8c7a42d 2013 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
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MD
2014 pci_get_function(child));
2015 return (0);
2016}
2017
2018int
2019pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
2020 size_t buflen)
2021{
2022 struct pci_devinfo *dinfo;
2023 pcicfgregs *cfg;
2024
2025 dinfo = device_get_ivars(child);
2026 cfg = &dinfo->cfg;
f8c7a42d 2027 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
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MD
2028 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
2029 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
2030 cfg->progif);
2031 return (0);
2032}
2033
2034int
2035pci_assign_interrupt_method(device_t dev, device_t child)
2036{
2037 struct pci_devinfo *dinfo = device_get_ivars(child);
2038 pcicfgregs *cfg = &dinfo->cfg;
2039
2040 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
2041 cfg->intpin));
2042}
2043
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2044static int
2045pci_modevent(module_t mod, int what, void *arg)
2046{
2047 switch (what) {
2048 case MOD_LOAD:
2049 STAILQ_INIT(&pci_devq);
2050 break;
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MD
2051 case MOD_UNLOAD:
2052 break;
2053 }
2054
2055 return 0;
2056}
2057
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MD
2058int
2059pci_resume(device_t dev)
2060{
2061 int numdevs;
2062 int i;
2063 device_t *children;
2064 device_t child;
2065 struct pci_devinfo *dinfo;
2066 pcicfgregs *cfg;
2067
2068 device_get_children(dev, &children, &numdevs);
2069
2070 for (i = 0; i < numdevs; i++) {
2071 child = children[i];
2072
2073 dinfo = device_get_ivars(child);
2074 cfg = &dinfo->cfg;
2075 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2076 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
2077 if (PCI_INTERRUPT_VALID(cfg->intline)) {
2078 pci_write_config(child, PCIR_INTLINE,
2079 cfg->intline, 1);
2080 }
2081 }
2082 }
2083
efda3bd0 2084 kfree(children, M_TEMP);
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2085
2086 return (bus_generic_resume(dev));
2087}
2088
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2089static device_method_t pci_methods[] = {
2090 /* Device interface */
4a5a2d63 2091 DEVMETHOD(device_probe, pci_probe),
e126caf1 2092 DEVMETHOD(device_attach, pci_attach),
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2093 DEVMETHOD(device_shutdown, bus_generic_shutdown),
2094 DEVMETHOD(device_suspend, bus_generic_suspend),
e126caf1 2095 DEVMETHOD(device_resume, pci_resume),
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2096
2097 /* Bus interface */
2098 DEVMETHOD(bus_print_child, pci_print_child),
2099 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
2100 DEVMETHOD(bus_read_ivar, pci_read_ivar),
2101 DEVMETHOD(bus_write_ivar, pci_write_ivar),
2102 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
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MD
2103 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
2104 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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MD
2105
2106 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
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MD
2107 DEVMETHOD(bus_set_resource, pci_set_resource),
2108 DEVMETHOD(bus_get_resource, pci_get_resource),
2109 DEVMETHOD(bus_delete_resource, pci_delete_resource),
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2110 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
2111 DEVMETHOD(bus_release_resource, pci_release_resource),
2112 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
2113 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
2114 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
2115 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
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MD
2116
2117 /* PCI interface */
2118 DEVMETHOD(pci_read_config, pci_read_config_method),
2119 DEVMETHOD(pci_write_config, pci_write_config_method),
2120 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
2121 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
2122 DEVMETHOD(pci_enable_io, pci_enable_io_method),
2123 DEVMETHOD(pci_disable_io, pci_disable_io_method),
2124 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
2125 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
e126caf1 2126 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
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MD
2127
2128 { 0, 0 }
2129};
2130
3aef8050 2131driver_t pci_driver = {
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MD
2132 "pci",
2133 pci_methods,
2134 1, /* no softc */
2135};
2136
2137DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
261fa16d 2138MODULE_VERSION(pci, 1);