Create 'k' versions of the kernel malloc API.
[dragonfly.git] / sys / bus / pci / pci.c
CommitLineData
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1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
20df2adc 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.31 2006/08/25 22:37:08 swildner Exp $
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28 *
29 */
30
31#include "opt_bus.h"
32#include "opt_pci.h"
33
34#include "opt_simos.h"
dc5a7bd2 35#include "opt_compat_oldpci.h"
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36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/malloc.h>
40#include <sys/module.h>
41#include <sys/fcntl.h>
42#include <sys/conf.h>
43#include <sys/kernel.h>
44#include <sys/queue.h>
45#include <sys/types.h>
46#include <sys/buf.h>
47
48#include <vm/vm.h>
49#include <vm/pmap.h>
50#include <vm/vm_extern.h>
51
52#include <sys/bus.h>
53#include <machine/bus.h>
54#include <sys/rman.h>
55#include <machine/resource.h>
97359a5b 56#include <machine/smp.h>
984263bc 57#ifdef __i386__
bbca97bc 58#include <bus/pci/i386/pci_cfgreg.h>
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59#endif
60
dc5a7bd2 61#include <sys/pciio.h>
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62#include "pcireg.h"
63#include "pcivar.h"
22457186 64#include "pci_private.h"
984263bc 65
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66#include "pcib_if.h"
67
e126caf1 68devclass_t pci_devclass;
2581072f 69const char *pcib_owner;
dc5a7bd2 70
4a5a2d63 71static void pci_read_extcap(device_t dev, pcicfgregs *cfg);
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72
73struct pci_quirk {
74 u_int32_t devid; /* Vendor/device of the card */
75 int type;
3e4db402 76#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
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77 int arg1;
78 int arg2;
79};
80
81struct pci_quirk pci_quirks[] = {
82 /*
83 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
84 */
85 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
86 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
f1f0bfb2
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87 /* As does the Serverworks OSB4 (the SMBus mapping register) */
88 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
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89
90 { 0 }
91};
92
93/* map register information */
94#define PCI_MAPMEM 0x01 /* memory map */
95#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
96#define PCI_MAPPORT 0x04 /* port map */
97
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98static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
99u_int32_t pci_numdevs = 0;
100static u_int32_t pci_generation = 0;
101
102device_t
103pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func)
104{
105 struct pci_devinfo *dinfo;
106
107 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
108 if ((dinfo->cfg.bus == bus) &&
109 (dinfo->cfg.slot == slot) &&
110 (dinfo->cfg.func == func)) {
111 return (dinfo->cfg.dev);
112 }
113 }
114
115 return (NULL);
116}
117
118device_t
119pci_find_device (u_int16_t vendor, u_int16_t device)
120{
121 struct pci_devinfo *dinfo;
122
123 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
124 if ((dinfo->cfg.vendor == vendor) &&
125 (dinfo->cfg.device == device)) {
126 return (dinfo->cfg.dev);
127 }
128 }
129
130 return (NULL);
131}
132
133/* return base address of memory or port map */
134
135static u_int32_t
136pci_mapbase(unsigned mapreg)
137{
138 int mask = 0x03;
139 if ((mapreg & 0x01) == 0)
140 mask = 0x0f;
141 return (mapreg & ~mask);
142}
143
144/* return map type of memory or port map */
145
146static int
147pci_maptype(unsigned mapreg)
148{
149 static u_int8_t maptype[0x10] = {
150 PCI_MAPMEM, PCI_MAPPORT,
151 PCI_MAPMEM, 0,
152 PCI_MAPMEM, PCI_MAPPORT,
153 0, 0,
154 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
155 PCI_MAPMEM|PCI_MAPMEMP, 0,
156 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
157 0, 0,
158 };
159
160 return maptype[mapreg & 0x0f];
161}
162
163/* return log2 of map size decoded for memory or port map */
164
165static int
166pci_mapsize(unsigned testval)
167{
168 int ln2size;
169
170 testval = pci_mapbase(testval);
171 ln2size = 0;
172 if (testval != 0) {
173 while ((testval & 1) == 0)
174 {
175 ln2size++;
176 testval >>= 1;
177 }
178 }
179 return (ln2size);
180}
181
182/* return log2 of address range supported by map register */
183
184static int
185pci_maprange(unsigned mapreg)
186{
187 int ln2range = 0;
188 switch (mapreg & 0x07) {
189 case 0x00:
190 case 0x01:
191 case 0x05:
192 ln2range = 32;
193 break;
194 case 0x02:
195 ln2range = 20;
196 break;
197 case 0x04:
198 ln2range = 64;
199 break;
200 }
201 return (ln2range);
202}
203
204/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
205
206static void
207pci_fixancient(pcicfgregs *cfg)
208{
209 if (cfg->hdrtype != 0)
210 return;
211
212 /* PCI to PCI bridges use header type 1 */
213 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
214 cfg->hdrtype = 1;
215}
216
217/* read config data specific to header type 1 device (PCI to PCI bridge) */
218
219static void *
4a5a2d63 220pci_readppb(device_t pcib, int b, int s, int f)
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221{
222 pcih1cfgregs *p;
223
4a5a2d63 224 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
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225 if (p == NULL)
226 return (NULL);
227
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228 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
229 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
984263bc 230
4a5a2d63 231 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
984263bc 232
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233 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
234 PCIR_IOBASEH_1, 2),
235 PCIB_READ_CONFIG(pcib, b, s, f,
236 PCIR_IOBASEL_1, 1));
237 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
238 PCIR_IOLIMITH_1, 2),
239 PCIB_READ_CONFIG(pcib, b, s, f,
240 PCIR_IOLIMITL_1, 1));
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241
242 p->membase = PCI_PPBMEMBASE (0,
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243 PCIB_READ_CONFIG(pcib, b, s, f,
244 PCIR_MEMBASE_1, 2));
984263bc 245 p->memlimit = PCI_PPBMEMLIMIT (0,
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246 PCIB_READ_CONFIG(pcib, b, s, f,
247 PCIR_MEMLIMIT_1, 2));
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248
249 p->pmembase = PCI_PPBMEMBASE (
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250 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
251 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
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252
253 p->pmemlimit = PCI_PPBMEMLIMIT (
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254 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
255 PCIR_PMLIMITH_1, 4),
256 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
257
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258 return (p);
259}
260
261/* read config data specific to header type 2 device (PCI to CardBus bridge) */
262
263static void *
4a5a2d63 264pci_readpcb(device_t pcib, int b, int s, int f)
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265{
266 pcih2cfgregs *p;
267
4a5a2d63 268 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
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269 if (p == NULL)
270 return (NULL);
271
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272 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
273 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
984263bc 274
4a5a2d63 275 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
984263bc 276
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277 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
278 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
279 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
280 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
984263bc 281
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282 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
283 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
284 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
285 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
984263bc 286
4a5a2d63 287 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
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288 return p;
289}
290
291/* extract header type specific config data */
292
293static void
4a5a2d63 294pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
984263bc 295{
4a5a2d63 296#define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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297 switch (cfg->hdrtype) {
298 case 0:
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299 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
300 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
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301 cfg->nummaps = PCI_MAXMAPS_0;
302 break;
303 case 1:
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304 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
305 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
306 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
307 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
984263bc 308 cfg->nummaps = PCI_MAXMAPS_1;
4a5a2d63 309 cfg->hdrspec = pci_readppb(pcib, b, s, f);
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310 break;
311 case 2:
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312 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
313 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
314 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
315 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
984263bc 316 cfg->nummaps = PCI_MAXMAPS_2;
4a5a2d63 317 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
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318 break;
319 }
4a5a2d63 320#undef REG
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321}
322
323/* read configuration header into pcicfgrect structure */
324
22457186 325struct pci_devinfo *
c01b8d84 326pci_read_device(device_t pcib, int b, int s, int f, size_t size)
984263bc 327{
4a5a2d63 328#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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329
330 pcicfgregs *cfg = NULL;
331 struct pci_devinfo *devlist_entry;
332 struct devlist *devlist_head;
333
334 devlist_head = &pci_devq;
335
336 devlist_entry = NULL;
337
4a5a2d63 338 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
984263bc 339
c01b8d84 340 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
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341 if (devlist_entry == NULL)
342 return (NULL);
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343
344 cfg = &devlist_entry->cfg;
345
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346 cfg->bus = b;
347 cfg->slot = s;
348 cfg->func = f;
349 cfg->vendor = REG(PCIR_VENDOR, 2);
350 cfg->device = REG(PCIR_DEVICE, 2);
351 cfg->cmdreg = REG(PCIR_COMMAND, 2);
352 cfg->statreg = REG(PCIR_STATUS, 2);
353 cfg->baseclass = REG(PCIR_CLASS, 1);
354 cfg->subclass = REG(PCIR_SUBCLASS, 1);
355 cfg->progif = REG(PCIR_PROGIF, 1);
356 cfg->revid = REG(PCIR_REVID, 1);
e126caf1 357 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
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358 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
359 cfg->lattimer = REG(PCIR_LATTIMER, 1);
360 cfg->intpin = REG(PCIR_INTPIN, 1);
361 cfg->intline = REG(PCIR_INTLINE, 1);
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362
363#ifdef APIC_IO
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364 /*
365 * If using the APIC the intpin is probably wrong, since it
366 * is often setup by the BIOS with the PIC in mind.
367 */
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368 if (cfg->intpin != 0) {
369 int airq;
370
371 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
372 if (airq >= 0) {
373 /* PCI specific entry found in MP table */
374 if (airq != cfg->intline) {
375 undirect_pci_irq(cfg->intline);
376 cfg->intline = airq;
377 }
378 } else {
379 /*
380 * PCI interrupts might be redirected to the
381 * ISA bus according to some MP tables. Use the
382 * same methods as used by the ISA devices
383 * devices to find the proper IOAPIC int pin.
384 */
385 airq = isa_apic_irq(cfg->intline);
386 if ((airq >= 0) && (airq != cfg->intline)) {
387 /* XXX: undirect_pci_irq() ? */
388 undirect_isa_irq(cfg->intline);
389 cfg->intline = airq;
390 }
391 }
392 }
393#endif /* APIC_IO */
394
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395 cfg->mingnt = REG(PCIR_MINGNT, 1);
396 cfg->maxlat = REG(PCIR_MAXLAT, 1);
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397
398 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
399 cfg->hdrtype &= ~PCIM_MFDEV;
400
401 pci_fixancient(cfg);
4a5a2d63 402 pci_hdrtypedata(pcib, b, s, f, cfg);
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403
404 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
4a5a2d63 405 pci_read_extcap(pcib, cfg);
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406
407 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
408
409 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
410 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
411 devlist_entry->conf.pc_sel.pc_func = cfg->func;
412 devlist_entry->conf.pc_hdr = cfg->hdrtype;
413
414 devlist_entry->conf.pc_subvendor = cfg->subvendor;
415 devlist_entry->conf.pc_subdevice = cfg->subdevice;
416 devlist_entry->conf.pc_vendor = cfg->vendor;
417 devlist_entry->conf.pc_device = cfg->device;
418
419 devlist_entry->conf.pc_class = cfg->baseclass;
420 devlist_entry->conf.pc_subclass = cfg->subclass;
421 devlist_entry->conf.pc_progif = cfg->progif;
422 devlist_entry->conf.pc_revid = cfg->revid;
423
424 pci_numdevs++;
425 pci_generation++;
426 }
427 return (devlist_entry);
428#undef REG
429}
430
431static void
4a5a2d63 432pci_read_extcap(device_t pcib, pcicfgregs *cfg)
984263bc 433{
4a5a2d63 434#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
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435 int ptr, nextptr, ptrptr;
436
437 switch (cfg->hdrtype) {
438 case 0:
439 ptrptr = 0x34;
440 break;
441 case 2:
442 ptrptr = 0x14;
443 break;
444 default:
445 return; /* no extended capabilities support */
446 }
447 nextptr = REG(ptrptr, 1); /* sanity check? */
448
449 /*
450 * Read capability entries.
451 */
452 while (nextptr != 0) {
453 /* Sanity check */
454 if (nextptr > 255) {
455 printf("illegal PCI extended capability offset %d\n",
456 nextptr);
457 return;
458 }
459 /* Find the next entry */
460 ptr = nextptr;
461 nextptr = REG(ptr + 1, 1);
462
463 /* Process this entry */
464 switch (REG(ptr, 1)) {
465 case 0x01: /* PCI power management */
466 if (cfg->pp_cap == 0) {
467 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
468 cfg->pp_status = ptr + PCIR_POWER_STATUS;
469 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
470 if ((nextptr - ptr) > PCIR_POWER_DATA)
471 cfg->pp_data = ptr + PCIR_POWER_DATA;
472 }
473 break;
474 default:
475 break;
476 }
477 }
478#undef REG
479}
480
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481/* free pcicfgregs structure and all depending data structures */
482
22457186 483int
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484pci_freecfg(struct pci_devinfo *dinfo)
485{
486 struct devlist *devlist_head;
487
488 devlist_head = &pci_devq;
489
490 if (dinfo->cfg.hdrspec != NULL)
491 free(dinfo->cfg.hdrspec, M_DEVBUF);
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492 /* XXX this hasn't been tested */
493 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
494 free(dinfo, M_DEVBUF);
495
496 /* increment the generation count */
497 pci_generation++;
498
499 /* we're losing one device */
500 pci_numdevs--;
501 return (0);
502}
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503
504
505/*
506 * PCI power manangement
507 */
e126caf1 508int
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509pci_set_powerstate_method(device_t dev, device_t child, int state)
510{
511 struct pci_devinfo *dinfo = device_get_ivars(child);
512 pcicfgregs *cfg = &dinfo->cfg;
513 u_int16_t status;
514 int result;
515
516 if (cfg->pp_cap != 0) {
517 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK;
518 result = 0;
519 switch (state) {
520 case PCI_POWERSTATE_D0:
521 status |= PCIM_PSTAT_D0;
522 break;
523 case PCI_POWERSTATE_D1:
524 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) {
525 status |= PCIM_PSTAT_D1;
526 } else {
527 result = EOPNOTSUPP;
528 }
529 break;
530 case PCI_POWERSTATE_D2:
531 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) {
532 status |= PCIM_PSTAT_D2;
533 } else {
534 result = EOPNOTSUPP;
535 }
536 break;
537 case PCI_POWERSTATE_D3:
538 status |= PCIM_PSTAT_D3;
539 break;
540 default:
541 result = EINVAL;
542 }
543 if (result == 0)
544 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2);
545 } else {
546 result = ENXIO;
547 }
548 return(result);
549}
550
e126caf1 551int
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552pci_get_powerstate_method(device_t dev, device_t child)
553{
554 struct pci_devinfo *dinfo = device_get_ivars(child);
555 pcicfgregs *cfg = &dinfo->cfg;
556 u_int16_t status;
557 int result;
558
559 if (cfg->pp_cap != 0) {
560 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2);
561 switch (status & PCIM_PSTAT_DMASK) {
562 case PCIM_PSTAT_D0:
563 result = PCI_POWERSTATE_D0;
564 break;
565 case PCIM_PSTAT_D1:
566 result = PCI_POWERSTATE_D1;
567 break;
568 case PCIM_PSTAT_D2:
569 result = PCI_POWERSTATE_D2;
570 break;
571 case PCIM_PSTAT_D3:
572 result = PCI_POWERSTATE_D3;
573 break;
574 default:
575 result = PCI_POWERSTATE_UNKNOWN;
576 break;
577 }
578 } else {
579 /* No support, device is always at D0 */
580 result = PCI_POWERSTATE_D0;
581 }
582 return(result);
583}
584
585/*
586 * Some convenience functions for PCI device drivers.
587 */
588
589static __inline void
590pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
591{
592 u_int16_t command;
593
594 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
595 command |= bit;
596 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
597}
598
599static __inline void
600pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
601{
602 u_int16_t command;
603
604 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
605 command &= ~bit;
606 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
607}
608
e126caf1 609int
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610pci_enable_busmaster_method(device_t dev, device_t child)
611{
612 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 613 return(0);
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614}
615
e126caf1 616int
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617pci_disable_busmaster_method(device_t dev, device_t child)
618{
619 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 620 return(0);
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621}
622
e126caf1 623int
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624pci_enable_io_method(device_t dev, device_t child, int space)
625{
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626 uint16_t command;
627 uint16_t bit;
628 char *error;
629
630 bit = 0;
631 error = NULL;
632
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633 switch(space) {
634 case SYS_RES_IOPORT:
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635 bit = PCIM_CMD_PORTEN;
636 error = "port";
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637 break;
638 case SYS_RES_MEMORY:
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639 bit = PCIM_CMD_MEMEN;
640 error = "memory";
984263bc 641 break;
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642 default:
643 return(EINVAL);
984263bc 644 }
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645 pci_set_command_bit(dev, child, bit);
646 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
647 if (command & bit)
648 return(0);
649 device_printf(child, "failed to enable %s mapping!\n", error);
650 return(ENXIO);
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651}
652
e126caf1 653int
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654pci_disable_io_method(device_t dev, device_t child, int space)
655{
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656 uint16_t command;
657 uint16_t bit;
658 char *error;
659
660 bit = 0;
661 error = NULL;
662
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663 switch(space) {
664 case SYS_RES_IOPORT:
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665 bit = PCIM_CMD_PORTEN;
666 error = "port";
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667 break;
668 case SYS_RES_MEMORY:
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669 bit = PCIM_CMD_MEMEN;
670 error = "memory";
984263bc 671 break;
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672 default:
673 return (EINVAL);
984263bc 674 }
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675 pci_clear_command_bit(dev, child, bit);
676 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
677 if (command & bit) {
678 device_printf(child, "failed to disable %s mapping!\n", error);
679 return (ENXIO);
680 }
681 return (0);
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682}
683
684/*
685 * This is the user interface to PCI configuration space.
686 */
687
688static int
fef8985e 689pci_open(struct dev_open_args *ap)
984263bc 690{
fef8985e 691 if ((ap->a_oflags & FWRITE) && securelevel > 0) {
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692 return EPERM;
693 }
694 return 0;
695}
696
697static int
fef8985e 698pci_close(struct dev_close_args *ap)
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699{
700 return 0;
701}
702
703/*
704 * Match a single pci_conf structure against an array of pci_match_conf
705 * structures. The first argument, 'matches', is an array of num_matches
706 * pci_match_conf structures. match_buf is a pointer to the pci_conf
707 * structure that will be compared to every entry in the matches array.
708 * This function returns 1 on failure, 0 on success.
709 */
710static int
711pci_conf_match(struct pci_match_conf *matches, int num_matches,
712 struct pci_conf *match_buf)
713{
714 int i;
715
716 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
717 return(1);
718
719 for (i = 0; i < num_matches; i++) {
720 /*
721 * I'm not sure why someone would do this...but...
722 */
723 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
724 continue;
725
726 /*
727 * Look at each of the match flags. If it's set, do the
728 * comparison. If the comparison fails, we don't have a
729 * match, go on to the next item if there is one.
730 */
731 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
732 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
733 continue;
734
735 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
736 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
737 continue;
738
739 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
740 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
741 continue;
742
743 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
744 && (match_buf->pc_vendor != matches[i].pc_vendor))
745 continue;
746
747 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
748 && (match_buf->pc_device != matches[i].pc_device))
749 continue;
750
751 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
752 && (match_buf->pc_class != matches[i].pc_class))
753 continue;
754
755 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
756 && (match_buf->pd_unit != matches[i].pd_unit))
757 continue;
758
759 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
760 && (strncmp(matches[i].pd_name, match_buf->pd_name,
761 sizeof(match_buf->pd_name)) != 0))
762 continue;
763
764 return(0);
765 }
766
767 return(1);
768}
769
770/*
771 * Locate the parent of a PCI device by scanning the PCI devlist
772 * and return the entry for the parent.
773 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
774 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
775 */
776
777pcicfgregs *
778pci_devlist_get_parent(pcicfgregs *cfg)
779{
780 struct devlist *devlist_head;
781 struct pci_devinfo *dinfo;
782 pcicfgregs *bridge_cfg;
783 int i;
784
785 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
786
787 /* If the device is on PCI bus 0, look for the host */
788 if (cfg->bus == 0) {
789 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
790 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
791 bridge_cfg = &dinfo->cfg;
792 if (bridge_cfg->baseclass == PCIC_BRIDGE
793 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
794 && bridge_cfg->bus == cfg->bus) {
795 return bridge_cfg;
796 }
797 }
798 }
799
800 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
801 if (cfg->bus > 0) {
802 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
803 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
804 bridge_cfg = &dinfo->cfg;
805 if (bridge_cfg->baseclass == PCIC_BRIDGE
806 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
807 && bridge_cfg->secondarybus == cfg->bus) {
808 return bridge_cfg;
809 }
810 }
811 }
812
813 return NULL;
814}
815
816static int
fef8985e 817pci_ioctl(struct dev_ioctl_args *ap)
984263bc 818{
4a5a2d63 819 device_t pci, pcib;
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820 struct pci_io *io;
821 const char *name;
822 int error;
823
fef8985e 824 if (!(ap->a_fflag & FWRITE))
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825 return EPERM;
826
fef8985e 827 switch(ap->a_cmd) {
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828 case PCIOCGETCONF:
829 {
830 struct pci_devinfo *dinfo;
831 struct pci_conf_io *cio;
832 struct devlist *devlist_head;
833 struct pci_match_conf *pattern_buf;
834 int num_patterns;
835 size_t iolen;
836 int ionum, i;
837
fef8985e 838 cio = (struct pci_conf_io *)ap->a_data;
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839
840 num_patterns = 0;
841 dinfo = NULL;
842
843 /*
844 * Hopefully the user won't pass in a null pointer, but it
845 * can't hurt to check.
846 */
847 if (cio == NULL) {
848 error = EINVAL;
849 break;
850 }
851
852 /*
853 * If the user specified an offset into the device list,
854 * but the list has changed since they last called this
855 * ioctl, tell them that the list has changed. They will
856 * have to get the list from the beginning.
857 */
858 if ((cio->offset != 0)
859 && (cio->generation != pci_generation)){
860 cio->num_matches = 0;
861 cio->status = PCI_GETCONF_LIST_CHANGED;
862 error = 0;
863 break;
864 }
865
866 /*
867 * Check to see whether the user has asked for an offset
868 * past the end of our list.
869 */
870 if (cio->offset >= pci_numdevs) {
871 cio->num_matches = 0;
872 cio->status = PCI_GETCONF_LAST_DEVICE;
873 error = 0;
874 break;
875 }
876
877 /* get the head of the device queue */
878 devlist_head = &pci_devq;
879
880 /*
881 * Determine how much room we have for pci_conf structures.
882 * Round the user's buffer size down to the nearest
883 * multiple of sizeof(struct pci_conf) in case the user
884 * didn't specify a multiple of that size.
885 */
886 iolen = min(cio->match_buf_len -
887 (cio->match_buf_len % sizeof(struct pci_conf)),
888 pci_numdevs * sizeof(struct pci_conf));
889
890 /*
891 * Since we know that iolen is a multiple of the size of
892 * the pciconf union, it's okay to do this.
893 */
894 ionum = iolen / sizeof(struct pci_conf);
895
896 /*
897 * If this test is true, the user wants the pci_conf
898 * structures returned to match the supplied entries.
899 */
900 if ((cio->num_patterns > 0)
901 && (cio->pat_buf_len > 0)) {
902 /*
903 * pat_buf_len needs to be:
904 * num_patterns * sizeof(struct pci_match_conf)
905 * While it is certainly possible the user just
906 * allocated a large buffer, but set the number of
907 * matches correctly, it is far more likely that
908 * their kernel doesn't match the userland utility
909 * they're using. It's also possible that the user
910 * forgot to initialize some variables. Yes, this
911 * may be overly picky, but I hazard to guess that
912 * it's far more likely to just catch folks that
913 * updated their kernel but not their userland.
914 */
915 if ((cio->num_patterns *
916 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
917 /* The user made a mistake, return an error*/
918 cio->status = PCI_GETCONF_ERROR;
919 printf("pci_ioctl: pat_buf_len %d != "
920 "num_patterns (%d) * sizeof(struct "
921 "pci_match_conf) (%d)\npci_ioctl: "
922 "pat_buf_len should be = %d\n",
923 cio->pat_buf_len, cio->num_patterns,
924 (int)sizeof(struct pci_match_conf),
925 (int)sizeof(struct pci_match_conf) *
926 cio->num_patterns);
927 printf("pci_ioctl: do your headers match your "
928 "kernel?\n");
929 cio->num_matches = 0;
930 error = EINVAL;
931 break;
932 }
933
934 /*
935 * Check the user's buffer to make sure it's readable.
936 */
937 if (!useracc((caddr_t)cio->patterns,
938 cio->pat_buf_len, VM_PROT_READ)) {
939 printf("pci_ioctl: pattern buffer %p, "
940 "length %u isn't user accessible for"
941 " READ\n", cio->patterns,
942 cio->pat_buf_len);
943 error = EACCES;
944 break;
945 }
946 /*
947 * Allocate a buffer to hold the patterns.
948 */
949 pattern_buf = malloc(cio->pat_buf_len, M_TEMP,
950 M_WAITOK);
951 error = copyin(cio->patterns, pattern_buf,
952 cio->pat_buf_len);
953 if (error != 0)
954 break;
955 num_patterns = cio->num_patterns;
956
957 } else if ((cio->num_patterns > 0)
958 || (cio->pat_buf_len > 0)) {
959 /*
960 * The user made a mistake, spit out an error.
961 */
962 cio->status = PCI_GETCONF_ERROR;
963 cio->num_matches = 0;
964 printf("pci_ioctl: invalid GETCONF arguments\n");
965 error = EINVAL;
966 break;
967 } else
968 pattern_buf = NULL;
969
970 /*
971 * Make sure we can write to the match buffer.
972 */
973 if (!useracc((caddr_t)cio->matches,
974 cio->match_buf_len, VM_PROT_WRITE)) {
975 printf("pci_ioctl: match buffer %p, length %u "
976 "isn't user accessible for WRITE\n",
977 cio->matches, cio->match_buf_len);
978 error = EACCES;
979 break;
980 }
981
982 /*
983 * Go through the list of devices and copy out the devices
984 * that match the user's criteria.
985 */
986 for (cio->num_matches = 0, error = 0, i = 0,
987 dinfo = STAILQ_FIRST(devlist_head);
988 (dinfo != NULL) && (cio->num_matches < ionum)
989 && (error == 0) && (i < pci_numdevs);
990 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
991
992 if (i < cio->offset)
993 continue;
994
995 /* Populate pd_name and pd_unit */
996 name = NULL;
997 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
998 name = device_get_name(dinfo->cfg.dev);
999 if (name) {
1000 strncpy(dinfo->conf.pd_name, name,
1001 sizeof(dinfo->conf.pd_name));
1002 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
1003 dinfo->conf.pd_unit =
1004 device_get_unit(dinfo->cfg.dev);
1005 }
1006
1007 if ((pattern_buf == NULL) ||
1008 (pci_conf_match(pattern_buf, num_patterns,
1009 &dinfo->conf) == 0)) {
1010
1011 /*
1012 * If we've filled up the user's buffer,
1013 * break out at this point. Since we've
1014 * got a match here, we'll pick right back
1015 * up at the matching entry. We can also
1016 * tell the user that there are more matches
1017 * left.
1018 */
1019 if (cio->num_matches >= ionum)
1020 break;
1021
1022 error = copyout(&dinfo->conf,
1023 &cio->matches[cio->num_matches],
1024 sizeof(struct pci_conf));
1025 cio->num_matches++;
1026 }
1027 }
1028
1029 /*
1030 * Set the pointer into the list, so if the user is getting
1031 * n records at a time, where n < pci_numdevs,
1032 */
1033 cio->offset = i;
1034
1035 /*
1036 * Set the generation, the user will need this if they make
1037 * another ioctl call with offset != 0.
1038 */
1039 cio->generation = pci_generation;
1040
1041 /*
1042 * If this is the last device, inform the user so he won't
1043 * bother asking for more devices. If dinfo isn't NULL, we
1044 * know that there are more matches in the list because of
1045 * the way the traversal is done.
1046 */
1047 if (dinfo == NULL)
1048 cio->status = PCI_GETCONF_LAST_DEVICE;
1049 else
1050 cio->status = PCI_GETCONF_MORE_DEVS;
1051
1052 if (pattern_buf != NULL)
1053 free(pattern_buf, M_TEMP);
1054
1055 break;
1056 }
1057 case PCIOCREAD:
fef8985e 1058 io = (struct pci_io *)ap->a_data;
984263bc 1059 switch(io->pi_width) {
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MD
1060 case 4:
1061 case 2:
1062 case 1:
4a5a2d63
JS
1063 /*
1064 * Assume that the user-level bus number is
1065 * actually the pciN instance number. We map
1066 * from that to the real pcib+bus combination.
1067 */
1068 pci = devclass_get_device(pci_devclass,
1069 io->pi_sel.pc_bus);
1070 if (pci) {
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1071 /*
1072 * pci is the pci device and may contain
1073 * several children (for each function code).
1074 * The governing pci bus is the parent to
1075 * the pci device.
1076 */
1077 int b;
1078
4a5a2d63 1079 pcib = device_get_parent(pci);
2581072f 1080 b = pcib_get_bus(pcib);
4a5a2d63
JS
1081 io->pi_data =
1082 PCIB_READ_CONFIG(pcib,
1083 b,
1084 io->pi_sel.pc_dev,
1085 io->pi_sel.pc_func,
1086 io->pi_reg,
1087 io->pi_width);
1088 error = 0;
1089 } else {
1090 error = ENODEV;
1091 }
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MD
1092 break;
1093 default:
1094 error = ENODEV;
1095 break;
1096 }
1097 break;
1098
1099 case PCIOCWRITE:
fef8985e 1100 io = (struct pci_io *)ap->a_data;
984263bc 1101 switch(io->pi_width) {
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MD
1102 case 4:
1103 case 2:
1104 case 1:
4a5a2d63
JS
1105 /*
1106 * Assume that the user-level bus number is
1107 * actually the pciN instance number. We map
1108 * from that to the real pcib+bus combination.
1109 */
1110 pci = devclass_get_device(pci_devclass,
1111 io->pi_sel.pc_bus);
1112 if (pci) {
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1113 /*
1114 * pci is the pci device and may contain
1115 * several children (for each function code).
1116 * The governing pci bus is the parent to
1117 * the pci device.
1118 */
1119 int b;
1120
4a5a2d63 1121 pcib = device_get_parent(pci);
2581072f 1122 b = pcib_get_bus(pcib);
4a5a2d63
JS
1123 PCIB_WRITE_CONFIG(pcib,
1124 b,
1125 io->pi_sel.pc_dev,
1126 io->pi_sel.pc_func,
1127 io->pi_reg,
1128 io->pi_data,
1129 io->pi_width);
1130 error = 0;
1131 } else {
1132 error = ENODEV;
1133 }
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MD
1134 break;
1135 default:
1136 error = ENODEV;
1137 break;
1138 }
1139 break;
1140
1141 default:
1142 error = ENOTTY;
1143 break;
1144 }
1145
1146 return (error);
1147}
1148
1149#define PCI_CDEV 78
1150
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MD
1151static struct dev_ops pcic_ops = {
1152 { "pci", PCI_CDEV, 0 },
1153 .d_open = pci_open,
1154 .d_close = pci_close,
1155 .d_ioctl = pci_ioctl,
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MD
1156};
1157
1158#include "pci_if.h"
1159
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MD
1160/*
1161 * New style pci driver. Parent device is either a pci-host-bridge or a
1162 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1163 */
ed1bd994
MD
1164const char *
1165pci_class_to_string(int baseclass)
1166{
1167 const char *name;
1168
1169 switch(baseclass) {
1170 case PCIC_OLD:
1171 name = "OLD";
1172 break;
1173 case PCIC_STORAGE:
1174 name = "STORAGE";
1175 break;
1176 case PCIC_NETWORK:
1177 name = "NETWORK";
1178 break;
1179 case PCIC_DISPLAY:
1180 name = "DISPLAY";
1181 break;
1182 case PCIC_MULTIMEDIA:
1183 name = "MULTIMEDIA";
1184 break;
1185 case PCIC_MEMORY:
1186 name = "MEMORY";
1187 break;
1188 case PCIC_BRIDGE:
1189 name = "BRIDGE";
1190 break;
1191 case PCIC_SIMPLECOMM:
1192 name = "SIMPLECOMM";
1193 break;
1194 case PCIC_BASEPERIPH:
1195 name = "BASEPERIPH";
1196 break;
1197 case PCIC_INPUTDEV:
1198 name = "INPUTDEV";
1199 break;
1200 case PCIC_DOCKING:
1201 name = "DOCKING";
1202 break;
1203 case PCIC_PROCESSOR:
1204 name = "PROCESSOR";
1205 break;
1206 case PCIC_SERIALBUS:
1207 name = "SERIALBUS";
1208 break;
1209 case PCIC_WIRELESS:
1210 name = "WIRELESS";
1211 break;
1212 case PCIC_I2O:
1213 name = "I20";
1214 break;
1215 case PCIC_SATELLITE:
1216 name = "SATELLITE";
1217 break;
1218 case PCIC_CRYPTO:
1219 name = "CRYPTO";
1220 break;
1221 case PCIC_SIGPROC:
1222 name = "SIGPROC";
1223 break;
1224 case PCIC_OTHER:
1225 name = "OTHER";
1226 break;
1227 default:
1228 name = "?";
1229 break;
1230 }
1231 return(name);
1232}
984263bc 1233
22457186 1234void
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MD
1235pci_print_verbose(struct pci_devinfo *dinfo)
1236{
1237 if (bootverbose) {
1238 pcicfgregs *cfg = &dinfo->cfg;
1239
1240 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
1241 cfg->vendor, cfg->device, cfg->revid);
4a5a2d63
JS
1242 printf("\tbus=%d, slot=%d, func=%d\n",
1243 cfg->bus, cfg->slot, cfg->func);
ed1bd994
MD
1244 printf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
1245 pci_class_to_string(cfg->baseclass),
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MD
1246 cfg->baseclass, cfg->subclass, cfg->progif,
1247 cfg->hdrtype, cfg->mfdev);
1248 printf("\tsubordinatebus=%x \tsecondarybus=%x\n",
1249 cfg->subordinatebus, cfg->secondarybus);
1250#ifdef PCI_DEBUG
1251 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
1252 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
1253 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
1254 cfg->lattimer, cfg->lattimer * 30,
1255 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1256#endif /* PCI_DEBUG */
1257 if (cfg->intpin > 0)
1258 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
1259 }
1260}
1261
1262static int
4a5a2d63 1263pci_porten(device_t pcib, int b, int s, int f)
984263bc 1264{
4a5a2d63
JS
1265 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1266 & PCIM_CMD_PORTEN) != 0;
984263bc
MD
1267}
1268
1269static int
4a5a2d63 1270pci_memen(device_t pcib, int b, int s, int f)
984263bc 1271{
4a5a2d63
JS
1272 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1273 & PCIM_CMD_MEMEN) != 0;
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MD
1274}
1275
1276/*
1277 * Add a resource based on a pci map register. Return 1 if the map
1278 * register is a 32bit map register or 2 if it is a 64bit register.
1279 */
1280static int
4a5a2d63
JS
1281pci_add_map(device_t pcib, int b, int s, int f, int reg,
1282 struct resource_list *rl)
984263bc 1283{
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MD
1284 u_int32_t map;
1285 u_int64_t base;
1286 u_int8_t ln2size;
1287 u_int8_t ln2range;
1288 u_int32_t testval;
4a5a2d63
JS
1289
1290
1291#ifdef PCI_ENABLE_IO_MODES
1292 u_int16_t cmd;
1293#endif
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MD
1294 int type;
1295
4a5a2d63 1296 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
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MD
1297
1298 if (map == 0 || map == 0xffffffff)
1299 return 1; /* skip invalid entry */
1300
4a5a2d63
JS
1301 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1302 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1303 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
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MD
1304
1305 base = pci_mapbase(map);
1306 if (pci_maptype(map) & PCI_MAPMEM)
1307 type = SYS_RES_MEMORY;
1308 else
1309 type = SYS_RES_IOPORT;
1310 ln2size = pci_mapsize(testval);
1311 ln2range = pci_maprange(testval);
1312 if (ln2range == 64) {
1313 /* Read the other half of a 64bit map register */
4a5a2d63 1314 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
984263bc
MD
1315 }
1316
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MD
1317 /*
1318 * This code theoretically does the right thing, but has
1319 * undesirable side effects in some cases where
1320 * peripherals respond oddly to having these bits
1321 * enabled. Leave them alone by default.
1322 */
1323#ifdef PCI_ENABLE_IO_MODES
4a5a2d63
JS
1324 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1325 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1326 cmd |= PCIM_CMD_PORTEN;
1327 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc 1328 }
4a5a2d63
JS
1329 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1330 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1331 cmd |= PCIM_CMD_MEMEN;
1332 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc
MD
1333 }
1334#else
4a5a2d63 1335 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
984263bc 1336 return 1;
4a5a2d63 1337 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
984263bc
MD
1338 return 1;
1339#endif
1340
1341 resource_list_add(rl, type, reg,
1342 base, base + (1 << ln2size) - 1,
1343 (1 << ln2size));
1344
1345 if (bootverbose) {
1346 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
1347 reg, pci_maptype(base), ln2range,
1348 (unsigned int) base, ln2size);
1349 }
1350
1351 return (ln2range == 64) ? 2 : 1;
1352}
1353
1354static void
e126caf1 1355pci_add_resources(device_t pcib, device_t bus, device_t dev)
984263bc
MD
1356{
1357 struct pci_devinfo *dinfo = device_get_ivars(dev);
4a5a2d63 1358 pcicfgregs *cfg = &dinfo->cfg;
984263bc
MD
1359 struct resource_list *rl = &dinfo->resources;
1360 struct pci_quirk *q;
e126caf1
MD
1361 int b, i, f, s;
1362#if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */
1363 int irq;
1364#endif
984263bc 1365
e126caf1
MD
1366 b = cfg->bus;
1367 s = cfg->slot;
1368 f = cfg->func;
984263bc 1369 for (i = 0; i < cfg->nummaps;) {
e126caf1 1370 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl);
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MD
1371 }
1372
1373 for (q = &pci_quirks[0]; q->devid; q++) {
1374 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1375 && q->type == PCI_QUIRK_MAP_REG)
4a5a2d63 1376 pci_add_map(pcib, b, s, f, q->arg1, rl);
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MD
1377 }
1378
1379 if (cfg->intpin > 0 && cfg->intline != 255)
1380 resource_list_add(rl, SYS_RES_IRQ, 0,
1381 cfg->intline, cfg->intline, 1);
1382}
1383
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MD
1384void
1385pci_add_children(device_t dev, int busno, size_t dinfo_size)
984263bc 1386{
e126caf1 1387#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
4a5a2d63 1388 device_t pcib = device_get_parent(dev);
e126caf1 1389 struct pci_devinfo *dinfo;
4a5a2d63 1390 int maxslots;
e126caf1
MD
1391 int s, f, pcifunchigh;
1392 uint8_t hdrtype;
1393
1394 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo));
984263bc 1395
4a5a2d63 1396 maxslots = PCIB_MAXSLOTS(pcib);
984263bc 1397
57e943f7 1398 for (s = 0; s <= maxslots; s++) {
e126caf1
MD
1399 pcifunchigh = 0;
1400 f = 0;
1401 hdrtype = REG(PCIR_HDRTYPE, 1);
1402 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1403 continue;
1404 if (hdrtype & PCIM_MFDEV)
1405 pcifunchigh = PCI_FUNCMAX;
5e658043 1406 for (f = 0; f <= pcifunchigh; f++) {
e126caf1 1407 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
984263bc 1408 if (dinfo != NULL) {
e126caf1 1409 pci_add_child(dev, dinfo);
984263bc
MD
1410 }
1411 }
1412 }
e126caf1
MD
1413#undef REG
1414}
1415
2581072f
MD
1416/*
1417 * The actual PCI child that we add has a NULL driver whos parent
1418 * device will be "pci". The child contains the ivars, not the parent.
1419 */
e126caf1
MD
1420void
1421pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1422{
1423 device_t pcib;
1424
1425 pcib = device_get_parent(bus);
1426 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1427 device_set_ivars(dinfo->cfg.dev, dinfo);
1428 pci_add_resources(pcib, bus, dinfo->cfg.dev);
1429 pci_print_verbose(dinfo);
984263bc
MD
1430}
1431
c01b8d84
MD
1432/*
1433 * Probe the PCI bus. Note: probe code is not supposed to add children
1434 * or call attach.
1435 */
984263bc 1436static int
4a5a2d63 1437pci_probe(device_t dev)
984263bc 1438{
984263bc 1439 device_set_desc(dev, "PCI bus");
4a5a2d63 1440
c01b8d84
MD
1441 /* Allow other subclasses to override this driver */
1442 return(-1000);
984263bc
MD
1443}
1444
e126caf1
MD
1445static int
1446pci_attach(device_t dev)
1447{
1448 int busno;
e4c9c0c8
MD
1449 int lunit = device_get_unit(dev);
1450
fef8985e
MD
1451 dev_ops_add(&pcic_ops, -1, lunit);
1452 make_dev(&pcic_ops, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit);
e126caf1
MD
1453
1454 /*
1455 * Since there can be multiple independantly numbered PCI
1456 * busses on some large alpha systems, we can't use the unit
1457 * number to decide what bus we are probing. We ask the parent
1458 * pcib what our bus number is.
2581072f
MD
1459 *
1460 * pcib_get_bus() must act on the pci bus device, not on the pci
1461 * device, because it uses badly hacked nexus-based ivars to
1462 * store and retrieve the physical bus number. XXX
e126caf1 1463 */
2581072f 1464 busno = pcib_get_bus(device_get_parent(dev));
e126caf1 1465 if (bootverbose)
ed1bd994 1466 device_printf(dev, "pci_attach() physical bus=%d\n", busno);
e126caf1
MD
1467
1468 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1469
1470 return (bus_generic_attach(dev));
1471}
1472
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MD
1473static int
1474pci_print_resources(struct resource_list *rl, const char *name, int type,
1475 const char *format)
1476{
1477 struct resource_list_entry *rle;
1478 int printed, retval;
1479
1480 printed = 0;
1481 retval = 0;
1482 /* Yes, this is kinda cheating */
1483 SLIST_FOREACH(rle, rl, link) {
1484 if (rle->type == type) {
1485 if (printed == 0)
1486 retval += printf(" %s ", name);
1487 else if (printed > 0)
1488 retval += printf(",");
1489 printed++;
1490 retval += printf(format, rle->start);
1491 if (rle->count > 1) {
1492 retval += printf("-");
1493 retval += printf(format, rle->start +
1494 rle->count - 1);
1495 }
1496 }
1497 }
1498 return retval;
1499}
1500
e126caf1 1501int
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MD
1502pci_print_child(device_t dev, device_t child)
1503{
1504 struct pci_devinfo *dinfo;
1505 struct resource_list *rl;
1506 pcicfgregs *cfg;
1507 int retval = 0;
1508
1509 dinfo = device_get_ivars(child);
1510 cfg = &dinfo->cfg;
1511 rl = &dinfo->resources;
1512
1513 retval += bus_print_child_header(dev, child);
1514
1515 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1516 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1517 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1518 if (device_get_flags(dev))
1519 retval += printf(" flags %#x", device_get_flags(dev));
1520
1521 retval += printf(" at device %d.%d", pci_get_slot(child),
1522 pci_get_function(child));
1523
1524 retval += bus_print_child_footer(dev, child);
1525
1526 return (retval);
1527}
1528
e126caf1 1529void
984263bc
MD
1530pci_probe_nomatch(device_t dev, device_t child)
1531{
1532 struct pci_devinfo *dinfo;
1533 pcicfgregs *cfg;
1534 const char *desc;
1535 int unknown;
1536
1537 unknown = 0;
1538 dinfo = device_get_ivars(child);
1539 cfg = &dinfo->cfg;
1540 desc = pci_ata_match(child);
1541 if (!desc) desc = pci_usb_match(child);
1542 if (!desc) desc = pci_vga_match(child);
27c23c6b 1543 if (!desc) desc = pci_chip_match(child);
984263bc
MD
1544 if (!desc) {
1545 desc = "unknown card";
1546 unknown++;
1547 }
1548 device_printf(dev, "<%s>", desc);
1549 if (bootverbose || unknown) {
1550 printf(" (vendor=0x%04x, dev=0x%04x)",
1551 cfg->vendor,
1552 cfg->device);
1553 }
1554 printf(" at %d.%d",
1555 pci_get_slot(child),
1556 pci_get_function(child));
1557 if (cfg->intpin > 0 && cfg->intline != 255) {
1558 printf(" irq %d", cfg->intline);
1559 }
1560 printf("\n");
1561
1562 return;
1563}
1564
22457186 1565int
4a5a2d63 1566pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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MD
1567{
1568 struct pci_devinfo *dinfo;
1569 pcicfgregs *cfg;
1570
1571 dinfo = device_get_ivars(child);
1572 cfg = &dinfo->cfg;
1573
1574 switch (which) {
1575 case PCI_IVAR_SUBVENDOR:
1576 *result = cfg->subvendor;
1577 break;
1578 case PCI_IVAR_SUBDEVICE:
1579 *result = cfg->subdevice;
1580 break;
1581 case PCI_IVAR_VENDOR:
1582 *result = cfg->vendor;
1583 break;
1584 case PCI_IVAR_DEVICE:
1585 *result = cfg->device;
1586 break;
1587 case PCI_IVAR_DEVID:
1588 *result = (cfg->device << 16) | cfg->vendor;
1589 break;
1590 case PCI_IVAR_CLASS:
1591 *result = cfg->baseclass;
1592 break;
1593 case PCI_IVAR_SUBCLASS:
1594 *result = cfg->subclass;
1595 break;
1596 case PCI_IVAR_PROGIF:
1597 *result = cfg->progif;
1598 break;
1599 case PCI_IVAR_REVID:
1600 *result = cfg->revid;
1601 break;
1602 case PCI_IVAR_INTPIN:
1603 *result = cfg->intpin;
1604 break;
1605 case PCI_IVAR_IRQ:
1606 *result = cfg->intline;
1607 break;
1608 case PCI_IVAR_BUS:
1609 *result = cfg->bus;
1610 break;
1611 case PCI_IVAR_SLOT:
1612 *result = cfg->slot;
1613 break;
1614 case PCI_IVAR_FUNCTION:
1615 *result = cfg->func;
1616 break;
1617 case PCI_IVAR_SECONDARYBUS:
1618 *result = cfg->secondarybus;
1619 break;
1620 case PCI_IVAR_SUBORDINATEBUS:
1621 *result = cfg->subordinatebus;
1622 break;
f72d3d23
JS
1623 case PCI_IVAR_ETHADDR:
1624 /*
1625 * The generic accessor doesn't deal with failure, so
1626 * we set the return value, then return an error.
1627 */
1628 *result = NULL;
1629 return (EINVAL);
984263bc
MD
1630 default:
1631 return ENOENT;
1632 }
1633 return 0;
1634}
1635
22457186 1636int
984263bc
MD
1637pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1638{
1639 struct pci_devinfo *dinfo;
1640 pcicfgregs *cfg;
1641
1642 dinfo = device_get_ivars(child);
1643 cfg = &dinfo->cfg;
1644
1645 switch (which) {
1646 case PCI_IVAR_SUBVENDOR:
1647 case PCI_IVAR_SUBDEVICE:
1648 case PCI_IVAR_VENDOR:
1649 case PCI_IVAR_DEVICE:
1650 case PCI_IVAR_DEVID:
1651 case PCI_IVAR_CLASS:
1652 case PCI_IVAR_SUBCLASS:
1653 case PCI_IVAR_PROGIF:
1654 case PCI_IVAR_REVID:
1655 case PCI_IVAR_INTPIN:
1656 case PCI_IVAR_IRQ:
1657 case PCI_IVAR_BUS:
1658 case PCI_IVAR_SLOT:
1659 case PCI_IVAR_FUNCTION:
f72d3d23 1660 case PCI_IVAR_ETHADDR:
984263bc
MD
1661 return EINVAL; /* disallow for now */
1662
1663 case PCI_IVAR_SECONDARYBUS:
1664 cfg->secondarybus = value;
1665 break;
1666 case PCI_IVAR_SUBORDINATEBUS:
1667 cfg->subordinatebus = value;
1668 break;
1669 default:
1670 return ENOENT;
1671 }
1672 return 0;
1673}
1674
261fa16d 1675struct resource *
984263bc
MD
1676pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1677 u_long start, u_long end, u_long count, u_int flags)
1678{
1679 struct pci_devinfo *dinfo = device_get_ivars(child);
1680 struct resource_list *rl = &dinfo->resources;
984263bc 1681 pcicfgregs *cfg = &dinfo->cfg;
de67e43b 1682
984263bc
MD
1683 /*
1684 * Perform lazy resource allocation
1685 *
1686 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY
1687 */
1688 if (device_get_parent(child) == dev) {
de67e43b
JS
1689 switch (type) {
1690 case SYS_RES_IRQ:
1691#ifdef __i386__
984263bc
MD
1692 /*
1693 * If device doesn't have an interrupt routed, and is
1694 * deserving of an interrupt, try to assign it one.
1695 */
de67e43b
JS
1696 if ((cfg->intline == 255 || cfg->intline == 0) &&
1697 (cfg->intpin != 0) &&
1698 (start == 0) && (end == ~0UL)) {
1699 cfg->intline = PCIB_ROUTE_INTERRUPT(
1700 device_get_parent(dev), child,
1701 cfg->intpin);
1702 if (cfg->intline != 255) {
1703 pci_write_config(child, PCIR_INTLINE,
1704 cfg->intline, 1);
1705 resource_list_add(rl, SYS_RES_IRQ, 0,
1706 cfg->intline, cfg->intline, 1);
1707 }
1708 }
820c1612 1709 break;
de67e43b
JS
1710#endif
1711 case SYS_RES_IOPORT:
1712 case SYS_RES_MEMORY:
1713 if (*rid < PCIR_BAR(cfg->nummaps)) {
1714 /*
1715 * Enable the I/O mode. We should
1716 * also be assigning resources too
1717 * when none are present. The
1718 * resource_list_alloc kind of sorta does
1719 * this...
1720 */
1721 if (PCI_ENABLE_IO(dev, child, type))
1722 return (NULL);
984263bc 1723 }
820c1612 1724 break;
984263bc
MD
1725 }
1726 }
984263bc
MD
1727 return resource_list_alloc(rl, dev, child, type, rid,
1728 start, end, count, flags);
1729}
1730
1731static int
1732pci_release_resource(device_t dev, device_t child, int type, int rid,
1733 struct resource *r)
1734{
1735 struct pci_devinfo *dinfo = device_get_ivars(child);
1736 struct resource_list *rl = &dinfo->resources;
1737
1738 return resource_list_release(rl, dev, child, type, rid, r);
1739}
1740
1741static int
1742pci_set_resource(device_t dev, device_t child, int type, int rid,
1743 u_long start, u_long count)
1744{
1745 struct pci_devinfo *dinfo = device_get_ivars(child);
1746 struct resource_list *rl = &dinfo->resources;
1747
1748 resource_list_add(rl, type, rid, start, start + count - 1, count);
1749 return 0;
1750}
1751
1752static int
1753pci_get_resource(device_t dev, device_t child, int type, int rid,
1754 u_long *startp, u_long *countp)
1755{
1756 struct pci_devinfo *dinfo = device_get_ivars(child);
1757 struct resource_list *rl = &dinfo->resources;
1758 struct resource_list_entry *rle;
1759
1760 rle = resource_list_find(rl, type, rid);
1761 if (!rle)
1762 return ENOENT;
1763
1764 if (startp)
1765 *startp = rle->start;
1766 if (countp)
1767 *countp = rle->count;
1768
1769 return 0;
1770}
1771
e126caf1 1772void
984263bc
MD
1773pci_delete_resource(device_t dev, device_t child, int type, int rid)
1774{
1775 printf("pci_delete_resource: PCI resources can not be deleted\n");
1776}
1777
e126caf1
MD
1778struct resource_list *
1779pci_get_resource_list (device_t dev, device_t child)
1780{
1781 struct pci_devinfo * dinfo = device_get_ivars(child);
1782 struct resource_list * rl = &dinfo->resources;
1783
1784 if (!rl)
1785 return (NULL);
1786
1787 return (rl);
1788}
1789
1790u_int32_t
984263bc
MD
1791pci_read_config_method(device_t dev, device_t child, int reg, int width)
1792{
1793 struct pci_devinfo *dinfo = device_get_ivars(child);
1794 pcicfgregs *cfg = &dinfo->cfg;
4a5a2d63
JS
1795
1796 return PCIB_READ_CONFIG(device_get_parent(dev),
1797 cfg->bus, cfg->slot, cfg->func,
1798 reg, width);
984263bc
MD
1799}
1800
e126caf1 1801void
984263bc
MD
1802pci_write_config_method(device_t dev, device_t child, int reg,
1803 u_int32_t val, int width)
1804{
1805 struct pci_devinfo *dinfo = device_get_ivars(child);
1806 pcicfgregs *cfg = &dinfo->cfg;
4a5a2d63
JS
1807
1808 PCIB_WRITE_CONFIG(device_get_parent(dev),
1809 cfg->bus, cfg->slot, cfg->func,
1810 reg, val, width);
984263bc
MD
1811}
1812
e126caf1
MD
1813int
1814pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
1815 size_t buflen)
1816{
1817 struct pci_devinfo *dinfo;
1818
1819 dinfo = device_get_ivars(child);
1820 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
1821 pci_get_function(child));
1822 return (0);
1823}
1824
1825int
1826pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
1827 size_t buflen)
1828{
1829 struct pci_devinfo *dinfo;
1830 pcicfgregs *cfg;
1831
1832 dinfo = device_get_ivars(child);
1833 cfg = &dinfo->cfg;
1834 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
1835 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
1836 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
1837 cfg->progif);
1838 return (0);
1839}
1840
1841int
1842pci_assign_interrupt_method(device_t dev, device_t child)
1843{
1844 struct pci_devinfo *dinfo = device_get_ivars(child);
1845 pcicfgregs *cfg = &dinfo->cfg;
1846
1847 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
1848 cfg->intpin));
1849}
1850
984263bc
MD
1851static int
1852pci_modevent(module_t mod, int what, void *arg)
1853{
1854 switch (what) {
1855 case MOD_LOAD:
1856 STAILQ_INIT(&pci_devq);
1857 break;
984263bc
MD
1858 case MOD_UNLOAD:
1859 break;
1860 }
1861
1862 return 0;
1863}
1864
e126caf1
MD
1865int
1866pci_resume(device_t dev)
1867{
1868 int numdevs;
1869 int i;
1870 device_t *children;
1871 device_t child;
1872 struct pci_devinfo *dinfo;
1873 pcicfgregs *cfg;
1874
1875 device_get_children(dev, &children, &numdevs);
1876
1877 for (i = 0; i < numdevs; i++) {
1878 child = children[i];
1879
1880 dinfo = device_get_ivars(child);
1881 cfg = &dinfo->cfg;
1882 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
1883 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
1884 if (PCI_INTERRUPT_VALID(cfg->intline)) {
1885 pci_write_config(child, PCIR_INTLINE,
1886 cfg->intline, 1);
1887 }
1888 }
1889 }
1890
1891 free(children, M_TEMP);
1892
1893 return (bus_generic_resume(dev));
1894}
1895
984263bc
MD
1896static device_method_t pci_methods[] = {
1897 /* Device interface */
4a5a2d63 1898 DEVMETHOD(device_probe, pci_probe),
e126caf1 1899 DEVMETHOD(device_attach, pci_attach),
984263bc
MD
1900 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1901 DEVMETHOD(device_suspend, bus_generic_suspend),
e126caf1 1902 DEVMETHOD(device_resume, pci_resume),
984263bc
MD
1903
1904 /* Bus interface */
1905 DEVMETHOD(bus_print_child, pci_print_child),
1906 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
1907 DEVMETHOD(bus_read_ivar, pci_read_ivar),
1908 DEVMETHOD(bus_write_ivar, pci_write_ivar),
1909 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
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1910 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1911 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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1912
1913 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
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1914 DEVMETHOD(bus_set_resource, pci_set_resource),
1915 DEVMETHOD(bus_get_resource, pci_get_resource),
1916 DEVMETHOD(bus_delete_resource, pci_delete_resource),
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1917 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
1918 DEVMETHOD(bus_release_resource, pci_release_resource),
1919 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1920 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1921 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
1922 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
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1923
1924 /* PCI interface */
1925 DEVMETHOD(pci_read_config, pci_read_config_method),
1926 DEVMETHOD(pci_write_config, pci_write_config_method),
1927 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
1928 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
1929 DEVMETHOD(pci_enable_io, pci_enable_io_method),
1930 DEVMETHOD(pci_disable_io, pci_disable_io_method),
1931 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
1932 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
e126caf1 1933 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
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1934
1935 { 0, 0 }
1936};
1937
1938static driver_t pci_driver = {
1939 "pci",
1940 pci_methods,
1941 1, /* no softc */
1942};
1943
1944DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
261fa16d 1945MODULE_VERSION(pci, 1);