timeout/untimeout ==> callout_*
[dragonfly.git] / sys / dev / serial / rc / rc.c
CommitLineData
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1/*
2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/i386/isa/rc.c,v 1.53.2.1 2001/02/26 04:23:10 jlemon Exp $
e4c9c0c8 28 * $DragonFly: src/sys/dev/serial/rc/rc.c,v 1.11 2004/05/19 22:52:49 dillon Exp $
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29 *
30 */
31
32/*
33 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver
34 *
35 */
36
1f2de5d4 37#include "use_rc.h"
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38
39/*#define RCDEBUG*/
40
41#include <sys/param.h>
42#include <sys/systm.h>
43#include <sys/tty.h>
44#include <sys/proc.h>
45#include <sys/conf.h>
46#include <sys/dkstat.h>
47#include <sys/fcntl.h>
48#include <sys/interrupt.h>
49#include <sys/kernel.h>
50#include <machine/clock.h>
51#include <machine/ipl.h>
52
1f2de5d4 53#include <bus/isa/i386/isa_device.h>
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54
55#include <i386/isa/ic/cd180.h>
1f2de5d4 56#include "rcreg.h"
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57
58/* Prototypes */
5ca58d54
RG
59static int rcprobe (struct isa_device *);
60static int rcattach (struct isa_device *);
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61
62#define rcin(port) RC_IN (nec, port)
63#define rcout(port,v) RC_OUT (nec, port, v)
64
65#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__)
66#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd))
67
68#define RC_IBUFSIZE 256
69#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE)
70#define RC_OBUFSIZE 512
71#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4)
72#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE)
73#define LOTS_OF_EVENTS 64
74
75#define RC_FAKEID 0x10
76
77#define RC_PROBED 1
78#define RC_ATTACHED 2
79
80#define GET_UNIT(dev) (minor(dev) & 0x3F)
81#define CALLOUT(dev) (minor(dev) & 0x80)
82
83/* For isa routines */
84struct isa_driver rcdriver = {
85 rcprobe, rcattach, "rc"
86};
87
88static d_open_t rcopen;
89static d_close_t rcclose;
90static d_ioctl_t rcioctl;
91
92#define CDEV_MAJOR 63
93static struct cdevsw rc_cdevsw = {
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94 /* name */ "rc",
95 /* maj */ CDEV_MAJOR,
96 /* flags */ D_TTY | D_KQFILTER,
97 /* port */ NULL,
455fcd7e 98 /* clone */ NULL,
fabb8ceb 99
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100 /* open */ rcopen,
101 /* close */ rcclose,
102 /* read */ ttyread,
103 /* write */ ttywrite,
104 /* ioctl */ rcioctl,
105 /* poll */ ttypoll,
106 /* mmap */ nommap,
107 /* strategy */ nostrategy,
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108 /* dump */ nodump,
109 /* psize */ nopsize,
fabb8ceb 110 /* kqfilter */ ttykqfilter
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111};
112
113/* Per-board structure */
114static struct rc_softc {
115 u_int rcb_probed; /* 1 - probed, 2 - attached */
116 u_int rcb_addr; /* Base I/O addr */
117 u_int rcb_unit; /* unit # */
118 u_char rcb_dtr; /* DTR status */
119 struct rc_chans *rcb_baserc; /* base rc ptr */
120} rc_softc[NRC];
121
122/* Per-channel structure */
123static struct rc_chans {
124 struct rc_softc *rc_rcb; /* back ptr */
125 u_short rc_flags; /* Misc. flags */
126 int rc_chan; /* Channel # */
127 u_char rc_ier; /* intr. enable reg */
128 u_char rc_msvr; /* modem sig. status */
129 u_char rc_cor2; /* options reg */
130 u_char rc_pendcmd; /* special cmd pending */
131 u_int rc_dtrwait; /* dtr timeout */
132 u_int rc_dcdwaits; /* how many waits DCD in open */
133 u_char rc_hotchar; /* end packed optimize */
134 struct tty *rc_tp; /* tty struct */
135 u_char *rc_iptr; /* Chars input buffer */
136 u_char *rc_hiwat; /* hi-water mark */
137 u_char *rc_bufend; /* end of buffer */
138 u_char *rc_optr; /* ptr in output buf */
139 u_char *rc_obufend; /* end of output buf */
140 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */
141 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */
142} rc_chans[NRC * CD180_NCHAN];
143
144static int rc_scheduled_event = 0;
145
146/* for pstat -t */
147static struct tty rc_tty[NRC * CD180_NCHAN];
148static const int nrc_tty = NRC * CD180_NCHAN;
149
150/* Flags */
151#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */
152#define RC_ACTOUT 0x0002 /* Dial-out port active */
153#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */
154#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */
155#define RC_DORXFER 0x0010 /* RXFER event planned */
156#define RC_DOXXFER 0x0020 /* XXFER event planned */
157#define RC_MODCHG 0x0040 /* Modem status changed */
158#define RC_OSUSP 0x0080 /* Output suspended */
159#define RC_OSBUSY 0x0100 /* start() routine in progress */
160#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */
161#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */
162#define RC_SEND_RDY 0x0800 /* ready to send */
163
164/* Table for translation of RCSR status bits to internal form */
165static int rc_rcsrt[16] = {
166 0, TTY_OE, TTY_FE,
167 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE,
168 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI,
169 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE,
170 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE,
171 TTY_BI|TTY_PE|TTY_FE|TTY_OE
172};
173
174/* Static prototypes */
175static ointhand2_t rcintr;
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176static void rc_hwreset (int, int, unsigned int);
177static int rc_test (int, int);
178static void rc_discard_output (struct rc_chans *);
179static void rc_hardclose (struct rc_chans *);
180static int rc_modctl (struct rc_chans *, int, int);
181static void rc_start (struct tty *);
182static void rc_stop (struct tty *, int rw);
183static int rc_param (struct tty *, struct termios *);
7b95be2a 184static inthand2_t rcpoll;
5ca58d54 185static void rc_reinit (struct rc_softc *);
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186#ifdef RCDEBUG
187static void printrcflags();
188#endif
189static timeout_t rc_dtrwakeup;
190static timeout_t rc_wakeup;
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191static void disc_optim (struct tty *tp, struct termios *t, struct rc_chans *);
192static void rc_wait0 (int nec, int unit, int chan, int line);
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193
194/**********************************************/
195
196/* Quick device probing */
197static int
198rcprobe(dvp)
199 struct isa_device *dvp;
200{
201 int irq = ffs(dvp->id_irq) - 1;
c9faf524 202 int nec = dvp->id_iobase;
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203
204 if (dvp->id_unit > NRC)
205 return 0;
206 if (!RC_VALIDADDR(nec)) {
207 printf("rc%d: illegal base address %x\n", dvp->id_unit, nec);
208 return 0;
209 }
210 if (!RC_VALIDIRQ(irq)) {
211 printf("rc%d: illegal IRQ value %d\n", dvp->id_unit, irq);
212 return 0;
213 }
214 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */
215 rcout(CD180_PPRH, 0x11);
216 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11)
217 return 0;
218 /* Now, test the board more thoroughly, with diagnostic */
219 if (rc_test(nec, dvp->id_unit))
220 return 0;
221 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED;
222
223 return 0xF;
224}
225
226static int
227rcattach(dvp)
228 struct isa_device *dvp;
229{
c9faf524 230 int chan, nec = dvp->id_iobase;
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231 struct rc_softc *rcb = &rc_softc[dvp->id_unit];
232 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN];
233 static int rc_started = 0;
234 struct tty *tp;
235
236 dvp->id_ointr = rcintr;
237
238 /* Thorooughly test the device */
239 if (rcb->rcb_probed != RC_PROBED)
240 return 0;
241 rcb->rcb_addr = nec;
242 rcb->rcb_dtr = 0;
243 rcb->rcb_baserc = rc;
244 rcb->rcb_unit = dvp->id_unit;
245 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/
246 printf("rc%d: %d chans, firmware rev. %c\n", rcb->rcb_unit,
247 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A');
248
249 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) {
250 rc->rc_rcb = rcb;
251 rc->rc_chan = chan;
252 rc->rc_iptr = rc->rc_ibuf;
253 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
254 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER];
255 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0;
256 rc->rc_cor2 = rc->rc_pendcmd = 0;
257 rc->rc_optr = rc->rc_obufend = rc->rc_obuf;
258 rc->rc_dtrwait = 3 * hz;
259 rc->rc_dcdwaits= 0;
260 rc->rc_hotchar = 0;
261 tp = rc->rc_tp = &rc_tty[chan + (dvp->id_unit * CD180_NCHAN)];
262 ttychars(tp);
263 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0;
264 tp->t_cflag = TTYDEF_CFLAG;
265 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
266 }
267 rcb->rcb_probed = RC_ATTACHED;
268 if (!rc_started) {
e4c9c0c8 269 cdevsw_add(&rc_cdevsw, -1, rcb->rcb_unit);
7b95be2a 270 register_swi(SWI_TTY, rcpoll, NULL, "rcpoll");
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MD
271 rc_wakeup((void *)NULL);
272 rc_started = 1;
273 }
274 return 1;
275}
276
277/* RC interrupt handling */
278static void
279rcintr(unit)
280 int unit;
281{
c9faf524
RG
282 struct rc_softc *rcb = &rc_softc[unit];
283 struct rc_chans *rc;
284 int nec, resid;
285 u_char val, iack, bsr, ucnt, *optr;
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MD
286 int good_data, t_state;
287
288 if (rcb->rcb_probed != RC_ATTACHED) {
289 printf("rc%d: bogus interrupt\n", unit);
290 return;
291 }
292 nec = rcb->rcb_addr;
293
294 bsr = ~(rcin(RC_BSR));
295
296 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) {
297 printf("rc%d: extra interrupt\n", unit);
298 rcout(CD180_EOIR, 0);
299 return;
300 }
301
302 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) {
303#ifdef RCDEBUG_DETAILED
304 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr,
305 (bsr & RC_BSR_TOUT)?"TOUT ":"",
306 (bsr & RC_BSR_RXINT)?"RXINT ":"",
307 (bsr & RC_BSR_TXINT)?"TXINT ":"",
308 (bsr & RC_BSR_MOINT)?"MOINT":"");
309#endif
310 if (bsr & RC_BSR_TOUT) {
311 printf("rc%d: hardware failure, reset board\n", unit);
312 rcout(RC_CTOUT, 0);
313 rc_reinit(rcb);
314 return;
315 }
316 if (bsr & RC_BSR_RXINT) {
317 iack = rcin(RC_PILR_RX);
318 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID));
319 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) {
320 printf("rc%d: fake rxint: %02x\n", unit, iack);
321 goto more_intrs;
322 }
323 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
324 t_state = rc->rc_tp->t_state;
325 /* Do RTS flow control stuff */
326 if ( (rc->rc_flags & RC_RTSFLOW)
327 || !(t_state & TS_ISOPEN)
328 ) {
329 if ( ( !(t_state & TS_ISOPEN)
330 || (t_state & TS_TBLOCK)
331 )
332 && (rc->rc_msvr & MSVR_RTS)
333 )
334 rcout(CD180_MSVR,
335 rc->rc_msvr &= ~MSVR_RTS);
336 else if (!(rc->rc_msvr & MSVR_RTS))
337 rcout(CD180_MSVR,
338 rc->rc_msvr |= MSVR_RTS);
339 }
340 ucnt = rcin(CD180_RDCR) & 0xF;
341 resid = 0;
342
343 if (t_state & TS_ISOPEN) {
344 /* check for input buffer overflow */
345 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) {
346 resid = ucnt;
347 ucnt = rc->rc_bufend - rc->rc_iptr;
348 resid -= ucnt;
349 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) {
350 rc->rc_flags |= RC_WAS_BUFOVFL;
351 rc_scheduled_event++;
352 }
353 }
354 optr = rc->rc_iptr;
355 /* check foor good data */
356 if (good_data) {
357 while (ucnt-- > 0) {
358 val = rcin(CD180_RDR);
359 optr[0] = val;
360 optr[INPUT_FLAGS_SHIFT] = 0;
361 optr++;
362 rc_scheduled_event++;
363 if (val != 0 && val == rc->rc_hotchar)
364 setsofttty();
365 }
366 } else {
367 /* Store also status data */
368 while (ucnt-- > 0) {
369 iack = rcin(CD180_RCSR);
370 if (iack & RCSR_Timeout)
371 break;
372 if ( (iack & RCSR_OE)
373 && !(rc->rc_flags & RC_WAS_SILOVFL)) {
374 rc->rc_flags |= RC_WAS_SILOVFL;
375 rc_scheduled_event++;
376 }
377 val = rcin(CD180_RDR);
378 /*
379 Don't store PE if IGNPAR and BREAK if IGNBRK,
380 this hack allows "raw" tty optimization
381 works even if IGN* is set.
382 */
383 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break))
384 || ((!(iack & (RCSR_PE|RCSR_FE))
385 || !(rc->rc_tp->t_iflag & IGNPAR))
386 && (!(iack & RCSR_Break)
387 || !(rc->rc_tp->t_iflag & IGNBRK)))) {
388 if ( (iack & (RCSR_PE|RCSR_FE))
389 && (t_state & TS_CAN_BYPASS_L_RINT)
390 && ((iack & RCSR_FE)
391 || ((iack & RCSR_PE)
392 && (rc->rc_tp->t_iflag & INPCK))))
393 val = 0;
394 else if (val != 0 && val == rc->rc_hotchar)
395 setsofttty();
396 optr[0] = val;
397 optr[INPUT_FLAGS_SHIFT] = iack;
398 optr++;
399 rc_scheduled_event++;
400 }
401 }
402 }
403 rc->rc_iptr = optr;
404 rc->rc_flags |= RC_DORXFER;
405 } else
406 resid = ucnt;
407 /* Clear FIFO if necessary */
408 while (resid-- > 0) {
409 if (!good_data)
410 iack = rcin(CD180_RCSR);
411 else
412 iack = 0;
413 if (iack & RCSR_Timeout)
414 break;
415 (void) rcin(CD180_RDR);
416 }
417 goto more_intrs;
418 }
419 if (bsr & RC_BSR_MOINT) {
420 iack = rcin(RC_PILR_MODEM);
421 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) {
422 printf("rc%d: fake moint: %02x\n", unit, iack);
423 goto more_intrs;
424 }
425 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
426 iack = rcin(CD180_MCR);
427 rc->rc_msvr = rcin(CD180_MSVR);
428 rcout(CD180_MCR, 0);
429#ifdef RCDEBUG
430 printrcflags(rc, "moint");
431#endif
432 if (rc->rc_flags & RC_CTSFLOW) {
433 if (rc->rc_msvr & MSVR_CTS)
434 rc->rc_flags |= RC_SEND_RDY;
435 else
436 rc->rc_flags &= ~RC_SEND_RDY;
437 } else
438 rc->rc_flags |= RC_SEND_RDY;
439 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) {
440 rc_scheduled_event += LOTS_OF_EVENTS;
441 rc->rc_flags |= RC_MODCHG;
442 setsofttty();
443 }
444 goto more_intrs;
445 }
446 if (bsr & RC_BSR_TXINT) {
447 iack = rcin(RC_PILR_TX);
448 if (iack != (GIVR_IT_TDI | RC_FAKEID)) {
449 printf("rc%d: fake txint: %02x\n", unit, iack);
450 goto more_intrs;
451 }
452 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
453 if ( (rc->rc_flags & RC_OSUSP)
454 || !(rc->rc_flags & RC_SEND_RDY)
455 )
456 goto more_intrs;
457 /* Handle breaks and other stuff */
458 if (rc->rc_pendcmd) {
459 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC);
460 rcout(CD180_TDR, CD180_C_ESC);
461 rcout(CD180_TDR, rc->rc_pendcmd);
462 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC);
463 rc->rc_pendcmd = 0;
464 goto more_intrs;
465 }
466 optr = rc->rc_optr;
467 resid = rc->rc_obufend - optr;
468 if (resid > CD180_NFIFO)
469 resid = CD180_NFIFO;
470 while (resid-- > 0)
471 rcout(CD180_TDR, *optr++);
472 rc->rc_optr = optr;
473
474 /* output completed? */
475 if (optr >= rc->rc_obufend) {
476 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy);
477#ifdef RCDEBUG
478 printf("rc%d/%d: output completed\n", unit, rc->rc_chan);
479#endif
480 if (!(rc->rc_flags & RC_DOXXFER)) {
481 rc_scheduled_event += LOTS_OF_EVENTS;
482 rc->rc_flags |= RC_DOXXFER;
483 setsofttty();
484 }
485 }
486 }
487 more_intrs:
488 rcout(CD180_EOIR, 0); /* end of interrupt */
489 rcout(RC_CTOUT, 0);
490 bsr = ~(rcin(RC_BSR));
491 }
492}
493
494/* Feed characters to output buffer */
495static void rc_start(tp)
c9faf524 496struct tty *tp;
984263bc 497{
c9faf524
RG
498 struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
499 int nec = rc->rc_rcb->rcb_addr, s;
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MD
500
501 if (rc->rc_flags & RC_OSBUSY)
502 return;
503 s = spltty();
504 rc->rc_flags |= RC_OSBUSY;
7b95be2a 505 cpu_disable_intr();
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MD
506 if (tp->t_state & TS_TTSTOP)
507 rc->rc_flags |= RC_OSUSP;
508 else
509 rc->rc_flags &= ~RC_OSUSP;
510 /* Do RTS flow control stuff */
511 if ( (rc->rc_flags & RC_RTSFLOW)
512 && (tp->t_state & TS_TBLOCK)
513 && (rc->rc_msvr & MSVR_RTS)
514 ) {
515 rcout(CD180_CAR, rc->rc_chan);
516 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS);
517 } else if (!(rc->rc_msvr & MSVR_RTS)) {
518 rcout(CD180_CAR, rc->rc_chan);
519 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS);
520 }
7b95be2a 521 cpu_enable_intr();
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MD
522 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP))
523 goto out;
524#ifdef RCDEBUG
525 printrcflags(rc, "rcstart");
526#endif
527 ttwwakeup(tp);
528#ifdef RCDEBUG
529 printf("rcstart: outq = %d obuf = %d\n",
530 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr);
531#endif
532 if (tp->t_state & TS_BUSY)
533 goto out; /* output still in progress ... */
534
535 if (tp->t_outq.c_cc > 0) {
536 u_int ocnt;
537
538 tp->t_state |= TS_BUSY;
539 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf);
7b95be2a 540 cpu_disable_intr();
984263bc
MD
541 rc->rc_optr = rc->rc_obuf;
542 rc->rc_obufend = rc->rc_optr + ocnt;
7b95be2a 543 cpu_enable_intr();
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MD
544 if (!(rc->rc_ier & IER_TxRdy)) {
545#ifdef RCDEBUG
546 printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan);
547#endif
548 rcout(CD180_CAR, rc->rc_chan);
549 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy);
550 }
551 }
552out:
553 rc->rc_flags &= ~RC_OSBUSY;
554 (void) splx(s);
555}
556
557/* Handle delayed events. */
7b95be2a
MD
558void
559rcpoll(void *dummy)
984263bc 560{
c9faf524
RG
561 struct rc_chans *rc;
562 struct rc_softc *rcb;
563 u_char *tptr, *eptr;
564 struct tty *tp;
565 int chan, icnt, nec, unit;
984263bc
MD
566
567 if (rc_scheduled_event == 0)
568 return;
569repeat:
570 for (unit = 0; unit < NRC; unit++) {
571 rcb = &rc_softc[unit];
572 rc = rcb->rcb_baserc;
573 nec = rc->rc_rcb->rcb_addr;
574 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) {
575 tp = rc->rc_tp;
576#ifdef RCDEBUG
577 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG|
578 RC_WAS_BUFOVFL|RC_WAS_SILOVFL))
579 printrcflags(rc, "rcevent");
580#endif
581 if (rc->rc_flags & RC_WAS_BUFOVFL) {
7b95be2a 582 cpu_disable_intr();
984263bc
MD
583 rc->rc_flags &= ~RC_WAS_BUFOVFL;
584 rc_scheduled_event--;
7b95be2a 585 cpu_enable_intr();
984263bc
MD
586 printf("rc%d/%d: interrupt-level buffer overflow\n",
587 unit, chan);
588 }
589 if (rc->rc_flags & RC_WAS_SILOVFL) {
7b95be2a 590 cpu_disable_intr();
984263bc
MD
591 rc->rc_flags &= ~RC_WAS_SILOVFL;
592 rc_scheduled_event--;
7b95be2a 593 cpu_enable_intr();
984263bc
MD
594 printf("rc%d/%d: silo overflow\n",
595 unit, chan);
596 }
597 if (rc->rc_flags & RC_MODCHG) {
7b95be2a 598 cpu_disable_intr();
984263bc
MD
599 rc->rc_flags &= ~RC_MODCHG;
600 rc_scheduled_event -= LOTS_OF_EVENTS;
7b95be2a 601 cpu_enable_intr();
984263bc
MD
602 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD));
603 }
604 if (rc->rc_flags & RC_DORXFER) {
7b95be2a 605 cpu_disable_intr();
984263bc
MD
606 rc->rc_flags &= ~RC_DORXFER;
607 eptr = rc->rc_iptr;
608 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE])
609 tptr = &rc->rc_ibuf[RC_IBUFSIZE];
610 else
611 tptr = rc->rc_ibuf;
612 icnt = eptr - tptr;
613 if (icnt > 0) {
614 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
615 rc->rc_iptr = rc->rc_ibuf;
616 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
617 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER];
618 } else {
619 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
620 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE];
621 rc->rc_hiwat =
622 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER];
623 }
624 if ( (rc->rc_flags & RC_RTSFLOW)
625 && (tp->t_state & TS_ISOPEN)
626 && !(tp->t_state & TS_TBLOCK)
627 && !(rc->rc_msvr & MSVR_RTS)
628 ) {
629 rcout(CD180_CAR, chan);
630 rcout(CD180_MSVR,
631 rc->rc_msvr |= MSVR_RTS);
632 }
633 rc_scheduled_event -= icnt;
634 }
7b95be2a 635 cpu_enable_intr();
984263bc
MD
636
637 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN))
638 goto done1;
639
640 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT)
641 && !(tp->t_state & TS_LOCAL)) {
642 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER
643 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF))
644 && !(tp->t_state & TS_TBLOCK))
645 ttyblock(tp);
646 tk_nin += icnt;
647 tk_rawcc += icnt;
648 tp->t_rawcc += icnt;
649 if (b_to_q(tptr, icnt, &tp->t_rawq))
650 printf("rc%d/%d: tty-level buffer overflow\n",
651 unit, chan);
652 ttwakeup(tp);
653 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY)
654 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) {
655 tp->t_state &= ~TS_TTSTOP;
656 tp->t_lflag &= ~FLUSHO;
657 rc_start(tp);
658 }
659 } else {
660 for (; tptr < eptr; tptr++)
661 (*linesw[tp->t_line].l_rint)
662 (tptr[0] |
663 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp);
664 }
665done1: ;
666 }
667 if (rc->rc_flags & RC_DOXXFER) {
7b95be2a 668 cpu_disable_intr();
984263bc
MD
669 rc_scheduled_event -= LOTS_OF_EVENTS;
670 rc->rc_flags &= ~RC_DOXXFER;
671 rc->rc_tp->t_state &= ~TS_BUSY;
7b95be2a 672 cpu_enable_intr();
984263bc
MD
673 (*linesw[tp->t_line].l_start)(tp);
674 }
675 }
676 if (rc_scheduled_event == 0)
677 break;
678 }
679 if (rc_scheduled_event >= LOTS_OF_EVENTS)
680 goto repeat;
681}
682
683static void
684rc_stop(tp, rw)
c9faf524 685 struct tty *tp;
984263bc
MD
686 int rw;
687{
c9faf524 688 struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
984263bc
MD
689 u_char *tptr, *eptr;
690
691#ifdef RCDEBUG
692 printf("rc%d/%d: rc_stop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan,
693 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":"");
694#endif
695 if (rw & FWRITE)
696 rc_discard_output(rc);
7b95be2a 697 cpu_disable_intr();
984263bc
MD
698 if (rw & FREAD) {
699 rc->rc_flags &= ~RC_DORXFER;
700 eptr = rc->rc_iptr;
701 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
702 tptr = &rc->rc_ibuf[RC_IBUFSIZE];
703 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
704 } else {
705 tptr = rc->rc_ibuf;
706 rc->rc_iptr = rc->rc_ibuf;
707 }
708 rc_scheduled_event -= eptr - tptr;
709 }
710 if (tp->t_state & TS_TTSTOP)
711 rc->rc_flags |= RC_OSUSP;
712 else
713 rc->rc_flags &= ~RC_OSUSP;
7b95be2a 714 cpu_enable_intr();
984263bc
MD
715}
716
717static int
7b95be2a 718rcopen(dev, flag, mode, td)
984263bc
MD
719 dev_t dev;
720 int flag, mode;
7b95be2a 721 struct thread *td;
984263bc 722{
c9faf524
RG
723 struct rc_chans *rc;
724 struct tty *tp;
984263bc
MD
725 int unit, nec, s, error = 0;
726
727 unit = GET_UNIT(dev);
728 if (unit >= NRC * CD180_NCHAN)
729 return ENXIO;
730 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED)
731 return ENXIO;
732 rc = &rc_chans[unit];
733 tp = rc->rc_tp;
734 dev->si_tty = tp;
735 nec = rc->rc_rcb->rcb_addr;
736#ifdef RCDEBUG
737 printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
738#endif
739 s = spltty();
740
741again:
742 while (rc->rc_flags & RC_DTR_OFF) {
377d4740 743 error = tsleep(&(rc->rc_dtrwait), PCATCH, "rcdtr", 0);
984263bc
MD
744 if (error != 0)
745 goto out;
746 }
747 if (tp->t_state & TS_ISOPEN) {
748 if (CALLOUT(dev)) {
749 if (!(rc->rc_flags & RC_ACTOUT)) {
750 error = EBUSY;
751 goto out;
752 }
753 } else {
754 if (rc->rc_flags & RC_ACTOUT) {
755 if (flag & O_NONBLOCK) {
756 error = EBUSY;
757 goto out;
758 }
377d4740 759 error = tsleep(&rc->rc_rcb, PCATCH, "rcbi", 0);
984263bc
MD
760 if (error)
761 goto out;
762 goto again;
763 }
764 }
765 if (tp->t_state & TS_XCLUDE &&
dadab5e9 766 suser(td)) {
984263bc
MD
767 error = EBUSY;
768 goto out;
769 }
770 } else {
771 tp->t_oproc = rc_start;
772 tp->t_param = rc_param;
773 tp->t_stop = rc_stop;
774 tp->t_dev = dev;
775
776 if (CALLOUT(dev))
777 tp->t_cflag |= CLOCAL;
778 else
779 tp->t_cflag &= ~CLOCAL;
780
781 error = rc_param(tp, &tp->t_termios);
782 if (error)
783 goto out;
784 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET);
785
786 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev))
787 (*linesw[tp->t_line].l_modem)(tp, 1);
788 }
789 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev)
790 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
791 rc->rc_dcdwaits++;
377d4740 792 error = tsleep(TSA_CARR_ON(tp), PCATCH, "rcdcd", 0);
984263bc
MD
793 rc->rc_dcdwaits--;
794 if (error != 0)
795 goto out;
796 goto again;
797 }
798 error = (*linesw[tp->t_line].l_open)(dev, tp);
799 disc_optim(tp, &tp->t_termios, rc);
800 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev))
801 rc->rc_flags |= RC_ACTOUT;
802out:
803 (void) splx(s);
804
805 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN))
806 rc_hardclose(rc);
807
808 return error;
809}
810
811static int
7b95be2a 812rcclose(dev, flag, mode, td)
984263bc
MD
813 dev_t dev;
814 int flag, mode;
7b95be2a 815 struct thread *td;
984263bc 816{
c9faf524
RG
817 struct rc_chans *rc;
818 struct tty *tp;
984263bc
MD
819 int s, unit = GET_UNIT(dev);
820
821 if (unit >= NRC * CD180_NCHAN)
822 return ENXIO;
823 rc = &rc_chans[unit];
824 tp = rc->rc_tp;
825#ifdef RCDEBUG
826 printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
827#endif
828 s = spltty();
829 (*linesw[tp->t_line].l_close)(tp, flag);
830 disc_optim(tp, &tp->t_termios, rc);
831 rc_stop(tp, FREAD | FWRITE);
832 rc_hardclose(rc);
833 ttyclose(tp);
834 splx(s);
835 return 0;
836}
837
838static void rc_hardclose(rc)
c9faf524 839struct rc_chans *rc;
984263bc 840{
c9faf524
RG
841 int s, nec = rc->rc_rcb->rcb_addr;
842 struct tty *tp = rc->rc_tp;
984263bc
MD
843
844 s = spltty();
845 rcout(CD180_CAR, rc->rc_chan);
846
847 /* Disable rx/tx intrs */
848 rcout(CD180_IER, rc->rc_ier = 0);
849 if ( (tp->t_cflag & HUPCL)
850 || (!(rc->rc_flags & RC_ACTOUT)
851 && !(rc->rc_msvr & MSVR_CD)
852 && !(tp->t_cflag & CLOCAL))
853 || !(tp->t_state & TS_ISOPEN)
854 ) {
855 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
856 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
857 (void) rc_modctl(rc, TIOCM_RTS, DMSET);
858 if (rc->rc_dtrwait) {
859 timeout(rc_dtrwakeup, rc, rc->rc_dtrwait);
860 rc->rc_flags |= RC_DTR_OFF;
861 }
862 }
863 rc->rc_flags &= ~RC_ACTOUT;
864 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */
865 wakeup(TSA_CARR_ON(tp));
866 (void) splx(s);
867}
868
869/* Reset the bastard */
870static void rc_hwreset(unit, nec, chipid)
c9faf524 871 int unit, nec;
984263bc
MD
872 unsigned int chipid;
873{
874 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */
875 DELAY(20000);
876 WAITFORCCR(unit, -1);
877
878 rcout(RC_CTOUT, 0); /* Clear timeout */
879 rcout(CD180_GIVR, chipid);
880 rcout(CD180_GICR, 0);
881
882 /* Set Prescaler Registers (1 msec) */
883 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF);
884 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8);
885
886 /* Initialize Priority Interrupt Level Registers */
887 rcout(CD180_PILR1, RC_PILR_MODEM);
888 rcout(CD180_PILR2, RC_PILR_TX);
889 rcout(CD180_PILR3, RC_PILR_RX);
890
891 /* Reset DTR */
892 rcout(RC_DTREG, ~0);
893}
894
895/* Set channel parameters */
896static int rc_param(tp, ts)
c9faf524 897 struct tty *tp;
984263bc
MD
898 struct termios *ts;
899{
c9faf524
RG
900 struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
901 int nec = rc->rc_rcb->rcb_addr;
984263bc
MD
902 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow;
903
904 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800
905 || ts->c_ispeed < 0 || ts->c_ispeed > 76800
906 )
907 return (EINVAL);
908 if (ts->c_ispeed == 0)
909 ts->c_ispeed = ts->c_ospeed;
910 odivs = RC_BRD(ts->c_ospeed);
911 idivs = RC_BRD(ts->c_ispeed);
912
913 s = spltty();
914
915 /* Select channel */
916 rcout(CD180_CAR, rc->rc_chan);
917
918 /* If speed == 0, hangup line */
919 if (ts->c_ospeed == 0) {
920 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
921 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
922 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
923 }
924
925 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
926 cflag = ts->c_cflag;
927 iflag = ts->c_iflag;
928 lflag = ts->c_lflag;
929
930 if (idivs > 0) {
931 rcout(CD180_RBPRL, idivs & 0xFF);
932 rcout(CD180_RBPRH, idivs >> 8);
933 }
934 if (odivs > 0) {
935 rcout(CD180_TBPRL, odivs & 0xFF);
936 rcout(CD180_TBPRH, odivs >> 8);
937 }
938
939 /* set timeout value */
940 if (ts->c_ispeed > 0) {
941 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1;
942
943 if ( !(lflag & ICANON)
944 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0
945 && ts->c_cc[VTIME] * 10 > itm)
946 itm = ts->c_cc[VTIME] * 10;
947
948 rcout(CD180_RTPR, itm <= 255 ? itm : 255);
949 }
950
951 switch (cflag & CSIZE) {
952 case CS5: val = COR1_5BITS; break;
953 case CS6: val = COR1_6BITS; break;
954 case CS7: val = COR1_7BITS; break;
955 default:
956 case CS8: val = COR1_8BITS; break;
957 }
958 if (cflag & PARENB) {
959 val |= COR1_NORMPAR;
960 if (cflag & PARODD)
961 val |= COR1_ODDP;
962 if (!(cflag & INPCK))
963 val |= COR1_Ignore;
964 } else
965 val |= COR1_Ignore;
966 if (cflag & CSTOPB)
967 val |= COR1_2SB;
968 rcout(CD180_COR1, val);
969
970 /* Set FIFO threshold */
971 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2;
972 inpflow = 0;
973 if ( (iflag & IXOFF)
974 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE
975 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE
976 || (iflag & IXANY)
977 )
978 )
979 ) {
980 inpflow = 1;
981 val |= COR3_SCDE|COR3_FCT;
982 }
983 rcout(CD180_COR3, val);
984
985 /* Initialize on-chip automatic flow control */
986 val = 0;
987 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY);
988 if (cflag & CCTS_OFLOW) {
989 rc->rc_flags |= RC_CTSFLOW;
990 val |= COR2_CtsAE;
991 } else
992 rc->rc_flags |= RC_SEND_RDY;
993 if (tp->t_state & TS_TTSTOP)
994 rc->rc_flags |= RC_OSUSP;
995 else
996 rc->rc_flags &= ~RC_OSUSP;
997 if (cflag & CRTS_IFLOW)
998 rc->rc_flags |= RC_RTSFLOW;
999 else
1000 rc->rc_flags &= ~RC_RTSFLOW;
1001
1002 if (inpflow) {
1003 if (ts->c_cc[VSTART] != _POSIX_VDISABLE)
1004 rcout(CD180_SCHR1, ts->c_cc[VSTART]);
1005 rcout(CD180_SCHR2, ts->c_cc[VSTOP]);
1006 val |= COR2_TxIBE;
1007 if (iflag & IXANY)
1008 val |= COR2_IXM;
1009 }
1010
1011 rcout(CD180_COR2, rc->rc_cor2 = val);
1012
1013 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1014 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1015
1016 disc_optim(tp, ts, rc);
1017
1018 /* modem ctl */
1019 val = cflag & CLOCAL ? 0 : MCOR1_CDzd;
1020 if (cflag & CCTS_OFLOW)
1021 val |= MCOR1_CTSzd;
1022 rcout(CD180_MCOR1, val);
1023
1024 val = cflag & CLOCAL ? 0 : MCOR2_CDod;
1025 if (cflag & CCTS_OFLOW)
1026 val |= MCOR2_CTSod;
1027 rcout(CD180_MCOR2, val);
1028
1029 /* enable i/o and interrupts */
1030 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1031 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS));
1032 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
1033
1034 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD;
1035 if (cflag & CCTS_OFLOW)
1036 rc->rc_ier |= IER_CTS;
1037 if (cflag & CREAD)
1038 rc->rc_ier |= IER_RxData;
1039 if (tp->t_state & TS_BUSY)
1040 rc->rc_ier |= IER_TxRdy;
1041 if (ts->c_ospeed != 0)
1042 rc_modctl(rc, TIOCM_DTR, DMBIS);
1043 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS))
1044 rc->rc_flags |= RC_SEND_RDY;
1045 rcout(CD180_IER, rc->rc_ier);
1046 (void) splx(s);
1047 return 0;
1048}
1049
1050/* Re-initialize board after bogus interrupts */
1051static void rc_reinit(rcb)
1052struct rc_softc *rcb;
1053{
c9faf524
RG
1054 struct rc_chans *rc, *rce;
1055 int nec;
984263bc
MD
1056
1057 nec = rcb->rcb_addr;
1058 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID);
1059 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN];
1060 rce = rc + CD180_NCHAN;
1061 for (; rc < rce; rc++)
1062 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios);
1063}
1064
1065static int
7b95be2a 1066rcioctl(dev, cmd, data, flag, td)
984263bc
MD
1067dev_t dev;
1068u_long cmd;
1069int flag;
1070caddr_t data;
7b95be2a 1071struct thread *td;
984263bc 1072{
c9faf524
RG
1073 struct rc_chans *rc = &rc_chans[GET_UNIT(dev)];
1074 int s, error;
984263bc
MD
1075 struct tty *tp = rc->rc_tp;
1076
7b95be2a 1077 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td);
984263bc
MD
1078 if (error != ENOIOCTL)
1079 return (error);
1080 error = ttioctl(tp, cmd, data, flag);
1081 disc_optim(tp, &tp->t_termios, rc);
1082 if (error != ENOIOCTL)
1083 return (error);
1084 s = spltty();
1085
1086 switch (cmd) {
1087 case TIOCSBRK:
1088 rc->rc_pendcmd = CD180_C_SBRK;
1089 break;
1090
1091 case TIOCCBRK:
1092 rc->rc_pendcmd = CD180_C_EBRK;
1093 break;
1094
1095 case TIOCSDTR:
1096 (void) rc_modctl(rc, TIOCM_DTR, DMBIS);
1097 break;
1098
1099 case TIOCCDTR:
1100 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
1101 break;
1102
1103 case TIOCMGET:
1104 *(int *) data = rc_modctl(rc, 0, DMGET);
1105 break;
1106
1107 case TIOCMSET:
1108 (void) rc_modctl(rc, *(int *) data, DMSET);
1109 break;
1110
1111 case TIOCMBIC:
1112 (void) rc_modctl(rc, *(int *) data, DMBIC);
1113 break;
1114
1115 case TIOCMBIS:
1116 (void) rc_modctl(rc, *(int *) data, DMBIS);
1117 break;
1118
1119 case TIOCMSDTRWAIT:
dadab5e9 1120 error = suser(td);
984263bc
MD
1121 if (error != 0) {
1122 splx(s);
1123 return (error);
1124 }
1125 rc->rc_dtrwait = *(int *)data * hz / 100;
1126 break;
1127
1128 case TIOCMGDTRWAIT:
1129 *(int *)data = rc->rc_dtrwait * 100 / hz;
1130 break;
1131
1132 default:
1133 (void) splx(s);
1134 return ENOTTY;
1135 }
1136 (void) splx(s);
1137 return 0;
1138}
1139
1140
1141/* Modem control routines */
1142
1143static int rc_modctl(rc, bits, cmd)
c9faf524 1144struct rc_chans *rc;
984263bc
MD
1145int bits, cmd;
1146{
c9faf524 1147 int nec = rc->rc_rcb->rcb_addr;
984263bc
MD
1148 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr;
1149
1150 rcout(CD180_CAR, rc->rc_chan);
1151
1152 switch (cmd) {
1153 case DMSET:
1154 rcout(RC_DTREG, (bits & TIOCM_DTR) ?
1155 ~(*dtr |= 1 << rc->rc_chan) :
1156 ~(*dtr &= ~(1 << rc->rc_chan)));
1157 msvr = rcin(CD180_MSVR);
1158 if (bits & TIOCM_RTS)
1159 msvr |= MSVR_RTS;
1160 else
1161 msvr &= ~MSVR_RTS;
1162 if (bits & TIOCM_DTR)
1163 msvr |= MSVR_DTR;
1164 else
1165 msvr &= ~MSVR_DTR;
1166 rcout(CD180_MSVR, msvr);
1167 break;
1168
1169 case DMBIS:
1170 if (bits & TIOCM_DTR)
1171 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan));
1172 msvr = rcin(CD180_MSVR);
1173 if (bits & TIOCM_RTS)
1174 msvr |= MSVR_RTS;
1175 if (bits & TIOCM_DTR)
1176 msvr |= MSVR_DTR;
1177 rcout(CD180_MSVR, msvr);
1178 break;
1179
1180 case DMGET:
1181 bits = TIOCM_LE;
1182 msvr = rc->rc_msvr = rcin(CD180_MSVR);
1183
1184 if (msvr & MSVR_RTS)
1185 bits |= TIOCM_RTS;
1186 if (msvr & MSVR_CTS)
1187 bits |= TIOCM_CTS;
1188 if (msvr & MSVR_DSR)
1189 bits |= TIOCM_DSR;
1190 if (msvr & MSVR_DTR)
1191 bits |= TIOCM_DTR;
1192 if (msvr & MSVR_CD)
1193 bits |= TIOCM_CD;
1194 if (~rcin(RC_RIREG) & (1 << rc->rc_chan))
1195 bits |= TIOCM_RI;
1196 return bits;
1197
1198 case DMBIC:
1199 if (bits & TIOCM_DTR)
1200 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan)));
1201 msvr = rcin(CD180_MSVR);
1202 if (bits & TIOCM_RTS)
1203 msvr &= ~MSVR_RTS;
1204 if (bits & TIOCM_DTR)
1205 msvr &= ~MSVR_DTR;
1206 rcout(CD180_MSVR, msvr);
1207 break;
1208 }
1209 rc->rc_msvr = rcin(CD180_MSVR);
1210 return 0;
1211}
1212
1213/* Test the board. */
1214int rc_test(nec, unit)
c9faf524 1215 int nec;
984263bc
MD
1216 int unit;
1217{
1218 int chan = 0;
1219 int i = 0, rcnt, old_level;
1220 unsigned int iack, chipid;
1221 unsigned short divs;
1222 static u_char ctest[] = "\377\125\252\045\244\0\377";
1223#define CTLEN 8
1224#define ERR(s) { \
1225 printf("rc%d: ", unit); printf s ; printf("\n"); \
1226 (void) splx(old_level); return 1; }
1227
1228 struct rtest {
1229 u_char txbuf[CD180_NFIFO]; /* TX buffer */
1230 u_char rxbuf[CD180_NFIFO]; /* RX buffer */
1231 int rxptr; /* RX pointer */
1232 int txptr; /* TX pointer */
1233 } tchans[CD180_NCHAN];
1234
1235 old_level = spltty();
1236
1237 chipid = RC_FAKEID;
1238
1239 /* First, reset board to inital state */
1240 rc_hwreset(unit, nec, chipid);
1241
1242 divs = RC_BRD(19200);
1243
1244 /* Initialize channels */
1245 for (chan = 0; chan < CD180_NCHAN; chan++) {
1246
1247 /* Select and reset channel */
1248 rcout(CD180_CAR, chan);
1249 CCRCMD(unit, chan, CCR_ResetChan);
1250 WAITFORCCR(unit, chan);
1251
1252 /* Set speed */
1253 rcout(CD180_RBPRL, divs & 0xFF);
1254 rcout(CD180_RBPRH, divs >> 8);
1255 rcout(CD180_TBPRL, divs & 0xFF);
1256 rcout(CD180_TBPRH, divs >> 8);
1257
1258 /* set timeout value */
1259 rcout(CD180_RTPR, 0);
1260
1261 /* Establish local loopback */
1262 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB);
1263 rcout(CD180_COR2, COR2_LLM);
1264 rcout(CD180_COR3, CD180_NFIFO);
1265 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1266 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN);
1267 WAITFORCCR(unit, chan);
1268 rcout(CD180_MSVR, MSVR_RTS);
1269
1270 /* Fill TXBUF with test data */
1271 for (i = 0; i < CD180_NFIFO; i++) {
1272 tchans[chan].txbuf[i] = ctest[i];
1273 tchans[chan].rxbuf[i] = 0;
1274 }
1275 tchans[chan].txptr = tchans[chan].rxptr = 0;
1276
1277 /* Now, start transmit */
1278 rcout(CD180_IER, IER_TxMpty|IER_RxData);
1279 }
1280 /* Pseudo-interrupt poll stuff */
1281 for (rcnt = 10000; rcnt-- > 0; rcnt--) {
1282 i = ~(rcin(RC_BSR));
1283 if (i & RC_BSR_TOUT)
1284 ERR(("BSR timeout bit set\n"))
1285 else if (i & RC_BSR_TXINT) {
1286 iack = rcin(RC_PILR_TX);
1287 if (iack != (GIVR_IT_TDI | chipid))
1288 ERR(("Bad TX intr ack (%02x != %02x)\n",
1289 iack, GIVR_IT_TDI | chipid));
1290 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1291 /* If no more data to transmit, disable TX intr */
1292 if (tchans[chan].txptr >= CD180_NFIFO) {
1293 iack = rcin(CD180_IER);
1294 rcout(CD180_IER, iack & ~IER_TxMpty);
1295 } else {
1296 for (iack = tchans[chan].txptr;
1297 iack < CD180_NFIFO; iack++)
1298 rcout(CD180_TDR,
1299 tchans[chan].txbuf[iack]);
1300 tchans[chan].txptr = iack;
1301 }
1302 rcout(CD180_EOIR, 0);
1303 } else if (i & RC_BSR_RXINT) {
1304 u_char ucnt;
1305
1306 iack = rcin(RC_PILR_RX);
1307 if (iack != (GIVR_IT_RGDI | chipid) &&
1308 iack != (GIVR_IT_REI | chipid))
1309 ERR(("Bad RX intr ack (%02x != %02x)\n",
1310 iack, GIVR_IT_RGDI | chipid))
1311 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1312 ucnt = rcin(CD180_RDCR) & 0xF;
1313 while (ucnt-- > 0) {
1314 iack = rcin(CD180_RCSR);
1315 if (iack & RCSR_Timeout)
1316 break;
1317 if (iack & 0xF)
1318 ERR(("Bad char chan %d (RCSR = %02X)\n",
1319 chan, iack))
1320 if (tchans[chan].rxptr > CD180_NFIFO)
1321 ERR(("Got extra chars chan %d\n",
1322 chan))
1323 tchans[chan].rxbuf[tchans[chan].rxptr++] =
1324 rcin(CD180_RDR);
1325 }
1326 rcout(CD180_EOIR, 0);
1327 }
1328 rcout(RC_CTOUT, 0);
1329 for (iack = chan = 0; chan < CD180_NCHAN; chan++)
1330 if (tchans[chan].rxptr >= CD180_NFIFO)
1331 iack++;
1332 if (iack == CD180_NCHAN)
1333 break;
1334 }
1335 for (chan = 0; chan < CD180_NCHAN; chan++) {
1336 /* Select and reset channel */
1337 rcout(CD180_CAR, chan);
1338 CCRCMD(unit, chan, CCR_ResetChan);
1339 }
1340
1341 if (!rcnt)
1342 ERR(("looses characters during local loopback\n"))
1343 /* Now, check data */
1344 for (chan = 0; chan < CD180_NCHAN; chan++)
1345 for (i = 0; i < CD180_NFIFO; i++)
1346 if (ctest[i] != tchans[chan].rxbuf[i])
1347 ERR(("data mismatch chan %d ptr %d (%d != %d)\n",
1348 chan, i, ctest[i], tchans[chan].rxbuf[i]))
1349 (void) splx(old_level);
1350 return 0;
1351}
1352
1353#ifdef RCDEBUG
1354static void printrcflags(rc, comment)
1355struct rc_chans *rc;
1356char *comment;
1357{
1358 u_short f = rc->rc_flags;
c9faf524 1359 int nec = rc->rc_rcb->rcb_addr;
984263bc
MD
1360
1361 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n",
1362 rc->rc_rcb->rcb_unit, rc->rc_chan, comment,
1363 (f & RC_DTR_OFF)?"DTR_OFF " :"",
1364 (f & RC_ACTOUT) ?"ACTOUT " :"",
1365 (f & RC_RTSFLOW)?"RTSFLOW " :"",
1366 (f & RC_CTSFLOW)?"CTSFLOW " :"",
1367 (f & RC_DORXFER)?"DORXFER " :"",
1368 (f & RC_DOXXFER)?"DOXXFER " :"",
1369 (f & RC_MODCHG) ?"MODCHG " :"",
1370 (f & RC_OSUSP) ?"OSUSP " :"",
1371 (f & RC_OSBUSY) ?"OSBUSY " :"",
1372 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"",
1373 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"",
1374 (f & RC_SEND_RDY) ?"SEND_RDY":"");
1375
1376 rcout(CD180_CAR, rc->rc_chan);
1377
1378 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n",
1379 rc->rc_rcb->rcb_unit, rc->rc_chan,
1380 rcin(CD180_MSVR),
1381 rcin(CD180_IER),
1382 rcin(CD180_CCSR));
1383}
1384#endif /* RCDEBUG */
1385
1386static void
1387rc_dtrwakeup(chan)
1388 void *chan;
1389{
1390 struct rc_chans *rc;
1391
1392 rc = (struct rc_chans *)chan;
1393 rc->rc_flags &= ~RC_DTR_OFF;
1394 wakeup(&rc->rc_dtrwait);
1395}
1396
1397static void
1398rc_discard_output(rc)
1399 struct rc_chans *rc;
1400{
7b95be2a 1401 cpu_disable_intr();
984263bc
MD
1402 if (rc->rc_flags & RC_DOXXFER) {
1403 rc_scheduled_event -= LOTS_OF_EVENTS;
1404 rc->rc_flags &= ~RC_DOXXFER;
1405 }
1406 rc->rc_optr = rc->rc_obufend;
1407 rc->rc_tp->t_state &= ~TS_BUSY;
7b95be2a 1408 cpu_enable_intr();
984263bc
MD
1409 ttwwakeup(rc->rc_tp);
1410}
1411
1412static void
1413rc_wakeup(chan)
1414 void *chan;
1415{
1416 timeout(rc_wakeup, (caddr_t)NULL, 1);
1417
1418 if (rc_scheduled_event != 0) {
1419 int s;
1420
1421 s = splsofttty();
7b95be2a 1422 rcpoll(NULL);
984263bc
MD
1423 splx(s);
1424 }
1425}
1426
1427static void
1428disc_optim(tp, t, rc)
1429 struct tty *tp;
1430 struct termios *t;
1431 struct rc_chans *rc;
1432{
1433
1434 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
1435 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
1436 && (!(t->c_iflag & PARMRK)
1437 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
1438 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
1439 && linesw[tp->t_line].l_rint == ttyinput)
1440 tp->t_state |= TS_CAN_BYPASS_L_RINT;
1441 else
1442 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
1443 rc->rc_hotchar = linesw[tp->t_line].l_hotchar;
1444}
1445
1446static void
1447rc_wait0(nec, unit, chan, line)
1448 int nec, unit, chan, line;
1449{
1450 int rcnt;
1451
1452 for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--)
1453 DELAY(30);
1454 if (rcnt == 0)
1455 printf("rc%d/%d: channel command timeout, rc.c line: %d\n",
1456 unit, chan, line);
1457}