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[dragonfly.git] / sys / bus / pci / pci.c
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1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
27 *
28 */
29
30#include "opt_bus.h"
31#include "opt_pci.h"
32
33#include "opt_simos.h"
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/malloc.h>
38#include <sys/module.h>
39#include <sys/fcntl.h>
40#include <sys/conf.h>
41#include <sys/kernel.h>
42#include <sys/queue.h>
43#include <sys/types.h>
44#include <sys/buf.h>
45
46#include <vm/vm.h>
47#include <vm/pmap.h>
48#include <vm/vm_extern.h>
49
50#include <sys/bus.h>
51#include <machine/bus.h>
52#include <sys/rman.h>
53#include <machine/resource.h>
54#include <machine/md_var.h> /* For the Alpha */
55#ifdef __i386__
56#include <machine/pci_cfgreg.h>
57#endif
58
59#include <pci/pcireg.h>
60#include <pci/pcivar.h>
61#include <sys/pciio.h>
62
63#ifdef __alpha__
64#include <machine/rpb.h>
65#endif
66
67#ifdef APIC_IO
68#include <machine/smp.h>
69#endif /* APIC_IO */
70
71static void pci_read_extcap(pcicfgregs *cfg);
72
73struct pci_quirk {
74 u_int32_t devid; /* Vendor/device of the card */
75 int type;
76#define PCI_QUIRK_MAP_REG 1 /* PCI map register in wierd place */
77 int arg1;
78 int arg2;
79};
80
81struct pci_quirk pci_quirks[] = {
82 /*
83 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
84 */
85 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
86 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
87
88 { 0 }
89};
90
91/* map register information */
92#define PCI_MAPMEM 0x01 /* memory map */
93#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
94#define PCI_MAPPORT 0x04 /* port map */
95
96struct pci_devinfo {
97 STAILQ_ENTRY(pci_devinfo) pci_links;
98 struct resource_list resources;
99 pcicfgregs cfg;
100 struct pci_conf conf;
101};
102
103static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
104u_int32_t pci_numdevs = 0;
105static u_int32_t pci_generation = 0;
106
107device_t
108pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func)
109{
110 struct pci_devinfo *dinfo;
111
112 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
113 if ((dinfo->cfg.bus == bus) &&
114 (dinfo->cfg.slot == slot) &&
115 (dinfo->cfg.func == func)) {
116 return (dinfo->cfg.dev);
117 }
118 }
119
120 return (NULL);
121}
122
123device_t
124pci_find_device (u_int16_t vendor, u_int16_t device)
125{
126 struct pci_devinfo *dinfo;
127
128 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
129 if ((dinfo->cfg.vendor == vendor) &&
130 (dinfo->cfg.device == device)) {
131 return (dinfo->cfg.dev);
132 }
133 }
134
135 return (NULL);
136}
137
138/* return base address of memory or port map */
139
140static u_int32_t
141pci_mapbase(unsigned mapreg)
142{
143 int mask = 0x03;
144 if ((mapreg & 0x01) == 0)
145 mask = 0x0f;
146 return (mapreg & ~mask);
147}
148
149/* return map type of memory or port map */
150
151static int
152pci_maptype(unsigned mapreg)
153{
154 static u_int8_t maptype[0x10] = {
155 PCI_MAPMEM, PCI_MAPPORT,
156 PCI_MAPMEM, 0,
157 PCI_MAPMEM, PCI_MAPPORT,
158 0, 0,
159 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
160 PCI_MAPMEM|PCI_MAPMEMP, 0,
161 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
162 0, 0,
163 };
164
165 return maptype[mapreg & 0x0f];
166}
167
168/* return log2 of map size decoded for memory or port map */
169
170static int
171pci_mapsize(unsigned testval)
172{
173 int ln2size;
174
175 testval = pci_mapbase(testval);
176 ln2size = 0;
177 if (testval != 0) {
178 while ((testval & 1) == 0)
179 {
180 ln2size++;
181 testval >>= 1;
182 }
183 }
184 return (ln2size);
185}
186
187/* return log2 of address range supported by map register */
188
189static int
190pci_maprange(unsigned mapreg)
191{
192 int ln2range = 0;
193 switch (mapreg & 0x07) {
194 case 0x00:
195 case 0x01:
196 case 0x05:
197 ln2range = 32;
198 break;
199 case 0x02:
200 ln2range = 20;
201 break;
202 case 0x04:
203 ln2range = 64;
204 break;
205 }
206 return (ln2range);
207}
208
209/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
210
211static void
212pci_fixancient(pcicfgregs *cfg)
213{
214 if (cfg->hdrtype != 0)
215 return;
216
217 /* PCI to PCI bridges use header type 1 */
218 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
219 cfg->hdrtype = 1;
220}
221
222/* read config data specific to header type 1 device (PCI to PCI bridge) */
223
224static void *
225pci_readppb(pcicfgregs *cfg)
226{
227 pcih1cfgregs *p;
228
229 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK);
230 if (p == NULL)
231 return (NULL);
232
233 bzero(p, sizeof *p);
234
235 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_1, 2);
236 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_1, 2);
237
238 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_1, 1);
239
240 p->iobase = PCI_PPBIOBASE (pci_cfgread(cfg, PCIR_IOBASEH_1, 2),
241 pci_cfgread(cfg, PCIR_IOBASEL_1, 1));
242 p->iolimit = PCI_PPBIOLIMIT (pci_cfgread(cfg, PCIR_IOLIMITH_1, 2),
243 pci_cfgread(cfg, PCIR_IOLIMITL_1, 1));
244
245 p->membase = PCI_PPBMEMBASE (0,
246 pci_cfgread(cfg, PCIR_MEMBASE_1, 2));
247 p->memlimit = PCI_PPBMEMLIMIT (0,
248 pci_cfgread(cfg, PCIR_MEMLIMIT_1, 2));
249
250 p->pmembase = PCI_PPBMEMBASE (
251 (pci_addr_t)pci_cfgread(cfg, PCIR_PMBASEH_1, 4),
252 pci_cfgread(cfg, PCIR_PMBASEL_1, 2));
253
254 p->pmemlimit = PCI_PPBMEMLIMIT (
255 (pci_addr_t)pci_cfgread(cfg, PCIR_PMLIMITH_1, 4),
256 pci_cfgread(cfg, PCIR_PMLIMITL_1, 2));
257 return (p);
258}
259
260/* read config data specific to header type 2 device (PCI to CardBus bridge) */
261
262static void *
263pci_readpcb(pcicfgregs *cfg)
264{
265 pcih2cfgregs *p;
266
267 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK);
268 if (p == NULL)
269 return (NULL);
270
271 bzero(p, sizeof *p);
272
273 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_2, 2);
274 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_2, 2);
275
276 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_2, 1);
277
278 p->membase0 = pci_cfgread(cfg, PCIR_MEMBASE0_2, 4);
279 p->memlimit0 = pci_cfgread(cfg, PCIR_MEMLIMIT0_2, 4);
280 p->membase1 = pci_cfgread(cfg, PCIR_MEMBASE1_2, 4);
281 p->memlimit1 = pci_cfgread(cfg, PCIR_MEMLIMIT1_2, 4);
282
283 p->iobase0 = pci_cfgread(cfg, PCIR_IOBASE0_2, 4);
284 p->iolimit0 = pci_cfgread(cfg, PCIR_IOLIMIT0_2, 4);
285 p->iobase1 = pci_cfgread(cfg, PCIR_IOBASE1_2, 4);
286 p->iolimit1 = pci_cfgread(cfg, PCIR_IOLIMIT1_2, 4);
287
288 p->pccardif = pci_cfgread(cfg, PCIR_PCCARDIF_2, 4);
289 return p;
290}
291
292/* extract header type specific config data */
293
294static void
295pci_hdrtypedata(pcicfgregs *cfg)
296{
297 switch (cfg->hdrtype) {
298 case 0:
299 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_0, 2);
300 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_0, 2);
301 cfg->nummaps = PCI_MAXMAPS_0;
302 break;
303 case 1:
304 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_1, 2);
305 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_1, 2);
306 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_1, 1);
307 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_1, 1);
308 cfg->nummaps = PCI_MAXMAPS_1;
309 cfg->hdrspec = pci_readppb(cfg);
310 break;
311 case 2:
312 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_2, 2);
313 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_2, 2);
314 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_2, 1);
315 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_2, 1);
316 cfg->nummaps = PCI_MAXMAPS_2;
317 cfg->hdrspec = pci_readpcb(cfg);
318 break;
319 }
320}
321
322/* read configuration header into pcicfgrect structure */
323
324static struct pci_devinfo *
325pci_readcfg(pcicfgregs *probe)
326{
327#define REG(n, w) pci_cfgread(probe, n, w)
328
329 pcicfgregs *cfg = NULL;
330 struct pci_devinfo *devlist_entry;
331 struct devlist *devlist_head;
332
333 devlist_head = &pci_devq;
334
335 devlist_entry = NULL;
336
337 if (pci_cfgread(probe, PCIR_DEVVENDOR, 4) != -1) {
338
339 devlist_entry = malloc(sizeof(struct pci_devinfo),
340 M_DEVBUF, M_WAITOK);
341 if (devlist_entry == NULL)
342 return (NULL);
343 bzero(devlist_entry, sizeof *devlist_entry);
344
345 cfg = &devlist_entry->cfg;
346
347 cfg->hose = probe->hose;
348 cfg->bus = probe->bus;
349 cfg->slot = probe->slot;
350 cfg->func = probe->func;
351 cfg->vendor = pci_cfgread(cfg, PCIR_VENDOR, 2);
352 cfg->device = pci_cfgread(cfg, PCIR_DEVICE, 2);
353 cfg->cmdreg = pci_cfgread(cfg, PCIR_COMMAND, 2);
354 cfg->statreg = pci_cfgread(cfg, PCIR_STATUS, 2);
355 cfg->baseclass = pci_cfgread(cfg, PCIR_CLASS, 1);
356 cfg->subclass = pci_cfgread(cfg, PCIR_SUBCLASS, 1);
357 cfg->progif = pci_cfgread(cfg, PCIR_PROGIF, 1);
358 cfg->revid = pci_cfgread(cfg, PCIR_REVID, 1);
359 cfg->hdrtype = pci_cfgread(cfg, PCIR_HEADERTYPE, 1);
360 cfg->cachelnsz = pci_cfgread(cfg, PCIR_CACHELNSZ, 1);
361 cfg->lattimer = pci_cfgread(cfg, PCIR_LATTIMER, 1);
362 cfg->intpin = pci_cfgread(cfg, PCIR_INTPIN, 1);
363 cfg->intline = pci_cfgread(cfg, PCIR_INTLINE, 1);
364#ifdef __alpha__
365 alpha_platform_assign_pciintr(cfg);
366#endif
367
368#ifdef APIC_IO
369 if (cfg->intpin != 0) {
370 int airq;
371
372 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
373 if (airq >= 0) {
374 /* PCI specific entry found in MP table */
375 if (airq != cfg->intline) {
376 undirect_pci_irq(cfg->intline);
377 cfg->intline = airq;
378 }
379 } else {
380 /*
381 * PCI interrupts might be redirected to the
382 * ISA bus according to some MP tables. Use the
383 * same methods as used by the ISA devices
384 * devices to find the proper IOAPIC int pin.
385 */
386 airq = isa_apic_irq(cfg->intline);
387 if ((airq >= 0) && (airq != cfg->intline)) {
388 /* XXX: undirect_pci_irq() ? */
389 undirect_isa_irq(cfg->intline);
390 cfg->intline = airq;
391 }
392 }
393 }
394#endif /* APIC_IO */
395
396 cfg->mingnt = pci_cfgread(cfg, PCIR_MINGNT, 1);
397 cfg->maxlat = pci_cfgread(cfg, PCIR_MAXLAT, 1);
398
399 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
400 cfg->hdrtype &= ~PCIM_MFDEV;
401
402 pci_fixancient(cfg);
403 pci_hdrtypedata(cfg);
404
405 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
406 pci_read_extcap(cfg);
407
408 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
409
410 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
411 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
412 devlist_entry->conf.pc_sel.pc_func = cfg->func;
413 devlist_entry->conf.pc_hdr = cfg->hdrtype;
414
415 devlist_entry->conf.pc_subvendor = cfg->subvendor;
416 devlist_entry->conf.pc_subdevice = cfg->subdevice;
417 devlist_entry->conf.pc_vendor = cfg->vendor;
418 devlist_entry->conf.pc_device = cfg->device;
419
420 devlist_entry->conf.pc_class = cfg->baseclass;
421 devlist_entry->conf.pc_subclass = cfg->subclass;
422 devlist_entry->conf.pc_progif = cfg->progif;
423 devlist_entry->conf.pc_revid = cfg->revid;
424
425 pci_numdevs++;
426 pci_generation++;
427 }
428 return (devlist_entry);
429#undef REG
430}
431
432static void
433pci_read_extcap(pcicfgregs *cfg)
434{
435#define REG(n, w) pci_cfgread(cfg, n, w)
436 int ptr, nextptr, ptrptr;
437
438 switch (cfg->hdrtype) {
439 case 0:
440 ptrptr = 0x34;
441 break;
442 case 2:
443 ptrptr = 0x14;
444 break;
445 default:
446 return; /* no extended capabilities support */
447 }
448 nextptr = REG(ptrptr, 1); /* sanity check? */
449
450 /*
451 * Read capability entries.
452 */
453 while (nextptr != 0) {
454 /* Sanity check */
455 if (nextptr > 255) {
456 printf("illegal PCI extended capability offset %d\n",
457 nextptr);
458 return;
459 }
460 /* Find the next entry */
461 ptr = nextptr;
462 nextptr = REG(ptr + 1, 1);
463
464 /* Process this entry */
465 switch (REG(ptr, 1)) {
466 case 0x01: /* PCI power management */
467 if (cfg->pp_cap == 0) {
468 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
469 cfg->pp_status = ptr + PCIR_POWER_STATUS;
470 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
471 if ((nextptr - ptr) > PCIR_POWER_DATA)
472 cfg->pp_data = ptr + PCIR_POWER_DATA;
473 }
474 break;
475 default:
476 break;
477 }
478 }
479#undef REG
480}
481
482#if 0
483/* free pcicfgregs structure and all depending data structures */
484
485static int
486pci_freecfg(struct pci_devinfo *dinfo)
487{
488 struct devlist *devlist_head;
489
490 devlist_head = &pci_devq;
491
492 if (dinfo->cfg.hdrspec != NULL)
493 free(dinfo->cfg.hdrspec, M_DEVBUF);
494 if (dinfo->cfg.map != NULL)
495 free(dinfo->cfg.map, M_DEVBUF);
496 /* XXX this hasn't been tested */
497 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
498 free(dinfo, M_DEVBUF);
499
500 /* increment the generation count */
501 pci_generation++;
502
503 /* we're losing one device */
504 pci_numdevs--;
505 return (0);
506}
507#endif
508
509
510/*
511 * PCI power manangement
512 */
513static int
514pci_set_powerstate_method(device_t dev, device_t child, int state)
515{
516 struct pci_devinfo *dinfo = device_get_ivars(child);
517 pcicfgregs *cfg = &dinfo->cfg;
518 u_int16_t status;
519 int result;
520
521 if (cfg->pp_cap != 0) {
522 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK;
523 result = 0;
524 switch (state) {
525 case PCI_POWERSTATE_D0:
526 status |= PCIM_PSTAT_D0;
527 break;
528 case PCI_POWERSTATE_D1:
529 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) {
530 status |= PCIM_PSTAT_D1;
531 } else {
532 result = EOPNOTSUPP;
533 }
534 break;
535 case PCI_POWERSTATE_D2:
536 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) {
537 status |= PCIM_PSTAT_D2;
538 } else {
539 result = EOPNOTSUPP;
540 }
541 break;
542 case PCI_POWERSTATE_D3:
543 status |= PCIM_PSTAT_D3;
544 break;
545 default:
546 result = EINVAL;
547 }
548 if (result == 0)
549 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2);
550 } else {
551 result = ENXIO;
552 }
553 return(result);
554}
555
556static int
557pci_get_powerstate_method(device_t dev, device_t child)
558{
559 struct pci_devinfo *dinfo = device_get_ivars(child);
560 pcicfgregs *cfg = &dinfo->cfg;
561 u_int16_t status;
562 int result;
563
564 if (cfg->pp_cap != 0) {
565 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2);
566 switch (status & PCIM_PSTAT_DMASK) {
567 case PCIM_PSTAT_D0:
568 result = PCI_POWERSTATE_D0;
569 break;
570 case PCIM_PSTAT_D1:
571 result = PCI_POWERSTATE_D1;
572 break;
573 case PCIM_PSTAT_D2:
574 result = PCI_POWERSTATE_D2;
575 break;
576 case PCIM_PSTAT_D3:
577 result = PCI_POWERSTATE_D3;
578 break;
579 default:
580 result = PCI_POWERSTATE_UNKNOWN;
581 break;
582 }
583 } else {
584 /* No support, device is always at D0 */
585 result = PCI_POWERSTATE_D0;
586 }
587 return(result);
588}
589
590/*
591 * Some convenience functions for PCI device drivers.
592 */
593
594static __inline void
595pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
596{
597 u_int16_t command;
598
599 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
600 command |= bit;
601 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
602}
603
604static __inline void
605pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
606{
607 u_int16_t command;
608
609 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
610 command &= ~bit;
611 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
612}
613
614static void
615pci_enable_busmaster_method(device_t dev, device_t child)
616{
617 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
618}
619
620static void
621pci_disable_busmaster_method(device_t dev, device_t child)
622{
623 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
624}
625
626static void
627pci_enable_io_method(device_t dev, device_t child, int space)
628{
629 switch(space) {
630 case SYS_RES_IOPORT:
631 pci_set_command_bit(dev, child, PCIM_CMD_PORTEN);
632 break;
633 case SYS_RES_MEMORY:
634 pci_set_command_bit(dev, child, PCIM_CMD_MEMEN);
635 break;
636 }
637}
638
639static void
640pci_disable_io_method(device_t dev, device_t child, int space)
641{
642 switch(space) {
643 case SYS_RES_IOPORT:
644 pci_clear_command_bit(dev, child, PCIM_CMD_PORTEN);
645 break;
646 case SYS_RES_MEMORY:
647 pci_clear_command_bit(dev, child, PCIM_CMD_MEMEN);
648 break;
649 }
650}
651
652/*
653 * This is the user interface to PCI configuration space.
654 */
655
656static int
657pci_open(dev_t dev, int oflags, int devtype, struct proc *p)
658{
659 if ((oflags & FWRITE) && securelevel > 0) {
660 return EPERM;
661 }
662 return 0;
663}
664
665static int
666pci_close(dev_t dev, int flag, int devtype, struct proc *p)
667{
668 return 0;
669}
670
671/*
672 * Match a single pci_conf structure against an array of pci_match_conf
673 * structures. The first argument, 'matches', is an array of num_matches
674 * pci_match_conf structures. match_buf is a pointer to the pci_conf
675 * structure that will be compared to every entry in the matches array.
676 * This function returns 1 on failure, 0 on success.
677 */
678static int
679pci_conf_match(struct pci_match_conf *matches, int num_matches,
680 struct pci_conf *match_buf)
681{
682 int i;
683
684 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
685 return(1);
686
687 for (i = 0; i < num_matches; i++) {
688 /*
689 * I'm not sure why someone would do this...but...
690 */
691 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
692 continue;
693
694 /*
695 * Look at each of the match flags. If it's set, do the
696 * comparison. If the comparison fails, we don't have a
697 * match, go on to the next item if there is one.
698 */
699 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
700 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
701 continue;
702
703 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
704 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
705 continue;
706
707 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
708 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
709 continue;
710
711 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
712 && (match_buf->pc_vendor != matches[i].pc_vendor))
713 continue;
714
715 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
716 && (match_buf->pc_device != matches[i].pc_device))
717 continue;
718
719 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
720 && (match_buf->pc_class != matches[i].pc_class))
721 continue;
722
723 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
724 && (match_buf->pd_unit != matches[i].pd_unit))
725 continue;
726
727 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
728 && (strncmp(matches[i].pd_name, match_buf->pd_name,
729 sizeof(match_buf->pd_name)) != 0))
730 continue;
731
732 return(0);
733 }
734
735 return(1);
736}
737
738/*
739 * Locate the parent of a PCI device by scanning the PCI devlist
740 * and return the entry for the parent.
741 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
742 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
743 */
744
745pcicfgregs *
746pci_devlist_get_parent(pcicfgregs *cfg)
747{
748 struct devlist *devlist_head;
749 struct pci_devinfo *dinfo;
750 pcicfgregs *bridge_cfg;
751 int i;
752
753 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
754
755 /* If the device is on PCI bus 0, look for the host */
756 if (cfg->bus == 0) {
757 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
758 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
759 bridge_cfg = &dinfo->cfg;
760 if (bridge_cfg->baseclass == PCIC_BRIDGE
761 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
762 && bridge_cfg->bus == cfg->bus) {
763 return bridge_cfg;
764 }
765 }
766 }
767
768 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
769 if (cfg->bus > 0) {
770 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
771 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
772 bridge_cfg = &dinfo->cfg;
773 if (bridge_cfg->baseclass == PCIC_BRIDGE
774 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
775 && bridge_cfg->secondarybus == cfg->bus) {
776 return bridge_cfg;
777 }
778 }
779 }
780
781 return NULL;
782}
783
784static int
785pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
786{
787 struct pci_io *io;
788 const char *name;
789 int error;
790
791 if (!(flag & FWRITE))
792 return EPERM;
793
794
795 switch(cmd) {
796 case PCIOCGETCONF:
797 {
798 struct pci_devinfo *dinfo;
799 struct pci_conf_io *cio;
800 struct devlist *devlist_head;
801 struct pci_match_conf *pattern_buf;
802 int num_patterns;
803 size_t iolen;
804 int ionum, i;
805
806 cio = (struct pci_conf_io *)data;
807
808 num_patterns = 0;
809 dinfo = NULL;
810
811 /*
812 * Hopefully the user won't pass in a null pointer, but it
813 * can't hurt to check.
814 */
815 if (cio == NULL) {
816 error = EINVAL;
817 break;
818 }
819
820 /*
821 * If the user specified an offset into the device list,
822 * but the list has changed since they last called this
823 * ioctl, tell them that the list has changed. They will
824 * have to get the list from the beginning.
825 */
826 if ((cio->offset != 0)
827 && (cio->generation != pci_generation)){
828 cio->num_matches = 0;
829 cio->status = PCI_GETCONF_LIST_CHANGED;
830 error = 0;
831 break;
832 }
833
834 /*
835 * Check to see whether the user has asked for an offset
836 * past the end of our list.
837 */
838 if (cio->offset >= pci_numdevs) {
839 cio->num_matches = 0;
840 cio->status = PCI_GETCONF_LAST_DEVICE;
841 error = 0;
842 break;
843 }
844
845 /* get the head of the device queue */
846 devlist_head = &pci_devq;
847
848 /*
849 * Determine how much room we have for pci_conf structures.
850 * Round the user's buffer size down to the nearest
851 * multiple of sizeof(struct pci_conf) in case the user
852 * didn't specify a multiple of that size.
853 */
854 iolen = min(cio->match_buf_len -
855 (cio->match_buf_len % sizeof(struct pci_conf)),
856 pci_numdevs * sizeof(struct pci_conf));
857
858 /*
859 * Since we know that iolen is a multiple of the size of
860 * the pciconf union, it's okay to do this.
861 */
862 ionum = iolen / sizeof(struct pci_conf);
863
864 /*
865 * If this test is true, the user wants the pci_conf
866 * structures returned to match the supplied entries.
867 */
868 if ((cio->num_patterns > 0)
869 && (cio->pat_buf_len > 0)) {
870 /*
871 * pat_buf_len needs to be:
872 * num_patterns * sizeof(struct pci_match_conf)
873 * While it is certainly possible the user just
874 * allocated a large buffer, but set the number of
875 * matches correctly, it is far more likely that
876 * their kernel doesn't match the userland utility
877 * they're using. It's also possible that the user
878 * forgot to initialize some variables. Yes, this
879 * may be overly picky, but I hazard to guess that
880 * it's far more likely to just catch folks that
881 * updated their kernel but not their userland.
882 */
883 if ((cio->num_patterns *
884 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
885 /* The user made a mistake, return an error*/
886 cio->status = PCI_GETCONF_ERROR;
887 printf("pci_ioctl: pat_buf_len %d != "
888 "num_patterns (%d) * sizeof(struct "
889 "pci_match_conf) (%d)\npci_ioctl: "
890 "pat_buf_len should be = %d\n",
891 cio->pat_buf_len, cio->num_patterns,
892 (int)sizeof(struct pci_match_conf),
893 (int)sizeof(struct pci_match_conf) *
894 cio->num_patterns);
895 printf("pci_ioctl: do your headers match your "
896 "kernel?\n");
897 cio->num_matches = 0;
898 error = EINVAL;
899 break;
900 }
901
902 /*
903 * Check the user's buffer to make sure it's readable.
904 */
905 if (!useracc((caddr_t)cio->patterns,
906 cio->pat_buf_len, VM_PROT_READ)) {
907 printf("pci_ioctl: pattern buffer %p, "
908 "length %u isn't user accessible for"
909 " READ\n", cio->patterns,
910 cio->pat_buf_len);
911 error = EACCES;
912 break;
913 }
914 /*
915 * Allocate a buffer to hold the patterns.
916 */
917 pattern_buf = malloc(cio->pat_buf_len, M_TEMP,
918 M_WAITOK);
919 error = copyin(cio->patterns, pattern_buf,
920 cio->pat_buf_len);
921 if (error != 0)
922 break;
923 num_patterns = cio->num_patterns;
924
925 } else if ((cio->num_patterns > 0)
926 || (cio->pat_buf_len > 0)) {
927 /*
928 * The user made a mistake, spit out an error.
929 */
930 cio->status = PCI_GETCONF_ERROR;
931 cio->num_matches = 0;
932 printf("pci_ioctl: invalid GETCONF arguments\n");
933 error = EINVAL;
934 break;
935 } else
936 pattern_buf = NULL;
937
938 /*
939 * Make sure we can write to the match buffer.
940 */
941 if (!useracc((caddr_t)cio->matches,
942 cio->match_buf_len, VM_PROT_WRITE)) {
943 printf("pci_ioctl: match buffer %p, length %u "
944 "isn't user accessible for WRITE\n",
945 cio->matches, cio->match_buf_len);
946 error = EACCES;
947 break;
948 }
949
950 /*
951 * Go through the list of devices and copy out the devices
952 * that match the user's criteria.
953 */
954 for (cio->num_matches = 0, error = 0, i = 0,
955 dinfo = STAILQ_FIRST(devlist_head);
956 (dinfo != NULL) && (cio->num_matches < ionum)
957 && (error == 0) && (i < pci_numdevs);
958 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
959
960 if (i < cio->offset)
961 continue;
962
963 /* Populate pd_name and pd_unit */
964 name = NULL;
965 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
966 name = device_get_name(dinfo->cfg.dev);
967 if (name) {
968 strncpy(dinfo->conf.pd_name, name,
969 sizeof(dinfo->conf.pd_name));
970 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
971 dinfo->conf.pd_unit =
972 device_get_unit(dinfo->cfg.dev);
973 }
974
975 if ((pattern_buf == NULL) ||
976 (pci_conf_match(pattern_buf, num_patterns,
977 &dinfo->conf) == 0)) {
978
979 /*
980 * If we've filled up the user's buffer,
981 * break out at this point. Since we've
982 * got a match here, we'll pick right back
983 * up at the matching entry. We can also
984 * tell the user that there are more matches
985 * left.
986 */
987 if (cio->num_matches >= ionum)
988 break;
989
990 error = copyout(&dinfo->conf,
991 &cio->matches[cio->num_matches],
992 sizeof(struct pci_conf));
993 cio->num_matches++;
994 }
995 }
996
997 /*
998 * Set the pointer into the list, so if the user is getting
999 * n records at a time, where n < pci_numdevs,
1000 */
1001 cio->offset = i;
1002
1003 /*
1004 * Set the generation, the user will need this if they make
1005 * another ioctl call with offset != 0.
1006 */
1007 cio->generation = pci_generation;
1008
1009 /*
1010 * If this is the last device, inform the user so he won't
1011 * bother asking for more devices. If dinfo isn't NULL, we
1012 * know that there are more matches in the list because of
1013 * the way the traversal is done.
1014 */
1015 if (dinfo == NULL)
1016 cio->status = PCI_GETCONF_LAST_DEVICE;
1017 else
1018 cio->status = PCI_GETCONF_MORE_DEVS;
1019
1020 if (pattern_buf != NULL)
1021 free(pattern_buf, M_TEMP);
1022
1023 break;
1024 }
1025 case PCIOCREAD:
1026 io = (struct pci_io *)data;
1027 switch(io->pi_width) {
1028 pcicfgregs probe;
1029 case 4:
1030 case 2:
1031 case 1:
1032 probe.hose = -1;
1033 probe.bus = io->pi_sel.pc_bus;
1034 probe.slot = io->pi_sel.pc_dev;
1035 probe.func = io->pi_sel.pc_func;
1036 io->pi_data = pci_cfgread(&probe,
1037 io->pi_reg, io->pi_width);
1038 error = 0;
1039 break;
1040 default:
1041 error = ENODEV;
1042 break;
1043 }
1044 break;
1045
1046 case PCIOCWRITE:
1047 io = (struct pci_io *)data;
1048 switch(io->pi_width) {
1049 pcicfgregs probe;
1050 case 4:
1051 case 2:
1052 case 1:
1053 probe.hose = -1;
1054 probe.bus = io->pi_sel.pc_bus;
1055 probe.slot = io->pi_sel.pc_dev;
1056 probe.func = io->pi_sel.pc_func;
1057 pci_cfgwrite(&probe,
1058 io->pi_reg, io->pi_data, io->pi_width);
1059 error = 0;
1060 break;
1061 default:
1062 error = ENODEV;
1063 break;
1064 }
1065 break;
1066
1067 default:
1068 error = ENOTTY;
1069 break;
1070 }
1071
1072 return (error);
1073}
1074
1075#define PCI_CDEV 78
1076
1077static struct cdevsw pcicdev = {
1078 /* open */ pci_open,
1079 /* close */ pci_close,
1080 /* read */ noread,
1081 /* write */ nowrite,
1082 /* ioctl */ pci_ioctl,
1083 /* poll */ nopoll,
1084 /* mmap */ nommap,
1085 /* strategy */ nostrategy,
1086 /* name */ "pci",
1087 /* maj */ PCI_CDEV,
1088 /* dump */ nodump,
1089 /* psize */ nopsize,
1090 /* flags */ 0,
1091 /* bmaj */ -1
1092};
1093
1094#include "pci_if.h"
1095
1096/*
1097 * A simple driver to wrap the old pci driver mechanism for back-compat.
1098 */
1099
1100static int
1101pci_compat_probe(device_t dev)
1102{
1103 struct pci_device *dvp;
1104 struct pci_devinfo *dinfo;
1105 pcicfgregs *cfg;
1106 const char *name;
1107 int error;
1108
1109 dinfo = device_get_ivars(dev);
1110 cfg = &dinfo->cfg;
1111 dvp = device_get_driver(dev)->priv;
1112
1113 /*
1114 * Do the wrapped probe.
1115 */
1116 error = ENXIO;
1117 if (dvp && dvp->pd_probe) {
1118 name = dvp->pd_probe(cfg, (cfg->device << 16) + cfg->vendor);
1119 if (name) {
1120 device_set_desc_copy(dev, name);
1121 /* Allow newbus drivers to match "better" */
1122 error = -200;
1123 }
1124 }
1125
1126 return error;
1127}
1128
1129static int
1130pci_compat_attach(device_t dev)
1131{
1132 struct pci_device *dvp;
1133 struct pci_devinfo *dinfo;
1134 pcicfgregs *cfg;
1135 int unit;
1136
1137 dinfo = device_get_ivars(dev);
1138 cfg = &dinfo->cfg;
1139 dvp = device_get_driver(dev)->priv;
1140
1141 unit = device_get_unit(dev);
1142 if (unit > *dvp->pd_count)
1143 *dvp->pd_count = unit;
1144 if (dvp->pd_attach)
1145 dvp->pd_attach(cfg, unit);
1146 device_printf(dev, "driver is using old-style compatibility shims\n");
1147 return 0;
1148}
1149
1150static device_method_t pci_compat_methods[] = {
1151 /* Device interface */
1152 DEVMETHOD(device_probe, pci_compat_probe),
1153 DEVMETHOD(device_attach, pci_compat_attach),
1154
1155 { 0, 0 }
1156};
1157
1158static devclass_t pci_devclass;
1159
1160/*
1161 * Create a new style driver around each old pci driver.
1162 */
1163int
1164compat_pci_handler(module_t mod, int type, void *data)
1165{
1166 struct pci_device *dvp = (struct pci_device *)data;
1167 driver_t *driver;
1168
1169 switch (type) {
1170 case MOD_LOAD:
1171 driver = malloc(sizeof(driver_t), M_DEVBUF, M_NOWAIT);
1172 if (!driver)
1173 return ENOMEM;
1174 bzero(driver, sizeof(driver_t));
1175 driver->name = dvp->pd_name;
1176 driver->methods = pci_compat_methods;
1177 driver->softc = sizeof(struct pci_devinfo *);
1178 driver->priv = dvp;
1179 devclass_add_driver(pci_devclass, driver);
1180 break;
1181 case MOD_UNLOAD:
1182 printf("%s: module unload not supported!\n", dvp->pd_name);
1183 return EOPNOTSUPP;
1184 default:
1185 break;
1186 }
1187 return 0;
1188}
1189
1190/*
1191 * New style pci driver. Parent device is either a pci-host-bridge or a
1192 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1193 */
1194
1195static void
1196pci_print_verbose(struct pci_devinfo *dinfo)
1197{
1198 if (bootverbose) {
1199 pcicfgregs *cfg = &dinfo->cfg;
1200
1201 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
1202 cfg->vendor, cfg->device, cfg->revid);
1203 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
1204 cfg->baseclass, cfg->subclass, cfg->progif,
1205 cfg->hdrtype, cfg->mfdev);
1206 printf("\tsubordinatebus=%x \tsecondarybus=%x\n",
1207 cfg->subordinatebus, cfg->secondarybus);
1208#ifdef PCI_DEBUG
1209 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
1210 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
1211 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
1212 cfg->lattimer, cfg->lattimer * 30,
1213 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1214#endif /* PCI_DEBUG */
1215 if (cfg->intpin > 0)
1216 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
1217 }
1218}
1219
1220static int
1221pci_porten(pcicfgregs *cfg)
1222{
1223 return ((cfg->cmdreg & PCIM_CMD_PORTEN) != 0);
1224}
1225
1226static int
1227pci_memen(pcicfgregs *cfg)
1228{
1229 return ((cfg->cmdreg & PCIM_CMD_MEMEN) != 0);
1230}
1231
1232/*
1233 * Add a resource based on a pci map register. Return 1 if the map
1234 * register is a 32bit map register or 2 if it is a 64bit register.
1235 */
1236static int
1237pci_add_map(device_t dev, pcicfgregs* cfg, int reg)
1238{
1239 struct pci_devinfo *dinfo = device_get_ivars(dev);
1240 struct resource_list *rl = &dinfo->resources;
1241 u_int32_t map;
1242 u_int64_t base;
1243 u_int8_t ln2size;
1244 u_int8_t ln2range;
1245 u_int32_t testval;
1246
1247 int type;
1248
1249 map = pci_cfgread(cfg, reg, 4);
1250
1251 if (map == 0 || map == 0xffffffff)
1252 return 1; /* skip invalid entry */
1253
1254 pci_cfgwrite(cfg, reg, 0xffffffff, 4);
1255 testval = pci_cfgread(cfg, reg, 4);
1256 pci_cfgwrite(cfg, reg, map, 4);
1257
1258 base = pci_mapbase(map);
1259 if (pci_maptype(map) & PCI_MAPMEM)
1260 type = SYS_RES_MEMORY;
1261 else
1262 type = SYS_RES_IOPORT;
1263 ln2size = pci_mapsize(testval);
1264 ln2range = pci_maprange(testval);
1265 if (ln2range == 64) {
1266 /* Read the other half of a 64bit map register */
1267 base |= (u_int64_t) pci_cfgread(cfg, reg + 4, 4) << 32;
1268 }
1269
1270#ifdef __alpha__
1271 /*
1272 * XXX: encode hose number in the base addr,
1273 * This will go away once the bus_space functions
1274 * can deal with multiple hoses
1275 */
1276
1277 if (cfg->hose) {
1278 u_int32_t mask, shift, maxh;
1279
1280 switch (hwrpb->rpb_type) {
1281 case ST_DEC_4100:
1282 case -ST_DEC_4100:
1283 mask = 0xc0000000;
1284 shift = 30;
1285 maxh = 4; /* not a hose. MCPCIA instance # */
1286 break;
1287 case ST_DEC_21000:
1288 mask = 0xf8000000;
1289 shift = 27;
1290 maxh = 32;
1291 break;
1292 case ST_DEC_6600:
1293 mask = 0x80000000;
1294 shift = 31;
1295 maxh = 2;
1296 break;
1297 default:
1298 mask = 0;
1299 shift = 0;
1300 maxh = 0;
1301 break;
1302 }
1303 if (base & mask) {
1304 printf("base addr = 0x%llx\n", (long long) base);
1305 printf("mask addr = 0x%lx\n", (long) mask);
1306 printf("hacked addr = 0x%llx\n", (long long)
1307 (base | ((u_int64_t)cfg->hose << shift)));
1308 panic("hose encoding hack would clobber base addr");
1309 /* NOTREACHED */
1310 }
1311 if (cfg->hose >= maxh) {
1312 panic("Hose %d - can only encode %d hose(s)",
1313 cfg->hose, maxh);
1314 /* NOTREACHED */
1315 }
1316 base |= ((u_int64_t)cfg->hose << shift);
1317 }
1318#endif
1319
1320 /*
1321 * This code theoretically does the right thing, but has
1322 * undesirable side effects in some cases where
1323 * peripherals respond oddly to having these bits
1324 * enabled. Leave them alone by default.
1325 */
1326#ifdef PCI_ENABLE_IO_MODES
1327 if (type == SYS_RES_IOPORT && !pci_porten(cfg)) {
1328 cfg->cmdreg |= PCIM_CMD_PORTEN;
1329 pci_cfgwrite(cfg, PCIR_COMMAND, cfg->cmdreg, 2);
1330 }
1331 if (type == SYS_RES_MEMORY && !pci_memen(cfg)) {
1332 cfg->cmdreg |= PCIM_CMD_MEMEN;
1333 pci_cfgwrite(cfg, PCIR_COMMAND, cfg->cmdreg, 2);
1334 }
1335#else
1336 if (type == SYS_RES_IOPORT && !pci_porten(cfg))
1337 return 1;
1338 if (type == SYS_RES_MEMORY && !pci_memen(cfg))
1339 return 1;
1340#endif
1341
1342 resource_list_add(rl, type, reg,
1343 base, base + (1 << ln2size) - 1,
1344 (1 << ln2size));
1345
1346 if (bootverbose) {
1347 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
1348 reg, pci_maptype(base), ln2range,
1349 (unsigned int) base, ln2size);
1350 }
1351
1352 return (ln2range == 64) ? 2 : 1;
1353}
1354
1355static void
1356pci_add_resources(device_t dev, pcicfgregs* cfg)
1357{
1358 struct pci_devinfo *dinfo = device_get_ivars(dev);
1359 struct resource_list *rl = &dinfo->resources;
1360 struct pci_quirk *q;
1361 int i;
1362
1363 for (i = 0; i < cfg->nummaps;) {
1364 i += pci_add_map(dev, cfg, PCIR_MAPS + i*4);
1365 }
1366
1367 for (q = &pci_quirks[0]; q->devid; q++) {
1368 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1369 && q->type == PCI_QUIRK_MAP_REG)
1370 pci_add_map(dev, cfg, q->arg1);
1371 }
1372
1373 if (cfg->intpin > 0 && cfg->intline != 255)
1374 resource_list_add(rl, SYS_RES_IRQ, 0,
1375 cfg->intline, cfg->intline, 1);
1376}
1377
1378static void
1379pci_add_children(device_t dev, int busno)
1380{
1381 pcicfgregs probe;
1382
1383#ifdef SIMOS
1384#undef PCI_SLOTMAX
1385#define PCI_SLOTMAX 0
1386#endif
1387
1388 bzero(&probe, sizeof probe);
1389#ifdef __alpha__
1390 probe.hose = pcib_get_hose(dev);
1391#endif
1392#ifdef __i386__
1393 probe.hose = 0;
1394#endif
1395 probe.bus = busno;
1396
1397 for (probe.slot = 0; probe.slot <= PCI_SLOTMAX; probe.slot++) {
1398 int pcifunchigh = 0;
1399 for (probe.func = 0; probe.func <= pcifunchigh; probe.func++) {
1400 struct pci_devinfo *dinfo = pci_readcfg(&probe);
1401 if (dinfo != NULL) {
1402 if (dinfo->cfg.mfdev)
1403 pcifunchigh = 7;
1404
1405 pci_print_verbose(dinfo);
1406 dinfo->cfg.dev = device_add_child(dev, NULL, -1);
1407 device_set_ivars(dinfo->cfg.dev, dinfo);
1408 pci_add_resources(dinfo->cfg.dev, &dinfo->cfg);
1409 }
1410 }
1411 }
1412}
1413
1414static int
1415pci_new_probe(device_t dev)
1416{
1417 static int once;
1418
1419 device_set_desc(dev, "PCI bus");
1420 pci_add_children(dev, device_get_unit(dev));
1421 if (!once) {
1422 make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci");
1423 once++;
1424 }
1425
1426 return 0;
1427}
1428
1429static int
1430pci_print_resources(struct resource_list *rl, const char *name, int type,
1431 const char *format)
1432{
1433 struct resource_list_entry *rle;
1434 int printed, retval;
1435
1436 printed = 0;
1437 retval = 0;
1438 /* Yes, this is kinda cheating */
1439 SLIST_FOREACH(rle, rl, link) {
1440 if (rle->type == type) {
1441 if (printed == 0)
1442 retval += printf(" %s ", name);
1443 else if (printed > 0)
1444 retval += printf(",");
1445 printed++;
1446 retval += printf(format, rle->start);
1447 if (rle->count > 1) {
1448 retval += printf("-");
1449 retval += printf(format, rle->start +
1450 rle->count - 1);
1451 }
1452 }
1453 }
1454 return retval;
1455}
1456
1457static int
1458pci_print_child(device_t dev, device_t child)
1459{
1460 struct pci_devinfo *dinfo;
1461 struct resource_list *rl;
1462 pcicfgregs *cfg;
1463 int retval = 0;
1464
1465 dinfo = device_get_ivars(child);
1466 cfg = &dinfo->cfg;
1467 rl = &dinfo->resources;
1468
1469 retval += bus_print_child_header(dev, child);
1470
1471 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1472 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1473 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1474 if (device_get_flags(dev))
1475 retval += printf(" flags %#x", device_get_flags(dev));
1476
1477 retval += printf(" at device %d.%d", pci_get_slot(child),
1478 pci_get_function(child));
1479
1480 retval += bus_print_child_footer(dev, child);
1481
1482 return (retval);
1483}
1484
1485static void
1486pci_probe_nomatch(device_t dev, device_t child)
1487{
1488 struct pci_devinfo *dinfo;
1489 pcicfgregs *cfg;
1490 const char *desc;
1491 int unknown;
1492
1493 unknown = 0;
1494 dinfo = device_get_ivars(child);
1495 cfg = &dinfo->cfg;
1496 desc = pci_ata_match(child);
1497 if (!desc) desc = pci_usb_match(child);
1498 if (!desc) desc = pci_vga_match(child);
1499 if (!desc) {
1500 desc = "unknown card";
1501 unknown++;
1502 }
1503 device_printf(dev, "<%s>", desc);
1504 if (bootverbose || unknown) {
1505 printf(" (vendor=0x%04x, dev=0x%04x)",
1506 cfg->vendor,
1507 cfg->device);
1508 }
1509 printf(" at %d.%d",
1510 pci_get_slot(child),
1511 pci_get_function(child));
1512 if (cfg->intpin > 0 && cfg->intline != 255) {
1513 printf(" irq %d", cfg->intline);
1514 }
1515 printf("\n");
1516
1517 return;
1518}
1519
1520static int
1521pci_read_ivar(device_t dev, device_t child, int which, u_long *result)
1522{
1523 struct pci_devinfo *dinfo;
1524 pcicfgregs *cfg;
1525
1526 dinfo = device_get_ivars(child);
1527 cfg = &dinfo->cfg;
1528
1529 switch (which) {
1530 case PCI_IVAR_SUBVENDOR:
1531 *result = cfg->subvendor;
1532 break;
1533 case PCI_IVAR_SUBDEVICE:
1534 *result = cfg->subdevice;
1535 break;
1536 case PCI_IVAR_VENDOR:
1537 *result = cfg->vendor;
1538 break;
1539 case PCI_IVAR_DEVICE:
1540 *result = cfg->device;
1541 break;
1542 case PCI_IVAR_DEVID:
1543 *result = (cfg->device << 16) | cfg->vendor;
1544 break;
1545 case PCI_IVAR_CLASS:
1546 *result = cfg->baseclass;
1547 break;
1548 case PCI_IVAR_SUBCLASS:
1549 *result = cfg->subclass;
1550 break;
1551 case PCI_IVAR_PROGIF:
1552 *result = cfg->progif;
1553 break;
1554 case PCI_IVAR_REVID:
1555 *result = cfg->revid;
1556 break;
1557 case PCI_IVAR_INTPIN:
1558 *result = cfg->intpin;
1559 break;
1560 case PCI_IVAR_IRQ:
1561 *result = cfg->intline;
1562 break;
1563 case PCI_IVAR_BUS:
1564 *result = cfg->bus;
1565 break;
1566 case PCI_IVAR_SLOT:
1567 *result = cfg->slot;
1568 break;
1569 case PCI_IVAR_FUNCTION:
1570 *result = cfg->func;
1571 break;
1572 case PCI_IVAR_SECONDARYBUS:
1573 *result = cfg->secondarybus;
1574 break;
1575 case PCI_IVAR_SUBORDINATEBUS:
1576 *result = cfg->subordinatebus;
1577 break;
1578 case PCI_IVAR_HOSE:
1579 /*
1580 * Pass up to parent bridge.
1581 */
1582 *result = pcib_get_hose(dev);
1583 break;
1584 default:
1585 return ENOENT;
1586 }
1587 return 0;
1588}
1589
1590static int
1591pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1592{
1593 struct pci_devinfo *dinfo;
1594 pcicfgregs *cfg;
1595
1596 dinfo = device_get_ivars(child);
1597 cfg = &dinfo->cfg;
1598
1599 switch (which) {
1600 case PCI_IVAR_SUBVENDOR:
1601 case PCI_IVAR_SUBDEVICE:
1602 case PCI_IVAR_VENDOR:
1603 case PCI_IVAR_DEVICE:
1604 case PCI_IVAR_DEVID:
1605 case PCI_IVAR_CLASS:
1606 case PCI_IVAR_SUBCLASS:
1607 case PCI_IVAR_PROGIF:
1608 case PCI_IVAR_REVID:
1609 case PCI_IVAR_INTPIN:
1610 case PCI_IVAR_IRQ:
1611 case PCI_IVAR_BUS:
1612 case PCI_IVAR_SLOT:
1613 case PCI_IVAR_FUNCTION:
1614 return EINVAL; /* disallow for now */
1615
1616 case PCI_IVAR_SECONDARYBUS:
1617 cfg->secondarybus = value;
1618 break;
1619 case PCI_IVAR_SUBORDINATEBUS:
1620 cfg->subordinatebus = value;
1621 break;
1622 default:
1623 return ENOENT;
1624 }
1625 return 0;
1626}
1627
1628static struct resource *
1629pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1630 u_long start, u_long end, u_long count, u_int flags)
1631{
1632 struct pci_devinfo *dinfo = device_get_ivars(child);
1633 struct resource_list *rl = &dinfo->resources;
1634
1635#ifdef __i386__ /* Only supported on x86 in stable */
1636 pcicfgregs *cfg = &dinfo->cfg;
1637 /*
1638 * Perform lazy resource allocation
1639 *
1640 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY
1641 */
1642 if (device_get_parent(child) == dev) {
1643 /*
1644 * If device doesn't have an interrupt routed, and is
1645 * deserving of an interrupt, try to assign it one.
1646 */
1647 if ((type == SYS_RES_IRQ) &&
1648 (cfg->intline == 255 || cfg->intline == 0) &&
1649 (cfg->intpin != 0) && (start == 0) && (end == ~0UL)) {
1650 cfg->intline = pci_cfgintr(pci_get_bus(child),
1651 pci_get_slot(child), cfg->intpin);
1652 if (cfg->intline != 255) {
1653 pci_write_config(child, PCIR_INTLINE,
1654 cfg->intline, 1);
1655 resource_list_add(rl, SYS_RES_IRQ, 0,
1656 cfg->intline, cfg->intline, 1);
1657 }
1658 }
1659 }
1660#endif
1661 return resource_list_alloc(rl, dev, child, type, rid,
1662 start, end, count, flags);
1663}
1664
1665static int
1666pci_release_resource(device_t dev, device_t child, int type, int rid,
1667 struct resource *r)
1668{
1669 struct pci_devinfo *dinfo = device_get_ivars(child);
1670 struct resource_list *rl = &dinfo->resources;
1671
1672 return resource_list_release(rl, dev, child, type, rid, r);
1673}
1674
1675static int
1676pci_set_resource(device_t dev, device_t child, int type, int rid,
1677 u_long start, u_long count)
1678{
1679 struct pci_devinfo *dinfo = device_get_ivars(child);
1680 struct resource_list *rl = &dinfo->resources;
1681
1682 resource_list_add(rl, type, rid, start, start + count - 1, count);
1683 return 0;
1684}
1685
1686static int
1687pci_get_resource(device_t dev, device_t child, int type, int rid,
1688 u_long *startp, u_long *countp)
1689{
1690 struct pci_devinfo *dinfo = device_get_ivars(child);
1691 struct resource_list *rl = &dinfo->resources;
1692 struct resource_list_entry *rle;
1693
1694 rle = resource_list_find(rl, type, rid);
1695 if (!rle)
1696 return ENOENT;
1697
1698 if (startp)
1699 *startp = rle->start;
1700 if (countp)
1701 *countp = rle->count;
1702
1703 return 0;
1704}
1705
1706static void
1707pci_delete_resource(device_t dev, device_t child, int type, int rid)
1708{
1709 printf("pci_delete_resource: PCI resources can not be deleted\n");
1710}
1711
1712static u_int32_t
1713pci_read_config_method(device_t dev, device_t child, int reg, int width)
1714{
1715 struct pci_devinfo *dinfo = device_get_ivars(child);
1716 pcicfgregs *cfg = &dinfo->cfg;
1717 return pci_cfgread(cfg, reg, width);
1718}
1719
1720static void
1721pci_write_config_method(device_t dev, device_t child, int reg,
1722 u_int32_t val, int width)
1723{
1724 struct pci_devinfo *dinfo = device_get_ivars(child);
1725 pcicfgregs *cfg = &dinfo->cfg;
1726 pci_cfgwrite(cfg, reg, val, width);
1727}
1728
1729static int
1730pci_modevent(module_t mod, int what, void *arg)
1731{
1732 switch (what) {
1733 case MOD_LOAD:
1734 STAILQ_INIT(&pci_devq);
1735 break;
1736
1737 case MOD_UNLOAD:
1738 break;
1739 }
1740
1741 return 0;
1742}
1743
1744static device_method_t pci_methods[] = {
1745 /* Device interface */
1746 DEVMETHOD(device_probe, pci_new_probe),
1747 DEVMETHOD(device_attach, bus_generic_attach),
1748 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1749 DEVMETHOD(device_suspend, bus_generic_suspend),
1750 DEVMETHOD(device_resume, bus_generic_resume),
1751
1752 /* Bus interface */
1753 DEVMETHOD(bus_print_child, pci_print_child),
1754 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
1755 DEVMETHOD(bus_read_ivar, pci_read_ivar),
1756 DEVMETHOD(bus_write_ivar, pci_write_ivar),
1757 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1758 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
1759 DEVMETHOD(bus_release_resource, pci_release_resource),
1760 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1761 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1762 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1763 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1764 DEVMETHOD(bus_set_resource, pci_set_resource),
1765 DEVMETHOD(bus_get_resource, pci_get_resource),
1766 DEVMETHOD(bus_delete_resource, pci_delete_resource),
1767
1768 /* PCI interface */
1769 DEVMETHOD(pci_read_config, pci_read_config_method),
1770 DEVMETHOD(pci_write_config, pci_write_config_method),
1771 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
1772 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
1773 DEVMETHOD(pci_enable_io, pci_enable_io_method),
1774 DEVMETHOD(pci_disable_io, pci_disable_io_method),
1775 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
1776 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
1777
1778 { 0, 0 }
1779};
1780
1781static driver_t pci_driver = {
1782 "pci",
1783 pci_methods,
1784 1, /* no softc */
1785};
1786
1787DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);