panic() shouldn't have a \n.
[dragonfly.git] / sys / bus / pci / pci.c
CommitLineData
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1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
e9d8f4df 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.46 2007/11/24 13:21:32 sephe Exp $
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28 *
29 */
30
31#include "opt_bus.h"
32#include "opt_pci.h"
33
dc5a7bd2 34#include "opt_compat_oldpci.h"
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35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/malloc.h>
39#include <sys/module.h>
40#include <sys/fcntl.h>
41#include <sys/conf.h>
42#include <sys/kernel.h>
43#include <sys/queue.h>
44#include <sys/types.h>
45#include <sys/buf.h>
46
47#include <vm/vm.h>
48#include <vm/pmap.h>
49#include <vm/vm_extern.h>
50
51#include <sys/bus.h>
984263bc 52#include <sys/rman.h>
97359a5b 53#include <machine/smp.h>
984263bc 54#ifdef __i386__
bbca97bc 55#include <bus/pci/i386/pci_cfgreg.h>
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56#endif
57
dc5a7bd2 58#include <sys/pciio.h>
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59#include "pcireg.h"
60#include "pcivar.h"
22457186 61#include "pci_private.h"
984263bc 62
4a5a2d63
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63#include "pcib_if.h"
64
e126caf1 65devclass_t pci_devclass;
2581072f 66const char *pcib_owner;
dc5a7bd2 67
e9d8f4df 68static void pci_read_capabilities(device_t dev, pcicfgregs *cfg);
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69
70struct pci_quirk {
71 u_int32_t devid; /* Vendor/device of the card */
72 int type;
3e4db402 73#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
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74 int arg1;
75 int arg2;
76};
77
78struct pci_quirk pci_quirks[] = {
79 /*
80 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
81 */
82 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
83 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
f1f0bfb2
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84 /* As does the Serverworks OSB4 (the SMBus mapping register) */
85 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
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86
87 { 0 }
88};
89
90/* map register information */
91#define PCI_MAPMEM 0x01 /* memory map */
92#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
93#define PCI_MAPPORT 0x04 /* port map */
94
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95static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
96u_int32_t pci_numdevs = 0;
97static u_int32_t pci_generation = 0;
98
99device_t
c0f16abb 100pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func)
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101{
102 struct pci_devinfo *dinfo;
103
104 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
105 if ((dinfo->cfg.bus == bus) &&
106 (dinfo->cfg.slot == slot) &&
107 (dinfo->cfg.func == func)) {
108 return (dinfo->cfg.dev);
109 }
110 }
111
112 return (NULL);
113}
114
115device_t
c0f16abb 116pci_find_device(u_int16_t vendor, u_int16_t device)
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117{
118 struct pci_devinfo *dinfo;
119
120 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
121 if ((dinfo->cfg.vendor == vendor) &&
122 (dinfo->cfg.device == device)) {
123 return (dinfo->cfg.dev);
124 }
125 }
126
127 return (NULL);
128}
129
130/* return base address of memory or port map */
131
132static u_int32_t
133pci_mapbase(unsigned mapreg)
134{
135 int mask = 0x03;
136 if ((mapreg & 0x01) == 0)
137 mask = 0x0f;
138 return (mapreg & ~mask);
139}
140
141/* return map type of memory or port map */
142
143static int
144pci_maptype(unsigned mapreg)
145{
146 static u_int8_t maptype[0x10] = {
147 PCI_MAPMEM, PCI_MAPPORT,
148 PCI_MAPMEM, 0,
149 PCI_MAPMEM, PCI_MAPPORT,
150 0, 0,
151 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
152 PCI_MAPMEM|PCI_MAPMEMP, 0,
153 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
154 0, 0,
155 };
156
157 return maptype[mapreg & 0x0f];
158}
159
160/* return log2 of map size decoded for memory or port map */
161
162static int
163pci_mapsize(unsigned testval)
164{
165 int ln2size;
166
167 testval = pci_mapbase(testval);
168 ln2size = 0;
169 if (testval != 0) {
170 while ((testval & 1) == 0)
171 {
172 ln2size++;
173 testval >>= 1;
174 }
175 }
176 return (ln2size);
177}
178
179/* return log2 of address range supported by map register */
180
181static int
182pci_maprange(unsigned mapreg)
183{
184 int ln2range = 0;
185 switch (mapreg & 0x07) {
186 case 0x00:
187 case 0x01:
188 case 0x05:
189 ln2range = 32;
190 break;
191 case 0x02:
192 ln2range = 20;
193 break;
194 case 0x04:
195 ln2range = 64;
196 break;
197 }
198 return (ln2range);
199}
200
201/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
202
203static void
204pci_fixancient(pcicfgregs *cfg)
205{
206 if (cfg->hdrtype != 0)
207 return;
208
209 /* PCI to PCI bridges use header type 1 */
210 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
211 cfg->hdrtype = 1;
212}
213
214/* read config data specific to header type 1 device (PCI to PCI bridge) */
215
216static void *
4a5a2d63 217pci_readppb(device_t pcib, int b, int s, int f)
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218{
219 pcih1cfgregs *p;
220
efda3bd0 221 p = kmalloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
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222 if (p == NULL)
223 return (NULL);
224
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225 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
226 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
984263bc 227
4a5a2d63 228 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
984263bc 229
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230 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
231 PCIR_IOBASEH_1, 2),
232 PCIB_READ_CONFIG(pcib, b, s, f,
233 PCIR_IOBASEL_1, 1));
234 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
235 PCIR_IOLIMITH_1, 2),
236 PCIB_READ_CONFIG(pcib, b, s, f,
237 PCIR_IOLIMITL_1, 1));
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238
239 p->membase = PCI_PPBMEMBASE (0,
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240 PCIB_READ_CONFIG(pcib, b, s, f,
241 PCIR_MEMBASE_1, 2));
984263bc 242 p->memlimit = PCI_PPBMEMLIMIT (0,
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243 PCIB_READ_CONFIG(pcib, b, s, f,
244 PCIR_MEMLIMIT_1, 2));
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245
246 p->pmembase = PCI_PPBMEMBASE (
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247 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
248 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
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249
250 p->pmemlimit = PCI_PPBMEMLIMIT (
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251 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
252 PCIR_PMLIMITH_1, 4),
253 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
254
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255 return (p);
256}
257
258/* read config data specific to header type 2 device (PCI to CardBus bridge) */
259
260static void *
4a5a2d63 261pci_readpcb(device_t pcib, int b, int s, int f)
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262{
263 pcih2cfgregs *p;
264
efda3bd0 265 p = kmalloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
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266 if (p == NULL)
267 return (NULL);
268
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269 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
270 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
984263bc 271
4a5a2d63 272 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
984263bc 273
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274 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
275 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
276 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
277 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
984263bc 278
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279 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
280 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
281 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
282 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
984263bc 283
4a5a2d63 284 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
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285 return p;
286}
287
288/* extract header type specific config data */
289
290static void
4a5a2d63 291pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
984263bc 292{
4a5a2d63 293#define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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294 switch (cfg->hdrtype) {
295 case 0:
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296 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
297 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
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298 cfg->nummaps = PCI_MAXMAPS_0;
299 break;
300 case 1:
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301 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
302 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
303 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
304 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
984263bc 305 cfg->nummaps = PCI_MAXMAPS_1;
4a5a2d63 306 cfg->hdrspec = pci_readppb(pcib, b, s, f);
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307 break;
308 case 2:
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309 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
310 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
311 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
312 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
984263bc 313 cfg->nummaps = PCI_MAXMAPS_2;
4a5a2d63 314 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
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315 break;
316 }
4a5a2d63 317#undef REG
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318}
319
320/* read configuration header into pcicfgrect structure */
321
22457186 322struct pci_devinfo *
c01b8d84 323pci_read_device(device_t pcib, int b, int s, int f, size_t size)
984263bc 324{
4a5a2d63 325#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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326
327 pcicfgregs *cfg = NULL;
328 struct pci_devinfo *devlist_entry;
329 struct devlist *devlist_head;
330
331 devlist_head = &pci_devq;
332
333 devlist_entry = NULL;
334
4a5a2d63 335 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
984263bc 336
efda3bd0 337 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
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338 if (devlist_entry == NULL)
339 return (NULL);
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340
341 cfg = &devlist_entry->cfg;
342
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343 cfg->bus = b;
344 cfg->slot = s;
345 cfg->func = f;
346 cfg->vendor = REG(PCIR_VENDOR, 2);
347 cfg->device = REG(PCIR_DEVICE, 2);
348 cfg->cmdreg = REG(PCIR_COMMAND, 2);
349 cfg->statreg = REG(PCIR_STATUS, 2);
350 cfg->baseclass = REG(PCIR_CLASS, 1);
351 cfg->subclass = REG(PCIR_SUBCLASS, 1);
352 cfg->progif = REG(PCIR_PROGIF, 1);
353 cfg->revid = REG(PCIR_REVID, 1);
e126caf1 354 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
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355 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
356 cfg->lattimer = REG(PCIR_LATTIMER, 1);
357 cfg->intpin = REG(PCIR_INTPIN, 1);
358 cfg->intline = REG(PCIR_INTLINE, 1);
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359
360#ifdef APIC_IO
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361 /*
362 * If using the APIC the intpin is probably wrong, since it
363 * is often setup by the BIOS with the PIC in mind.
364 */
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365 if (cfg->intpin != 0) {
366 int airq;
367
368 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
369 if (airq >= 0) {
370 /* PCI specific entry found in MP table */
371 if (airq != cfg->intline) {
372 undirect_pci_irq(cfg->intline);
373 cfg->intline = airq;
374 }
375 } else {
376 /*
377 * PCI interrupts might be redirected to the
378 * ISA bus according to some MP tables. Use the
379 * same methods as used by the ISA devices
380 * devices to find the proper IOAPIC int pin.
381 */
382 airq = isa_apic_irq(cfg->intline);
383 if ((airq >= 0) && (airq != cfg->intline)) {
384 /* XXX: undirect_pci_irq() ? */
385 undirect_isa_irq(cfg->intline);
386 cfg->intline = airq;
387 }
388 }
389 }
390#endif /* APIC_IO */
391
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392 cfg->mingnt = REG(PCIR_MINGNT, 1);
393 cfg->maxlat = REG(PCIR_MAXLAT, 1);
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394
395 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
396 cfg->hdrtype &= ~PCIM_MFDEV;
397
398 pci_fixancient(cfg);
4a5a2d63 399 pci_hdrtypedata(pcib, b, s, f, cfg);
e9d8f4df 400 pci_read_capabilities(pcib, cfg);
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401
402 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
403
404 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
405 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
406 devlist_entry->conf.pc_sel.pc_func = cfg->func;
407 devlist_entry->conf.pc_hdr = cfg->hdrtype;
408
409 devlist_entry->conf.pc_subvendor = cfg->subvendor;
410 devlist_entry->conf.pc_subdevice = cfg->subdevice;
411 devlist_entry->conf.pc_vendor = cfg->vendor;
412 devlist_entry->conf.pc_device = cfg->device;
413
414 devlist_entry->conf.pc_class = cfg->baseclass;
415 devlist_entry->conf.pc_subclass = cfg->subclass;
416 devlist_entry->conf.pc_progif = cfg->progif;
417 devlist_entry->conf.pc_revid = cfg->revid;
418
419 pci_numdevs++;
420 pci_generation++;
421 }
422 return (devlist_entry);
423#undef REG
424}
425
1361c4cd
SZ
426static int
427pci_fixup_nextptr(int *nextptr0)
428{
429 int nextptr = *nextptr0;
430
431 /* "Next pointer" is only one byte */
432 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
433
434 if (nextptr & 0x3) {
435 /*
436 * PCI local bus spec 3.0:
437 *
438 * "... The bottom two bits of all pointers are reserved
439 * and must be implemented as 00b although software must
440 * mask them to allow for future uses of these bits ..."
441 */
442 if (bootverbose) {
443 kprintf("Illegal PCI extended capability "
444 "offset, fixup 0x%02x -> 0x%02x\n",
445 nextptr, nextptr & ~0x3);
446 }
447 nextptr &= ~0x3;
448 }
449 *nextptr0 = nextptr;
450
451 if (nextptr < 0x40) {
452 if (nextptr != 0) {
453 kprintf("Illegal PCI extended capability "
454 "offset 0x%02x", nextptr);
455 }
456 return 0;
457 }
458 return 1;
459}
460
984263bc 461static void
e9d8f4df 462pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
984263bc 463{
4a5a2d63 464#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
1361c4cd 465 int nextptr, ptrptr;
984263bc 466
0c78fe3f
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467 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
468 /* No capabilities */
469 return;
470 }
471
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472 switch (cfg->hdrtype) {
473 case 0:
81c29ce4
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474 case 1:
475 ptrptr = PCIR_CAP_PTR;
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476 break;
477 case 2:
81c29ce4 478 ptrptr = PCIR_CAP_PTR_2;
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479 break;
480 default:
0c78fe3f 481 return; /* No capabilities support */
984263bc 482 }
0c78fe3f 483 nextptr = REG(ptrptr, 1);
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484
485 /*
486 * Read capability entries.
487 */
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488 while (pci_fixup_nextptr(&nextptr)) {
489 int ptr = nextptr;
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490
491 /* Process this entry */
492 switch (REG(ptr, 1)) {
81c29ce4 493 case PCIY_PMG: /* PCI power management */
1f7d9fe0
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494 if (cfg->pmgt.pp_cap == 0) {
495 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
496
497 pmgt->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
498 pmgt->pp_status = ptr + PCIR_POWER_STATUS;
499 pmgt->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
1361c4cd
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500 /*
501 * XXX
502 * Following way may be used to to test whether
503 * 'data' register exists:
504 * if 'data_select' register of
505 * PCIR_POWER_STATUS(bits[12,9]) is read-only
506 * then 'data' register is _not_ implemented.
507 */
508 pmgt->pp_data = 0;
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509 }
510 break;
511 default:
512 break;
513 }
1361c4cd
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514
515 /* Find the next entry */
516 nextptr = REG(ptr + 1, 1);
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517 }
518#undef REG
519}
520
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521/* free pcicfgregs structure and all depending data structures */
522
22457186 523int
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524pci_freecfg(struct pci_devinfo *dinfo)
525{
526 struct devlist *devlist_head;
527
528 devlist_head = &pci_devq;
529
530 if (dinfo->cfg.hdrspec != NULL)
efda3bd0 531 kfree(dinfo->cfg.hdrspec, M_DEVBUF);
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532 /* XXX this hasn't been tested */
533 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
efda3bd0 534 kfree(dinfo, M_DEVBUF);
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535
536 /* increment the generation count */
537 pci_generation++;
538
539 /* we're losing one device */
540 pci_numdevs--;
541 return (0);
542}
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543
544
545/*
546 * PCI power manangement
547 */
e126caf1 548int
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549pci_set_powerstate_method(device_t dev, device_t child, int state)
550{
551 struct pci_devinfo *dinfo = device_get_ivars(child);
552 pcicfgregs *cfg = &dinfo->cfg;
1f7d9fe0 553 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
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554 u_int16_t status;
555 int result;
556
1f7d9fe0
SZ
557 if (pmgt->pp_cap != 0) {
558 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2) & ~PCIM_PSTAT_DMASK;
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559 result = 0;
560 switch (state) {
561 case PCI_POWERSTATE_D0:
562 status |= PCIM_PSTAT_D0;
563 break;
564 case PCI_POWERSTATE_D1:
1f7d9fe0 565 if (pmgt->pp_cap & PCIM_PCAP_D1SUPP) {
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566 status |= PCIM_PSTAT_D1;
567 } else {
568 result = EOPNOTSUPP;
569 }
570 break;
571 case PCI_POWERSTATE_D2:
1f7d9fe0 572 if (pmgt->pp_cap & PCIM_PCAP_D2SUPP) {
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573 status |= PCIM_PSTAT_D2;
574 } else {
575 result = EOPNOTSUPP;
576 }
577 break;
578 case PCI_POWERSTATE_D3:
579 status |= PCIM_PSTAT_D3;
580 break;
581 default:
582 result = EINVAL;
583 }
584 if (result == 0)
1f7d9fe0 585 PCI_WRITE_CONFIG(dev, child, pmgt->pp_status, status, 2);
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586 } else {
587 result = ENXIO;
588 }
589 return(result);
590}
591
e126caf1 592int
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593pci_get_powerstate_method(device_t dev, device_t child)
594{
595 struct pci_devinfo *dinfo = device_get_ivars(child);
596 pcicfgregs *cfg = &dinfo->cfg;
1f7d9fe0 597 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
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598 u_int16_t status;
599 int result;
600
1f7d9fe0
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601 if (pmgt->pp_cap != 0) {
602 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2);
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603 switch (status & PCIM_PSTAT_DMASK) {
604 case PCIM_PSTAT_D0:
605 result = PCI_POWERSTATE_D0;
606 break;
607 case PCIM_PSTAT_D1:
608 result = PCI_POWERSTATE_D1;
609 break;
610 case PCIM_PSTAT_D2:
611 result = PCI_POWERSTATE_D2;
612 break;
613 case PCIM_PSTAT_D3:
614 result = PCI_POWERSTATE_D3;
615 break;
616 default:
617 result = PCI_POWERSTATE_UNKNOWN;
618 break;
619 }
620 } else {
621 /* No support, device is always at D0 */
622 result = PCI_POWERSTATE_D0;
623 }
624 return(result);
625}
626
627/*
628 * Some convenience functions for PCI device drivers.
629 */
630
631static __inline void
632pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
633{
634 u_int16_t command;
635
636 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
637 command |= bit;
638 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
639}
640
641static __inline void
642pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
643{
644 u_int16_t command;
645
646 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
647 command &= ~bit;
648 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
649}
650
e126caf1 651int
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652pci_enable_busmaster_method(device_t dev, device_t child)
653{
654 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 655 return(0);
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656}
657
e126caf1 658int
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659pci_disable_busmaster_method(device_t dev, device_t child)
660{
661 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 662 return(0);
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663}
664
e126caf1 665int
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666pci_enable_io_method(device_t dev, device_t child, int space)
667{
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668 uint16_t command;
669 uint16_t bit;
670 char *error;
671
672 bit = 0;
673 error = NULL;
674
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675 switch(space) {
676 case SYS_RES_IOPORT:
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677 bit = PCIM_CMD_PORTEN;
678 error = "port";
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679 break;
680 case SYS_RES_MEMORY:
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681 bit = PCIM_CMD_MEMEN;
682 error = "memory";
984263bc 683 break;
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MD
684 default:
685 return(EINVAL);
984263bc 686 }
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687 pci_set_command_bit(dev, child, bit);
688 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
689 if (command & bit)
690 return(0);
691 device_printf(child, "failed to enable %s mapping!\n", error);
692 return(ENXIO);
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693}
694
e126caf1 695int
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696pci_disable_io_method(device_t dev, device_t child, int space)
697{
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698 uint16_t command;
699 uint16_t bit;
700 char *error;
701
702 bit = 0;
703 error = NULL;
704
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705 switch(space) {
706 case SYS_RES_IOPORT:
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707 bit = PCIM_CMD_PORTEN;
708 error = "port";
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709 break;
710 case SYS_RES_MEMORY:
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711 bit = PCIM_CMD_MEMEN;
712 error = "memory";
984263bc 713 break;
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714 default:
715 return (EINVAL);
984263bc 716 }
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717 pci_clear_command_bit(dev, child, bit);
718 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
719 if (command & bit) {
720 device_printf(child, "failed to disable %s mapping!\n", error);
721 return (ENXIO);
722 }
723 return (0);
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724}
725
726/*
727 * This is the user interface to PCI configuration space.
728 */
729
730static int
fef8985e 731pci_open(struct dev_open_args *ap)
984263bc 732{
fef8985e 733 if ((ap->a_oflags & FWRITE) && securelevel > 0) {
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734 return EPERM;
735 }
736 return 0;
737}
738
739static int
fef8985e 740pci_close(struct dev_close_args *ap)
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741{
742 return 0;
743}
744
745/*
746 * Match a single pci_conf structure against an array of pci_match_conf
747 * structures. The first argument, 'matches', is an array of num_matches
748 * pci_match_conf structures. match_buf is a pointer to the pci_conf
749 * structure that will be compared to every entry in the matches array.
750 * This function returns 1 on failure, 0 on success.
751 */
752static int
753pci_conf_match(struct pci_match_conf *matches, int num_matches,
754 struct pci_conf *match_buf)
755{
756 int i;
757
758 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
759 return(1);
760
761 for (i = 0; i < num_matches; i++) {
762 /*
763 * I'm not sure why someone would do this...but...
764 */
765 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
766 continue;
767
768 /*
769 * Look at each of the match flags. If it's set, do the
770 * comparison. If the comparison fails, we don't have a
771 * match, go on to the next item if there is one.
772 */
773 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
774 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
775 continue;
776
777 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
778 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
779 continue;
780
781 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
782 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
783 continue;
784
785 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
786 && (match_buf->pc_vendor != matches[i].pc_vendor))
787 continue;
788
789 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
790 && (match_buf->pc_device != matches[i].pc_device))
791 continue;
792
793 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
794 && (match_buf->pc_class != matches[i].pc_class))
795 continue;
796
797 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
798 && (match_buf->pd_unit != matches[i].pd_unit))
799 continue;
800
801 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
802 && (strncmp(matches[i].pd_name, match_buf->pd_name,
803 sizeof(match_buf->pd_name)) != 0))
804 continue;
805
806 return(0);
807 }
808
809 return(1);
810}
811
812/*
813 * Locate the parent of a PCI device by scanning the PCI devlist
814 * and return the entry for the parent.
815 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
816 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
817 */
818
819pcicfgregs *
820pci_devlist_get_parent(pcicfgregs *cfg)
821{
822 struct devlist *devlist_head;
823 struct pci_devinfo *dinfo;
824 pcicfgregs *bridge_cfg;
825 int i;
826
827 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
828
829 /* If the device is on PCI bus 0, look for the host */
830 if (cfg->bus == 0) {
831 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
832 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
833 bridge_cfg = &dinfo->cfg;
834 if (bridge_cfg->baseclass == PCIC_BRIDGE
835 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
836 && bridge_cfg->bus == cfg->bus) {
837 return bridge_cfg;
838 }
839 }
840 }
841
842 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
843 if (cfg->bus > 0) {
844 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
845 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
846 bridge_cfg = &dinfo->cfg;
847 if (bridge_cfg->baseclass == PCIC_BRIDGE
848 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
849 && bridge_cfg->secondarybus == cfg->bus) {
850 return bridge_cfg;
851 }
852 }
853 }
854
855 return NULL;
856}
857
858static int
fef8985e 859pci_ioctl(struct dev_ioctl_args *ap)
984263bc 860{
4a5a2d63 861 device_t pci, pcib;
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862 struct pci_io *io;
863 const char *name;
864 int error;
865
fef8985e 866 if (!(ap->a_fflag & FWRITE))
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867 return EPERM;
868
fef8985e 869 switch(ap->a_cmd) {
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870 case PCIOCGETCONF:
871 {
872 struct pci_devinfo *dinfo;
873 struct pci_conf_io *cio;
874 struct devlist *devlist_head;
875 struct pci_match_conf *pattern_buf;
876 int num_patterns;
877 size_t iolen;
878 int ionum, i;
879
fef8985e 880 cio = (struct pci_conf_io *)ap->a_data;
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881
882 num_patterns = 0;
883 dinfo = NULL;
884
885 /*
886 * Hopefully the user won't pass in a null pointer, but it
887 * can't hurt to check.
888 */
889 if (cio == NULL) {
890 error = EINVAL;
891 break;
892 }
893
894 /*
895 * If the user specified an offset into the device list,
896 * but the list has changed since they last called this
897 * ioctl, tell them that the list has changed. They will
898 * have to get the list from the beginning.
899 */
900 if ((cio->offset != 0)
901 && (cio->generation != pci_generation)){
902 cio->num_matches = 0;
903 cio->status = PCI_GETCONF_LIST_CHANGED;
904 error = 0;
905 break;
906 }
907
908 /*
909 * Check to see whether the user has asked for an offset
910 * past the end of our list.
911 */
912 if (cio->offset >= pci_numdevs) {
913 cio->num_matches = 0;
914 cio->status = PCI_GETCONF_LAST_DEVICE;
915 error = 0;
916 break;
917 }
918
919 /* get the head of the device queue */
920 devlist_head = &pci_devq;
921
922 /*
923 * Determine how much room we have for pci_conf structures.
924 * Round the user's buffer size down to the nearest
925 * multiple of sizeof(struct pci_conf) in case the user
926 * didn't specify a multiple of that size.
927 */
928 iolen = min(cio->match_buf_len -
929 (cio->match_buf_len % sizeof(struct pci_conf)),
930 pci_numdevs * sizeof(struct pci_conf));
931
932 /*
933 * Since we know that iolen is a multiple of the size of
934 * the pciconf union, it's okay to do this.
935 */
936 ionum = iolen / sizeof(struct pci_conf);
937
938 /*
939 * If this test is true, the user wants the pci_conf
940 * structures returned to match the supplied entries.
941 */
942 if ((cio->num_patterns > 0)
943 && (cio->pat_buf_len > 0)) {
944 /*
945 * pat_buf_len needs to be:
946 * num_patterns * sizeof(struct pci_match_conf)
947 * While it is certainly possible the user just
948 * allocated a large buffer, but set the number of
949 * matches correctly, it is far more likely that
950 * their kernel doesn't match the userland utility
951 * they're using. It's also possible that the user
952 * forgot to initialize some variables. Yes, this
953 * may be overly picky, but I hazard to guess that
954 * it's far more likely to just catch folks that
955 * updated their kernel but not their userland.
956 */
957 if ((cio->num_patterns *
958 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
959 /* The user made a mistake, return an error*/
960 cio->status = PCI_GETCONF_ERROR;
85f8e2ea 961 kprintf("pci_ioctl: pat_buf_len %d != "
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962 "num_patterns (%d) * sizeof(struct "
963 "pci_match_conf) (%d)\npci_ioctl: "
964 "pat_buf_len should be = %d\n",
965 cio->pat_buf_len, cio->num_patterns,
966 (int)sizeof(struct pci_match_conf),
967 (int)sizeof(struct pci_match_conf) *
968 cio->num_patterns);
85f8e2ea 969 kprintf("pci_ioctl: do your headers match your "
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MD
970 "kernel?\n");
971 cio->num_matches = 0;
972 error = EINVAL;
973 break;
974 }
975
976 /*
977 * Check the user's buffer to make sure it's readable.
978 */
979 if (!useracc((caddr_t)cio->patterns,
980 cio->pat_buf_len, VM_PROT_READ)) {
85f8e2ea 981 kprintf("pci_ioctl: pattern buffer %p, "
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MD
982 "length %u isn't user accessible for"
983 " READ\n", cio->patterns,
984 cio->pat_buf_len);
985 error = EACCES;
986 break;
987 }
988 /*
989 * Allocate a buffer to hold the patterns.
990 */
efda3bd0 991 pattern_buf = kmalloc(cio->pat_buf_len, M_TEMP,
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MD
992 M_WAITOK);
993 error = copyin(cio->patterns, pattern_buf,
994 cio->pat_buf_len);
995 if (error != 0)
996 break;
997 num_patterns = cio->num_patterns;
998
999 } else if ((cio->num_patterns > 0)
1000 || (cio->pat_buf_len > 0)) {
1001 /*
1002 * The user made a mistake, spit out an error.
1003 */
1004 cio->status = PCI_GETCONF_ERROR;
1005 cio->num_matches = 0;
85f8e2ea 1006 kprintf("pci_ioctl: invalid GETCONF arguments\n");
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1007 error = EINVAL;
1008 break;
1009 } else
1010 pattern_buf = NULL;
1011
1012 /*
1013 * Make sure we can write to the match buffer.
1014 */
1015 if (!useracc((caddr_t)cio->matches,
1016 cio->match_buf_len, VM_PROT_WRITE)) {
85f8e2ea 1017 kprintf("pci_ioctl: match buffer %p, length %u "
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1018 "isn't user accessible for WRITE\n",
1019 cio->matches, cio->match_buf_len);
1020 error = EACCES;
1021 break;
1022 }
1023
1024 /*
1025 * Go through the list of devices and copy out the devices
1026 * that match the user's criteria.
1027 */
1028 for (cio->num_matches = 0, error = 0, i = 0,
1029 dinfo = STAILQ_FIRST(devlist_head);
1030 (dinfo != NULL) && (cio->num_matches < ionum)
1031 && (error == 0) && (i < pci_numdevs);
1032 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
1033
1034 if (i < cio->offset)
1035 continue;
1036
1037 /* Populate pd_name and pd_unit */
1038 name = NULL;
1039 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
1040 name = device_get_name(dinfo->cfg.dev);
1041 if (name) {
1042 strncpy(dinfo->conf.pd_name, name,
1043 sizeof(dinfo->conf.pd_name));
1044 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
1045 dinfo->conf.pd_unit =
1046 device_get_unit(dinfo->cfg.dev);
1047 }
1048
1049 if ((pattern_buf == NULL) ||
1050 (pci_conf_match(pattern_buf, num_patterns,
1051 &dinfo->conf) == 0)) {
1052
1053 /*
1054 * If we've filled up the user's buffer,
1055 * break out at this point. Since we've
1056 * got a match here, we'll pick right back
1057 * up at the matching entry. We can also
1058 * tell the user that there are more matches
1059 * left.
1060 */
1061 if (cio->num_matches >= ionum)
1062 break;
1063
1064 error = copyout(&dinfo->conf,
1065 &cio->matches[cio->num_matches],
1066 sizeof(struct pci_conf));
1067 cio->num_matches++;
1068 }
1069 }
1070
1071 /*
1072 * Set the pointer into the list, so if the user is getting
1073 * n records at a time, where n < pci_numdevs,
1074 */
1075 cio->offset = i;
1076
1077 /*
1078 * Set the generation, the user will need this if they make
1079 * another ioctl call with offset != 0.
1080 */
1081 cio->generation = pci_generation;
1082
1083 /*
1084 * If this is the last device, inform the user so he won't
1085 * bother asking for more devices. If dinfo isn't NULL, we
1086 * know that there are more matches in the list because of
1087 * the way the traversal is done.
1088 */
1089 if (dinfo == NULL)
1090 cio->status = PCI_GETCONF_LAST_DEVICE;
1091 else
1092 cio->status = PCI_GETCONF_MORE_DEVS;
1093
1094 if (pattern_buf != NULL)
efda3bd0 1095 kfree(pattern_buf, M_TEMP);
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1096
1097 break;
1098 }
1099 case PCIOCREAD:
fef8985e 1100 io = (struct pci_io *)ap->a_data;
984263bc 1101 switch(io->pi_width) {
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MD
1102 case 4:
1103 case 2:
1104 case 1:
4a5a2d63
JS
1105 /*
1106 * Assume that the user-level bus number is
1107 * actually the pciN instance number. We map
1108 * from that to the real pcib+bus combination.
1109 */
1110 pci = devclass_get_device(pci_devclass,
1111 io->pi_sel.pc_bus);
1112 if (pci) {
2581072f
MD
1113 /*
1114 * pci is the pci device and may contain
1115 * several children (for each function code).
1116 * The governing pci bus is the parent to
1117 * the pci device.
1118 */
1119 int b;
1120
4a5a2d63 1121 pcib = device_get_parent(pci);
2581072f 1122 b = pcib_get_bus(pcib);
4a5a2d63
JS
1123 io->pi_data =
1124 PCIB_READ_CONFIG(pcib,
1125 b,
1126 io->pi_sel.pc_dev,
1127 io->pi_sel.pc_func,
1128 io->pi_reg,
1129 io->pi_width);
1130 error = 0;
1131 } else {
1132 error = ENODEV;
1133 }
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MD
1134 break;
1135 default:
1136 error = ENODEV;
1137 break;
1138 }
1139 break;
1140
1141 case PCIOCWRITE:
fef8985e 1142 io = (struct pci_io *)ap->a_data;
984263bc 1143 switch(io->pi_width) {
984263bc
MD
1144 case 4:
1145 case 2:
1146 case 1:
4a5a2d63
JS
1147 /*
1148 * Assume that the user-level bus number is
1149 * actually the pciN instance number. We map
1150 * from that to the real pcib+bus combination.
1151 */
1152 pci = devclass_get_device(pci_devclass,
1153 io->pi_sel.pc_bus);
1154 if (pci) {
2581072f
MD
1155 /*
1156 * pci is the pci device and may contain
1157 * several children (for each function code).
1158 * The governing pci bus is the parent to
1159 * the pci device.
1160 */
1161 int b;
1162
4a5a2d63 1163 pcib = device_get_parent(pci);
2581072f 1164 b = pcib_get_bus(pcib);
4a5a2d63
JS
1165 PCIB_WRITE_CONFIG(pcib,
1166 b,
1167 io->pi_sel.pc_dev,
1168 io->pi_sel.pc_func,
1169 io->pi_reg,
1170 io->pi_data,
1171 io->pi_width);
1172 error = 0;
1173 } else {
1174 error = ENODEV;
1175 }
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1176 break;
1177 default:
1178 error = ENODEV;
1179 break;
1180 }
1181 break;
1182
1183 default:
1184 error = ENOTTY;
1185 break;
1186 }
1187
1188 return (error);
1189}
1190
1191#define PCI_CDEV 78
1192
fef8985e
MD
1193static struct dev_ops pcic_ops = {
1194 { "pci", PCI_CDEV, 0 },
1195 .d_open = pci_open,
1196 .d_close = pci_close,
1197 .d_ioctl = pci_ioctl,
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MD
1198};
1199
1200#include "pci_if.h"
1201
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1202/*
1203 * New style pci driver. Parent device is either a pci-host-bridge or a
1204 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1205 */
ed1bd994
MD
1206const char *
1207pci_class_to_string(int baseclass)
1208{
1209 const char *name;
1210
1211 switch(baseclass) {
1212 case PCIC_OLD:
1213 name = "OLD";
1214 break;
1215 case PCIC_STORAGE:
1216 name = "STORAGE";
1217 break;
1218 case PCIC_NETWORK:
1219 name = "NETWORK";
1220 break;
1221 case PCIC_DISPLAY:
1222 name = "DISPLAY";
1223 break;
1224 case PCIC_MULTIMEDIA:
1225 name = "MULTIMEDIA";
1226 break;
1227 case PCIC_MEMORY:
1228 name = "MEMORY";
1229 break;
1230 case PCIC_BRIDGE:
1231 name = "BRIDGE";
1232 break;
1233 case PCIC_SIMPLECOMM:
1234 name = "SIMPLECOMM";
1235 break;
1236 case PCIC_BASEPERIPH:
1237 name = "BASEPERIPH";
1238 break;
1239 case PCIC_INPUTDEV:
1240 name = "INPUTDEV";
1241 break;
1242 case PCIC_DOCKING:
1243 name = "DOCKING";
1244 break;
1245 case PCIC_PROCESSOR:
1246 name = "PROCESSOR";
1247 break;
1248 case PCIC_SERIALBUS:
1249 name = "SERIALBUS";
1250 break;
1251 case PCIC_WIRELESS:
1252 name = "WIRELESS";
1253 break;
1254 case PCIC_I2O:
1255 name = "I20";
1256 break;
1257 case PCIC_SATELLITE:
1258 name = "SATELLITE";
1259 break;
1260 case PCIC_CRYPTO:
1261 name = "CRYPTO";
1262 break;
1263 case PCIC_SIGPROC:
1264 name = "SIGPROC";
1265 break;
1266 case PCIC_OTHER:
1267 name = "OTHER";
1268 break;
1269 default:
1270 name = "?";
1271 break;
1272 }
1273 return(name);
1274}
984263bc 1275
22457186 1276void
984263bc
MD
1277pci_print_verbose(struct pci_devinfo *dinfo)
1278{
1279 if (bootverbose) {
1280 pcicfgregs *cfg = &dinfo->cfg;
1281
85f8e2ea 1282 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
984263bc 1283 cfg->vendor, cfg->device, cfg->revid);
85f8e2ea 1284 kprintf("\tbus=%d, slot=%d, func=%d\n",
4a5a2d63 1285 cfg->bus, cfg->slot, cfg->func);
85f8e2ea 1286 kprintf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
ed1bd994 1287 pci_class_to_string(cfg->baseclass),
984263bc
MD
1288 cfg->baseclass, cfg->subclass, cfg->progif,
1289 cfg->hdrtype, cfg->mfdev);
85f8e2ea 1290 kprintf("\tsubordinatebus=%x \tsecondarybus=%x\n",
984263bc
MD
1291 cfg->subordinatebus, cfg->secondarybus);
1292#ifdef PCI_DEBUG
85f8e2ea 1293 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
984263bc 1294 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
85f8e2ea 1295 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
984263bc
MD
1296 cfg->lattimer, cfg->lattimer * 30,
1297 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1298#endif /* PCI_DEBUG */
1299 if (cfg->intpin > 0)
85f8e2ea 1300 kprintf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
984263bc
MD
1301 }
1302}
1303
1304static int
4a5a2d63 1305pci_porten(device_t pcib, int b, int s, int f)
984263bc 1306{
4a5a2d63
JS
1307 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1308 & PCIM_CMD_PORTEN) != 0;
984263bc
MD
1309}
1310
1311static int
4a5a2d63 1312pci_memen(device_t pcib, int b, int s, int f)
984263bc 1313{
4a5a2d63
JS
1314 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1315 & PCIM_CMD_MEMEN) != 0;
984263bc
MD
1316}
1317
1318/*
1319 * Add a resource based on a pci map register. Return 1 if the map
1320 * register is a 32bit map register or 2 if it is a 64bit register.
1321 */
1322static int
4a5a2d63
JS
1323pci_add_map(device_t pcib, int b, int s, int f, int reg,
1324 struct resource_list *rl)
984263bc 1325{
984263bc
MD
1326 u_int32_t map;
1327 u_int64_t base;
1328 u_int8_t ln2size;
1329 u_int8_t ln2range;
1330 u_int32_t testval;
4a5a2d63
JS
1331
1332
1333#ifdef PCI_ENABLE_IO_MODES
1334 u_int16_t cmd;
1335#endif
984263bc
MD
1336 int type;
1337
4a5a2d63 1338 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
984263bc
MD
1339
1340 if (map == 0 || map == 0xffffffff)
1341 return 1; /* skip invalid entry */
1342
4a5a2d63
JS
1343 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1344 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1345 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
984263bc
MD
1346
1347 base = pci_mapbase(map);
1348 if (pci_maptype(map) & PCI_MAPMEM)
1349 type = SYS_RES_MEMORY;
1350 else
1351 type = SYS_RES_IOPORT;
1352 ln2size = pci_mapsize(testval);
1353 ln2range = pci_maprange(testval);
1354 if (ln2range == 64) {
1355 /* Read the other half of a 64bit map register */
4a5a2d63 1356 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
984263bc
MD
1357 }
1358
984263bc
MD
1359 /*
1360 * This code theoretically does the right thing, but has
1361 * undesirable side effects in some cases where
1362 * peripherals respond oddly to having these bits
1363 * enabled. Leave them alone by default.
1364 */
1365#ifdef PCI_ENABLE_IO_MODES
4a5a2d63
JS
1366 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1367 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1368 cmd |= PCIM_CMD_PORTEN;
1369 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc 1370 }
4a5a2d63
JS
1371 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1372 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1373 cmd |= PCIM_CMD_MEMEN;
1374 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc
MD
1375 }
1376#else
4a5a2d63 1377 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
984263bc 1378 return 1;
4a5a2d63 1379 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
984263bc
MD
1380 return 1;
1381#endif
1382
1383 resource_list_add(rl, type, reg,
1384 base, base + (1 << ln2size) - 1,
1385 (1 << ln2size));
1386
1387 if (bootverbose) {
85f8e2ea 1388 kprintf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
984263bc
MD
1389 reg, pci_maptype(base), ln2range,
1390 (unsigned int) base, ln2size);
1391 }
1392
1393 return (ln2range == 64) ? 2 : 1;
1394}
1395
201eb0a7
TS
1396#ifdef PCI_MAP_FIXUP
1397/*
1398 * For ATA devices we need to decide early on what addressing mode to use.
1399 * Legacy demands that the primary and secondary ATA ports sits on the
1400 * same addresses that old ISA hardware did. This dictates that we use
1401 * those addresses and ignore the BARs if we cannot set PCI native
1402 * addressing mode.
1403 */
1404static void
1405pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, int s, int f,
1406 struct resource_list *rl)
1407{
1408 int rid, type, progif;
1409#if 0
1410 /* if this device supports PCI native addressing use it */
1411 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1412 if ((progif &0x8a) == 0x8a) {
1413 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
1414 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
85f8e2ea 1415 kprintf("Trying ATA native PCI addressing mode\n");
201eb0a7
TS
1416 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
1417 }
1418 }
1419#endif
1420 /*
1421 * Because we return any preallocated resources for lazy
1422 * allocation for PCI devices in pci_alloc_resource(), we can
1423 * allocate our legacy resources here.
1424 */
1425 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1426 type = SYS_RES_IOPORT;
1427 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
1428 pci_add_map(pcib, b, s, f, PCIR_BAR(0), rl);
1429 pci_add_map(pcib, b, s, f, PCIR_BAR(1), rl);
1430 } else {
1431 rid = PCIR_BAR(0);
1432 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
1433 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
1434 0);
1435 rid = PCIR_BAR(1);
1436 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
1437 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
1438 0);
1439 }
1440 if (progif & PCIP_STORAGE_IDE_MODESEC) {
1441 pci_add_map(pcib, b, s, f, PCIR_BAR(2), rl);
1442 pci_add_map(pcib, b, s, f, PCIR_BAR(3), rl);
1443 } else {
1444 rid = PCIR_BAR(2);
1445 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
1446 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
1447 0);
1448 rid = PCIR_BAR(3);
1449 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
1450 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
1451 0);
1452 }
1453 pci_add_map(pcib, b, s, f, PCIR_BAR(4), rl);
1454 pci_add_map(pcib, b, s, f, PCIR_BAR(5), rl);
1455}
1456#endif /* PCI_MAP_FIXUP */
1457
984263bc 1458static void
e126caf1 1459pci_add_resources(device_t pcib, device_t bus, device_t dev)
984263bc
MD
1460{
1461 struct pci_devinfo *dinfo = device_get_ivars(dev);
4a5a2d63 1462 pcicfgregs *cfg = &dinfo->cfg;
984263bc
MD
1463 struct resource_list *rl = &dinfo->resources;
1464 struct pci_quirk *q;
e126caf1
MD
1465 int b, i, f, s;
1466#if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */
1467 int irq;
1468#endif
984263bc 1469
e126caf1
MD
1470 b = cfg->bus;
1471 s = cfg->slot;
1472 f = cfg->func;
201eb0a7
TS
1473#ifdef PCI_MAP_FIXUP
1474 /* atapci devices in legacy mode need special map treatment */
1475 if ((pci_get_class(dev) == PCIC_STORAGE) &&
1476 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
d3d1ea7a
MD
1477 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
1478 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
1479 !pci_read_config(dev, PCIR_BAR(2), 4))) )
201eb0a7
TS
1480 pci_ata_maps(pcib, bus, dev, b, s, f, rl);
1481 else
1482#endif /* PCI_MAP_FIXUP */
1483 for (i = 0; i < cfg->nummaps;) {
1484 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl);
1485 }
984263bc
MD
1486
1487 for (q = &pci_quirks[0]; q->devid; q++) {
1488 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1489 && q->type == PCI_QUIRK_MAP_REG)
4a5a2d63 1490 pci_add_map(pcib, b, s, f, q->arg1, rl);
984263bc
MD
1491 }
1492
1493 if (cfg->intpin > 0 && cfg->intline != 255)
1494 resource_list_add(rl, SYS_RES_IRQ, 0,
1495 cfg->intline, cfg->intline, 1);
1496}
1497
e126caf1
MD
1498void
1499pci_add_children(device_t dev, int busno, size_t dinfo_size)
984263bc 1500{
e126caf1 1501#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
4a5a2d63 1502 device_t pcib = device_get_parent(dev);
e126caf1 1503 struct pci_devinfo *dinfo;
4a5a2d63 1504 int maxslots;
e126caf1
MD
1505 int s, f, pcifunchigh;
1506 uint8_t hdrtype;
1507
1508 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo));
984263bc 1509
4a5a2d63 1510 maxslots = PCIB_MAXSLOTS(pcib);
984263bc 1511
57e943f7 1512 for (s = 0; s <= maxslots; s++) {
e126caf1
MD
1513 pcifunchigh = 0;
1514 f = 0;
1515 hdrtype = REG(PCIR_HDRTYPE, 1);
1516 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1517 continue;
1518 if (hdrtype & PCIM_MFDEV)
1519 pcifunchigh = PCI_FUNCMAX;
5e658043 1520 for (f = 0; f <= pcifunchigh; f++) {
e126caf1 1521 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
984263bc 1522 if (dinfo != NULL) {
e126caf1 1523 pci_add_child(dev, dinfo);
984263bc
MD
1524 }
1525 }
1526 }
e126caf1
MD
1527#undef REG
1528}
1529
2581072f
MD
1530/*
1531 * The actual PCI child that we add has a NULL driver whos parent
1532 * device will be "pci". The child contains the ivars, not the parent.
1533 */
e126caf1
MD
1534void
1535pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1536{
1537 device_t pcib;
1538
1539 pcib = device_get_parent(bus);
1540 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1541 device_set_ivars(dinfo->cfg.dev, dinfo);
1542 pci_add_resources(pcib, bus, dinfo->cfg.dev);
1543 pci_print_verbose(dinfo);
984263bc
MD
1544}
1545
c01b8d84
MD
1546/*
1547 * Probe the PCI bus. Note: probe code is not supposed to add children
1548 * or call attach.
1549 */
984263bc 1550static int
4a5a2d63 1551pci_probe(device_t dev)
984263bc 1552{
984263bc 1553 device_set_desc(dev, "PCI bus");
4a5a2d63 1554
c01b8d84
MD
1555 /* Allow other subclasses to override this driver */
1556 return(-1000);
984263bc
MD
1557}
1558
e126caf1
MD
1559static int
1560pci_attach(device_t dev)
1561{
1562 int busno;
e4c9c0c8
MD
1563 int lunit = device_get_unit(dev);
1564
fef8985e
MD
1565 dev_ops_add(&pcic_ops, -1, lunit);
1566 make_dev(&pcic_ops, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit);
e126caf1
MD
1567
1568 /*
1569 * Since there can be multiple independantly numbered PCI
1570 * busses on some large alpha systems, we can't use the unit
1571 * number to decide what bus we are probing. We ask the parent
1572 * pcib what our bus number is.
2581072f
MD
1573 *
1574 * pcib_get_bus() must act on the pci bus device, not on the pci
1575 * device, because it uses badly hacked nexus-based ivars to
1576 * store and retrieve the physical bus number. XXX
e126caf1 1577 */
2581072f 1578 busno = pcib_get_bus(device_get_parent(dev));
e126caf1 1579 if (bootverbose)
ed1bd994 1580 device_printf(dev, "pci_attach() physical bus=%d\n", busno);
e126caf1
MD
1581
1582 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1583
1584 return (bus_generic_attach(dev));
1585}
1586
984263bc
MD
1587static int
1588pci_print_resources(struct resource_list *rl, const char *name, int type,
1589 const char *format)
1590{
1591 struct resource_list_entry *rle;
1592 int printed, retval;
1593
1594 printed = 0;
1595 retval = 0;
1596 /* Yes, this is kinda cheating */
1597 SLIST_FOREACH(rle, rl, link) {
1598 if (rle->type == type) {
1599 if (printed == 0)
85f8e2ea 1600 retval += kprintf(" %s ", name);
984263bc 1601 else if (printed > 0)
85f8e2ea 1602 retval += kprintf(",");
984263bc 1603 printed++;
85f8e2ea 1604 retval += kprintf(format, rle->start);
984263bc 1605 if (rle->count > 1) {
85f8e2ea
SW
1606 retval += kprintf("-");
1607 retval += kprintf(format, rle->start +
984263bc
MD
1608 rle->count - 1);
1609 }
1610 }
1611 }
1612 return retval;
1613}
1614
e126caf1 1615int
984263bc
MD
1616pci_print_child(device_t dev, device_t child)
1617{
1618 struct pci_devinfo *dinfo;
1619 struct resource_list *rl;
1620 pcicfgregs *cfg;
1621 int retval = 0;
1622
1623 dinfo = device_get_ivars(child);
1624 cfg = &dinfo->cfg;
1625 rl = &dinfo->resources;
1626
1627 retval += bus_print_child_header(dev, child);
1628
1629 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1630 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1631 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1632 if (device_get_flags(dev))
85f8e2ea 1633 retval += kprintf(" flags %#x", device_get_flags(dev));
984263bc 1634
85f8e2ea 1635 retval += kprintf(" at device %d.%d", pci_get_slot(child),
984263bc
MD
1636 pci_get_function(child));
1637
1638 retval += bus_print_child_footer(dev, child);
1639
1640 return (retval);
1641}
1642
e126caf1 1643void
984263bc
MD
1644pci_probe_nomatch(device_t dev, device_t child)
1645{
1646 struct pci_devinfo *dinfo;
1647 pcicfgregs *cfg;
1648 const char *desc;
1649 int unknown;
1650
1651 unknown = 0;
1652 dinfo = device_get_ivars(child);
1653 cfg = &dinfo->cfg;
1654 desc = pci_ata_match(child);
1655 if (!desc) desc = pci_usb_match(child);
1656 if (!desc) desc = pci_vga_match(child);
27c23c6b 1657 if (!desc) desc = pci_chip_match(child);
984263bc
MD
1658 if (!desc) {
1659 desc = "unknown card";
1660 unknown++;
1661 }
1662 device_printf(dev, "<%s>", desc);
1663 if (bootverbose || unknown) {
85f8e2ea 1664 kprintf(" (vendor=0x%04x, dev=0x%04x)",
984263bc
MD
1665 cfg->vendor,
1666 cfg->device);
1667 }
85f8e2ea 1668 kprintf(" at %d.%d",
984263bc
MD
1669 pci_get_slot(child),
1670 pci_get_function(child));
1671 if (cfg->intpin > 0 && cfg->intline != 255) {
85f8e2ea 1672 kprintf(" irq %d", cfg->intline);
984263bc 1673 }
85f8e2ea 1674 kprintf("\n");
984263bc
MD
1675
1676 return;
1677}
1678
22457186 1679int
4a5a2d63 1680pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
984263bc
MD
1681{
1682 struct pci_devinfo *dinfo;
1683 pcicfgregs *cfg;
1684
1685 dinfo = device_get_ivars(child);
1686 cfg = &dinfo->cfg;
1687
1688 switch (which) {
1689 case PCI_IVAR_SUBVENDOR:
1690 *result = cfg->subvendor;
1691 break;
1692 case PCI_IVAR_SUBDEVICE:
1693 *result = cfg->subdevice;
1694 break;
1695 case PCI_IVAR_VENDOR:
1696 *result = cfg->vendor;
1697 break;
1698 case PCI_IVAR_DEVICE:
1699 *result = cfg->device;
1700 break;
1701 case PCI_IVAR_DEVID:
1702 *result = (cfg->device << 16) | cfg->vendor;
1703 break;
1704 case PCI_IVAR_CLASS:
1705 *result = cfg->baseclass;
1706 break;
1707 case PCI_IVAR_SUBCLASS:
1708 *result = cfg->subclass;
1709 break;
1710 case PCI_IVAR_PROGIF:
1711 *result = cfg->progif;
1712 break;
1713 case PCI_IVAR_REVID:
1714 *result = cfg->revid;
1715 break;
1716 case PCI_IVAR_INTPIN:
1717 *result = cfg->intpin;
1718 break;
1719 case PCI_IVAR_IRQ:
1720 *result = cfg->intline;
1721 break;
1722 case PCI_IVAR_BUS:
1723 *result = cfg->bus;
1724 break;
1725 case PCI_IVAR_SLOT:
1726 *result = cfg->slot;
1727 break;
1728 case PCI_IVAR_FUNCTION:
1729 *result = cfg->func;
1730 break;
1731 case PCI_IVAR_SECONDARYBUS:
1732 *result = cfg->secondarybus;
1733 break;
1734 case PCI_IVAR_SUBORDINATEBUS:
1735 *result = cfg->subordinatebus;
1736 break;
f72d3d23
JS
1737 case PCI_IVAR_ETHADDR:
1738 /*
1739 * The generic accessor doesn't deal with failure, so
1740 * we set the return value, then return an error.
1741 */
1742 *result = NULL;
1743 return (EINVAL);
984263bc
MD
1744 default:
1745 return ENOENT;
1746 }
1747 return 0;
1748}
1749
22457186 1750int
984263bc
MD
1751pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1752{
1753 struct pci_devinfo *dinfo;
1754 pcicfgregs *cfg;
1755
1756 dinfo = device_get_ivars(child);
1757 cfg = &dinfo->cfg;
1758
1759 switch (which) {
1760 case PCI_IVAR_SUBVENDOR:
1761 case PCI_IVAR_SUBDEVICE:
1762 case PCI_IVAR_VENDOR:
1763 case PCI_IVAR_DEVICE:
1764 case PCI_IVAR_DEVID:
1765 case PCI_IVAR_CLASS:
1766 case PCI_IVAR_SUBCLASS:
1767 case PCI_IVAR_PROGIF:
1768 case PCI_IVAR_REVID:
1769 case PCI_IVAR_INTPIN:
1770 case PCI_IVAR_IRQ:
1771 case PCI_IVAR_BUS:
1772 case PCI_IVAR_SLOT:
1773 case PCI_IVAR_FUNCTION:
f72d3d23 1774 case PCI_IVAR_ETHADDR:
984263bc
MD
1775 return EINVAL; /* disallow for now */
1776
1777 case PCI_IVAR_SECONDARYBUS:
1778 cfg->secondarybus = value;
1779 break;
1780 case PCI_IVAR_SUBORDINATEBUS:
1781 cfg->subordinatebus = value;
1782 break;
1783 default:
1784 return ENOENT;
1785 }
1786 return 0;
1787}
1788
201eb0a7
TS
1789#ifdef PCI_MAP_FIXUP
1790static struct resource *
1791pci_alloc_map(device_t dev, device_t child, int type, int *rid, u_long start,
1792 u_long end, u_long count, u_int flags)
1793{
1794 struct pci_devinfo *dinfo = device_get_ivars(child);
1795 struct resource_list *rl = &dinfo->resources;
1796 struct resource_list_entry *rle;
1797 struct resource *res;
1798 uint32_t map, testval;
1799 int mapsize;
1800
1801 /*
1802 * Weed out the bogons, and figure out how large the BAR/map
1803 * is. BARs that read back 0 here are bogus and unimplemented.
1804 *
1805 * Note: atapci in legacy mode are special and handled elsewhere
1806 * in the code. If you have an atapci device in legacy mode and
1807 * it fails here, that other code is broken.
1808 */
1809 res = NULL;
1810 map = pci_read_config(child, *rid, 4);
1811 pci_write_config(child, *rid, 0xffffffff, 4);
1812 testval = pci_read_config(child, *rid, 4);
1813 if (pci_mapbase(testval) == 0)
1814 goto out;
1815 if (pci_maptype(testval) & PCI_MAPMEM) {
1816 if (type != SYS_RES_MEMORY) {
1817 if (bootverbose)
1818 device_printf(dev, "child %s requested type %d"
1819 " for rid %#x, but the BAR says "
1820 "it is a memio\n",
1821 device_get_nameunit(child), type,
1822 *rid);
1823 goto out;
1824 }
1825 } else {
1826 if (type != SYS_RES_IOPORT) {
1827 if (bootverbose)
1828 device_printf(dev, "child %s requested type %d"
1829 " for rid %#x, but the BAR says "
1830 "it is an ioport\n",
1831 device_get_nameunit(child), type,
1832 *rid);
1833 goto out;
1834 }
1835 }
1836 /*
1837 * For real BARs, we need to override the size that
1838 * the driver requests, because that's what the BAR
1839 * actually uses and we would otherwise have a
1840 * situation where we might allocate the excess to
1841 * another driver, which won't work.
1842 */
1843 mapsize = pci_mapsize(testval);
1844 count = 1 << mapsize;
1845 if (RF_ALIGNMENT(flags) < mapsize)
1846 flags = (flags & ~RF_ALIGNMENT_MASK) |
1847 RF_ALIGNMENT_LOG2(mapsize);
1848 /*
1849 * Allocate enough resource, and then write back the
1850 * appropriate BAR for that resource.
1851 */
1852 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
1853 start, end, count, flags);
1854 if (res == NULL) {
1855 device_printf(child, "%#lx bytes at rid %#x res %d failed "
1856 "(%#lx, %#lx)\n", count, *rid, type, start, end);
1857 goto out;
1858 }
1859 resource_list_add(rl, type, *rid, start, end, count);
1860 rle = resource_list_find(rl, type, *rid);
1861 if (rle == NULL)
1862 panic("pci_alloc_map: unexpectedly can't find resource.");
1863 rle->res = res;
1864 rle->start = rman_get_start(res);
1865 rle->end = rman_get_end(res);
1866 rle->count = count;
1867 if (bootverbose)
1868 device_printf(child, "lazy allocation of %#lx bytes rid %#x "
1869 "type %d at %#lx\n", count, *rid, type,
1870 rman_get_start(res));
1871 map = rman_get_start(res);
1872out:;
1873 pci_write_config(child, *rid, map, 4);
1874 return res;
1875}
1876#endif /* PCI_MAP_FIXUP */
1877
261fa16d 1878struct resource *
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1879pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1880 u_long start, u_long end, u_long count, u_int flags)
1881{
1882 struct pci_devinfo *dinfo = device_get_ivars(child);
1883 struct resource_list *rl = &dinfo->resources;
201eb0a7
TS
1884#ifdef PCI_MAP_FIXUP
1885 struct resource_list_entry *rle;
1886#endif /* PCI_MAP_FIXUP */
984263bc 1887 pcicfgregs *cfg = &dinfo->cfg;
de67e43b 1888
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1889 /*
1890 * Perform lazy resource allocation
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1891 */
1892 if (device_get_parent(child) == dev) {
de67e43b
JS
1893 switch (type) {
1894 case SYS_RES_IRQ:
1895#ifdef __i386__
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1896 /*
1897 * If device doesn't have an interrupt routed, and is
1898 * deserving of an interrupt, try to assign it one.
1899 */
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JS
1900 if ((cfg->intline == 255 || cfg->intline == 0) &&
1901 (cfg->intpin != 0) &&
1902 (start == 0) && (end == ~0UL)) {
1903 cfg->intline = PCIB_ROUTE_INTERRUPT(
1904 device_get_parent(dev), child,
1905 cfg->intpin);
1906 if (cfg->intline != 255) {
1907 pci_write_config(child, PCIR_INTLINE,
1908 cfg->intline, 1);
1909 resource_list_add(rl, SYS_RES_IRQ, 0,
1910 cfg->intline, cfg->intline, 1);
1911 }
1912 }
820c1612 1913 break;
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JS
1914#endif
1915 case SYS_RES_IOPORT:
201eb0a7 1916 /* FALLTHROUGH */
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1917 case SYS_RES_MEMORY:
1918 if (*rid < PCIR_BAR(cfg->nummaps)) {
1919 /*
1920 * Enable the I/O mode. We should
1921 * also be assigning resources too
1922 * when none are present. The
1923 * resource_list_alloc kind of sorta does
1924 * this...
1925 */
1926 if (PCI_ENABLE_IO(dev, child, type))
1927 return (NULL);
984263bc 1928 }
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TS
1929#ifdef PCI_MAP_FIXUP
1930 rle = resource_list_find(rl, type, *rid);
1931 if (rle == NULL)
1932 return pci_alloc_map(dev, child, type, rid,
1933 start, end, count, flags);
1934#endif /* PCI_MAP_FIXUP */
820c1612 1935 break;
984263bc 1936 }
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1937#ifdef PCI_MAP_FIXUP
1938 /*
1939 * If we've already allocated the resource, then
1940 * return it now. But first we may need to activate
1941 * it, since we don't allocate the resource as active
1942 * above. Normally this would be done down in the
1943 * nexus, but since we short-circuit that path we have
1944 * to do its job here. Not sure if we should free the
1945 * resource if it fails to activate.
1946 *
1947 * Note: this also finds and returns resources for
1948 * atapci devices in legacy mode as allocated in
1949 * pci_ata_maps().
1950 */
1951 rle = resource_list_find(rl, type, *rid);
1952 if (rle != NULL && rle->res != NULL) {
1953 if (bootverbose)
1954 device_printf(child, "reserved %#lx bytes for "
1955 "rid %#x type %d at %#lx\n",
1956 rman_get_size(rle->res), *rid,
1957 type, rman_get_start(rle->res));
1958 if ((flags & RF_ACTIVE) &&
1959 bus_generic_activate_resource(dev, child, type,
1960 *rid, rle->res) != 0)
1961 return NULL;
1962 return rle->res;
1963 }
1964#endif /* PCI_MAP_FIXUP */
984263bc 1965 }
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1966 return resource_list_alloc(rl, dev, child, type, rid,
1967 start, end, count, flags);
1968}
1969
1970static int
1971pci_release_resource(device_t dev, device_t child, int type, int rid,
1972 struct resource *r)
1973{
1974 struct pci_devinfo *dinfo = device_get_ivars(child);
1975 struct resource_list *rl = &dinfo->resources;
1976
1977 return resource_list_release(rl, dev, child, type, rid, r);
1978}
1979
1980static int
1981pci_set_resource(device_t dev, device_t child, int type, int rid,
1982 u_long start, u_long count)
1983{
1984 struct pci_devinfo *dinfo = device_get_ivars(child);
1985 struct resource_list *rl = &dinfo->resources;
1986
1987 resource_list_add(rl, type, rid, start, start + count - 1, count);
1988 return 0;
1989}
1990
1991static int
1992pci_get_resource(device_t dev, device_t child, int type, int rid,
1993 u_long *startp, u_long *countp)
1994{
1995 struct pci_devinfo *dinfo = device_get_ivars(child);
1996 struct resource_list *rl = &dinfo->resources;
1997 struct resource_list_entry *rle;
1998
1999 rle = resource_list_find(rl, type, rid);
2000 if (!rle)
2001 return ENOENT;
2002
2003 if (startp)
2004 *startp = rle->start;
2005 if (countp)
2006 *countp = rle->count;
2007
2008 return 0;
2009}
2010
e126caf1 2011void
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2012pci_delete_resource(device_t dev, device_t child, int type, int rid)
2013{
85f8e2ea 2014 kprintf("pci_delete_resource: PCI resources can not be deleted\n");
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2015}
2016
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2017struct resource_list *
2018pci_get_resource_list (device_t dev, device_t child)
2019{
b0486c83 2020 struct pci_devinfo *dinfo = device_get_ivars(child);
e126caf1 2021
b0486c83 2022 if (dinfo == NULL)
e126caf1 2023 return (NULL);
b0486c83 2024 return (&dinfo->resources);
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MD
2025}
2026
2027u_int32_t
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MD
2028pci_read_config_method(device_t dev, device_t child, int reg, int width)
2029{
2030 struct pci_devinfo *dinfo = device_get_ivars(child);
2031 pcicfgregs *cfg = &dinfo->cfg;
4a5a2d63
JS
2032
2033 return PCIB_READ_CONFIG(device_get_parent(dev),
2034 cfg->bus, cfg->slot, cfg->func,
2035 reg, width);
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2036}
2037
e126caf1 2038void
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MD
2039pci_write_config_method(device_t dev, device_t child, int reg,
2040 u_int32_t val, int width)
2041{
2042 struct pci_devinfo *dinfo = device_get_ivars(child);
2043 pcicfgregs *cfg = &dinfo->cfg;
4a5a2d63
JS
2044
2045 PCIB_WRITE_CONFIG(device_get_parent(dev),
2046 cfg->bus, cfg->slot, cfg->func,
2047 reg, val, width);
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MD
2048}
2049
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MD
2050int
2051pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
2052 size_t buflen)
2053{
2054 struct pci_devinfo *dinfo;
2055
2056 dinfo = device_get_ivars(child);
f8c7a42d 2057 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
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MD
2058 pci_get_function(child));
2059 return (0);
2060}
2061
2062int
2063pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
2064 size_t buflen)
2065{
2066 struct pci_devinfo *dinfo;
2067 pcicfgregs *cfg;
2068
2069 dinfo = device_get_ivars(child);
2070 cfg = &dinfo->cfg;
f8c7a42d 2071 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
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MD
2072 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
2073 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
2074 cfg->progif);
2075 return (0);
2076}
2077
2078int
2079pci_assign_interrupt_method(device_t dev, device_t child)
2080{
2081 struct pci_devinfo *dinfo = device_get_ivars(child);
2082 pcicfgregs *cfg = &dinfo->cfg;
2083
2084 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
2085 cfg->intpin));
2086}
2087
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2088static int
2089pci_modevent(module_t mod, int what, void *arg)
2090{
2091 switch (what) {
2092 case MOD_LOAD:
2093 STAILQ_INIT(&pci_devq);
2094 break;
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MD
2095 case MOD_UNLOAD:
2096 break;
2097 }
2098
2099 return 0;
2100}
2101
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MD
2102int
2103pci_resume(device_t dev)
2104{
2105 int numdevs;
2106 int i;
2107 device_t *children;
2108 device_t child;
2109 struct pci_devinfo *dinfo;
2110 pcicfgregs *cfg;
2111
2112 device_get_children(dev, &children, &numdevs);
2113
2114 for (i = 0; i < numdevs; i++) {
2115 child = children[i];
2116
2117 dinfo = device_get_ivars(child);
2118 cfg = &dinfo->cfg;
2119 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2120 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
2121 if (PCI_INTERRUPT_VALID(cfg->intline)) {
2122 pci_write_config(child, PCIR_INTLINE,
2123 cfg->intline, 1);
2124 }
2125 }
2126 }
2127
efda3bd0 2128 kfree(children, M_TEMP);
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MD
2129
2130 return (bus_generic_resume(dev));
2131}
2132
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2133static device_method_t pci_methods[] = {
2134 /* Device interface */
4a5a2d63 2135 DEVMETHOD(device_probe, pci_probe),
e126caf1 2136 DEVMETHOD(device_attach, pci_attach),
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MD
2137 DEVMETHOD(device_shutdown, bus_generic_shutdown),
2138 DEVMETHOD(device_suspend, bus_generic_suspend),
e126caf1 2139 DEVMETHOD(device_resume, pci_resume),
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2140
2141 /* Bus interface */
2142 DEVMETHOD(bus_print_child, pci_print_child),
2143 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
2144 DEVMETHOD(bus_read_ivar, pci_read_ivar),
2145 DEVMETHOD(bus_write_ivar, pci_write_ivar),
2146 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
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MD
2147 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
2148 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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MD
2149
2150 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
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MD
2151 DEVMETHOD(bus_set_resource, pci_set_resource),
2152 DEVMETHOD(bus_get_resource, pci_get_resource),
2153 DEVMETHOD(bus_delete_resource, pci_delete_resource),
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MD
2154 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
2155 DEVMETHOD(bus_release_resource, pci_release_resource),
2156 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
2157 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
2158 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
2159 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
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MD
2160
2161 /* PCI interface */
2162 DEVMETHOD(pci_read_config, pci_read_config_method),
2163 DEVMETHOD(pci_write_config, pci_write_config_method),
2164 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
2165 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
2166 DEVMETHOD(pci_enable_io, pci_enable_io_method),
2167 DEVMETHOD(pci_disable_io, pci_disable_io_method),
2168 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
2169 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
e126caf1 2170 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
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MD
2171
2172 { 0, 0 }
2173};
2174
3aef8050 2175driver_t pci_driver = {
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MD
2176 "pci",
2177 pci_methods,
2178 1, /* no softc */
2179};
2180
2181DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
261fa16d 2182MODULE_VERSION(pci, 1);