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[dragonfly.git] / sys / bus / pci / pci.c
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1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
638744c5 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.54 2008/09/05 10:39:36 hasso Exp $
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28 *
29 */
30
31#include "opt_bus.h"
32#include "opt_pci.h"
33
dc5a7bd2 34#include "opt_compat_oldpci.h"
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35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/malloc.h>
39#include <sys/module.h>
40#include <sys/fcntl.h>
41#include <sys/conf.h>
42#include <sys/kernel.h>
43#include <sys/queue.h>
44#include <sys/types.h>
638744c5 45#include <sys/sysctl.h>
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46#include <sys/buf.h>
47
48#include <vm/vm.h>
49#include <vm/pmap.h>
50#include <vm/vm_extern.h>
51
52#include <sys/bus.h>
984263bc 53#include <sys/rman.h>
97359a5b 54#include <machine/smp.h>
21ce0dfa 55#include "pci_cfgreg.h"
984263bc 56
dc5a7bd2 57#include <sys/pciio.h>
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58#include "pcireg.h"
59#include "pcivar.h"
22457186 60#include "pci_private.h"
984263bc 61
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62#include "pcib_if.h"
63
e126caf1 64devclass_t pci_devclass;
2581072f 65const char *pcib_owner;
dc5a7bd2 66
e9d8f4df 67static void pci_read_capabilities(device_t dev, pcicfgregs *cfg);
8c5b0f9a 68static int pcie_slotimpl(const pcicfgregs *);
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69
70struct pci_quirk {
71 u_int32_t devid; /* Vendor/device of the card */
72 int type;
3e4db402 73#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
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74 int arg1;
75 int arg2;
76};
77
78struct pci_quirk pci_quirks[] = {
79 /*
80 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
81 */
82 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
83 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
f1f0bfb2
JS
84 /* As does the Serverworks OSB4 (the SMBus mapping register) */
85 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
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86
87 { 0 }
88};
89
90/* map register information */
91#define PCI_MAPMEM 0x01 /* memory map */
92#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
93#define PCI_MAPPORT 0x04 /* port map */
94
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95static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
96u_int32_t pci_numdevs = 0;
97static u_int32_t pci_generation = 0;
98
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99SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "pci parameters");
100static int pci_do_power_nodriver = 0;
101TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
102SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
103 &pci_do_power_nodriver, 0,
104 "Place a function into D3 state when no driver attaches to it. 0 means\n\
105disable. 1 means conservatively place devices into D3 state. 2 means\n\
106agressively place devices into D3 state. 3 means put absolutely everything\n\
107in D3 state.");
108
984263bc 109device_t
c0f16abb 110pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func)
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111{
112 struct pci_devinfo *dinfo;
113
114 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
115 if ((dinfo->cfg.bus == bus) &&
116 (dinfo->cfg.slot == slot) &&
117 (dinfo->cfg.func == func)) {
118 return (dinfo->cfg.dev);
119 }
120 }
121
122 return (NULL);
123}
124
125device_t
c0f16abb 126pci_find_device(u_int16_t vendor, u_int16_t device)
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127{
128 struct pci_devinfo *dinfo;
129
130 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
131 if ((dinfo->cfg.vendor == vendor) &&
132 (dinfo->cfg.device == device)) {
133 return (dinfo->cfg.dev);
134 }
135 }
136
137 return (NULL);
138}
139
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140int
141pcie_slot_implemented(device_t dev)
142{
143 struct pci_devinfo *dinfo = device_get_ivars(dev);
144
145 return pcie_slotimpl(&dinfo->cfg);
146}
147
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148/* return base address of memory or port map */
149
150static u_int32_t
151pci_mapbase(unsigned mapreg)
152{
153 int mask = 0x03;
154 if ((mapreg & 0x01) == 0)
155 mask = 0x0f;
156 return (mapreg & ~mask);
157}
158
159/* return map type of memory or port map */
160
161static int
162pci_maptype(unsigned mapreg)
163{
164 static u_int8_t maptype[0x10] = {
165 PCI_MAPMEM, PCI_MAPPORT,
166 PCI_MAPMEM, 0,
167 PCI_MAPMEM, PCI_MAPPORT,
168 0, 0,
169 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
170 PCI_MAPMEM|PCI_MAPMEMP, 0,
171 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
172 0, 0,
173 };
174
175 return maptype[mapreg & 0x0f];
176}
177
178/* return log2 of map size decoded for memory or port map */
179
180static int
181pci_mapsize(unsigned testval)
182{
183 int ln2size;
184
185 testval = pci_mapbase(testval);
186 ln2size = 0;
187 if (testval != 0) {
188 while ((testval & 1) == 0)
189 {
190 ln2size++;
191 testval >>= 1;
192 }
193 }
194 return (ln2size);
195}
196
197/* return log2 of address range supported by map register */
198
199static int
200pci_maprange(unsigned mapreg)
201{
202 int ln2range = 0;
203 switch (mapreg & 0x07) {
204 case 0x00:
205 case 0x01:
206 case 0x05:
207 ln2range = 32;
208 break;
209 case 0x02:
210 ln2range = 20;
211 break;
212 case 0x04:
213 ln2range = 64;
214 break;
215 }
216 return (ln2range);
217}
218
219/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
220
221static void
222pci_fixancient(pcicfgregs *cfg)
223{
224 if (cfg->hdrtype != 0)
225 return;
226
227 /* PCI to PCI bridges use header type 1 */
228 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
229 cfg->hdrtype = 1;
230}
231
232/* read config data specific to header type 1 device (PCI to PCI bridge) */
233
234static void *
4a5a2d63 235pci_readppb(device_t pcib, int b, int s, int f)
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236{
237 pcih1cfgregs *p;
238
efda3bd0 239 p = kmalloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
984263bc 240
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241 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
242 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
984263bc 243
4a5a2d63 244 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
984263bc 245
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246 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
247 PCIR_IOBASEH_1, 2),
248 PCIB_READ_CONFIG(pcib, b, s, f,
249 PCIR_IOBASEL_1, 1));
250 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
251 PCIR_IOLIMITH_1, 2),
252 PCIB_READ_CONFIG(pcib, b, s, f,
253 PCIR_IOLIMITL_1, 1));
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254
255 p->membase = PCI_PPBMEMBASE (0,
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256 PCIB_READ_CONFIG(pcib, b, s, f,
257 PCIR_MEMBASE_1, 2));
984263bc 258 p->memlimit = PCI_PPBMEMLIMIT (0,
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259 PCIB_READ_CONFIG(pcib, b, s, f,
260 PCIR_MEMLIMIT_1, 2));
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261
262 p->pmembase = PCI_PPBMEMBASE (
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263 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
264 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
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265
266 p->pmemlimit = PCI_PPBMEMLIMIT (
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267 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
268 PCIR_PMLIMITH_1, 4),
269 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
270
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271 return (p);
272}
273
274/* read config data specific to header type 2 device (PCI to CardBus bridge) */
275
276static void *
4a5a2d63 277pci_readpcb(device_t pcib, int b, int s, int f)
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278{
279 pcih2cfgregs *p;
280
efda3bd0 281 p = kmalloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
984263bc 282
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283 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
284 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
984263bc 285
4a5a2d63 286 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
984263bc 287
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288 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
289 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
290 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
291 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
984263bc 292
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293 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
294 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
295 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
296 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
984263bc 297
4a5a2d63 298 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
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299 return p;
300}
301
302/* extract header type specific config data */
303
304static void
4a5a2d63 305pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
984263bc 306{
4a5a2d63 307#define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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308 switch (cfg->hdrtype) {
309 case 0:
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310 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
311 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
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312 cfg->nummaps = PCI_MAXMAPS_0;
313 break;
314 case 1:
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315 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
316 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
317 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
318 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
984263bc 319 cfg->nummaps = PCI_MAXMAPS_1;
4a5a2d63 320 cfg->hdrspec = pci_readppb(pcib, b, s, f);
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321 break;
322 case 2:
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323 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
324 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
325 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
326 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
984263bc 327 cfg->nummaps = PCI_MAXMAPS_2;
4a5a2d63 328 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
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329 break;
330 }
4a5a2d63 331#undef REG
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332}
333
334/* read configuration header into pcicfgrect structure */
335
22457186 336struct pci_devinfo *
c01b8d84 337pci_read_device(device_t pcib, int b, int s, int f, size_t size)
984263bc 338{
4a5a2d63 339#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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340
341 pcicfgregs *cfg = NULL;
342 struct pci_devinfo *devlist_entry;
343 struct devlist *devlist_head;
344
345 devlist_head = &pci_devq;
346
347 devlist_entry = NULL;
348
4a5a2d63 349 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
984263bc 350
efda3bd0 351 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
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352
353 cfg = &devlist_entry->cfg;
354
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355 cfg->bus = b;
356 cfg->slot = s;
357 cfg->func = f;
358 cfg->vendor = REG(PCIR_VENDOR, 2);
359 cfg->device = REG(PCIR_DEVICE, 2);
360 cfg->cmdreg = REG(PCIR_COMMAND, 2);
361 cfg->statreg = REG(PCIR_STATUS, 2);
362 cfg->baseclass = REG(PCIR_CLASS, 1);
363 cfg->subclass = REG(PCIR_SUBCLASS, 1);
364 cfg->progif = REG(PCIR_PROGIF, 1);
365 cfg->revid = REG(PCIR_REVID, 1);
e126caf1 366 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
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367 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
368 cfg->lattimer = REG(PCIR_LATTIMER, 1);
369 cfg->intpin = REG(PCIR_INTPIN, 1);
370 cfg->intline = REG(PCIR_INTLINE, 1);
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371
372#ifdef APIC_IO
97359a5b
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373 /*
374 * If using the APIC the intpin is probably wrong, since it
375 * is often setup by the BIOS with the PIC in mind.
376 */
984263bc
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377 if (cfg->intpin != 0) {
378 int airq;
379
380 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
381 if (airq >= 0) {
382 /* PCI specific entry found in MP table */
383 if (airq != cfg->intline) {
384 undirect_pci_irq(cfg->intline);
385 cfg->intline = airq;
386 }
387 } else {
388 /*
389 * PCI interrupts might be redirected to the
390 * ISA bus according to some MP tables. Use the
391 * same methods as used by the ISA devices
392 * devices to find the proper IOAPIC int pin.
393 */
394 airq = isa_apic_irq(cfg->intline);
395 if ((airq >= 0) && (airq != cfg->intline)) {
396 /* XXX: undirect_pci_irq() ? */
397 undirect_isa_irq(cfg->intline);
398 cfg->intline = airq;
399 }
400 }
401 }
402#endif /* APIC_IO */
403
4a5a2d63
JS
404 cfg->mingnt = REG(PCIR_MINGNT, 1);
405 cfg->maxlat = REG(PCIR_MAXLAT, 1);
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406
407 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
408 cfg->hdrtype &= ~PCIM_MFDEV;
409
410 pci_fixancient(cfg);
4a5a2d63 411 pci_hdrtypedata(pcib, b, s, f, cfg);
e9d8f4df 412 pci_read_capabilities(pcib, cfg);
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413
414 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
415
416 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
417 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
418 devlist_entry->conf.pc_sel.pc_func = cfg->func;
419 devlist_entry->conf.pc_hdr = cfg->hdrtype;
420
421 devlist_entry->conf.pc_subvendor = cfg->subvendor;
422 devlist_entry->conf.pc_subdevice = cfg->subdevice;
423 devlist_entry->conf.pc_vendor = cfg->vendor;
424 devlist_entry->conf.pc_device = cfg->device;
425
426 devlist_entry->conf.pc_class = cfg->baseclass;
427 devlist_entry->conf.pc_subclass = cfg->subclass;
428 devlist_entry->conf.pc_progif = cfg->progif;
429 devlist_entry->conf.pc_revid = cfg->revid;
430
431 pci_numdevs++;
432 pci_generation++;
433 }
434 return (devlist_entry);
435#undef REG
436}
437
1361c4cd
SZ
438static int
439pci_fixup_nextptr(int *nextptr0)
440{
441 int nextptr = *nextptr0;
442
443 /* "Next pointer" is only one byte */
444 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
445
446 if (nextptr & 0x3) {
447 /*
448 * PCI local bus spec 3.0:
449 *
450 * "... The bottom two bits of all pointers are reserved
451 * and must be implemented as 00b although software must
452 * mask them to allow for future uses of these bits ..."
453 */
454 if (bootverbose) {
455 kprintf("Illegal PCI extended capability "
456 "offset, fixup 0x%02x -> 0x%02x\n",
457 nextptr, nextptr & ~0x3);
458 }
459 nextptr &= ~0x3;
460 }
461 *nextptr0 = nextptr;
462
463 if (nextptr < 0x40) {
464 if (nextptr != 0) {
465 kprintf("Illegal PCI extended capability "
466 "offset 0x%02x", nextptr);
467 }
468 return 0;
469 }
470 return 1;
471}
472
8475d8bb
SZ
473static void
474pci_read_cap_pmgt(device_t pcib, int ptr, pcicfgregs *cfg)
475{
476#define REG(n, w) \
477 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
478
479 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
480
481 if (pmgt->pp_cap)
482 return;
483
484 pmgt->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
485 pmgt->pp_status = ptr + PCIR_POWER_STATUS;
486 pmgt->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
487 /*
488 * XXX
489 * Following way may be used to to test whether
490 * 'data' register exists:
491 * if 'data_select' register of
492 * PCIR_POWER_STATUS(bits[12,9]) is read-only
493 * then 'data' register is _not_ implemented.
494 */
495 pmgt->pp_data = 0;
496
497#undef REG
498}
499
8c5b0f9a
SZ
500static int
501pcie_slotimpl(const pcicfgregs *cfg)
b4c0a845 502{
8c5b0f9a 503 const struct pcicfg_expr *expr = &cfg->expr;
b4c0a845
SZ
504 uint16_t port_type;
505
b4c0a845
SZ
506 /*
507 * Only version 1 can be parsed currently
508 */
509 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
8c5b0f9a 510 return 0;
b4c0a845
SZ
511
512 /*
b4c0a845
SZ
513 * - Slot implemented bit is meaningful iff current port is
514 * root port or down stream port.
8c5b0f9a
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515 * - Testing for root port or down stream port is meanningful
516 * iff PCI configure has type 1 header.
b4c0a845 517 */
8c5b0f9a 518
b4c0a845 519 if (cfg->hdrtype != 1)
8c5b0f9a 520 return 0;
b4c0a845
SZ
521
522 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
8c5b0f9a
SZ
523 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT)
524 return 0;
b4c0a845
SZ
525
526 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
8c5b0f9a
SZ
527 return 0;
528
529 return 1;
530}
531
532static void
533pci_read_cap_expr(device_t pcib, int ptr, pcicfgregs *cfg)
534{
535#define REG(n, w) \
536 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
537
538 struct pcicfg_expr *expr = &cfg->expr;
539
540 expr->expr_ptr = ptr;
541 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
542
543 /*
544 * Only version 1 can be parsed currently
545 */
546 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
b4c0a845
SZ
547 return;
548
8c5b0f9a
SZ
549 /*
550 * Read slot capabilities. Slot capabilities exists iff
551 * current port's slot is implemented
552 */
553 if (pcie_slotimpl(cfg))
554 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
b4c0a845
SZ
555
556#undef REG
557}
558
984263bc 559static void
e9d8f4df 560pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
984263bc 561{
8475d8bb
SZ
562#define REG(n, w) \
563 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
564
1361c4cd 565 int nextptr, ptrptr;
984263bc 566
0c78fe3f
SZ
567 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
568 /* No capabilities */
569 return;
570 }
571
984263bc
MD
572 switch (cfg->hdrtype) {
573 case 0:
81c29ce4
SZ
574 case 1:
575 ptrptr = PCIR_CAP_PTR;
984263bc
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576 break;
577 case 2:
81c29ce4 578 ptrptr = PCIR_CAP_PTR_2;
984263bc
MD
579 break;
580 default:
0c78fe3f 581 return; /* No capabilities support */
984263bc 582 }
0c78fe3f 583 nextptr = REG(ptrptr, 1);
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584
585 /*
586 * Read capability entries.
587 */
1361c4cd
SZ
588 while (pci_fixup_nextptr(&nextptr)) {
589 int ptr = nextptr;
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590
591 /* Process this entry */
592 switch (REG(ptr, 1)) {
81c29ce4 593 case PCIY_PMG: /* PCI power management */
8475d8bb 594 pci_read_cap_pmgt(pcib, ptr, cfg);
984263bc 595 break;
c7e4e7eb
SZ
596 case PCIY_PCIX: /* PCI-X */
597 cfg->pcixcap_ptr = ptr;
598 break;
b4c0a845
SZ
599 case PCIY_EXPRESS: /* PCI Express */
600 pci_read_cap_expr(pcib, ptr, cfg);
601 break;
984263bc
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602 default:
603 break;
604 }
1361c4cd
SZ
605
606 /* Find the next entry */
607 nextptr = REG(ptr + 1, 1);
984263bc 608 }
8475d8bb 609
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610#undef REG
611}
612
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613/* free pcicfgregs structure and all depending data structures */
614
22457186 615int
984263bc
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616pci_freecfg(struct pci_devinfo *dinfo)
617{
618 struct devlist *devlist_head;
619
620 devlist_head = &pci_devq;
621
622 if (dinfo->cfg.hdrspec != NULL)
efda3bd0 623 kfree(dinfo->cfg.hdrspec, M_DEVBUF);
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624 /* XXX this hasn't been tested */
625 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
efda3bd0 626 kfree(dinfo, M_DEVBUF);
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627
628 /* increment the generation count */
629 pci_generation++;
630
631 /* we're losing one device */
632 pci_numdevs--;
633 return (0);
634}
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635
636
637/*
638 * PCI power manangement
639 */
e126caf1 640int
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641pci_set_powerstate_method(device_t dev, device_t child, int state)
642{
643 struct pci_devinfo *dinfo = device_get_ivars(child);
644 pcicfgregs *cfg = &dinfo->cfg;
1f7d9fe0 645 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
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MD
646 u_int16_t status;
647 int result;
648
1f7d9fe0
SZ
649 if (pmgt->pp_cap != 0) {
650 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2) & ~PCIM_PSTAT_DMASK;
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651 result = 0;
652 switch (state) {
653 case PCI_POWERSTATE_D0:
654 status |= PCIM_PSTAT_D0;
655 break;
656 case PCI_POWERSTATE_D1:
1f7d9fe0 657 if (pmgt->pp_cap & PCIM_PCAP_D1SUPP) {
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658 status |= PCIM_PSTAT_D1;
659 } else {
660 result = EOPNOTSUPP;
661 }
662 break;
663 case PCI_POWERSTATE_D2:
1f7d9fe0 664 if (pmgt->pp_cap & PCIM_PCAP_D2SUPP) {
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665 status |= PCIM_PSTAT_D2;
666 } else {
667 result = EOPNOTSUPP;
668 }
669 break;
670 case PCI_POWERSTATE_D3:
671 status |= PCIM_PSTAT_D3;
672 break;
673 default:
674 result = EINVAL;
675 }
676 if (result == 0)
1f7d9fe0 677 PCI_WRITE_CONFIG(dev, child, pmgt->pp_status, status, 2);
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678 } else {
679 result = ENXIO;
680 }
681 return(result);
682}
683
e126caf1 684int
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685pci_get_powerstate_method(device_t dev, device_t child)
686{
687 struct pci_devinfo *dinfo = device_get_ivars(child);
688 pcicfgregs *cfg = &dinfo->cfg;
1f7d9fe0 689 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
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690 u_int16_t status;
691 int result;
692
1f7d9fe0
SZ
693 if (pmgt->pp_cap != 0) {
694 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2);
984263bc
MD
695 switch (status & PCIM_PSTAT_DMASK) {
696 case PCIM_PSTAT_D0:
697 result = PCI_POWERSTATE_D0;
698 break;
699 case PCIM_PSTAT_D1:
700 result = PCI_POWERSTATE_D1;
701 break;
702 case PCIM_PSTAT_D2:
703 result = PCI_POWERSTATE_D2;
704 break;
705 case PCIM_PSTAT_D3:
706 result = PCI_POWERSTATE_D3;
707 break;
708 default:
709 result = PCI_POWERSTATE_UNKNOWN;
710 break;
711 }
712 } else {
713 /* No support, device is always at D0 */
714 result = PCI_POWERSTATE_D0;
715 }
716 return(result);
717}
718
719/*
720 * Some convenience functions for PCI device drivers.
721 */
722
723static __inline void
724pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
725{
726 u_int16_t command;
727
728 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
729 command |= bit;
730 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
731}
732
733static __inline void
734pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
735{
736 u_int16_t command;
737
738 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
739 command &= ~bit;
740 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
741}
742
e126caf1 743int
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744pci_enable_busmaster_method(device_t dev, device_t child)
745{
746 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 747 return(0);
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MD
748}
749
e126caf1 750int
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751pci_disable_busmaster_method(device_t dev, device_t child)
752{
753 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 754 return(0);
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MD
755}
756
e126caf1 757int
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MD
758pci_enable_io_method(device_t dev, device_t child, int space)
759{
e126caf1
MD
760 uint16_t command;
761 uint16_t bit;
762 char *error;
763
764 bit = 0;
765 error = NULL;
766
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767 switch(space) {
768 case SYS_RES_IOPORT:
e126caf1
MD
769 bit = PCIM_CMD_PORTEN;
770 error = "port";
984263bc
MD
771 break;
772 case SYS_RES_MEMORY:
e126caf1
MD
773 bit = PCIM_CMD_MEMEN;
774 error = "memory";
984263bc 775 break;
e126caf1
MD
776 default:
777 return(EINVAL);
984263bc 778 }
e126caf1
MD
779 pci_set_command_bit(dev, child, bit);
780 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
781 if (command & bit)
782 return(0);
783 device_printf(child, "failed to enable %s mapping!\n", error);
784 return(ENXIO);
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MD
785}
786
e126caf1 787int
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MD
788pci_disable_io_method(device_t dev, device_t child, int space)
789{
e126caf1
MD
790 uint16_t command;
791 uint16_t bit;
792 char *error;
793
794 bit = 0;
795 error = NULL;
796
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797 switch(space) {
798 case SYS_RES_IOPORT:
e126caf1
MD
799 bit = PCIM_CMD_PORTEN;
800 error = "port";
984263bc
MD
801 break;
802 case SYS_RES_MEMORY:
e126caf1
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803 bit = PCIM_CMD_MEMEN;
804 error = "memory";
984263bc 805 break;
e126caf1
MD
806 default:
807 return (EINVAL);
984263bc 808 }
e126caf1
MD
809 pci_clear_command_bit(dev, child, bit);
810 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
811 if (command & bit) {
812 device_printf(child, "failed to disable %s mapping!\n", error);
813 return (ENXIO);
814 }
815 return (0);
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MD
816}
817
818/*
819 * This is the user interface to PCI configuration space.
820 */
821
822static int
fef8985e 823pci_open(struct dev_open_args *ap)
984263bc 824{
fef8985e 825 if ((ap->a_oflags & FWRITE) && securelevel > 0) {
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MD
826 return EPERM;
827 }
828 return 0;
829}
830
831static int
fef8985e 832pci_close(struct dev_close_args *ap)
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MD
833{
834 return 0;
835}
836
837/*
838 * Match a single pci_conf structure against an array of pci_match_conf
839 * structures. The first argument, 'matches', is an array of num_matches
840 * pci_match_conf structures. match_buf is a pointer to the pci_conf
841 * structure that will be compared to every entry in the matches array.
842 * This function returns 1 on failure, 0 on success.
843 */
844static int
845pci_conf_match(struct pci_match_conf *matches, int num_matches,
846 struct pci_conf *match_buf)
847{
848 int i;
849
850 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
851 return(1);
852
853 for (i = 0; i < num_matches; i++) {
854 /*
855 * I'm not sure why someone would do this...but...
856 */
857 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
858 continue;
859
860 /*
861 * Look at each of the match flags. If it's set, do the
862 * comparison. If the comparison fails, we don't have a
863 * match, go on to the next item if there is one.
864 */
865 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
866 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
867 continue;
868
869 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
870 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
871 continue;
872
873 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
874 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
875 continue;
876
877 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
878 && (match_buf->pc_vendor != matches[i].pc_vendor))
879 continue;
880
881 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
882 && (match_buf->pc_device != matches[i].pc_device))
883 continue;
884
885 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
886 && (match_buf->pc_class != matches[i].pc_class))
887 continue;
888
889 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
890 && (match_buf->pd_unit != matches[i].pd_unit))
891 continue;
892
893 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
894 && (strncmp(matches[i].pd_name, match_buf->pd_name,
895 sizeof(match_buf->pd_name)) != 0))
896 continue;
897
898 return(0);
899 }
900
901 return(1);
902}
903
904/*
905 * Locate the parent of a PCI device by scanning the PCI devlist
906 * and return the entry for the parent.
907 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
908 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
909 */
910
911pcicfgregs *
912pci_devlist_get_parent(pcicfgregs *cfg)
913{
914 struct devlist *devlist_head;
915 struct pci_devinfo *dinfo;
916 pcicfgregs *bridge_cfg;
917 int i;
918
919 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
920
921 /* If the device is on PCI bus 0, look for the host */
922 if (cfg->bus == 0) {
923 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
924 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
925 bridge_cfg = &dinfo->cfg;
926 if (bridge_cfg->baseclass == PCIC_BRIDGE
927 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
928 && bridge_cfg->bus == cfg->bus) {
929 return bridge_cfg;
930 }
931 }
932 }
933
934 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
935 if (cfg->bus > 0) {
936 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
937 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
938 bridge_cfg = &dinfo->cfg;
939 if (bridge_cfg->baseclass == PCIC_BRIDGE
940 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
941 && bridge_cfg->secondarybus == cfg->bus) {
942 return bridge_cfg;
943 }
944 }
945 }
946
947 return NULL;
948}
949
950static int
fef8985e 951pci_ioctl(struct dev_ioctl_args *ap)
984263bc 952{
4a5a2d63 953 device_t pci, pcib;
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MD
954 struct pci_io *io;
955 const char *name;
956 int error;
957
fef8985e 958 if (!(ap->a_fflag & FWRITE))
984263bc
MD
959 return EPERM;
960
fef8985e 961 switch(ap->a_cmd) {
984263bc
MD
962 case PCIOCGETCONF:
963 {
964 struct pci_devinfo *dinfo;
965 struct pci_conf_io *cio;
966 struct devlist *devlist_head;
967 struct pci_match_conf *pattern_buf;
968 int num_patterns;
969 size_t iolen;
970 int ionum, i;
971
fef8985e 972 cio = (struct pci_conf_io *)ap->a_data;
984263bc
MD
973
974 num_patterns = 0;
975 dinfo = NULL;
976
977 /*
978 * Hopefully the user won't pass in a null pointer, but it
979 * can't hurt to check.
980 */
981 if (cio == NULL) {
982 error = EINVAL;
983 break;
984 }
985
986 /*
987 * If the user specified an offset into the device list,
988 * but the list has changed since they last called this
989 * ioctl, tell them that the list has changed. They will
990 * have to get the list from the beginning.
991 */
992 if ((cio->offset != 0)
993 && (cio->generation != pci_generation)){
994 cio->num_matches = 0;
995 cio->status = PCI_GETCONF_LIST_CHANGED;
996 error = 0;
997 break;
998 }
999
1000 /*
1001 * Check to see whether the user has asked for an offset
1002 * past the end of our list.
1003 */
1004 if (cio->offset >= pci_numdevs) {
1005 cio->num_matches = 0;
1006 cio->status = PCI_GETCONF_LAST_DEVICE;
1007 error = 0;
1008 break;
1009 }
1010
1011 /* get the head of the device queue */
1012 devlist_head = &pci_devq;
1013
1014 /*
1015 * Determine how much room we have for pci_conf structures.
1016 * Round the user's buffer size down to the nearest
1017 * multiple of sizeof(struct pci_conf) in case the user
1018 * didn't specify a multiple of that size.
1019 */
1020 iolen = min(cio->match_buf_len -
1021 (cio->match_buf_len % sizeof(struct pci_conf)),
1022 pci_numdevs * sizeof(struct pci_conf));
1023
1024 /*
1025 * Since we know that iolen is a multiple of the size of
1026 * the pciconf union, it's okay to do this.
1027 */
1028 ionum = iolen / sizeof(struct pci_conf);
1029
1030 /*
1031 * If this test is true, the user wants the pci_conf
1032 * structures returned to match the supplied entries.
1033 */
1034 if ((cio->num_patterns > 0)
1035 && (cio->pat_buf_len > 0)) {
1036 /*
1037 * pat_buf_len needs to be:
1038 * num_patterns * sizeof(struct pci_match_conf)
1039 * While it is certainly possible the user just
1040 * allocated a large buffer, but set the number of
1041 * matches correctly, it is far more likely that
1042 * their kernel doesn't match the userland utility
1043 * they're using. It's also possible that the user
1044 * forgot to initialize some variables. Yes, this
1045 * may be overly picky, but I hazard to guess that
1046 * it's far more likely to just catch folks that
1047 * updated their kernel but not their userland.
1048 */
1049 if ((cio->num_patterns *
1050 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
1051 /* The user made a mistake, return an error*/
1052 cio->status = PCI_GETCONF_ERROR;
85f8e2ea 1053 kprintf("pci_ioctl: pat_buf_len %d != "
984263bc
MD
1054 "num_patterns (%d) * sizeof(struct "
1055 "pci_match_conf) (%d)\npci_ioctl: "
1056 "pat_buf_len should be = %d\n",
1057 cio->pat_buf_len, cio->num_patterns,
1058 (int)sizeof(struct pci_match_conf),
1059 (int)sizeof(struct pci_match_conf) *
1060 cio->num_patterns);
85f8e2ea 1061 kprintf("pci_ioctl: do your headers match your "
984263bc
MD
1062 "kernel?\n");
1063 cio->num_matches = 0;
1064 error = EINVAL;
1065 break;
1066 }
1067
1068 /*
1069 * Check the user's buffer to make sure it's readable.
1070 */
1071 if (!useracc((caddr_t)cio->patterns,
1072 cio->pat_buf_len, VM_PROT_READ)) {
85f8e2ea 1073 kprintf("pci_ioctl: pattern buffer %p, "
984263bc
MD
1074 "length %u isn't user accessible for"
1075 " READ\n", cio->patterns,
1076 cio->pat_buf_len);
1077 error = EACCES;
1078 break;
1079 }
1080 /*
1081 * Allocate a buffer to hold the patterns.
1082 */
efda3bd0 1083 pattern_buf = kmalloc(cio->pat_buf_len, M_TEMP,
984263bc
MD
1084 M_WAITOK);
1085 error = copyin(cio->patterns, pattern_buf,
1086 cio->pat_buf_len);
1087 if (error != 0)
1088 break;
1089 num_patterns = cio->num_patterns;
1090
1091 } else if ((cio->num_patterns > 0)
1092 || (cio->pat_buf_len > 0)) {
1093 /*
1094 * The user made a mistake, spit out an error.
1095 */
1096 cio->status = PCI_GETCONF_ERROR;
1097 cio->num_matches = 0;
85f8e2ea 1098 kprintf("pci_ioctl: invalid GETCONF arguments\n");
984263bc
MD
1099 error = EINVAL;
1100 break;
1101 } else
1102 pattern_buf = NULL;
1103
1104 /*
1105 * Make sure we can write to the match buffer.
1106 */
1107 if (!useracc((caddr_t)cio->matches,
1108 cio->match_buf_len, VM_PROT_WRITE)) {
85f8e2ea 1109 kprintf("pci_ioctl: match buffer %p, length %u "
984263bc
MD
1110 "isn't user accessible for WRITE\n",
1111 cio->matches, cio->match_buf_len);
1112 error = EACCES;
1113 break;
1114 }
1115
1116 /*
1117 * Go through the list of devices and copy out the devices
1118 * that match the user's criteria.
1119 */
1120 for (cio->num_matches = 0, error = 0, i = 0,
1121 dinfo = STAILQ_FIRST(devlist_head);
1122 (dinfo != NULL) && (cio->num_matches < ionum)
1123 && (error == 0) && (i < pci_numdevs);
1124 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
1125
1126 if (i < cio->offset)
1127 continue;
1128
1129 /* Populate pd_name and pd_unit */
1130 name = NULL;
1131 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
1132 name = device_get_name(dinfo->cfg.dev);
1133 if (name) {
1134 strncpy(dinfo->conf.pd_name, name,
1135 sizeof(dinfo->conf.pd_name));
1136 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
1137 dinfo->conf.pd_unit =
1138 device_get_unit(dinfo->cfg.dev);
1139 }
1140
1141 if ((pattern_buf == NULL) ||
1142 (pci_conf_match(pattern_buf, num_patterns,
1143 &dinfo->conf) == 0)) {
1144
1145 /*
1146 * If we've filled up the user's buffer,
1147 * break out at this point. Since we've
1148 * got a match here, we'll pick right back
1149 * up at the matching entry. We can also
1150 * tell the user that there are more matches
1151 * left.
1152 */
1153 if (cio->num_matches >= ionum)
1154 break;
1155
1156 error = copyout(&dinfo->conf,
1157 &cio->matches[cio->num_matches],
1158 sizeof(struct pci_conf));
1159 cio->num_matches++;
1160 }
1161 }
1162
1163 /*
1164 * Set the pointer into the list, so if the user is getting
1165 * n records at a time, where n < pci_numdevs,
1166 */
1167 cio->offset = i;
1168
1169 /*
1170 * Set the generation, the user will need this if they make
1171 * another ioctl call with offset != 0.
1172 */
1173 cio->generation = pci_generation;
1174
1175 /*
1176 * If this is the last device, inform the user so he won't
1177 * bother asking for more devices. If dinfo isn't NULL, we
1178 * know that there are more matches in the list because of
1179 * the way the traversal is done.
1180 */
1181 if (dinfo == NULL)
1182 cio->status = PCI_GETCONF_LAST_DEVICE;
1183 else
1184 cio->status = PCI_GETCONF_MORE_DEVS;
1185
1186 if (pattern_buf != NULL)
efda3bd0 1187 kfree(pattern_buf, M_TEMP);
984263bc
MD
1188
1189 break;
1190 }
1191 case PCIOCREAD:
fef8985e 1192 io = (struct pci_io *)ap->a_data;
984263bc 1193 switch(io->pi_width) {
984263bc
MD
1194 case 4:
1195 case 2:
1196 case 1:
4a5a2d63
JS
1197 /*
1198 * Assume that the user-level bus number is
1199 * actually the pciN instance number. We map
1200 * from that to the real pcib+bus combination.
1201 */
1202 pci = devclass_get_device(pci_devclass,
1203 io->pi_sel.pc_bus);
1204 if (pci) {
2581072f
MD
1205 /*
1206 * pci is the pci device and may contain
1207 * several children (for each function code).
1208 * The governing pci bus is the parent to
1209 * the pci device.
1210 */
1211 int b;
1212
4a5a2d63 1213 pcib = device_get_parent(pci);
2581072f 1214 b = pcib_get_bus(pcib);
4a5a2d63
JS
1215 io->pi_data =
1216 PCIB_READ_CONFIG(pcib,
1217 b,
1218 io->pi_sel.pc_dev,
1219 io->pi_sel.pc_func,
1220 io->pi_reg,
1221 io->pi_width);
1222 error = 0;
1223 } else {
1224 error = ENODEV;
1225 }
984263bc
MD
1226 break;
1227 default:
1228 error = ENODEV;
1229 break;
1230 }
1231 break;
1232
1233 case PCIOCWRITE:
fef8985e 1234 io = (struct pci_io *)ap->a_data;
984263bc 1235 switch(io->pi_width) {
984263bc
MD
1236 case 4:
1237 case 2:
1238 case 1:
4a5a2d63
JS
1239 /*
1240 * Assume that the user-level bus number is
1241 * actually the pciN instance number. We map
1242 * from that to the real pcib+bus combination.
1243 */
1244 pci = devclass_get_device(pci_devclass,
1245 io->pi_sel.pc_bus);
1246 if (pci) {
2581072f
MD
1247 /*
1248 * pci is the pci device and may contain
1249 * several children (for each function code).
1250 * The governing pci bus is the parent to
1251 * the pci device.
1252 */
1253 int b;
1254
4a5a2d63 1255 pcib = device_get_parent(pci);
2581072f 1256 b = pcib_get_bus(pcib);
4a5a2d63
JS
1257 PCIB_WRITE_CONFIG(pcib,
1258 b,
1259 io->pi_sel.pc_dev,
1260 io->pi_sel.pc_func,
1261 io->pi_reg,
1262 io->pi_data,
1263 io->pi_width);
1264 error = 0;
1265 } else {
1266 error = ENODEV;
1267 }
984263bc
MD
1268 break;
1269 default:
1270 error = ENODEV;
1271 break;
1272 }
1273 break;
1274
1275 default:
1276 error = ENOTTY;
1277 break;
1278 }
1279
1280 return (error);
1281}
1282
1283#define PCI_CDEV 78
1284
fef8985e
MD
1285static struct dev_ops pcic_ops = {
1286 { "pci", PCI_CDEV, 0 },
1287 .d_open = pci_open,
1288 .d_close = pci_close,
1289 .d_ioctl = pci_ioctl,
984263bc
MD
1290};
1291
1292#include "pci_if.h"
1293
984263bc
MD
1294/*
1295 * New style pci driver. Parent device is either a pci-host-bridge or a
1296 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1297 */
ed1bd994
MD
1298const char *
1299pci_class_to_string(int baseclass)
1300{
1301 const char *name;
1302
1303 switch(baseclass) {
1304 case PCIC_OLD:
1305 name = "OLD";
1306 break;
1307 case PCIC_STORAGE:
1308 name = "STORAGE";
1309 break;
1310 case PCIC_NETWORK:
1311 name = "NETWORK";
1312 break;
1313 case PCIC_DISPLAY:
1314 name = "DISPLAY";
1315 break;
1316 case PCIC_MULTIMEDIA:
1317 name = "MULTIMEDIA";
1318 break;
1319 case PCIC_MEMORY:
1320 name = "MEMORY";
1321 break;
1322 case PCIC_BRIDGE:
1323 name = "BRIDGE";
1324 break;
1325 case PCIC_SIMPLECOMM:
1326 name = "SIMPLECOMM";
1327 break;
1328 case PCIC_BASEPERIPH:
1329 name = "BASEPERIPH";
1330 break;
1331 case PCIC_INPUTDEV:
1332 name = "INPUTDEV";
1333 break;
1334 case PCIC_DOCKING:
1335 name = "DOCKING";
1336 break;
1337 case PCIC_PROCESSOR:
1338 name = "PROCESSOR";
1339 break;
1340 case PCIC_SERIALBUS:
1341 name = "SERIALBUS";
1342 break;
1343 case PCIC_WIRELESS:
1344 name = "WIRELESS";
1345 break;
1346 case PCIC_I2O:
1347 name = "I20";
1348 break;
1349 case PCIC_SATELLITE:
1350 name = "SATELLITE";
1351 break;
1352 case PCIC_CRYPTO:
1353 name = "CRYPTO";
1354 break;
1355 case PCIC_SIGPROC:
1356 name = "SIGPROC";
1357 break;
1358 case PCIC_OTHER:
1359 name = "OTHER";
1360 break;
1361 default:
1362 name = "?";
1363 break;
1364 }
1365 return(name);
1366}
984263bc 1367
b4c0a845
SZ
1368static void
1369pci_print_verbose_expr(const pcicfgregs *cfg)
1370{
1371 const struct pcicfg_expr *expr = &cfg->expr;
1372 const char *port_name;
1373 uint16_t port_type;
1374
1375 if (!bootverbose)
1376 return;
1377
1378 if (expr->expr_ptr == 0) /* No PCI Express capability */
1379 return;
1380
1381 kprintf("\tPCI Express ver.%d cap=0x%04x",
1382 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
1383 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
1384 goto back;
1385
1386 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
1387
1388 switch (port_type) {
8c5b0f9a 1389 case PCIE_END_POINT:
b4c0a845
SZ
1390 port_name = "DEVICE";
1391 break;
8c5b0f9a 1392 case PCIE_LEG_END_POINT:
b4c0a845
SZ
1393 port_name = "LEGDEV";
1394 break;
8c5b0f9a 1395 case PCIE_ROOT_PORT:
b4c0a845
SZ
1396 port_name = "ROOT";
1397 break;
8c5b0f9a 1398 case PCIE_UP_STREAM_PORT:
b4c0a845
SZ
1399 port_name = "UPSTREAM";
1400 break;
8c5b0f9a 1401 case PCIE_DOWN_STREAM_PORT:
b4c0a845
SZ
1402 port_name = "DOWNSTRM";
1403 break;
8c5b0f9a 1404 case PCIE_PCIE2PCI_BRIDGE:
b4c0a845
SZ
1405 port_name = "PCIE2PCI";
1406 break;
8c5b0f9a 1407 case PCIE_PCI2PCIE_BRIDGE:
b4c0a845
SZ
1408 port_name = "PCI2PCIE";
1409 break;
1410 default:
1411 port_name = NULL;
1412 break;
1413 }
8c5b0f9a
SZ
1414 if ((port_type == PCIE_ROOT_PORT ||
1415 port_type == PCIE_DOWN_STREAM_PORT) &&
b4c0a845
SZ
1416 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
1417 port_name = NULL;
1418 if (port_name != NULL)
1419 kprintf("[%s]", port_name);
1420
8c5b0f9a 1421 if (pcie_slotimpl(cfg)) {
b4c0a845
SZ
1422 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
1423 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
1424 kprintf("[HOTPLUG]");
1425 }
1426back:
1427 kprintf("\n");
1428}
1429
22457186 1430void
984263bc
MD
1431pci_print_verbose(struct pci_devinfo *dinfo)
1432{
1433 if (bootverbose) {
1434 pcicfgregs *cfg = &dinfo->cfg;
1435
85f8e2ea 1436 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
984263bc 1437 cfg->vendor, cfg->device, cfg->revid);
85f8e2ea 1438 kprintf("\tbus=%d, slot=%d, func=%d\n",
4a5a2d63 1439 cfg->bus, cfg->slot, cfg->func);
85f8e2ea 1440 kprintf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
ed1bd994 1441 pci_class_to_string(cfg->baseclass),
984263bc
MD
1442 cfg->baseclass, cfg->subclass, cfg->progif,
1443 cfg->hdrtype, cfg->mfdev);
85f8e2ea 1444 kprintf("\tsubordinatebus=%x \tsecondarybus=%x\n",
984263bc
MD
1445 cfg->subordinatebus, cfg->secondarybus);
1446#ifdef PCI_DEBUG
85f8e2ea 1447 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
984263bc 1448 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
85f8e2ea 1449 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
984263bc
MD
1450 cfg->lattimer, cfg->lattimer * 30,
1451 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1452#endif /* PCI_DEBUG */
1453 if (cfg->intpin > 0)
85f8e2ea 1454 kprintf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
b4c0a845
SZ
1455
1456 pci_print_verbose_expr(cfg);
984263bc
MD
1457 }
1458}
1459
1460static int
4a5a2d63 1461pci_porten(device_t pcib, int b, int s, int f)
984263bc 1462{
4a5a2d63
JS
1463 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1464 & PCIM_CMD_PORTEN) != 0;
984263bc
MD
1465}
1466
1467static int
4a5a2d63 1468pci_memen(device_t pcib, int b, int s, int f)
984263bc 1469{
4a5a2d63
JS
1470 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1471 & PCIM_CMD_MEMEN) != 0;
984263bc
MD
1472}
1473
1474/*
1475 * Add a resource based on a pci map register. Return 1 if the map
1476 * register is a 32bit map register or 2 if it is a 64bit register.
1477 */
1478static int
4a5a2d63
JS
1479pci_add_map(device_t pcib, int b, int s, int f, int reg,
1480 struct resource_list *rl)
984263bc 1481{
984263bc
MD
1482 u_int32_t map;
1483 u_int64_t base;
1484 u_int8_t ln2size;
1485 u_int8_t ln2range;
1486 u_int32_t testval;
4a5a2d63
JS
1487
1488
1489#ifdef PCI_ENABLE_IO_MODES
1490 u_int16_t cmd;
1491#endif
984263bc
MD
1492 int type;
1493
4a5a2d63 1494 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
984263bc
MD
1495
1496 if (map == 0 || map == 0xffffffff)
1497 return 1; /* skip invalid entry */
1498
4a5a2d63
JS
1499 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1500 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1501 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
984263bc
MD
1502
1503 base = pci_mapbase(map);
1504 if (pci_maptype(map) & PCI_MAPMEM)
1505 type = SYS_RES_MEMORY;
1506 else
1507 type = SYS_RES_IOPORT;
1508 ln2size = pci_mapsize(testval);
1509 ln2range = pci_maprange(testval);
1510 if (ln2range == 64) {
1511 /* Read the other half of a 64bit map register */
4a5a2d63 1512 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
984263bc
MD
1513 }
1514
984263bc
MD
1515 /*
1516 * This code theoretically does the right thing, but has
1517 * undesirable side effects in some cases where
1518 * peripherals respond oddly to having these bits
1519 * enabled. Leave them alone by default.
1520 */
1521#ifdef PCI_ENABLE_IO_MODES
4a5a2d63
JS
1522 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1523 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1524 cmd |= PCIM_CMD_PORTEN;
1525 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc 1526 }
4a5a2d63
JS
1527 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1528 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1529 cmd |= PCIM_CMD_MEMEN;
1530 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc
MD
1531 }
1532#else
4a5a2d63 1533 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
984263bc 1534 return 1;
4a5a2d63 1535 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
984263bc
MD
1536 return 1;
1537#endif
1538
1539 resource_list_add(rl, type, reg,
1540 base, base + (1 << ln2size) - 1,
1541 (1 << ln2size));
1542
1543 if (bootverbose) {
85f8e2ea 1544 kprintf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
984263bc
MD
1545 reg, pci_maptype(base), ln2range,
1546 (unsigned int) base, ln2size);
1547 }
1548
1549 return (ln2range == 64) ? 2 : 1;
1550}
1551
201eb0a7
TS
1552#ifdef PCI_MAP_FIXUP
1553/*
1554 * For ATA devices we need to decide early on what addressing mode to use.
1555 * Legacy demands that the primary and secondary ATA ports sits on the
1556 * same addresses that old ISA hardware did. This dictates that we use
1557 * those addresses and ignore the BARs if we cannot set PCI native
1558 * addressing mode.
1559 */
1560static void
1561pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, int s, int f,
1562 struct resource_list *rl)
1563{
1564 int rid, type, progif;
1565#if 0
1566 /* if this device supports PCI native addressing use it */
1567 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1568 if ((progif &0x8a) == 0x8a) {
1569 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
1570 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
85f8e2ea 1571 kprintf("Trying ATA native PCI addressing mode\n");
201eb0a7
TS
1572 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
1573 }
1574 }
1575#endif
1576 /*
1577 * Because we return any preallocated resources for lazy
1578 * allocation for PCI devices in pci_alloc_resource(), we can
1579 * allocate our legacy resources here.
1580 */
1581 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1582 type = SYS_RES_IOPORT;
1583 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
1584 pci_add_map(pcib, b, s, f, PCIR_BAR(0), rl);
1585 pci_add_map(pcib, b, s, f, PCIR_BAR(1), rl);
1586 } else {
1587 rid = PCIR_BAR(0);
1588 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
1589 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
1590 0);
1591 rid = PCIR_BAR(1);
1592 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
1593 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
1594 0);
1595 }
1596 if (progif & PCIP_STORAGE_IDE_MODESEC) {
1597 pci_add_map(pcib, b, s, f, PCIR_BAR(2), rl);
1598 pci_add_map(pcib, b, s, f, PCIR_BAR(3), rl);
1599 } else {
1600 rid = PCIR_BAR(2);
1601 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
1602 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
1603 0);
1604 rid = PCIR_BAR(3);
1605 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
1606 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
1607 0);
1608 }
1609 pci_add_map(pcib, b, s, f, PCIR_BAR(4), rl);
1610 pci_add_map(pcib, b, s, f, PCIR_BAR(5), rl);
1611}
1612#endif /* PCI_MAP_FIXUP */
1613
984263bc 1614static void
e126caf1 1615pci_add_resources(device_t pcib, device_t bus, device_t dev)
984263bc
MD
1616{
1617 struct pci_devinfo *dinfo = device_get_ivars(dev);
4a5a2d63 1618 pcicfgregs *cfg = &dinfo->cfg;
984263bc
MD
1619 struct resource_list *rl = &dinfo->resources;
1620 struct pci_quirk *q;
e126caf1
MD
1621 int b, i, f, s;
1622#if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */
1623 int irq;
1624#endif
984263bc 1625
e126caf1
MD
1626 b = cfg->bus;
1627 s = cfg->slot;
1628 f = cfg->func;
201eb0a7
TS
1629#ifdef PCI_MAP_FIXUP
1630 /* atapci devices in legacy mode need special map treatment */
1631 if ((pci_get_class(dev) == PCIC_STORAGE) &&
1632 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
d3d1ea7a
MD
1633 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
1634 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
1635 !pci_read_config(dev, PCIR_BAR(2), 4))) )
201eb0a7
TS
1636 pci_ata_maps(pcib, bus, dev, b, s, f, rl);
1637 else
1638#endif /* PCI_MAP_FIXUP */
1639 for (i = 0; i < cfg->nummaps;) {
1640 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl);
1641 }
984263bc
MD
1642
1643 for (q = &pci_quirks[0]; q->devid; q++) {
1644 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1645 && q->type == PCI_QUIRK_MAP_REG)
4a5a2d63 1646 pci_add_map(pcib, b, s, f, q->arg1, rl);
984263bc
MD
1647 }
1648
1649 if (cfg->intpin > 0 && cfg->intline != 255)
1650 resource_list_add(rl, SYS_RES_IRQ, 0,
1651 cfg->intline, cfg->intline, 1);
1652}
1653
e126caf1
MD
1654void
1655pci_add_children(device_t dev, int busno, size_t dinfo_size)
984263bc 1656{
e126caf1 1657#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
4a5a2d63 1658 device_t pcib = device_get_parent(dev);
e126caf1 1659 struct pci_devinfo *dinfo;
4a5a2d63 1660 int maxslots;
e126caf1
MD
1661 int s, f, pcifunchigh;
1662 uint8_t hdrtype;
1663
1664 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo));
984263bc 1665
4a5a2d63 1666 maxslots = PCIB_MAXSLOTS(pcib);
984263bc 1667
57e943f7 1668 for (s = 0; s <= maxslots; s++) {
e126caf1
MD
1669 pcifunchigh = 0;
1670 f = 0;
1671 hdrtype = REG(PCIR_HDRTYPE, 1);
1672 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1673 continue;
1674 if (hdrtype & PCIM_MFDEV)
1675 pcifunchigh = PCI_FUNCMAX;
5e658043 1676 for (f = 0; f <= pcifunchigh; f++) {
e126caf1 1677 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
984263bc 1678 if (dinfo != NULL) {
e126caf1 1679 pci_add_child(dev, dinfo);
984263bc
MD
1680 }
1681 }
1682 }
e126caf1
MD
1683#undef REG
1684}
1685
2581072f
MD
1686/*
1687 * The actual PCI child that we add has a NULL driver whos parent
1688 * device will be "pci". The child contains the ivars, not the parent.
1689 */
e126caf1
MD
1690void
1691pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1692{
1693 device_t pcib;
1694
1695 pcib = device_get_parent(bus);
1696 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1697 device_set_ivars(dinfo->cfg.dev, dinfo);
638744c5
HT
1698 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
1699 pci_cfg_restore(dinfo->cfg.dev, dinfo);
e126caf1
MD
1700 pci_add_resources(pcib, bus, dinfo->cfg.dev);
1701 pci_print_verbose(dinfo);
984263bc
MD
1702}
1703
c01b8d84
MD
1704/*
1705 * Probe the PCI bus. Note: probe code is not supposed to add children
1706 * or call attach.
1707 */
984263bc 1708static int
4a5a2d63 1709pci_probe(device_t dev)
984263bc 1710{
984263bc 1711 device_set_desc(dev, "PCI bus");
4a5a2d63 1712
c01b8d84
MD
1713 /* Allow other subclasses to override this driver */
1714 return(-1000);
984263bc
MD
1715}
1716
e126caf1
MD
1717static int
1718pci_attach(device_t dev)
1719{
1720 int busno;
e4c9c0c8
MD
1721 int lunit = device_get_unit(dev);
1722
fef8985e
MD
1723 dev_ops_add(&pcic_ops, -1, lunit);
1724 make_dev(&pcic_ops, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit);
e126caf1
MD
1725
1726 /*
1727 * Since there can be multiple independantly numbered PCI
1728 * busses on some large alpha systems, we can't use the unit
1729 * number to decide what bus we are probing. We ask the parent
1730 * pcib what our bus number is.
2581072f
MD
1731 *
1732 * pcib_get_bus() must act on the pci bus device, not on the pci
1733 * device, because it uses badly hacked nexus-based ivars to
1734 * store and retrieve the physical bus number. XXX
e126caf1 1735 */
2581072f 1736 busno = pcib_get_bus(device_get_parent(dev));
e126caf1 1737 if (bootverbose)
ed1bd994 1738 device_printf(dev, "pci_attach() physical bus=%d\n", busno);
e126caf1
MD
1739
1740 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1741
1742 return (bus_generic_attach(dev));
1743}
1744
984263bc
MD
1745static int
1746pci_print_resources(struct resource_list *rl, const char *name, int type,
1747 const char *format)
1748{
1749 struct resource_list_entry *rle;
1750 int printed, retval;
1751
1752 printed = 0;
1753 retval = 0;
1754 /* Yes, this is kinda cheating */
1755 SLIST_FOREACH(rle, rl, link) {
1756 if (rle->type == type) {
1757 if (printed == 0)
85f8e2ea 1758 retval += kprintf(" %s ", name);
984263bc 1759 else if (printed > 0)
85f8e2ea 1760 retval += kprintf(",");
984263bc 1761 printed++;
85f8e2ea 1762 retval += kprintf(format, rle->start);
984263bc 1763 if (rle->count > 1) {
85f8e2ea
SW
1764 retval += kprintf("-");
1765 retval += kprintf(format, rle->start +
984263bc
MD
1766 rle->count - 1);
1767 }
1768 }
1769 }
1770 return retval;
1771}
1772
e126caf1 1773int
984263bc
MD
1774pci_print_child(device_t dev, device_t child)
1775{
1776 struct pci_devinfo *dinfo;
1777 struct resource_list *rl;
1778 pcicfgregs *cfg;
1779 int retval = 0;
1780
1781 dinfo = device_get_ivars(child);
1782 cfg = &dinfo->cfg;
1783 rl = &dinfo->resources;
1784
1785 retval += bus_print_child_header(dev, child);
1786
1787 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1788 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1789 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1790 if (device_get_flags(dev))
85f8e2ea 1791 retval += kprintf(" flags %#x", device_get_flags(dev));
984263bc 1792
85f8e2ea 1793 retval += kprintf(" at device %d.%d", pci_get_slot(child),
984263bc
MD
1794 pci_get_function(child));
1795
1796 retval += bus_print_child_footer(dev, child);
1797
1798 return (retval);
1799}
1800
e126caf1 1801void
984263bc
MD
1802pci_probe_nomatch(device_t dev, device_t child)
1803{
1804 struct pci_devinfo *dinfo;
1805 pcicfgregs *cfg;
1806 const char *desc;
1807 int unknown;
1808
1809 unknown = 0;
1810 dinfo = device_get_ivars(child);
1811 cfg = &dinfo->cfg;
1812 desc = pci_ata_match(child);
1813 if (!desc) desc = pci_usb_match(child);
1814 if (!desc) desc = pci_vga_match(child);
27c23c6b 1815 if (!desc) desc = pci_chip_match(child);
984263bc
MD
1816 if (!desc) {
1817 desc = "unknown card";
1818 unknown++;
1819 }
1820 device_printf(dev, "<%s>", desc);
1821 if (bootverbose || unknown) {
85f8e2ea 1822 kprintf(" (vendor=0x%04x, dev=0x%04x)",
984263bc
MD
1823 cfg->vendor,
1824 cfg->device);
1825 }
85f8e2ea 1826 kprintf(" at %d.%d",
984263bc
MD
1827 pci_get_slot(child),
1828 pci_get_function(child));
1829 if (cfg->intpin > 0 && cfg->intline != 255) {
85f8e2ea 1830 kprintf(" irq %d", cfg->intline);
984263bc 1831 }
85f8e2ea 1832 kprintf("\n");
638744c5 1833 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
984263bc
MD
1834
1835 return;
1836}
1837
22457186 1838int
4a5a2d63 1839pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
984263bc
MD
1840{
1841 struct pci_devinfo *dinfo;
1842 pcicfgregs *cfg;
1843
1844 dinfo = device_get_ivars(child);
1845 cfg = &dinfo->cfg;
1846
1847 switch (which) {
1848 case PCI_IVAR_SUBVENDOR:
1849 *result = cfg->subvendor;
1850 break;
1851 case PCI_IVAR_SUBDEVICE:
1852 *result = cfg->subdevice;
1853 break;
1854 case PCI_IVAR_VENDOR:
1855 *result = cfg->vendor;
1856 break;
1857 case PCI_IVAR_DEVICE:
1858 *result = cfg->device;
1859 break;
1860 case PCI_IVAR_DEVID:
1861 *result = (cfg->device << 16) | cfg->vendor;
1862 break;
1863 case PCI_IVAR_CLASS:
1864 *result = cfg->baseclass;
1865 break;
1866 case PCI_IVAR_SUBCLASS:
1867 *result = cfg->subclass;
1868 break;
1869 case PCI_IVAR_PROGIF:
1870 *result = cfg->progif;
1871 break;
1872 case PCI_IVAR_REVID:
1873 *result = cfg->revid;
1874 break;
1875 case PCI_IVAR_INTPIN:
1876 *result = cfg->intpin;
1877 break;
1878 case PCI_IVAR_IRQ:
1879 *result = cfg->intline;
1880 break;
1881 case PCI_IVAR_BUS:
1882 *result = cfg->bus;
1883 break;
1884 case PCI_IVAR_SLOT:
1885 *result = cfg->slot;
1886 break;
1887 case PCI_IVAR_FUNCTION:
1888 *result = cfg->func;
1889 break;
1890 case PCI_IVAR_SECONDARYBUS:
1891 *result = cfg->secondarybus;
1892 break;
1893 case PCI_IVAR_SUBORDINATEBUS:
1894 *result = cfg->subordinatebus;
1895 break;
f72d3d23
JS
1896 case PCI_IVAR_ETHADDR:
1897 /*
1898 * The generic accessor doesn't deal with failure, so
1899 * we set the return value, then return an error.
1900 */
3641b7ca 1901 *result = 0;
f72d3d23 1902 return (EINVAL);
c7e4e7eb
SZ
1903 case PCI_IVAR_PCIXCAP_PTR:
1904 *result = cfg->pcixcap_ptr;
1905 break;
1906 case PCI_IVAR_PCIECAP_PTR:
1907 *result = cfg->expr.expr_ptr;
1908 break;
984263bc
MD
1909 default:
1910 return ENOENT;
1911 }
1912 return 0;
1913}
1914
22457186 1915int
984263bc
MD
1916pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1917{
1918 struct pci_devinfo *dinfo;
1919 pcicfgregs *cfg;
1920
1921 dinfo = device_get_ivars(child);
1922 cfg = &dinfo->cfg;
1923
1924 switch (which) {
1925 case PCI_IVAR_SUBVENDOR:
1926 case PCI_IVAR_SUBDEVICE:
1927 case PCI_IVAR_VENDOR:
1928 case PCI_IVAR_DEVICE:
1929 case PCI_IVAR_DEVID:
1930 case PCI_IVAR_CLASS:
1931 case PCI_IVAR_SUBCLASS:
1932 case PCI_IVAR_PROGIF:
1933 case PCI_IVAR_REVID:
1934 case PCI_IVAR_INTPIN:
1935 case PCI_IVAR_IRQ:
1936 case PCI_IVAR_BUS:
1937 case PCI_IVAR_SLOT:
1938 case PCI_IVAR_FUNCTION:
f72d3d23 1939 case PCI_IVAR_ETHADDR:
c7e4e7eb
SZ
1940 case PCI_IVAR_PCIXCAP_PTR:
1941 case PCI_IVAR_PCIECAP_PTR:
984263bc
MD
1942 return EINVAL; /* disallow for now */
1943
1944 case PCI_IVAR_SECONDARYBUS:
1945 cfg->secondarybus = value;
1946 break;
1947 case PCI_IVAR_SUBORDINATEBUS:
1948 cfg->subordinatebus = value;
1949 break;
1950 default:
1951 return ENOENT;
1952 }
1953 return 0;
1954}
1955
201eb0a7
TS
1956#ifdef PCI_MAP_FIXUP
1957static struct resource *
1958pci_alloc_map(device_t dev, device_t child, int type, int *rid, u_long start,
1959 u_long end, u_long count, u_int flags)
1960{
1961 struct pci_devinfo *dinfo = device_get_ivars(child);
1962 struct resource_list *rl = &dinfo->resources;
1963 struct resource_list_entry *rle;
1964 struct resource *res;
1965 uint32_t map, testval;
1966 int mapsize;
1967
1968 /*
1969 * Weed out the bogons, and figure out how large the BAR/map
1970 * is. BARs that read back 0 here are bogus and unimplemented.
1971 *
1972 * Note: atapci in legacy mode are special and handled elsewhere
1973 * in the code. If you have an atapci device in legacy mode and
1974 * it fails here, that other code is broken.
1975 */
1976 res = NULL;
1977 map = pci_read_config(child, *rid, 4);
1978 pci_write_config(child, *rid, 0xffffffff, 4);
1979 testval = pci_read_config(child, *rid, 4);
1980 if (pci_mapbase(testval) == 0)
1981 goto out;
1982 if (pci_maptype(testval) & PCI_MAPMEM) {
1983 if (type != SYS_RES_MEMORY) {
1984 if (bootverbose)
1985 device_printf(dev, "child %s requested type %d"
1986 " for rid %#x, but the BAR says "
1987 "it is a memio\n",
1988 device_get_nameunit(child), type,
1989 *rid);
1990 goto out;
1991 }
1992 } else {
1993 if (type != SYS_RES_IOPORT) {
1994 if (bootverbose)
1995 device_printf(dev, "child %s requested type %d"
1996 " for rid %#x, but the BAR says "
1997 "it is an ioport\n",
1998 device_get_nameunit(child), type,
1999 *rid);
2000 goto out;
2001 }
2002 }
2003 /*
2004 * For real BARs, we need to override the size that
2005 * the driver requests, because that's what the BAR
2006 * actually uses and we would otherwise have a
2007 * situation where we might allocate the excess to
2008 * another driver, which won't work.
2009 */
2010 mapsize = pci_mapsize(testval);
2011 count = 1 << mapsize;
2012 if (RF_ALIGNMENT(flags) < mapsize)
2013 flags = (flags & ~RF_ALIGNMENT_MASK) |
2014 RF_ALIGNMENT_LOG2(mapsize);
2015 /*
2016 * Allocate enough resource, and then write back the
2017 * appropriate BAR for that resource.
2018 */
2019 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
2020 start, end, count, flags);
2021 if (res == NULL) {
2022 device_printf(child, "%#lx bytes at rid %#x res %d failed "
2023 "(%#lx, %#lx)\n", count, *rid, type, start, end);
2024 goto out;
2025 }
2026 resource_list_add(rl, type, *rid, start, end, count);
2027 rle = resource_list_find(rl, type, *rid);
2028 if (rle == NULL)
2029 panic("pci_alloc_map: unexpectedly can't find resource.");
2030 rle->res = res;
2031 rle->start = rman_get_start(res);
2032 rle->end = rman_get_end(res);
2033 rle->count = count;
2034 if (bootverbose)
2035 device_printf(child, "lazy allocation of %#lx bytes rid %#x "
2036 "type %d at %#lx\n", count, *rid, type,
2037 rman_get_start(res));
2038 map = rman_get_start(res);
2039out:;
2040 pci_write_config(child, *rid, map, 4);
2041 return res;
2042}
2043#endif /* PCI_MAP_FIXUP */
2044
261fa16d 2045struct resource *
984263bc
MD
2046pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
2047 u_long start, u_long end, u_long count, u_int flags)
2048{
2049 struct pci_devinfo *dinfo = device_get_ivars(child);
2050 struct resource_list *rl = &dinfo->resources;
201eb0a7
TS
2051#ifdef PCI_MAP_FIXUP
2052 struct resource_list_entry *rle;
2053#endif /* PCI_MAP_FIXUP */
984263bc 2054 pcicfgregs *cfg = &dinfo->cfg;
de67e43b 2055
984263bc
MD
2056 /*
2057 * Perform lazy resource allocation
984263bc
MD
2058 */
2059 if (device_get_parent(child) == dev) {
de67e43b
JS
2060 switch (type) {
2061 case SYS_RES_IRQ:
2062#ifdef __i386__
984263bc
MD
2063 /*
2064 * If device doesn't have an interrupt routed, and is
2065 * deserving of an interrupt, try to assign it one.
2066 */
de67e43b
JS
2067 if ((cfg->intline == 255 || cfg->intline == 0) &&
2068 (cfg->intpin != 0) &&
2069 (start == 0) && (end == ~0UL)) {
2070 cfg->intline = PCIB_ROUTE_INTERRUPT(
2071 device_get_parent(dev), child,
2072 cfg->intpin);
2073 if (cfg->intline != 255) {
2074 pci_write_config(child, PCIR_INTLINE,
2075 cfg->intline, 1);
2076 resource_list_add(rl, SYS_RES_IRQ, 0,
2077 cfg->intline, cfg->intline, 1);
2078 }
2079 }
820c1612 2080 break;
de67e43b
JS
2081#endif
2082 case SYS_RES_IOPORT:
201eb0a7 2083 /* FALLTHROUGH */
de67e43b
JS
2084 case SYS_RES_MEMORY:
2085 if (*rid < PCIR_BAR(cfg->nummaps)) {
2086 /*
2087 * Enable the I/O mode. We should
2088 * also be assigning resources too
2089 * when none are present. The
2090 * resource_list_alloc kind of sorta does
2091 * this...
2092 */
2093 if (PCI_ENABLE_IO(dev, child, type))
2094 return (NULL);
984263bc 2095 }
201eb0a7
TS
2096#ifdef PCI_MAP_FIXUP
2097 rle = resource_list_find(rl, type, *rid);
2098 if (rle == NULL)
2099 return pci_alloc_map(dev, child, type, rid,
2100 start, end, count, flags);
2101#endif /* PCI_MAP_FIXUP */
820c1612 2102 break;
984263bc 2103 }
201eb0a7
TS
2104#ifdef PCI_MAP_FIXUP
2105 /*
2106 * If we've already allocated the resource, then
2107 * return it now. But first we may need to activate
2108 * it, since we don't allocate the resource as active
2109 * above. Normally this would be done down in the
2110 * nexus, but since we short-circuit that path we have
2111 * to do its job here. Not sure if we should free the
2112 * resource if it fails to activate.
2113 *
2114 * Note: this also finds and returns resources for
2115 * atapci devices in legacy mode as allocated in
2116 * pci_ata_maps().
2117 */
2118 rle = resource_list_find(rl, type, *rid);
2119 if (rle != NULL && rle->res != NULL) {
2120 if (bootverbose)
2121 device_printf(child, "reserved %#lx bytes for "
2122 "rid %#x type %d at %#lx\n",
2123 rman_get_size(rle->res), *rid,
2124 type, rman_get_start(rle->res));
2125 if ((flags & RF_ACTIVE) &&
2126 bus_generic_activate_resource(dev, child, type,
2127 *rid, rle->res) != 0)
2128 return NULL;
2129 return rle->res;
2130 }
2131#endif /* PCI_MAP_FIXUP */
984263bc 2132 }
984263bc
MD
2133 return resource_list_alloc(rl, dev, child, type, rid,
2134 start, end, count, flags);
2135}
2136
2137static int
2138pci_release_resource(device_t dev, device_t child, int type, int rid,
2139 struct resource *r)
2140{
2141 struct pci_devinfo *dinfo = device_get_ivars(child);
2142 struct resource_list *rl = &dinfo->resources;
2143
2144 return resource_list_release(rl, dev, child, type, rid, r);
2145}
2146
2147static int
2148pci_set_resource(device_t dev, device_t child, int type, int rid,
2149 u_long start, u_long count)
2150{
2151 struct pci_devinfo *dinfo = device_get_ivars(child);
2152 struct resource_list *rl = &dinfo->resources;
2153
2154 resource_list_add(rl, type, rid, start, start + count - 1, count);
2155 return 0;
2156}
2157
2158static int
2159pci_get_resource(device_t dev, device_t child, int type, int rid,
2160 u_long *startp, u_long *countp)
2161{
2162 struct pci_devinfo *dinfo = device_get_ivars(child);
2163 struct resource_list *rl = &dinfo->resources;
2164 struct resource_list_entry *rle;
2165
2166 rle = resource_list_find(rl, type, rid);
2167 if (!rle)
2168 return ENOENT;
2169
2170 if (startp)
2171 *startp = rle->start;
2172 if (countp)
2173 *countp = rle->count;
2174
2175 return 0;
2176}
2177
e126caf1 2178void
984263bc
MD
2179pci_delete_resource(device_t dev, device_t child, int type, int rid)
2180{
85f8e2ea 2181 kprintf("pci_delete_resource: PCI resources can not be deleted\n");
984263bc
MD
2182}
2183
e126caf1
MD
2184struct resource_list *
2185pci_get_resource_list (device_t dev, device_t child)
2186{
b0486c83 2187 struct pci_devinfo *dinfo = device_get_ivars(child);
e126caf1 2188
b0486c83 2189 if (dinfo == NULL)
e126caf1 2190 return (NULL);
b0486c83 2191 return (&dinfo->resources);
e126caf1
MD
2192}
2193
2194u_int32_t
984263bc
MD
2195pci_read_config_method(device_t dev, device_t child, int reg, int width)
2196{
2197 struct pci_devinfo *dinfo = device_get_ivars(child);
2198 pcicfgregs *cfg = &dinfo->cfg;
4a5a2d63
JS
2199
2200 return PCIB_READ_CONFIG(device_get_parent(dev),
2201 cfg->bus, cfg->slot, cfg->func,
2202 reg, width);
984263bc
MD
2203}
2204
e126caf1 2205void
984263bc
MD
2206pci_write_config_method(device_t dev, device_t child, int reg,
2207 u_int32_t val, int width)
2208{
2209 struct pci_devinfo *dinfo = device_get_ivars(child);
2210 pcicfgregs *cfg = &dinfo->cfg;
4a5a2d63
JS
2211
2212 PCIB_WRITE_CONFIG(device_get_parent(dev),
2213 cfg->bus, cfg->slot, cfg->func,
2214 reg, val, width);
984263bc
MD
2215}
2216
e126caf1
MD
2217int
2218pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
2219 size_t buflen)
2220{
2221 struct pci_devinfo *dinfo;
2222
2223 dinfo = device_get_ivars(child);
f8c7a42d 2224 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
e126caf1
MD
2225 pci_get_function(child));
2226 return (0);
2227}
2228
2229int
2230pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
2231 size_t buflen)
2232{
2233 struct pci_devinfo *dinfo;
2234 pcicfgregs *cfg;
2235
2236 dinfo = device_get_ivars(child);
2237 cfg = &dinfo->cfg;
f8c7a42d 2238 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
e126caf1
MD
2239 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
2240 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
2241 cfg->progif);
2242 return (0);
2243}
2244
2245int
2246pci_assign_interrupt_method(device_t dev, device_t child)
2247{
2248 struct pci_devinfo *dinfo = device_get_ivars(child);
2249 pcicfgregs *cfg = &dinfo->cfg;
2250
2251 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
2252 cfg->intpin));
2253}
2254
984263bc
MD
2255static int
2256pci_modevent(module_t mod, int what, void *arg)
2257{
2258 switch (what) {
2259 case MOD_LOAD:
2260 STAILQ_INIT(&pci_devq);
2261 break;
984263bc
MD
2262 case MOD_UNLOAD:
2263 break;
2264 }
2265
2266 return 0;
2267}
2268
638744c5
HT
2269void
2270pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
2271{
2272 int i;
2273
2274 /*
2275 * Only do header type 0 devices. Type 1 devices are bridges,
2276 * which we know need special treatment. Type 2 devices are
2277 * cardbus bridges which also require special treatment.
2278 * Other types are unknown, and we err on the side of safety
2279 * by ignoring them.
2280 */
2281 if (dinfo->cfg.hdrtype != 0)
2282 return;
2283
2284 /*
2285 * Restore the device to full power mode. We must do this
2286 * before we restore the registers because moving from D3 to
2287 * D0 will cause the chip's BARs and some other registers to
2288 * be reset to some unknown power on reset values. Cut down
2289 * the noise on boot by doing nothing if we are already in
2290 * state D0.
2291 */
2292 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
2293 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
2294 }
2295 for (i = 0; i < dinfo->cfg.nummaps; i++)
2296 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
2297 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
2298 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
2299 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
2300 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
2301 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
2302 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
2303 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
2304 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
2305 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
2306 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
2307#if 0
2308 /* Restore MSI and MSI-X configurations if they are present. */
2309 if (dinfo->cfg.msi.msi_location != 0)
2310 pci_resume_msi(dev);
2311 if (dinfo->cfg.msix.msix_location != 0)
2312 pci_resume_msix(dev);
2313#endif
2314}
2315
2316void
2317pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
2318{
2319 int i;
2320 uint32_t cls;
2321 int ps;
2322
2323 /*
2324 * Only do header type 0 devices. Type 1 devices are bridges, which
2325 * we know need special treatment. Type 2 devices are cardbus bridges
2326 * which also require special treatment. Other types are unknown, and
2327 * we err on the side of safety by ignoring them. Powering down
2328 * bridges should not be undertaken lightly.
2329 */
2330 if (dinfo->cfg.hdrtype != 0)
2331 return;
2332 for (i = 0; i < dinfo->cfg.nummaps; i++)
2333 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
2334 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
2335
2336 /*
2337 * Some drivers apparently write to these registers w/o updating our
2338 * cached copy. No harm happens if we update the copy, so do so here
2339 * so we can restore them. The COMMAND register is modified by the
2340 * bus w/o updating the cache. This should represent the normally
2341 * writable portion of the 'defined' part of type 0 headers. In
2342 * theory we also need to save/restore the PCI capability structures
2343 * we know about, but apart from power we don't know any that are
2344 * writable.
2345 */
2346 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
2347 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
2348 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
2349 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
2350 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
2351 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
2352 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
2353 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
2354 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
2355 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2356 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2357 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
2358 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
2359 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
2360 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
2361
2362 /*
2363 * don't set the state for display devices, base peripherals and
2364 * memory devices since bad things happen when they are powered down.
2365 * We should (a) have drivers that can easily detach and (b) use
2366 * generic drivers for these devices so that some device actually
2367 * attaches. We need to make sure that when we implement (a) we don't
2368 * power the device down on a reattach.
2369 */
2370 cls = pci_get_class(dev);
2371 if (!setstate)
2372 return;
2373
2374 switch (pci_do_power_nodriver)
2375 {
2376 case 0: /* NO powerdown at all */
2377 return;
2378 case 1: /* Conservative about what to power down */
2379 if (cls == PCIC_STORAGE)
2380 return;
2381 /*FALLTHROUGH*/
2382 case 2: /* Agressive about what to power down */
2383 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
2384 cls == PCIC_BASEPERIPH)
2385 return;
2386 /*FALLTHROUGH*/
2387 case 3: /* Power down everything */
2388 break;
2389 }
2390
2391 if (cls == PCIC_STORAGE)
2392 return;
2393
2394 /*
2395 * PCI spec says we can only go into D3 state from D0 state.
2396 * Transition from D[12] into D0 before going to D3 state.
2397 */
2398 ps = pci_get_powerstate(dev);
2399 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
2400 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
2401 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
2402 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
2403}
2404
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2405int
2406pci_resume(device_t dev)
2407{
2408 int numdevs;
2409 int i;
2410 device_t *children;
2411 device_t child;
2412 struct pci_devinfo *dinfo;
2413 pcicfgregs *cfg;
2414
2415 device_get_children(dev, &children, &numdevs);
2416
2417 for (i = 0; i < numdevs; i++) {
2418 child = children[i];
2419
2420 dinfo = device_get_ivars(child);
2421 cfg = &dinfo->cfg;
2422 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2423 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
2424 if (PCI_INTERRUPT_VALID(cfg->intline)) {
2425 pci_write_config(child, PCIR_INTLINE,
2426 cfg->intline, 1);
2427 }
2428 }
2429 }
2430
efda3bd0 2431 kfree(children, M_TEMP);
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MD
2432
2433 return (bus_generic_resume(dev));
2434}
2435
638744c5
HT
2436void
2437pci_driver_added(device_t dev, driver_t *driver)
2438{
2439 int numdevs;
2440 device_t *devlist;
2441 device_t child;
2442 struct pci_devinfo *dinfo;
2443 int i;
2444
2445 if (bootverbose)
2446 device_printf(dev, "driver added\n");
2447 DEVICE_IDENTIFY(driver, dev);
2448 device_get_children(dev, &devlist, &numdevs);
2449 for (i = 0; i < numdevs; i++) {
2450 child = devlist[i];
2451 if (device_get_state(child) != DS_NOTPRESENT)
2452 continue;
2453 dinfo = device_get_ivars(child);
2454 pci_print_verbose(dinfo);
2455 if (bootverbose)
2456 kprintf("pci%d:%d:%d: reprobing on driver added\n",
2457 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func);
2458 pci_cfg_restore(child, dinfo);
2459 if (device_probe_and_attach(child) != 0)
2460 pci_cfg_save(child, dinfo, 1);
2461 }
2462 kfree(devlist, M_TEMP);
2463}
2464
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2465static device_method_t pci_methods[] = {
2466 /* Device interface */
4a5a2d63 2467 DEVMETHOD(device_probe, pci_probe),
e126caf1 2468 DEVMETHOD(device_attach, pci_attach),
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2469 DEVMETHOD(device_shutdown, bus_generic_shutdown),
2470 DEVMETHOD(device_suspend, bus_generic_suspend),
e126caf1 2471 DEVMETHOD(device_resume, pci_resume),
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2472
2473 /* Bus interface */
2474 DEVMETHOD(bus_print_child, pci_print_child),
2475 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
2476 DEVMETHOD(bus_read_ivar, pci_read_ivar),
2477 DEVMETHOD(bus_write_ivar, pci_write_ivar),
638744c5 2478 DEVMETHOD(bus_driver_added, pci_driver_added),
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MD
2479 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
2480 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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2481
2482 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
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2483 DEVMETHOD(bus_set_resource, pci_set_resource),
2484 DEVMETHOD(bus_get_resource, pci_get_resource),
2485 DEVMETHOD(bus_delete_resource, pci_delete_resource),
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MD
2486 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
2487 DEVMETHOD(bus_release_resource, pci_release_resource),
2488 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
2489 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
2490 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
2491 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
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MD
2492
2493 /* PCI interface */
2494 DEVMETHOD(pci_read_config, pci_read_config_method),
2495 DEVMETHOD(pci_write_config, pci_write_config_method),
2496 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
2497 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
2498 DEVMETHOD(pci_enable_io, pci_enable_io_method),
2499 DEVMETHOD(pci_disable_io, pci_disable_io_method),
2500 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
2501 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
e126caf1 2502 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
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MD
2503
2504 { 0, 0 }
2505};
2506
3aef8050 2507driver_t pci_driver = {
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MD
2508 "pci",
2509 pci_methods,
2510 1, /* no softc */
2511};
2512
2513DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
261fa16d 2514MODULE_VERSION(pci, 1);