Add m_devpad() to avoid code duplication in various network device drivers
[dragonfly.git] / sys / bus / pci / pci.c
CommitLineData
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1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
72876ce0 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.56 2008/09/08 10:16:23 hasso Exp $
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28 *
29 */
30
31#include "opt_bus.h"
32#include "opt_pci.h"
33
dc5a7bd2 34#include "opt_compat_oldpci.h"
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35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/malloc.h>
39#include <sys/module.h>
40#include <sys/fcntl.h>
41#include <sys/conf.h>
42#include <sys/kernel.h>
43#include <sys/queue.h>
44#include <sys/types.h>
638744c5 45#include <sys/sysctl.h>
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46#include <sys/buf.h>
47
48#include <vm/vm.h>
49#include <vm/pmap.h>
50#include <vm/vm_extern.h>
51
52#include <sys/bus.h>
984263bc 53#include <sys/rman.h>
97359a5b 54#include <machine/smp.h>
21ce0dfa 55#include "pci_cfgreg.h"
984263bc 56
dc5a7bd2 57#include <sys/pciio.h>
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58#include "pcireg.h"
59#include "pcivar.h"
22457186 60#include "pci_private.h"
984263bc 61
4a5a2d63
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62#include "pcib_if.h"
63
e126caf1 64devclass_t pci_devclass;
2581072f 65const char *pcib_owner;
dc5a7bd2 66
e9d8f4df 67static void pci_read_capabilities(device_t dev, pcicfgregs *cfg);
8c5b0f9a 68static int pcie_slotimpl(const pcicfgregs *);
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69
70struct pci_quirk {
71 u_int32_t devid; /* Vendor/device of the card */
72 int type;
3e4db402 73#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
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74 int arg1;
75 int arg2;
76};
77
78struct pci_quirk pci_quirks[] = {
79 /*
80 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
81 */
82 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
83 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
f1f0bfb2
JS
84 /* As does the Serverworks OSB4 (the SMBus mapping register) */
85 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
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86
87 { 0 }
88};
89
90/* map register information */
91#define PCI_MAPMEM 0x01 /* memory map */
92#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
93#define PCI_MAPPORT 0x04 /* port map */
94
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95static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
96u_int32_t pci_numdevs = 0;
97static u_int32_t pci_generation = 0;
98
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99SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "pci parameters");
100static int pci_do_power_nodriver = 0;
101TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
102SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
103 &pci_do_power_nodriver, 0,
104 "Place a function into D3 state when no driver attaches to it. 0 means\n\
105disable. 1 means conservatively place devices into D3 state. 2 means\n\
106agressively place devices into D3 state. 3 means put absolutely everything\n\
107in D3 state.");
108
984263bc 109device_t
c0f16abb 110pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func)
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111{
112 struct pci_devinfo *dinfo;
113
114 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
115 if ((dinfo->cfg.bus == bus) &&
116 (dinfo->cfg.slot == slot) &&
117 (dinfo->cfg.func == func)) {
118 return (dinfo->cfg.dev);
119 }
120 }
121
122 return (NULL);
123}
124
125device_t
c0f16abb 126pci_find_device(u_int16_t vendor, u_int16_t device)
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127{
128 struct pci_devinfo *dinfo;
129
130 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
131 if ((dinfo->cfg.vendor == vendor) &&
132 (dinfo->cfg.device == device)) {
133 return (dinfo->cfg.dev);
134 }
135 }
136
137 return (NULL);
138}
139
8c5b0f9a
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140int
141pcie_slot_implemented(device_t dev)
142{
143 struct pci_devinfo *dinfo = device_get_ivars(dev);
144
145 return pcie_slotimpl(&dinfo->cfg);
146}
147
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148/* return base address of memory or port map */
149
150static u_int32_t
151pci_mapbase(unsigned mapreg)
152{
153 int mask = 0x03;
154 if ((mapreg & 0x01) == 0)
155 mask = 0x0f;
156 return (mapreg & ~mask);
157}
158
159/* return map type of memory or port map */
160
161static int
162pci_maptype(unsigned mapreg)
163{
164 static u_int8_t maptype[0x10] = {
165 PCI_MAPMEM, PCI_MAPPORT,
166 PCI_MAPMEM, 0,
167 PCI_MAPMEM, PCI_MAPPORT,
168 0, 0,
169 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
170 PCI_MAPMEM|PCI_MAPMEMP, 0,
171 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
172 0, 0,
173 };
174
175 return maptype[mapreg & 0x0f];
176}
177
178/* return log2 of map size decoded for memory or port map */
179
180static int
181pci_mapsize(unsigned testval)
182{
183 int ln2size;
184
185 testval = pci_mapbase(testval);
186 ln2size = 0;
187 if (testval != 0) {
188 while ((testval & 1) == 0)
189 {
190 ln2size++;
191 testval >>= 1;
192 }
193 }
194 return (ln2size);
195}
196
197/* return log2 of address range supported by map register */
198
199static int
200pci_maprange(unsigned mapreg)
201{
202 int ln2range = 0;
203 switch (mapreg & 0x07) {
204 case 0x00:
205 case 0x01:
206 case 0x05:
207 ln2range = 32;
208 break;
209 case 0x02:
210 ln2range = 20;
211 break;
212 case 0x04:
213 ln2range = 64;
214 break;
215 }
216 return (ln2range);
217}
218
219/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
220
221static void
222pci_fixancient(pcicfgregs *cfg)
223{
224 if (cfg->hdrtype != 0)
225 return;
226
227 /* PCI to PCI bridges use header type 1 */
228 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
229 cfg->hdrtype = 1;
230}
231
232/* read config data specific to header type 1 device (PCI to PCI bridge) */
233
234static void *
4a5a2d63 235pci_readppb(device_t pcib, int b, int s, int f)
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236{
237 pcih1cfgregs *p;
238
efda3bd0 239 p = kmalloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
984263bc 240
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241 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
242 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
984263bc 243
4a5a2d63 244 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
984263bc 245
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246 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
247 PCIR_IOBASEH_1, 2),
248 PCIB_READ_CONFIG(pcib, b, s, f,
249 PCIR_IOBASEL_1, 1));
250 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
251 PCIR_IOLIMITH_1, 2),
252 PCIB_READ_CONFIG(pcib, b, s, f,
253 PCIR_IOLIMITL_1, 1));
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254
255 p->membase = PCI_PPBMEMBASE (0,
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256 PCIB_READ_CONFIG(pcib, b, s, f,
257 PCIR_MEMBASE_1, 2));
984263bc 258 p->memlimit = PCI_PPBMEMLIMIT (0,
4a5a2d63
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259 PCIB_READ_CONFIG(pcib, b, s, f,
260 PCIR_MEMLIMIT_1, 2));
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261
262 p->pmembase = PCI_PPBMEMBASE (
4a5a2d63
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263 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
264 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
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265
266 p->pmemlimit = PCI_PPBMEMLIMIT (
4a5a2d63
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267 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
268 PCIR_PMLIMITH_1, 4),
269 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
270
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271 return (p);
272}
273
274/* read config data specific to header type 2 device (PCI to CardBus bridge) */
275
276static void *
4a5a2d63 277pci_readpcb(device_t pcib, int b, int s, int f)
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278{
279 pcih2cfgregs *p;
280
efda3bd0 281 p = kmalloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
984263bc 282
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283 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
284 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
984263bc 285
4a5a2d63 286 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
984263bc 287
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288 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
289 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
290 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
291 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
984263bc 292
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293 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
294 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
295 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
296 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
984263bc 297
4a5a2d63 298 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
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299 return p;
300}
301
302/* extract header type specific config data */
303
304static void
4a5a2d63 305pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
984263bc 306{
4a5a2d63 307#define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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308 switch (cfg->hdrtype) {
309 case 0:
4a5a2d63
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310 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
311 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
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312 cfg->nummaps = PCI_MAXMAPS_0;
313 break;
314 case 1:
4a5a2d63
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315 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
316 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
317 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
318 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
984263bc 319 cfg->nummaps = PCI_MAXMAPS_1;
4a5a2d63 320 cfg->hdrspec = pci_readppb(pcib, b, s, f);
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321 break;
322 case 2:
4a5a2d63
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323 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
324 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
325 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
326 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
984263bc 327 cfg->nummaps = PCI_MAXMAPS_2;
4a5a2d63 328 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
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329 break;
330 }
4a5a2d63 331#undef REG
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332}
333
334/* read configuration header into pcicfgrect structure */
335
22457186 336struct pci_devinfo *
c01b8d84 337pci_read_device(device_t pcib, int b, int s, int f, size_t size)
984263bc 338{
4a5a2d63 339#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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MD
340
341 pcicfgregs *cfg = NULL;
342 struct pci_devinfo *devlist_entry;
343 struct devlist *devlist_head;
344
345 devlist_head = &pci_devq;
346
347 devlist_entry = NULL;
348
4a5a2d63 349 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
984263bc 350
efda3bd0 351 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
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352
353 cfg = &devlist_entry->cfg;
354
4a5a2d63
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355 cfg->bus = b;
356 cfg->slot = s;
357 cfg->func = f;
358 cfg->vendor = REG(PCIR_VENDOR, 2);
359 cfg->device = REG(PCIR_DEVICE, 2);
360 cfg->cmdreg = REG(PCIR_COMMAND, 2);
361 cfg->statreg = REG(PCIR_STATUS, 2);
362 cfg->baseclass = REG(PCIR_CLASS, 1);
363 cfg->subclass = REG(PCIR_SUBCLASS, 1);
364 cfg->progif = REG(PCIR_PROGIF, 1);
365 cfg->revid = REG(PCIR_REVID, 1);
e126caf1 366 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
4a5a2d63
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367 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
368 cfg->lattimer = REG(PCIR_LATTIMER, 1);
369 cfg->intpin = REG(PCIR_INTPIN, 1);
370 cfg->intline = REG(PCIR_INTLINE, 1);
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371
372#ifdef APIC_IO
97359a5b
MD
373 /*
374 * If using the APIC the intpin is probably wrong, since it
375 * is often setup by the BIOS with the PIC in mind.
376 */
984263bc
MD
377 if (cfg->intpin != 0) {
378 int airq;
379
380 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
381 if (airq >= 0) {
382 /* PCI specific entry found in MP table */
383 if (airq != cfg->intline) {
384 undirect_pci_irq(cfg->intline);
385 cfg->intline = airq;
386 }
387 } else {
388 /*
389 * PCI interrupts might be redirected to the
390 * ISA bus according to some MP tables. Use the
391 * same methods as used by the ISA devices
392 * devices to find the proper IOAPIC int pin.
393 */
394 airq = isa_apic_irq(cfg->intline);
395 if ((airq >= 0) && (airq != cfg->intline)) {
396 /* XXX: undirect_pci_irq() ? */
397 undirect_isa_irq(cfg->intline);
398 cfg->intline = airq;
399 }
400 }
401 }
402#endif /* APIC_IO */
403
4a5a2d63
JS
404 cfg->mingnt = REG(PCIR_MINGNT, 1);
405 cfg->maxlat = REG(PCIR_MAXLAT, 1);
984263bc
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406
407 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
408 cfg->hdrtype &= ~PCIM_MFDEV;
409
410 pci_fixancient(cfg);
4a5a2d63 411 pci_hdrtypedata(pcib, b, s, f, cfg);
e9d8f4df 412 pci_read_capabilities(pcib, cfg);
984263bc
MD
413
414 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
415
416 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
417 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
418 devlist_entry->conf.pc_sel.pc_func = cfg->func;
419 devlist_entry->conf.pc_hdr = cfg->hdrtype;
420
421 devlist_entry->conf.pc_subvendor = cfg->subvendor;
422 devlist_entry->conf.pc_subdevice = cfg->subdevice;
423 devlist_entry->conf.pc_vendor = cfg->vendor;
424 devlist_entry->conf.pc_device = cfg->device;
425
426 devlist_entry->conf.pc_class = cfg->baseclass;
427 devlist_entry->conf.pc_subclass = cfg->subclass;
428 devlist_entry->conf.pc_progif = cfg->progif;
429 devlist_entry->conf.pc_revid = cfg->revid;
430
431 pci_numdevs++;
432 pci_generation++;
433 }
434 return (devlist_entry);
435#undef REG
436}
437
1361c4cd
SZ
438static int
439pci_fixup_nextptr(int *nextptr0)
440{
441 int nextptr = *nextptr0;
442
443 /* "Next pointer" is only one byte */
444 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
445
446 if (nextptr & 0x3) {
447 /*
448 * PCI local bus spec 3.0:
449 *
450 * "... The bottom two bits of all pointers are reserved
451 * and must be implemented as 00b although software must
452 * mask them to allow for future uses of these bits ..."
453 */
454 if (bootverbose) {
455 kprintf("Illegal PCI extended capability "
456 "offset, fixup 0x%02x -> 0x%02x\n",
457 nextptr, nextptr & ~0x3);
458 }
459 nextptr &= ~0x3;
460 }
461 *nextptr0 = nextptr;
462
463 if (nextptr < 0x40) {
464 if (nextptr != 0) {
465 kprintf("Illegal PCI extended capability "
466 "offset 0x%02x", nextptr);
467 }
468 return 0;
469 }
470 return 1;
471}
472
8475d8bb
SZ
473static void
474pci_read_cap_pmgt(device_t pcib, int ptr, pcicfgregs *cfg)
475{
476#define REG(n, w) \
477 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
478
479 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
480
481 if (pmgt->pp_cap)
482 return;
483
484 pmgt->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
485 pmgt->pp_status = ptr + PCIR_POWER_STATUS;
486 pmgt->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
487 /*
488 * XXX
489 * Following way may be used to to test whether
490 * 'data' register exists:
491 * if 'data_select' register of
492 * PCIR_POWER_STATUS(bits[12,9]) is read-only
493 * then 'data' register is _not_ implemented.
494 */
495 pmgt->pp_data = 0;
496
497#undef REG
498}
499
8c5b0f9a
SZ
500static int
501pcie_slotimpl(const pcicfgregs *cfg)
b4c0a845 502{
8c5b0f9a 503 const struct pcicfg_expr *expr = &cfg->expr;
b4c0a845
SZ
504 uint16_t port_type;
505
b4c0a845
SZ
506 /*
507 * Only version 1 can be parsed currently
508 */
509 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
8c5b0f9a 510 return 0;
b4c0a845
SZ
511
512 /*
b4c0a845
SZ
513 * - Slot implemented bit is meaningful iff current port is
514 * root port or down stream port.
8c5b0f9a
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515 * - Testing for root port or down stream port is meanningful
516 * iff PCI configure has type 1 header.
b4c0a845 517 */
8c5b0f9a 518
b4c0a845 519 if (cfg->hdrtype != 1)
8c5b0f9a 520 return 0;
b4c0a845
SZ
521
522 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
8c5b0f9a
SZ
523 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT)
524 return 0;
b4c0a845
SZ
525
526 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
8c5b0f9a
SZ
527 return 0;
528
529 return 1;
530}
531
532static void
533pci_read_cap_expr(device_t pcib, int ptr, pcicfgregs *cfg)
534{
535#define REG(n, w) \
536 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
537
538 struct pcicfg_expr *expr = &cfg->expr;
539
540 expr->expr_ptr = ptr;
541 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
542
543 /*
544 * Only version 1 can be parsed currently
545 */
546 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
b4c0a845
SZ
547 return;
548
8c5b0f9a
SZ
549 /*
550 * Read slot capabilities. Slot capabilities exists iff
551 * current port's slot is implemented
552 */
553 if (pcie_slotimpl(cfg))
554 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
b4c0a845
SZ
555
556#undef REG
557}
558
984263bc 559static void
e9d8f4df 560pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
984263bc 561{
8475d8bb
SZ
562#define REG(n, w) \
563 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
564
1361c4cd 565 int nextptr, ptrptr;
984263bc 566
0c78fe3f
SZ
567 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
568 /* No capabilities */
569 return;
570 }
571
984263bc
MD
572 switch (cfg->hdrtype) {
573 case 0:
81c29ce4
SZ
574 case 1:
575 ptrptr = PCIR_CAP_PTR;
984263bc
MD
576 break;
577 case 2:
81c29ce4 578 ptrptr = PCIR_CAP_PTR_2;
984263bc
MD
579 break;
580 default:
0c78fe3f 581 return; /* No capabilities support */
984263bc 582 }
0c78fe3f 583 nextptr = REG(ptrptr, 1);
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584
585 /*
586 * Read capability entries.
587 */
1361c4cd
SZ
588 while (pci_fixup_nextptr(&nextptr)) {
589 int ptr = nextptr;
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590
591 /* Process this entry */
592 switch (REG(ptr, 1)) {
81c29ce4 593 case PCIY_PMG: /* PCI power management */
8475d8bb 594 pci_read_cap_pmgt(pcib, ptr, cfg);
984263bc 595 break;
c7e4e7eb
SZ
596 case PCIY_PCIX: /* PCI-X */
597 cfg->pcixcap_ptr = ptr;
598 break;
b4c0a845
SZ
599 case PCIY_EXPRESS: /* PCI Express */
600 pci_read_cap_expr(pcib, ptr, cfg);
601 break;
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602 default:
603 break;
604 }
1361c4cd
SZ
605
606 /* Find the next entry */
607 nextptr = REG(ptr + 1, 1);
984263bc 608 }
8475d8bb 609
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610#undef REG
611}
612
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613/* free pcicfgregs structure and all depending data structures */
614
22457186 615int
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616pci_freecfg(struct pci_devinfo *dinfo)
617{
618 struct devlist *devlist_head;
619
620 devlist_head = &pci_devq;
621
622 if (dinfo->cfg.hdrspec != NULL)
efda3bd0 623 kfree(dinfo->cfg.hdrspec, M_DEVBUF);
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624 /* XXX this hasn't been tested */
625 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
efda3bd0 626 kfree(dinfo, M_DEVBUF);
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627
628 /* increment the generation count */
629 pci_generation++;
630
631 /* we're losing one device */
632 pci_numdevs--;
633 return (0);
634}
984263bc
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635
636
637/*
638 * PCI power manangement
639 */
e126caf1 640int
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641pci_set_powerstate_method(device_t dev, device_t child, int state)
642{
643 struct pci_devinfo *dinfo = device_get_ivars(child);
644 pcicfgregs *cfg = &dinfo->cfg;
f4754a59
HT
645 uint16_t status;
646 int result, oldstate, highest, delay;
984263bc 647
f4754a59
HT
648 if (cfg->pmgt.pp_cap == 0)
649 return (EOPNOTSUPP);
650
651 /*
652 * Optimize a no state change request away. While it would be OK to
653 * write to the hardware in theory, some devices have shown odd
654 * behavior when going from D3 -> D3.
655 */
656 oldstate = pci_get_powerstate(child);
657 if (oldstate == state)
658 return (0);
659
660 /*
661 * The PCI power management specification states that after a state
662 * transition between PCI power states, system software must
663 * guarantee a minimal delay before the function accesses the device.
664 * Compute the worst case delay that we need to guarantee before we
665 * access the device. Many devices will be responsive much more
666 * quickly than this delay, but there are some that don't respond
667 * instantly to state changes. Transitions to/from D3 state require
668 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
669 * is done below with DELAY rather than a sleeper function because
670 * this function can be called from contexts where we cannot sleep.
671 */
672 highest = (oldstate > state) ? oldstate : state;
673 if (highest == PCI_POWERSTATE_D3)
674 delay = 10000;
675 else if (highest == PCI_POWERSTATE_D2)
676 delay = 200;
677 else
678 delay = 0;
679 status = PCI_READ_CONFIG(dev, child, cfg->pmgt.pp_status, 2)
680 & ~PCIM_PSTAT_DMASK;
681 result = 0;
682 switch (state) {
683 case PCI_POWERSTATE_D0:
684 status |= PCIM_PSTAT_D0;
685 break;
686 case PCI_POWERSTATE_D1:
687 if ((cfg->pmgt.pp_cap & PCIM_PCAP_D1SUPP) == 0)
688 return (EOPNOTSUPP);
689 status |= PCIM_PSTAT_D1;
690 break;
691 case PCI_POWERSTATE_D2:
692 if ((cfg->pmgt.pp_cap & PCIM_PCAP_D2SUPP) == 0)
693 return (EOPNOTSUPP);
694 status |= PCIM_PSTAT_D2;
695 break;
696 case PCI_POWERSTATE_D3:
697 status |= PCIM_PSTAT_D3;
698 break;
699 default:
700 return (EINVAL);
984263bc 701 }
f4754a59
HT
702
703 if (bootverbose)
704 kprintf(
705 "pci%d:%d:%d: Transition from D%d to D%d\n",
706 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func,
707 oldstate, state);
708
709 PCI_WRITE_CONFIG(dev, child, cfg->pmgt.pp_status, status, 2);
710 if (delay)
711 DELAY(delay);
712 return (0);
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MD
713}
714
e126caf1 715int
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716pci_get_powerstate_method(device_t dev, device_t child)
717{
718 struct pci_devinfo *dinfo = device_get_ivars(child);
719 pcicfgregs *cfg = &dinfo->cfg;
f4754a59 720 uint16_t status;
984263bc
MD
721 int result;
722
f4754a59
HT
723 if (cfg->pmgt.pp_cap != 0) {
724 status = PCI_READ_CONFIG(dev, child, cfg->pmgt.pp_status, 2);
984263bc
MD
725 switch (status & PCIM_PSTAT_DMASK) {
726 case PCIM_PSTAT_D0:
727 result = PCI_POWERSTATE_D0;
728 break;
729 case PCIM_PSTAT_D1:
730 result = PCI_POWERSTATE_D1;
731 break;
732 case PCIM_PSTAT_D2:
733 result = PCI_POWERSTATE_D2;
734 break;
735 case PCIM_PSTAT_D3:
736 result = PCI_POWERSTATE_D3;
737 break;
738 default:
739 result = PCI_POWERSTATE_UNKNOWN;
740 break;
741 }
742 } else {
743 /* No support, device is always at D0 */
744 result = PCI_POWERSTATE_D0;
745 }
f4754a59 746 return (result);
984263bc
MD
747}
748
749/*
750 * Some convenience functions for PCI device drivers.
751 */
752
753static __inline void
754pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
755{
756 u_int16_t command;
757
758 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
759 command |= bit;
760 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
761}
762
763static __inline void
764pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
765{
766 u_int16_t command;
767
768 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
769 command &= ~bit;
770 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
771}
772
e126caf1 773int
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774pci_enable_busmaster_method(device_t dev, device_t child)
775{
776 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 777 return(0);
984263bc
MD
778}
779
e126caf1 780int
984263bc
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781pci_disable_busmaster_method(device_t dev, device_t child)
782{
783 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 784 return(0);
984263bc
MD
785}
786
e126caf1 787int
984263bc
MD
788pci_enable_io_method(device_t dev, device_t child, int space)
789{
e126caf1
MD
790 uint16_t command;
791 uint16_t bit;
792 char *error;
793
794 bit = 0;
795 error = NULL;
796
984263bc
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797 switch(space) {
798 case SYS_RES_IOPORT:
e126caf1
MD
799 bit = PCIM_CMD_PORTEN;
800 error = "port";
984263bc
MD
801 break;
802 case SYS_RES_MEMORY:
e126caf1
MD
803 bit = PCIM_CMD_MEMEN;
804 error = "memory";
984263bc 805 break;
e126caf1
MD
806 default:
807 return(EINVAL);
984263bc 808 }
e126caf1
MD
809 pci_set_command_bit(dev, child, bit);
810 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
811 if (command & bit)
812 return(0);
813 device_printf(child, "failed to enable %s mapping!\n", error);
814 return(ENXIO);
984263bc
MD
815}
816
e126caf1 817int
984263bc
MD
818pci_disable_io_method(device_t dev, device_t child, int space)
819{
e126caf1
MD
820 uint16_t command;
821 uint16_t bit;
822 char *error;
823
824 bit = 0;
825 error = NULL;
826
984263bc
MD
827 switch(space) {
828 case SYS_RES_IOPORT:
e126caf1
MD
829 bit = PCIM_CMD_PORTEN;
830 error = "port";
984263bc
MD
831 break;
832 case SYS_RES_MEMORY:
e126caf1
MD
833 bit = PCIM_CMD_MEMEN;
834 error = "memory";
984263bc 835 break;
e126caf1
MD
836 default:
837 return (EINVAL);
984263bc 838 }
e126caf1
MD
839 pci_clear_command_bit(dev, child, bit);
840 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
841 if (command & bit) {
842 device_printf(child, "failed to disable %s mapping!\n", error);
843 return (ENXIO);
844 }
845 return (0);
984263bc
MD
846}
847
848/*
849 * This is the user interface to PCI configuration space.
850 */
851
852static int
fef8985e 853pci_open(struct dev_open_args *ap)
984263bc 854{
fef8985e 855 if ((ap->a_oflags & FWRITE) && securelevel > 0) {
984263bc
MD
856 return EPERM;
857 }
858 return 0;
859}
860
861static int
fef8985e 862pci_close(struct dev_close_args *ap)
984263bc
MD
863{
864 return 0;
865}
866
867/*
868 * Match a single pci_conf structure against an array of pci_match_conf
869 * structures. The first argument, 'matches', is an array of num_matches
870 * pci_match_conf structures. match_buf is a pointer to the pci_conf
871 * structure that will be compared to every entry in the matches array.
872 * This function returns 1 on failure, 0 on success.
873 */
874static int
875pci_conf_match(struct pci_match_conf *matches, int num_matches,
876 struct pci_conf *match_buf)
877{
878 int i;
879
880 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
881 return(1);
882
883 for (i = 0; i < num_matches; i++) {
884 /*
885 * I'm not sure why someone would do this...but...
886 */
887 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
888 continue;
889
890 /*
891 * Look at each of the match flags. If it's set, do the
892 * comparison. If the comparison fails, we don't have a
893 * match, go on to the next item if there is one.
894 */
895 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
896 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
897 continue;
898
899 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
900 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
901 continue;
902
903 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
904 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
905 continue;
906
907 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
908 && (match_buf->pc_vendor != matches[i].pc_vendor))
909 continue;
910
911 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
912 && (match_buf->pc_device != matches[i].pc_device))
913 continue;
914
915 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
916 && (match_buf->pc_class != matches[i].pc_class))
917 continue;
918
919 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
920 && (match_buf->pd_unit != matches[i].pd_unit))
921 continue;
922
923 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
924 && (strncmp(matches[i].pd_name, match_buf->pd_name,
925 sizeof(match_buf->pd_name)) != 0))
926 continue;
927
928 return(0);
929 }
930
931 return(1);
932}
933
934/*
935 * Locate the parent of a PCI device by scanning the PCI devlist
936 * and return the entry for the parent.
937 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
938 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
939 */
940
941pcicfgregs *
942pci_devlist_get_parent(pcicfgregs *cfg)
943{
944 struct devlist *devlist_head;
945 struct pci_devinfo *dinfo;
946 pcicfgregs *bridge_cfg;
947 int i;
948
949 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
950
951 /* If the device is on PCI bus 0, look for the host */
952 if (cfg->bus == 0) {
953 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
954 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
955 bridge_cfg = &dinfo->cfg;
956 if (bridge_cfg->baseclass == PCIC_BRIDGE
957 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
958 && bridge_cfg->bus == cfg->bus) {
959 return bridge_cfg;
960 }
961 }
962 }
963
964 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
965 if (cfg->bus > 0) {
966 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
967 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
968 bridge_cfg = &dinfo->cfg;
969 if (bridge_cfg->baseclass == PCIC_BRIDGE
970 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
971 && bridge_cfg->secondarybus == cfg->bus) {
972 return bridge_cfg;
973 }
974 }
975 }
976
977 return NULL;
978}
979
980static int
fef8985e 981pci_ioctl(struct dev_ioctl_args *ap)
984263bc 982{
4a5a2d63 983 device_t pci, pcib;
984263bc
MD
984 struct pci_io *io;
985 const char *name;
986 int error;
987
fef8985e 988 if (!(ap->a_fflag & FWRITE))
984263bc
MD
989 return EPERM;
990
fef8985e 991 switch(ap->a_cmd) {
984263bc
MD
992 case PCIOCGETCONF:
993 {
994 struct pci_devinfo *dinfo;
995 struct pci_conf_io *cio;
996 struct devlist *devlist_head;
997 struct pci_match_conf *pattern_buf;
998 int num_patterns;
999 size_t iolen;
1000 int ionum, i;
1001
fef8985e 1002 cio = (struct pci_conf_io *)ap->a_data;
984263bc
MD
1003
1004 num_patterns = 0;
1005 dinfo = NULL;
1006
1007 /*
1008 * Hopefully the user won't pass in a null pointer, but it
1009 * can't hurt to check.
1010 */
1011 if (cio == NULL) {
1012 error = EINVAL;
1013 break;
1014 }
1015
1016 /*
1017 * If the user specified an offset into the device list,
1018 * but the list has changed since they last called this
1019 * ioctl, tell them that the list has changed. They will
1020 * have to get the list from the beginning.
1021 */
1022 if ((cio->offset != 0)
1023 && (cio->generation != pci_generation)){
1024 cio->num_matches = 0;
1025 cio->status = PCI_GETCONF_LIST_CHANGED;
1026 error = 0;
1027 break;
1028 }
1029
1030 /*
1031 * Check to see whether the user has asked for an offset
1032 * past the end of our list.
1033 */
1034 if (cio->offset >= pci_numdevs) {
1035 cio->num_matches = 0;
1036 cio->status = PCI_GETCONF_LAST_DEVICE;
1037 error = 0;
1038 break;
1039 }
1040
1041 /* get the head of the device queue */
1042 devlist_head = &pci_devq;
1043
1044 /*
1045 * Determine how much room we have for pci_conf structures.
1046 * Round the user's buffer size down to the nearest
1047 * multiple of sizeof(struct pci_conf) in case the user
1048 * didn't specify a multiple of that size.
1049 */
1050 iolen = min(cio->match_buf_len -
1051 (cio->match_buf_len % sizeof(struct pci_conf)),
1052 pci_numdevs * sizeof(struct pci_conf));
1053
1054 /*
1055 * Since we know that iolen is a multiple of the size of
1056 * the pciconf union, it's okay to do this.
1057 */
1058 ionum = iolen / sizeof(struct pci_conf);
1059
1060 /*
1061 * If this test is true, the user wants the pci_conf
1062 * structures returned to match the supplied entries.
1063 */
1064 if ((cio->num_patterns > 0)
1065 && (cio->pat_buf_len > 0)) {
1066 /*
1067 * pat_buf_len needs to be:
1068 * num_patterns * sizeof(struct pci_match_conf)
1069 * While it is certainly possible the user just
1070 * allocated a large buffer, but set the number of
1071 * matches correctly, it is far more likely that
1072 * their kernel doesn't match the userland utility
1073 * they're using. It's also possible that the user
1074 * forgot to initialize some variables. Yes, this
1075 * may be overly picky, but I hazard to guess that
1076 * it's far more likely to just catch folks that
1077 * updated their kernel but not their userland.
1078 */
1079 if ((cio->num_patterns *
1080 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
1081 /* The user made a mistake, return an error*/
1082 cio->status = PCI_GETCONF_ERROR;
85f8e2ea 1083 kprintf("pci_ioctl: pat_buf_len %d != "
984263bc
MD
1084 "num_patterns (%d) * sizeof(struct "
1085 "pci_match_conf) (%d)\npci_ioctl: "
1086 "pat_buf_len should be = %d\n",
1087 cio->pat_buf_len, cio->num_patterns,
1088 (int)sizeof(struct pci_match_conf),
1089 (int)sizeof(struct pci_match_conf) *
1090 cio->num_patterns);
85f8e2ea 1091 kprintf("pci_ioctl: do your headers match your "
984263bc
MD
1092 "kernel?\n");
1093 cio->num_matches = 0;
1094 error = EINVAL;
1095 break;
1096 }
1097
1098 /*
1099 * Check the user's buffer to make sure it's readable.
1100 */
1101 if (!useracc((caddr_t)cio->patterns,
1102 cio->pat_buf_len, VM_PROT_READ)) {
85f8e2ea 1103 kprintf("pci_ioctl: pattern buffer %p, "
984263bc
MD
1104 "length %u isn't user accessible for"
1105 " READ\n", cio->patterns,
1106 cio->pat_buf_len);
1107 error = EACCES;
1108 break;
1109 }
1110 /*
1111 * Allocate a buffer to hold the patterns.
1112 */
efda3bd0 1113 pattern_buf = kmalloc(cio->pat_buf_len, M_TEMP,
984263bc
MD
1114 M_WAITOK);
1115 error = copyin(cio->patterns, pattern_buf,
1116 cio->pat_buf_len);
1117 if (error != 0)
1118 break;
1119 num_patterns = cio->num_patterns;
1120
1121 } else if ((cio->num_patterns > 0)
1122 || (cio->pat_buf_len > 0)) {
1123 /*
1124 * The user made a mistake, spit out an error.
1125 */
1126 cio->status = PCI_GETCONF_ERROR;
1127 cio->num_matches = 0;
85f8e2ea 1128 kprintf("pci_ioctl: invalid GETCONF arguments\n");
984263bc
MD
1129 error = EINVAL;
1130 break;
1131 } else
1132 pattern_buf = NULL;
1133
1134 /*
1135 * Make sure we can write to the match buffer.
1136 */
1137 if (!useracc((caddr_t)cio->matches,
1138 cio->match_buf_len, VM_PROT_WRITE)) {
85f8e2ea 1139 kprintf("pci_ioctl: match buffer %p, length %u "
984263bc
MD
1140 "isn't user accessible for WRITE\n",
1141 cio->matches, cio->match_buf_len);
1142 error = EACCES;
1143 break;
1144 }
1145
1146 /*
1147 * Go through the list of devices and copy out the devices
1148 * that match the user's criteria.
1149 */
1150 for (cio->num_matches = 0, error = 0, i = 0,
1151 dinfo = STAILQ_FIRST(devlist_head);
1152 (dinfo != NULL) && (cio->num_matches < ionum)
1153 && (error == 0) && (i < pci_numdevs);
1154 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
1155
1156 if (i < cio->offset)
1157 continue;
1158
1159 /* Populate pd_name and pd_unit */
1160 name = NULL;
1161 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
1162 name = device_get_name(dinfo->cfg.dev);
1163 if (name) {
1164 strncpy(dinfo->conf.pd_name, name,
1165 sizeof(dinfo->conf.pd_name));
1166 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
1167 dinfo->conf.pd_unit =
1168 device_get_unit(dinfo->cfg.dev);
1169 }
1170
1171 if ((pattern_buf == NULL) ||
1172 (pci_conf_match(pattern_buf, num_patterns,
1173 &dinfo->conf) == 0)) {
1174
1175 /*
1176 * If we've filled up the user's buffer,
1177 * break out at this point. Since we've
1178 * got a match here, we'll pick right back
1179 * up at the matching entry. We can also
1180 * tell the user that there are more matches
1181 * left.
1182 */
1183 if (cio->num_matches >= ionum)
1184 break;
1185
1186 error = copyout(&dinfo->conf,
1187 &cio->matches[cio->num_matches],
1188 sizeof(struct pci_conf));
1189 cio->num_matches++;
1190 }
1191 }
1192
1193 /*
1194 * Set the pointer into the list, so if the user is getting
1195 * n records at a time, where n < pci_numdevs,
1196 */
1197 cio->offset = i;
1198
1199 /*
1200 * Set the generation, the user will need this if they make
1201 * another ioctl call with offset != 0.
1202 */
1203 cio->generation = pci_generation;
1204
1205 /*
1206 * If this is the last device, inform the user so he won't
1207 * bother asking for more devices. If dinfo isn't NULL, we
1208 * know that there are more matches in the list because of
1209 * the way the traversal is done.
1210 */
1211 if (dinfo == NULL)
1212 cio->status = PCI_GETCONF_LAST_DEVICE;
1213 else
1214 cio->status = PCI_GETCONF_MORE_DEVS;
1215
1216 if (pattern_buf != NULL)
efda3bd0 1217 kfree(pattern_buf, M_TEMP);
984263bc
MD
1218
1219 break;
1220 }
1221 case PCIOCREAD:
fef8985e 1222 io = (struct pci_io *)ap->a_data;
984263bc 1223 switch(io->pi_width) {
984263bc
MD
1224 case 4:
1225 case 2:
1226 case 1:
4a5a2d63
JS
1227 /*
1228 * Assume that the user-level bus number is
1229 * actually the pciN instance number. We map
1230 * from that to the real pcib+bus combination.
1231 */
1232 pci = devclass_get_device(pci_devclass,
1233 io->pi_sel.pc_bus);
1234 if (pci) {
2581072f
MD
1235 /*
1236 * pci is the pci device and may contain
1237 * several children (for each function code).
1238 * The governing pci bus is the parent to
1239 * the pci device.
1240 */
1241 int b;
1242
4a5a2d63 1243 pcib = device_get_parent(pci);
2581072f 1244 b = pcib_get_bus(pcib);
4a5a2d63
JS
1245 io->pi_data =
1246 PCIB_READ_CONFIG(pcib,
1247 b,
1248 io->pi_sel.pc_dev,
1249 io->pi_sel.pc_func,
1250 io->pi_reg,
1251 io->pi_width);
1252 error = 0;
1253 } else {
1254 error = ENODEV;
1255 }
984263bc
MD
1256 break;
1257 default:
1258 error = ENODEV;
1259 break;
1260 }
1261 break;
1262
1263 case PCIOCWRITE:
fef8985e 1264 io = (struct pci_io *)ap->a_data;
984263bc 1265 switch(io->pi_width) {
984263bc
MD
1266 case 4:
1267 case 2:
1268 case 1:
4a5a2d63
JS
1269 /*
1270 * Assume that the user-level bus number is
1271 * actually the pciN instance number. We map
1272 * from that to the real pcib+bus combination.
1273 */
1274 pci = devclass_get_device(pci_devclass,
1275 io->pi_sel.pc_bus);
1276 if (pci) {
2581072f
MD
1277 /*
1278 * pci is the pci device and may contain
1279 * several children (for each function code).
1280 * The governing pci bus is the parent to
1281 * the pci device.
1282 */
1283 int b;
1284
4a5a2d63 1285 pcib = device_get_parent(pci);
2581072f 1286 b = pcib_get_bus(pcib);
4a5a2d63
JS
1287 PCIB_WRITE_CONFIG(pcib,
1288 b,
1289 io->pi_sel.pc_dev,
1290 io->pi_sel.pc_func,
1291 io->pi_reg,
1292 io->pi_data,
1293 io->pi_width);
1294 error = 0;
1295 } else {
1296 error = ENODEV;
1297 }
984263bc
MD
1298 break;
1299 default:
1300 error = ENODEV;
1301 break;
1302 }
1303 break;
1304
1305 default:
1306 error = ENOTTY;
1307 break;
1308 }
1309
1310 return (error);
1311}
1312
1313#define PCI_CDEV 78
1314
fef8985e
MD
1315static struct dev_ops pcic_ops = {
1316 { "pci", PCI_CDEV, 0 },
1317 .d_open = pci_open,
1318 .d_close = pci_close,
1319 .d_ioctl = pci_ioctl,
984263bc
MD
1320};
1321
1322#include "pci_if.h"
1323
984263bc
MD
1324/*
1325 * New style pci driver. Parent device is either a pci-host-bridge or a
1326 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1327 */
ed1bd994
MD
1328const char *
1329pci_class_to_string(int baseclass)
1330{
1331 const char *name;
1332
1333 switch(baseclass) {
1334 case PCIC_OLD:
1335 name = "OLD";
1336 break;
1337 case PCIC_STORAGE:
1338 name = "STORAGE";
1339 break;
1340 case PCIC_NETWORK:
1341 name = "NETWORK";
1342 break;
1343 case PCIC_DISPLAY:
1344 name = "DISPLAY";
1345 break;
1346 case PCIC_MULTIMEDIA:
1347 name = "MULTIMEDIA";
1348 break;
1349 case PCIC_MEMORY:
1350 name = "MEMORY";
1351 break;
1352 case PCIC_BRIDGE:
1353 name = "BRIDGE";
1354 break;
1355 case PCIC_SIMPLECOMM:
1356 name = "SIMPLECOMM";
1357 break;
1358 case PCIC_BASEPERIPH:
1359 name = "BASEPERIPH";
1360 break;
1361 case PCIC_INPUTDEV:
1362 name = "INPUTDEV";
1363 break;
1364 case PCIC_DOCKING:
1365 name = "DOCKING";
1366 break;
1367 case PCIC_PROCESSOR:
1368 name = "PROCESSOR";
1369 break;
1370 case PCIC_SERIALBUS:
1371 name = "SERIALBUS";
1372 break;
1373 case PCIC_WIRELESS:
1374 name = "WIRELESS";
1375 break;
1376 case PCIC_I2O:
1377 name = "I20";
1378 break;
1379 case PCIC_SATELLITE:
1380 name = "SATELLITE";
1381 break;
1382 case PCIC_CRYPTO:
1383 name = "CRYPTO";
1384 break;
1385 case PCIC_SIGPROC:
1386 name = "SIGPROC";
1387 break;
1388 case PCIC_OTHER:
1389 name = "OTHER";
1390 break;
1391 default:
1392 name = "?";
1393 break;
1394 }
1395 return(name);
1396}
984263bc 1397
b4c0a845
SZ
1398static void
1399pci_print_verbose_expr(const pcicfgregs *cfg)
1400{
1401 const struct pcicfg_expr *expr = &cfg->expr;
1402 const char *port_name;
1403 uint16_t port_type;
1404
1405 if (!bootverbose)
1406 return;
1407
1408 if (expr->expr_ptr == 0) /* No PCI Express capability */
1409 return;
1410
1411 kprintf("\tPCI Express ver.%d cap=0x%04x",
1412 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
1413 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
1414 goto back;
1415
1416 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
1417
1418 switch (port_type) {
8c5b0f9a 1419 case PCIE_END_POINT:
b4c0a845
SZ
1420 port_name = "DEVICE";
1421 break;
8c5b0f9a 1422 case PCIE_LEG_END_POINT:
b4c0a845
SZ
1423 port_name = "LEGDEV";
1424 break;
8c5b0f9a 1425 case PCIE_ROOT_PORT:
b4c0a845
SZ
1426 port_name = "ROOT";
1427 break;
8c5b0f9a 1428 case PCIE_UP_STREAM_PORT:
b4c0a845
SZ
1429 port_name = "UPSTREAM";
1430 break;
8c5b0f9a 1431 case PCIE_DOWN_STREAM_PORT:
b4c0a845
SZ
1432 port_name = "DOWNSTRM";
1433 break;
8c5b0f9a 1434 case PCIE_PCIE2PCI_BRIDGE:
b4c0a845
SZ
1435 port_name = "PCIE2PCI";
1436 break;
8c5b0f9a 1437 case PCIE_PCI2PCIE_BRIDGE:
b4c0a845
SZ
1438 port_name = "PCI2PCIE";
1439 break;
1440 default:
1441 port_name = NULL;
1442 break;
1443 }
8c5b0f9a
SZ
1444 if ((port_type == PCIE_ROOT_PORT ||
1445 port_type == PCIE_DOWN_STREAM_PORT) &&
b4c0a845
SZ
1446 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
1447 port_name = NULL;
1448 if (port_name != NULL)
1449 kprintf("[%s]", port_name);
1450
8c5b0f9a 1451 if (pcie_slotimpl(cfg)) {
b4c0a845
SZ
1452 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
1453 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
1454 kprintf("[HOTPLUG]");
1455 }
1456back:
1457 kprintf("\n");
1458}
1459
22457186 1460void
984263bc
MD
1461pci_print_verbose(struct pci_devinfo *dinfo)
1462{
1463 if (bootverbose) {
1464 pcicfgregs *cfg = &dinfo->cfg;
1465
85f8e2ea 1466 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
984263bc 1467 cfg->vendor, cfg->device, cfg->revid);
85f8e2ea 1468 kprintf("\tbus=%d, slot=%d, func=%d\n",
4a5a2d63 1469 cfg->bus, cfg->slot, cfg->func);
85f8e2ea 1470 kprintf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
ed1bd994 1471 pci_class_to_string(cfg->baseclass),
984263bc
MD
1472 cfg->baseclass, cfg->subclass, cfg->progif,
1473 cfg->hdrtype, cfg->mfdev);
85f8e2ea 1474 kprintf("\tsubordinatebus=%x \tsecondarybus=%x\n",
984263bc
MD
1475 cfg->subordinatebus, cfg->secondarybus);
1476#ifdef PCI_DEBUG
85f8e2ea 1477 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
984263bc 1478 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
85f8e2ea 1479 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
984263bc
MD
1480 cfg->lattimer, cfg->lattimer * 30,
1481 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1482#endif /* PCI_DEBUG */
1483 if (cfg->intpin > 0)
85f8e2ea 1484 kprintf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
b4c0a845
SZ
1485
1486 pci_print_verbose_expr(cfg);
984263bc
MD
1487 }
1488}
1489
1490static int
4a5a2d63 1491pci_porten(device_t pcib, int b, int s, int f)
984263bc 1492{
4a5a2d63
JS
1493 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1494 & PCIM_CMD_PORTEN) != 0;
984263bc
MD
1495}
1496
1497static int
4a5a2d63 1498pci_memen(device_t pcib, int b, int s, int f)
984263bc 1499{
4a5a2d63
JS
1500 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1501 & PCIM_CMD_MEMEN) != 0;
984263bc
MD
1502}
1503
1504/*
1505 * Add a resource based on a pci map register. Return 1 if the map
1506 * register is a 32bit map register or 2 if it is a 64bit register.
1507 */
1508static int
4a5a2d63
JS
1509pci_add_map(device_t pcib, int b, int s, int f, int reg,
1510 struct resource_list *rl)
984263bc 1511{
984263bc
MD
1512 u_int32_t map;
1513 u_int64_t base;
1514 u_int8_t ln2size;
1515 u_int8_t ln2range;
1516 u_int32_t testval;
4a5a2d63
JS
1517
1518
1519#ifdef PCI_ENABLE_IO_MODES
1520 u_int16_t cmd;
1521#endif
984263bc
MD
1522 int type;
1523
4a5a2d63 1524 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
984263bc
MD
1525
1526 if (map == 0 || map == 0xffffffff)
1527 return 1; /* skip invalid entry */
1528
4a5a2d63
JS
1529 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1530 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1531 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
984263bc
MD
1532
1533 base = pci_mapbase(map);
1534 if (pci_maptype(map) & PCI_MAPMEM)
1535 type = SYS_RES_MEMORY;
1536 else
1537 type = SYS_RES_IOPORT;
1538 ln2size = pci_mapsize(testval);
1539 ln2range = pci_maprange(testval);
1540 if (ln2range == 64) {
1541 /* Read the other half of a 64bit map register */
4a5a2d63 1542 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
984263bc
MD
1543 }
1544
984263bc
MD
1545 /*
1546 * This code theoretically does the right thing, but has
1547 * undesirable side effects in some cases where
1548 * peripherals respond oddly to having these bits
1549 * enabled. Leave them alone by default.
1550 */
1551#ifdef PCI_ENABLE_IO_MODES
4a5a2d63
JS
1552 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1553 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1554 cmd |= PCIM_CMD_PORTEN;
1555 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc 1556 }
4a5a2d63
JS
1557 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1558 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1559 cmd |= PCIM_CMD_MEMEN;
1560 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc
MD
1561 }
1562#else
4a5a2d63 1563 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
984263bc 1564 return 1;
4a5a2d63 1565 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
984263bc
MD
1566 return 1;
1567#endif
1568
1569 resource_list_add(rl, type, reg,
1570 base, base + (1 << ln2size) - 1,
1571 (1 << ln2size));
1572
1573 if (bootverbose) {
85f8e2ea 1574 kprintf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
984263bc
MD
1575 reg, pci_maptype(base), ln2range,
1576 (unsigned int) base, ln2size);
1577 }
1578
1579 return (ln2range == 64) ? 2 : 1;
1580}
1581
201eb0a7
TS
1582#ifdef PCI_MAP_FIXUP
1583/*
1584 * For ATA devices we need to decide early on what addressing mode to use.
1585 * Legacy demands that the primary and secondary ATA ports sits on the
1586 * same addresses that old ISA hardware did. This dictates that we use
1587 * those addresses and ignore the BARs if we cannot set PCI native
1588 * addressing mode.
1589 */
1590static void
1591pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, int s, int f,
1592 struct resource_list *rl)
1593{
1594 int rid, type, progif;
1595#if 0
1596 /* if this device supports PCI native addressing use it */
1597 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1598 if ((progif &0x8a) == 0x8a) {
1599 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
1600 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
85f8e2ea 1601 kprintf("Trying ATA native PCI addressing mode\n");
201eb0a7
TS
1602 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
1603 }
1604 }
1605#endif
1606 /*
1607 * Because we return any preallocated resources for lazy
1608 * allocation for PCI devices in pci_alloc_resource(), we can
1609 * allocate our legacy resources here.
1610 */
1611 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1612 type = SYS_RES_IOPORT;
1613 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
1614 pci_add_map(pcib, b, s, f, PCIR_BAR(0), rl);
1615 pci_add_map(pcib, b, s, f, PCIR_BAR(1), rl);
1616 } else {
1617 rid = PCIR_BAR(0);
1618 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
1619 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
1620 0);
1621 rid = PCIR_BAR(1);
1622 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
1623 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
1624 0);
1625 }
1626 if (progif & PCIP_STORAGE_IDE_MODESEC) {
1627 pci_add_map(pcib, b, s, f, PCIR_BAR(2), rl);
1628 pci_add_map(pcib, b, s, f, PCIR_BAR(3), rl);
1629 } else {
1630 rid = PCIR_BAR(2);
1631 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
1632 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
1633 0);
1634 rid = PCIR_BAR(3);
1635 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
1636 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
1637 0);
1638 }
1639 pci_add_map(pcib, b, s, f, PCIR_BAR(4), rl);
1640 pci_add_map(pcib, b, s, f, PCIR_BAR(5), rl);
1641}
1642#endif /* PCI_MAP_FIXUP */
1643
984263bc 1644static void
e126caf1 1645pci_add_resources(device_t pcib, device_t bus, device_t dev)
984263bc
MD
1646{
1647 struct pci_devinfo *dinfo = device_get_ivars(dev);
4a5a2d63 1648 pcicfgregs *cfg = &dinfo->cfg;
984263bc
MD
1649 struct resource_list *rl = &dinfo->resources;
1650 struct pci_quirk *q;
e126caf1
MD
1651 int b, i, f, s;
1652#if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */
1653 int irq;
1654#endif
984263bc 1655
e126caf1
MD
1656 b = cfg->bus;
1657 s = cfg->slot;
1658 f = cfg->func;
201eb0a7
TS
1659#ifdef PCI_MAP_FIXUP
1660 /* atapci devices in legacy mode need special map treatment */
1661 if ((pci_get_class(dev) == PCIC_STORAGE) &&
1662 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
d3d1ea7a
MD
1663 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
1664 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
1665 !pci_read_config(dev, PCIR_BAR(2), 4))) )
201eb0a7
TS
1666 pci_ata_maps(pcib, bus, dev, b, s, f, rl);
1667 else
1668#endif /* PCI_MAP_FIXUP */
1669 for (i = 0; i < cfg->nummaps;) {
1670 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl);
1671 }
984263bc
MD
1672
1673 for (q = &pci_quirks[0]; q->devid; q++) {
1674 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1675 && q->type == PCI_QUIRK_MAP_REG)
4a5a2d63 1676 pci_add_map(pcib, b, s, f, q->arg1, rl);
984263bc
MD
1677 }
1678
1679 if (cfg->intpin > 0 && cfg->intline != 255)
1680 resource_list_add(rl, SYS_RES_IRQ, 0,
1681 cfg->intline, cfg->intline, 1);
1682}
1683
e126caf1
MD
1684void
1685pci_add_children(device_t dev, int busno, size_t dinfo_size)
984263bc 1686{
e126caf1 1687#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
4a5a2d63 1688 device_t pcib = device_get_parent(dev);
e126caf1 1689 struct pci_devinfo *dinfo;
4a5a2d63 1690 int maxslots;
e126caf1
MD
1691 int s, f, pcifunchigh;
1692 uint8_t hdrtype;
1693
1694 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo));
984263bc 1695
4a5a2d63 1696 maxslots = PCIB_MAXSLOTS(pcib);
984263bc 1697
57e943f7 1698 for (s = 0; s <= maxslots; s++) {
e126caf1
MD
1699 pcifunchigh = 0;
1700 f = 0;
1701 hdrtype = REG(PCIR_HDRTYPE, 1);
1702 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1703 continue;
1704 if (hdrtype & PCIM_MFDEV)
1705 pcifunchigh = PCI_FUNCMAX;
5e658043 1706 for (f = 0; f <= pcifunchigh; f++) {
e126caf1 1707 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
984263bc 1708 if (dinfo != NULL) {
e126caf1 1709 pci_add_child(dev, dinfo);
984263bc
MD
1710 }
1711 }
1712 }
e126caf1
MD
1713#undef REG
1714}
1715
2581072f
MD
1716/*
1717 * The actual PCI child that we add has a NULL driver whos parent
1718 * device will be "pci". The child contains the ivars, not the parent.
1719 */
e126caf1
MD
1720void
1721pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1722{
1723 device_t pcib;
1724
1725 pcib = device_get_parent(bus);
1726 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1727 device_set_ivars(dinfo->cfg.dev, dinfo);
638744c5
HT
1728 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
1729 pci_cfg_restore(dinfo->cfg.dev, dinfo);
e126caf1
MD
1730 pci_add_resources(pcib, bus, dinfo->cfg.dev);
1731 pci_print_verbose(dinfo);
984263bc
MD
1732}
1733
c01b8d84
MD
1734/*
1735 * Probe the PCI bus. Note: probe code is not supposed to add children
1736 * or call attach.
1737 */
984263bc 1738static int
4a5a2d63 1739pci_probe(device_t dev)
984263bc 1740{
984263bc 1741 device_set_desc(dev, "PCI bus");
4a5a2d63 1742
c01b8d84
MD
1743 /* Allow other subclasses to override this driver */
1744 return(-1000);
984263bc
MD
1745}
1746
e126caf1
MD
1747static int
1748pci_attach(device_t dev)
1749{
1750 int busno;
e4c9c0c8
MD
1751 int lunit = device_get_unit(dev);
1752
fef8985e
MD
1753 dev_ops_add(&pcic_ops, -1, lunit);
1754 make_dev(&pcic_ops, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit);
e126caf1
MD
1755
1756 /*
1757 * Since there can be multiple independantly numbered PCI
1758 * busses on some large alpha systems, we can't use the unit
1759 * number to decide what bus we are probing. We ask the parent
1760 * pcib what our bus number is.
2581072f
MD
1761 *
1762 * pcib_get_bus() must act on the pci bus device, not on the pci
1763 * device, because it uses badly hacked nexus-based ivars to
1764 * store and retrieve the physical bus number. XXX
e126caf1 1765 */
2581072f 1766 busno = pcib_get_bus(device_get_parent(dev));
e126caf1 1767 if (bootverbose)
ed1bd994 1768 device_printf(dev, "pci_attach() physical bus=%d\n", busno);
e126caf1
MD
1769
1770 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1771
1772 return (bus_generic_attach(dev));
1773}
1774
984263bc
MD
1775static int
1776pci_print_resources(struct resource_list *rl, const char *name, int type,
1777 const char *format)
1778{
1779 struct resource_list_entry *rle;
1780 int printed, retval;
1781
1782 printed = 0;
1783 retval = 0;
1784 /* Yes, this is kinda cheating */
1785 SLIST_FOREACH(rle, rl, link) {
1786 if (rle->type == type) {
1787 if (printed == 0)
85f8e2ea 1788 retval += kprintf(" %s ", name);
984263bc 1789 else if (printed > 0)
85f8e2ea 1790 retval += kprintf(",");
984263bc 1791 printed++;
85f8e2ea 1792 retval += kprintf(format, rle->start);
984263bc 1793 if (rle->count > 1) {
85f8e2ea
SW
1794 retval += kprintf("-");
1795 retval += kprintf(format, rle->start +
984263bc
MD
1796 rle->count - 1);
1797 }
1798 }
1799 }
1800 return retval;
1801}
1802
e126caf1 1803int
984263bc
MD
1804pci_print_child(device_t dev, device_t child)
1805{
1806 struct pci_devinfo *dinfo;
1807 struct resource_list *rl;
1808 pcicfgregs *cfg;
1809 int retval = 0;
1810
1811 dinfo = device_get_ivars(child);
1812 cfg = &dinfo->cfg;
1813 rl = &dinfo->resources;
1814
1815 retval += bus_print_child_header(dev, child);
1816
1817 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1818 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1819 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1820 if (device_get_flags(dev))
85f8e2ea 1821 retval += kprintf(" flags %#x", device_get_flags(dev));
984263bc 1822
85f8e2ea 1823 retval += kprintf(" at device %d.%d", pci_get_slot(child),
984263bc
MD
1824 pci_get_function(child));
1825
1826 retval += bus_print_child_footer(dev, child);
1827
1828 return (retval);
1829}
1830
e126caf1 1831void
984263bc
MD
1832pci_probe_nomatch(device_t dev, device_t child)
1833{
1834 struct pci_devinfo *dinfo;
1835 pcicfgregs *cfg;
1836 const char *desc;
1837 int unknown;
1838
1839 unknown = 0;
1840 dinfo = device_get_ivars(child);
1841 cfg = &dinfo->cfg;
1842 desc = pci_ata_match(child);
1843 if (!desc) desc = pci_usb_match(child);
1844 if (!desc) desc = pci_vga_match(child);
27c23c6b 1845 if (!desc) desc = pci_chip_match(child);
984263bc
MD
1846 if (!desc) {
1847 desc = "unknown card";
1848 unknown++;
1849 }
1850 device_printf(dev, "<%s>", desc);
1851 if (bootverbose || unknown) {
85f8e2ea 1852 kprintf(" (vendor=0x%04x, dev=0x%04x)",
984263bc
MD
1853 cfg->vendor,
1854 cfg->device);
1855 }
85f8e2ea 1856 kprintf(" at %d.%d",
984263bc
MD
1857 pci_get_slot(child),
1858 pci_get_function(child));
1859 if (cfg->intpin > 0 && cfg->intline != 255) {
85f8e2ea 1860 kprintf(" irq %d", cfg->intline);
984263bc 1861 }
85f8e2ea 1862 kprintf("\n");
638744c5 1863 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
984263bc
MD
1864
1865 return;
1866}
1867
22457186 1868int
4a5a2d63 1869pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
984263bc
MD
1870{
1871 struct pci_devinfo *dinfo;
1872 pcicfgregs *cfg;
1873
1874 dinfo = device_get_ivars(child);
1875 cfg = &dinfo->cfg;
1876
1877 switch (which) {
1878 case PCI_IVAR_SUBVENDOR:
1879 *result = cfg->subvendor;
1880 break;
1881 case PCI_IVAR_SUBDEVICE:
1882 *result = cfg->subdevice;
1883 break;
1884 case PCI_IVAR_VENDOR:
1885 *result = cfg->vendor;
1886 break;
1887 case PCI_IVAR_DEVICE:
1888 *result = cfg->device;
1889 break;
1890 case PCI_IVAR_DEVID:
1891 *result = (cfg->device << 16) | cfg->vendor;
1892 break;
1893 case PCI_IVAR_CLASS:
1894 *result = cfg->baseclass;
1895 break;
1896 case PCI_IVAR_SUBCLASS:
1897 *result = cfg->subclass;
1898 break;
1899 case PCI_IVAR_PROGIF:
1900 *result = cfg->progif;
1901 break;
1902 case PCI_IVAR_REVID:
1903 *result = cfg->revid;
1904 break;
1905 case PCI_IVAR_INTPIN:
1906 *result = cfg->intpin;
1907 break;
1908 case PCI_IVAR_IRQ:
1909 *result = cfg->intline;
1910 break;
1911 case PCI_IVAR_BUS:
1912 *result = cfg->bus;
1913 break;
1914 case PCI_IVAR_SLOT:
1915 *result = cfg->slot;
1916 break;
1917 case PCI_IVAR_FUNCTION:
1918 *result = cfg->func;
1919 break;
1920 case PCI_IVAR_SECONDARYBUS:
1921 *result = cfg->secondarybus;
1922 break;
1923 case PCI_IVAR_SUBORDINATEBUS:
1924 *result = cfg->subordinatebus;
1925 break;
f72d3d23
JS
1926 case PCI_IVAR_ETHADDR:
1927 /*
1928 * The generic accessor doesn't deal with failure, so
1929 * we set the return value, then return an error.
1930 */
3641b7ca 1931 *result = 0;
f72d3d23 1932 return (EINVAL);
c7e4e7eb
SZ
1933 case PCI_IVAR_PCIXCAP_PTR:
1934 *result = cfg->pcixcap_ptr;
1935 break;
1936 case PCI_IVAR_PCIECAP_PTR:
1937 *result = cfg->expr.expr_ptr;
1938 break;
984263bc
MD
1939 default:
1940 return ENOENT;
1941 }
1942 return 0;
1943}
1944
22457186 1945int
984263bc
MD
1946pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1947{
1948 struct pci_devinfo *dinfo;
1949 pcicfgregs *cfg;
1950
1951 dinfo = device_get_ivars(child);
1952 cfg = &dinfo->cfg;
1953
1954 switch (which) {
1955 case PCI_IVAR_SUBVENDOR:
1956 case PCI_IVAR_SUBDEVICE:
1957 case PCI_IVAR_VENDOR:
1958 case PCI_IVAR_DEVICE:
1959 case PCI_IVAR_DEVID:
1960 case PCI_IVAR_CLASS:
1961 case PCI_IVAR_SUBCLASS:
1962 case PCI_IVAR_PROGIF:
1963 case PCI_IVAR_REVID:
1964 case PCI_IVAR_INTPIN:
1965 case PCI_IVAR_IRQ:
1966 case PCI_IVAR_BUS:
1967 case PCI_IVAR_SLOT:
1968 case PCI_IVAR_FUNCTION:
f72d3d23 1969 case PCI_IVAR_ETHADDR:
c7e4e7eb
SZ
1970 case PCI_IVAR_PCIXCAP_PTR:
1971 case PCI_IVAR_PCIECAP_PTR:
984263bc
MD
1972 return EINVAL; /* disallow for now */
1973
1974 case PCI_IVAR_SECONDARYBUS:
1975 cfg->secondarybus = value;
1976 break;
1977 case PCI_IVAR_SUBORDINATEBUS:
1978 cfg->subordinatebus = value;
1979 break;
1980 default:
1981 return ENOENT;
1982 }
1983 return 0;
1984}
1985
201eb0a7
TS
1986#ifdef PCI_MAP_FIXUP
1987static struct resource *
1988pci_alloc_map(device_t dev, device_t child, int type, int *rid, u_long start,
1989 u_long end, u_long count, u_int flags)
1990{
1991 struct pci_devinfo *dinfo = device_get_ivars(child);
1992 struct resource_list *rl = &dinfo->resources;
1993 struct resource_list_entry *rle;
1994 struct resource *res;
1995 uint32_t map, testval;
1996 int mapsize;
1997
1998 /*
1999 * Weed out the bogons, and figure out how large the BAR/map
2000 * is. BARs that read back 0 here are bogus and unimplemented.
2001 *
2002 * Note: atapci in legacy mode are special and handled elsewhere
2003 * in the code. If you have an atapci device in legacy mode and
2004 * it fails here, that other code is broken.
2005 */
2006 res = NULL;
2007 map = pci_read_config(child, *rid, 4);
2008 pci_write_config(child, *rid, 0xffffffff, 4);
2009 testval = pci_read_config(child, *rid, 4);
2010 if (pci_mapbase(testval) == 0)
2011 goto out;
2012 if (pci_maptype(testval) & PCI_MAPMEM) {
2013 if (type != SYS_RES_MEMORY) {
2014 if (bootverbose)
2015 device_printf(dev, "child %s requested type %d"
2016 " for rid %#x, but the BAR says "
2017 "it is a memio\n",
2018 device_get_nameunit(child), type,
2019 *rid);
2020 goto out;
2021 }
2022 } else {
2023 if (type != SYS_RES_IOPORT) {
2024 if (bootverbose)
2025 device_printf(dev, "child %s requested type %d"
2026 " for rid %#x, but the BAR says "
2027 "it is an ioport\n",
2028 device_get_nameunit(child), type,
2029 *rid);
2030 goto out;
2031 }
2032 }
2033 /*
2034 * For real BARs, we need to override the size that
2035 * the driver requests, because that's what the BAR
2036 * actually uses and we would otherwise have a
2037 * situation where we might allocate the excess to
2038 * another driver, which won't work.
2039 */
2040 mapsize = pci_mapsize(testval);
2041 count = 1 << mapsize;
2042 if (RF_ALIGNMENT(flags) < mapsize)
2043 flags = (flags & ~RF_ALIGNMENT_MASK) |
2044 RF_ALIGNMENT_LOG2(mapsize);
2045 /*
2046 * Allocate enough resource, and then write back the
2047 * appropriate BAR for that resource.
2048 */
2049 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
2050 start, end, count, flags);
2051 if (res == NULL) {
2052 device_printf(child, "%#lx bytes at rid %#x res %d failed "
2053 "(%#lx, %#lx)\n", count, *rid, type, start, end);
2054 goto out;
2055 }
2056 resource_list_add(rl, type, *rid, start, end, count);
2057 rle = resource_list_find(rl, type, *rid);
2058 if (rle == NULL)
2059 panic("pci_alloc_map: unexpectedly can't find resource.");
2060 rle->res = res;
2061 rle->start = rman_get_start(res);
2062 rle->end = rman_get_end(res);
2063 rle->count = count;
2064 if (bootverbose)
2065 device_printf(child, "lazy allocation of %#lx bytes rid %#x "
2066 "type %d at %#lx\n", count, *rid, type,
2067 rman_get_start(res));
2068 map = rman_get_start(res);
2069out:;
2070 pci_write_config(child, *rid, map, 4);
2071 return res;
2072}
2073#endif /* PCI_MAP_FIXUP */
2074
261fa16d 2075struct resource *
984263bc
MD
2076pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
2077 u_long start, u_long end, u_long count, u_int flags)
2078{
2079 struct pci_devinfo *dinfo = device_get_ivars(child);
2080 struct resource_list *rl = &dinfo->resources;
201eb0a7
TS
2081#ifdef PCI_MAP_FIXUP
2082 struct resource_list_entry *rle;
2083#endif /* PCI_MAP_FIXUP */
984263bc 2084 pcicfgregs *cfg = &dinfo->cfg;
de67e43b 2085
984263bc
MD
2086 /*
2087 * Perform lazy resource allocation
984263bc
MD
2088 */
2089 if (device_get_parent(child) == dev) {
de67e43b
JS
2090 switch (type) {
2091 case SYS_RES_IRQ:
2092#ifdef __i386__
984263bc
MD
2093 /*
2094 * If device doesn't have an interrupt routed, and is
2095 * deserving of an interrupt, try to assign it one.
2096 */
de67e43b
JS
2097 if ((cfg->intline == 255 || cfg->intline == 0) &&
2098 (cfg->intpin != 0) &&
2099 (start == 0) && (end == ~0UL)) {
2100 cfg->intline = PCIB_ROUTE_INTERRUPT(
2101 device_get_parent(dev), child,
2102 cfg->intpin);
2103 if (cfg->intline != 255) {
2104 pci_write_config(child, PCIR_INTLINE,
2105 cfg->intline, 1);
2106 resource_list_add(rl, SYS_RES_IRQ, 0,
2107 cfg->intline, cfg->intline, 1);
2108 }
2109 }
820c1612 2110 break;
de67e43b
JS
2111#endif
2112 case SYS_RES_IOPORT:
201eb0a7 2113 /* FALLTHROUGH */
de67e43b
JS
2114 case SYS_RES_MEMORY:
2115 if (*rid < PCIR_BAR(cfg->nummaps)) {
2116 /*
2117 * Enable the I/O mode. We should
2118 * also be assigning resources too
2119 * when none are present. The
2120 * resource_list_alloc kind of sorta does
2121 * this...
2122 */
2123 if (PCI_ENABLE_IO(dev, child, type))
2124 return (NULL);
984263bc 2125 }
201eb0a7
TS
2126#ifdef PCI_MAP_FIXUP
2127 rle = resource_list_find(rl, type, *rid);
2128 if (rle == NULL)
2129 return pci_alloc_map(dev, child, type, rid,
2130 start, end, count, flags);
2131#endif /* PCI_MAP_FIXUP */
820c1612 2132 break;
984263bc 2133 }
201eb0a7
TS
2134#ifdef PCI_MAP_FIXUP
2135 /*
2136 * If we've already allocated the resource, then
2137 * return it now. But first we may need to activate
2138 * it, since we don't allocate the resource as active
2139 * above. Normally this would be done down in the
2140 * nexus, but since we short-circuit that path we have
2141 * to do its job here. Not sure if we should free the
2142 * resource if it fails to activate.
2143 *
2144 * Note: this also finds and returns resources for
2145 * atapci devices in legacy mode as allocated in
2146 * pci_ata_maps().
2147 */
2148 rle = resource_list_find(rl, type, *rid);
2149 if (rle != NULL && rle->res != NULL) {
2150 if (bootverbose)
2151 device_printf(child, "reserved %#lx bytes for "
2152 "rid %#x type %d at %#lx\n",
2153 rman_get_size(rle->res), *rid,
2154 type, rman_get_start(rle->res));
2155 if ((flags & RF_ACTIVE) &&
2156 bus_generic_activate_resource(dev, child, type,
2157 *rid, rle->res) != 0)
2158 return NULL;
2159 return rle->res;
2160 }
2161#endif /* PCI_MAP_FIXUP */
984263bc 2162 }
984263bc
MD
2163 return resource_list_alloc(rl, dev, child, type, rid,
2164 start, end, count, flags);
2165}
2166
2167static int
2168pci_release_resource(device_t dev, device_t child, int type, int rid,
2169 struct resource *r)
2170{
2171 struct pci_devinfo *dinfo = device_get_ivars(child);
2172 struct resource_list *rl = &dinfo->resources;
2173
2174 return resource_list_release(rl, dev, child, type, rid, r);
2175}
2176
2177static int
2178pci_set_resource(device_t dev, device_t child, int type, int rid,
2179 u_long start, u_long count)
2180{
2181 struct pci_devinfo *dinfo = device_get_ivars(child);
2182 struct resource_list *rl = &dinfo->resources;
2183
2184 resource_list_add(rl, type, rid, start, start + count - 1, count);
2185 return 0;
2186}
2187
2188static int
2189pci_get_resource(device_t dev, device_t child, int type, int rid,
2190 u_long *startp, u_long *countp)
2191{
2192 struct pci_devinfo *dinfo = device_get_ivars(child);
2193 struct resource_list *rl = &dinfo->resources;
2194 struct resource_list_entry *rle;
2195
2196 rle = resource_list_find(rl, type, rid);
2197 if (!rle)
2198 return ENOENT;
2199
2200 if (startp)
2201 *startp = rle->start;
2202 if (countp)
2203 *countp = rle->count;
2204
2205 return 0;
2206}
2207
e126caf1 2208void
984263bc
MD
2209pci_delete_resource(device_t dev, device_t child, int type, int rid)
2210{
85f8e2ea 2211 kprintf("pci_delete_resource: PCI resources can not be deleted\n");
984263bc
MD
2212}
2213
e126caf1
MD
2214struct resource_list *
2215pci_get_resource_list (device_t dev, device_t child)
2216{
b0486c83 2217 struct pci_devinfo *dinfo = device_get_ivars(child);
e126caf1 2218
b0486c83 2219 if (dinfo == NULL)
e126caf1 2220 return (NULL);
b0486c83 2221 return (&dinfo->resources);
e126caf1
MD
2222}
2223
2224u_int32_t
984263bc
MD
2225pci_read_config_method(device_t dev, device_t child, int reg, int width)
2226{
2227 struct pci_devinfo *dinfo = device_get_ivars(child);
2228 pcicfgregs *cfg = &dinfo->cfg;
4a5a2d63
JS
2229
2230 return PCIB_READ_CONFIG(device_get_parent(dev),
2231 cfg->bus, cfg->slot, cfg->func,
2232 reg, width);
984263bc
MD
2233}
2234
e126caf1 2235void
984263bc
MD
2236pci_write_config_method(device_t dev, device_t child, int reg,
2237 u_int32_t val, int width)
2238{
2239 struct pci_devinfo *dinfo = device_get_ivars(child);
2240 pcicfgregs *cfg = &dinfo->cfg;
4a5a2d63
JS
2241
2242 PCIB_WRITE_CONFIG(device_get_parent(dev),
2243 cfg->bus, cfg->slot, cfg->func,
2244 reg, val, width);
984263bc
MD
2245}
2246
e126caf1
MD
2247int
2248pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
2249 size_t buflen)
2250{
2251 struct pci_devinfo *dinfo;
2252
2253 dinfo = device_get_ivars(child);
f8c7a42d 2254 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
e126caf1
MD
2255 pci_get_function(child));
2256 return (0);
2257}
2258
2259int
2260pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
2261 size_t buflen)
2262{
2263 struct pci_devinfo *dinfo;
2264 pcicfgregs *cfg;
2265
2266 dinfo = device_get_ivars(child);
2267 cfg = &dinfo->cfg;
f8c7a42d 2268 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
e126caf1
MD
2269 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
2270 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
2271 cfg->progif);
2272 return (0);
2273}
2274
2275int
2276pci_assign_interrupt_method(device_t dev, device_t child)
2277{
2278 struct pci_devinfo *dinfo = device_get_ivars(child);
2279 pcicfgregs *cfg = &dinfo->cfg;
2280
2281 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
2282 cfg->intpin));
2283}
2284
984263bc
MD
2285static int
2286pci_modevent(module_t mod, int what, void *arg)
2287{
2288 switch (what) {
2289 case MOD_LOAD:
2290 STAILQ_INIT(&pci_devq);
2291 break;
984263bc
MD
2292 case MOD_UNLOAD:
2293 break;
2294 }
2295
2296 return 0;
2297}
2298
638744c5
HT
2299void
2300pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
2301{
2302 int i;
2303
2304 /*
2305 * Only do header type 0 devices. Type 1 devices are bridges,
2306 * which we know need special treatment. Type 2 devices are
2307 * cardbus bridges which also require special treatment.
2308 * Other types are unknown, and we err on the side of safety
2309 * by ignoring them.
2310 */
2311 if (dinfo->cfg.hdrtype != 0)
2312 return;
2313
2314 /*
2315 * Restore the device to full power mode. We must do this
2316 * before we restore the registers because moving from D3 to
2317 * D0 will cause the chip's BARs and some other registers to
2318 * be reset to some unknown power on reset values. Cut down
2319 * the noise on boot by doing nothing if we are already in
2320 * state D0.
2321 */
2322 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
2323 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
2324 }
2325 for (i = 0; i < dinfo->cfg.nummaps; i++)
2326 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
2327 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
2328 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
2329 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
2330 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
2331 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
2332 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
2333 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
2334 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
2335 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
2336 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
2337#if 0
2338 /* Restore MSI and MSI-X configurations if they are present. */
2339 if (dinfo->cfg.msi.msi_location != 0)
2340 pci_resume_msi(dev);
2341 if (dinfo->cfg.msix.msix_location != 0)
2342 pci_resume_msix(dev);
2343#endif
2344}
2345
2346void
2347pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
2348{
2349 int i;
2350 uint32_t cls;
2351 int ps;
2352
2353 /*
2354 * Only do header type 0 devices. Type 1 devices are bridges, which
2355 * we know need special treatment. Type 2 devices are cardbus bridges
2356 * which also require special treatment. Other types are unknown, and
2357 * we err on the side of safety by ignoring them. Powering down
2358 * bridges should not be undertaken lightly.
2359 */
2360 if (dinfo->cfg.hdrtype != 0)
2361 return;
2362 for (i = 0; i < dinfo->cfg.nummaps; i++)
2363 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
2364 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
2365
2366 /*
2367 * Some drivers apparently write to these registers w/o updating our
2368 * cached copy. No harm happens if we update the copy, so do so here
2369 * so we can restore them. The COMMAND register is modified by the
2370 * bus w/o updating the cache. This should represent the normally
2371 * writable portion of the 'defined' part of type 0 headers. In
2372 * theory we also need to save/restore the PCI capability structures
2373 * we know about, but apart from power we don't know any that are
2374 * writable.
2375 */
2376 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
2377 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
2378 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
2379 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
2380 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
2381 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
2382 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
2383 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
2384 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
2385 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2386 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2387 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
2388 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
2389 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
2390 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
2391
2392 /*
2393 * don't set the state for display devices, base peripherals and
2394 * memory devices since bad things happen when they are powered down.
2395 * We should (a) have drivers that can easily detach and (b) use
2396 * generic drivers for these devices so that some device actually
2397 * attaches. We need to make sure that when we implement (a) we don't
2398 * power the device down on a reattach.
2399 */
2400 cls = pci_get_class(dev);
2401 if (!setstate)
2402 return;
2403
2404 switch (pci_do_power_nodriver)
2405 {
2406 case 0: /* NO powerdown at all */
2407 return;
2408 case 1: /* Conservative about what to power down */
2409 if (cls == PCIC_STORAGE)
2410 return;
2411 /*FALLTHROUGH*/
2412 case 2: /* Agressive about what to power down */
2413 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
2414 cls == PCIC_BASEPERIPH)
2415 return;
2416 /*FALLTHROUGH*/
2417 case 3: /* Power down everything */
2418 break;
2419 }
2420
2421 if (cls == PCIC_STORAGE)
2422 return;
2423
2424 /*
2425 * PCI spec says we can only go into D3 state from D0 state.
2426 * Transition from D[12] into D0 before going to D3 state.
2427 */
2428 ps = pci_get_powerstate(dev);
2429 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
2430 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
2431 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
2432 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
2433}
2434
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2435int
2436pci_resume(device_t dev)
2437{
2438 int numdevs;
2439 int i;
2440 device_t *children;
2441 device_t child;
2442 struct pci_devinfo *dinfo;
2443 pcicfgregs *cfg;
2444
2445 device_get_children(dev, &children, &numdevs);
2446
2447 for (i = 0; i < numdevs; i++) {
2448 child = children[i];
2449
2450 dinfo = device_get_ivars(child);
2451 cfg = &dinfo->cfg;
2452 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2453 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
2454 if (PCI_INTERRUPT_VALID(cfg->intline)) {
2455 pci_write_config(child, PCIR_INTLINE,
2456 cfg->intline, 1);
2457 }
2458 }
2459 }
2460
efda3bd0 2461 kfree(children, M_TEMP);
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2462
2463 return (bus_generic_resume(dev));
2464}
2465
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2466void
2467pci_driver_added(device_t dev, driver_t *driver)
2468{
2469 int numdevs;
2470 device_t *devlist;
2471 device_t child;
2472 struct pci_devinfo *dinfo;
2473 int i;
2474
2475 if (bootverbose)
2476 device_printf(dev, "driver added\n");
2477 DEVICE_IDENTIFY(driver, dev);
2478 device_get_children(dev, &devlist, &numdevs);
2479 for (i = 0; i < numdevs; i++) {
2480 child = devlist[i];
2481 if (device_get_state(child) != DS_NOTPRESENT)
2482 continue;
2483 dinfo = device_get_ivars(child);
2484 pci_print_verbose(dinfo);
2485 if (bootverbose)
2486 kprintf("pci%d:%d:%d: reprobing on driver added\n",
2487 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func);
2488 pci_cfg_restore(child, dinfo);
2489 if (device_probe_and_attach(child) != 0)
2490 pci_cfg_save(child, dinfo, 1);
2491 }
2492 kfree(devlist, M_TEMP);
2493}
2494
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2495static void
2496pci_child_detached(device_t parent __unused, device_t child) {
2497 /* Turn child's power off */
2498 pci_cfg_save(child, device_get_ivars(child), 1);
2499}
2500
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2501static device_method_t pci_methods[] = {
2502 /* Device interface */
4a5a2d63 2503 DEVMETHOD(device_probe, pci_probe),
e126caf1 2504 DEVMETHOD(device_attach, pci_attach),
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2505 DEVMETHOD(device_shutdown, bus_generic_shutdown),
2506 DEVMETHOD(device_suspend, bus_generic_suspend),
e126caf1 2507 DEVMETHOD(device_resume, pci_resume),
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2508
2509 /* Bus interface */
2510 DEVMETHOD(bus_print_child, pci_print_child),
2511 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
2512 DEVMETHOD(bus_read_ivar, pci_read_ivar),
2513 DEVMETHOD(bus_write_ivar, pci_write_ivar),
638744c5 2514 DEVMETHOD(bus_driver_added, pci_driver_added),
72876ce0 2515 DEVMETHOD(bus_child_detached, pci_child_detached),
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2516 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
2517 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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2518
2519 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
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2520 DEVMETHOD(bus_set_resource, pci_set_resource),
2521 DEVMETHOD(bus_get_resource, pci_get_resource),
2522 DEVMETHOD(bus_delete_resource, pci_delete_resource),
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2523 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
2524 DEVMETHOD(bus_release_resource, pci_release_resource),
2525 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
2526 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
2527 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
2528 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
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2529
2530 /* PCI interface */
2531 DEVMETHOD(pci_read_config, pci_read_config_method),
2532 DEVMETHOD(pci_write_config, pci_write_config_method),
2533 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
2534 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
2535 DEVMETHOD(pci_enable_io, pci_enable_io_method),
2536 DEVMETHOD(pci_disable_io, pci_disable_io_method),
2537 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
2538 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
e126caf1 2539 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
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2540
2541 { 0, 0 }
2542};
2543
3aef8050 2544driver_t pci_driver = {
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2545 "pci",
2546 pci_methods,
2547 1, /* no softc */
2548};
2549
2550DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
261fa16d 2551MODULE_VERSION(pci, 1);