When read BBP registers, avoid writing to BBPCSR until it is no longer busy.
[dragonfly.git] / sys / dev / serial / rc / rc.c
CommitLineData
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1/*
2 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
3 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/i386/isa/rc.c,v 1.53.2.1 2001/02/26 04:23:10 jlemon Exp $
e3869ec7 28 * $DragonFly: src/sys/dev/serial/rc/rc.c,v 1.22 2006/12/22 23:26:24 swildner Exp $
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29 *
30 */
31
32/*
33 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver
34 *
35 */
36
1f2de5d4 37#include "use_rc.h"
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38
39/*#define RCDEBUG*/
40
41#include <sys/param.h>
42#include <sys/systm.h>
43#include <sys/tty.h>
44#include <sys/proc.h>
45#include <sys/conf.h>
46#include <sys/dkstat.h>
47#include <sys/fcntl.h>
48#include <sys/interrupt.h>
49#include <sys/kernel.h>
8d77660e 50#include <sys/thread2.h>
984263bc 51#include <machine/clock.h>
984263bc 52
1f2de5d4 53#include <bus/isa/i386/isa_device.h>
984263bc 54
a9295349 55#include <machine_base/isa/ic/cd180.h>
1f2de5d4 56#include "rcreg.h"
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57
58/* Prototypes */
5ca58d54
RG
59static int rcprobe (struct isa_device *);
60static int rcattach (struct isa_device *);
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61
62#define rcin(port) RC_IN (nec, port)
63#define rcout(port,v) RC_OUT (nec, port, v)
64
65#define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__)
66#define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd))
67
68#define RC_IBUFSIZE 256
69#define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE)
70#define RC_OBUFSIZE 512
71#define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4)
72#define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE)
73#define LOTS_OF_EVENTS 64
74
75#define RC_FAKEID 0x10
76
77#define RC_PROBED 1
78#define RC_ATTACHED 2
79
80#define GET_UNIT(dev) (minor(dev) & 0x3F)
81#define CALLOUT(dev) (minor(dev) & 0x80)
82
83/* For isa routines */
84struct isa_driver rcdriver = {
85 rcprobe, rcattach, "rc"
86};
87
88static d_open_t rcopen;
89static d_close_t rcclose;
90static d_ioctl_t rcioctl;
91
92#define CDEV_MAJOR 63
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93static struct dev_ops rc_ops = {
94 { "rc", CDEV_MAJOR, D_TTY | D_KQFILTER },
95 .d_open = rcopen,
96 .d_close = rcclose,
97 .d_read = ttyread,
98 .d_write = ttywrite,
99 .d_ioctl = rcioctl,
100 .d_poll = ttypoll,
101 .d_kqfilter = ttykqfilter
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102};
103
104/* Per-board structure */
105static struct rc_softc {
106 u_int rcb_probed; /* 1 - probed, 2 - attached */
107 u_int rcb_addr; /* Base I/O addr */
108 u_int rcb_unit; /* unit # */
109 u_char rcb_dtr; /* DTR status */
110 struct rc_chans *rcb_baserc; /* base rc ptr */
111} rc_softc[NRC];
112
113/* Per-channel structure */
114static struct rc_chans {
115 struct rc_softc *rc_rcb; /* back ptr */
116 u_short rc_flags; /* Misc. flags */
117 int rc_chan; /* Channel # */
118 u_char rc_ier; /* intr. enable reg */
119 u_char rc_msvr; /* modem sig. status */
120 u_char rc_cor2; /* options reg */
121 u_char rc_pendcmd; /* special cmd pending */
122 u_int rc_dtrwait; /* dtr timeout */
123 u_int rc_dcdwaits; /* how many waits DCD in open */
124 u_char rc_hotchar; /* end packed optimize */
125 struct tty *rc_tp; /* tty struct */
126 u_char *rc_iptr; /* Chars input buffer */
127 u_char *rc_hiwat; /* hi-water mark */
128 u_char *rc_bufend; /* end of buffer */
129 u_char *rc_optr; /* ptr in output buf */
130 u_char *rc_obufend; /* end of output buf */
7a08a71e 131 struct callout rc_dtr_ch;
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132 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */
133 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */
134} rc_chans[NRC * CD180_NCHAN];
135
136static int rc_scheduled_event = 0;
7a08a71e 137static struct callout rc_wakeup_ch;
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138
139/* for pstat -t */
140static struct tty rc_tty[NRC * CD180_NCHAN];
141static const int nrc_tty = NRC * CD180_NCHAN;
142
143/* Flags */
144#define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */
145#define RC_ACTOUT 0x0002 /* Dial-out port active */
146#define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */
147#define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */
148#define RC_DORXFER 0x0010 /* RXFER event planned */
149#define RC_DOXXFER 0x0020 /* XXFER event planned */
150#define RC_MODCHG 0x0040 /* Modem status changed */
151#define RC_OSUSP 0x0080 /* Output suspended */
152#define RC_OSBUSY 0x0100 /* start() routine in progress */
153#define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */
154#define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */
155#define RC_SEND_RDY 0x0800 /* ready to send */
156
157/* Table for translation of RCSR status bits to internal form */
158static int rc_rcsrt[16] = {
159 0, TTY_OE, TTY_FE,
160 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE,
161 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI,
162 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE,
163 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE,
164 TTY_BI|TTY_PE|TTY_FE|TTY_OE
165};
166
167/* Static prototypes */
477d3c1c 168static inthand2_t rcintr;
5ca58d54
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169static void rc_hwreset (int, int, unsigned int);
170static int rc_test (int, int);
171static void rc_discard_output (struct rc_chans *);
172static void rc_hardclose (struct rc_chans *);
173static int rc_modctl (struct rc_chans *, int, int);
174static void rc_start (struct tty *);
175static void rc_stop (struct tty *, int rw);
176static int rc_param (struct tty *, struct termios *);
7b95be2a 177static inthand2_t rcpoll;
5ca58d54 178static void rc_reinit (struct rc_softc *);
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179#ifdef RCDEBUG
180static void printrcflags();
181#endif
182static timeout_t rc_dtrwakeup;
183static timeout_t rc_wakeup;
5ca58d54
RG
184static void disc_optim (struct tty *tp, struct termios *t, struct rc_chans *);
185static void rc_wait0 (int nec, int unit, int chan, int line);
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186
187/**********************************************/
188
189/* Quick device probing */
190static int
191rcprobe(dvp)
192 struct isa_device *dvp;
193{
194 int irq = ffs(dvp->id_irq) - 1;
c9faf524 195 int nec = dvp->id_iobase;
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196
197 if (dvp->id_unit > NRC)
198 return 0;
199 if (!RC_VALIDADDR(nec)) {
e3869ec7 200 kprintf("rc%d: illegal base address %x\n", dvp->id_unit, nec);
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201 return 0;
202 }
203 if (!RC_VALIDIRQ(irq)) {
e3869ec7 204 kprintf("rc%d: illegal IRQ value %d\n", dvp->id_unit, irq);
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205 return 0;
206 }
207 rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */
208 rcout(CD180_PPRH, 0x11);
209 if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11)
210 return 0;
211 /* Now, test the board more thoroughly, with diagnostic */
212 if (rc_test(nec, dvp->id_unit))
213 return 0;
214 rc_softc[dvp->id_unit].rcb_probed = RC_PROBED;
215
216 return 0xF;
217}
218
219static int
220rcattach(dvp)
221 struct isa_device *dvp;
222{
c9faf524 223 int chan, nec = dvp->id_iobase;
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224 struct rc_softc *rcb = &rc_softc[dvp->id_unit];
225 struct rc_chans *rc = &rc_chans[dvp->id_unit * CD180_NCHAN];
226 static int rc_started = 0;
227 struct tty *tp;
228
477d3c1c 229 dvp->id_intr = rcintr;
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230
231 /* Thorooughly test the device */
232 if (rcb->rcb_probed != RC_PROBED)
233 return 0;
234 rcb->rcb_addr = nec;
235 rcb->rcb_dtr = 0;
236 rcb->rcb_baserc = rc;
237 rcb->rcb_unit = dvp->id_unit;
238 /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/
e3869ec7 239 kprintf("rc%d: %d chans, firmware rev. %c\n", rcb->rcb_unit,
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240 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A');
241
242 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) {
7a08a71e 243 callout_init(&rc->rc_dtr_ch);
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244 rc->rc_rcb = rcb;
245 rc->rc_chan = chan;
246 rc->rc_iptr = rc->rc_ibuf;
247 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
248 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER];
249 rc->rc_flags = rc->rc_ier = rc->rc_msvr = 0;
250 rc->rc_cor2 = rc->rc_pendcmd = 0;
251 rc->rc_optr = rc->rc_obufend = rc->rc_obuf;
252 rc->rc_dtrwait = 3 * hz;
253 rc->rc_dcdwaits= 0;
254 rc->rc_hotchar = 0;
255 tp = rc->rc_tp = &rc_tty[chan + (dvp->id_unit * CD180_NCHAN)];
256 ttychars(tp);
257 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0;
258 tp->t_cflag = TTYDEF_CFLAG;
259 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
260 }
261 rcb->rcb_probed = RC_ATTACHED;
262 if (!rc_started) {
fef8985e 263 dev_ops_add(&rc_ops, -1, rcb->rcb_unit);
477d3c1c 264 register_swi(SWI_TTY, rcpoll, NULL, "rcpoll", NULL);
7a08a71e
MD
265 callout_init(&rc_wakeup_ch);
266 rc_wakeup(NULL);
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267 rc_started = 1;
268 }
269 return 1;
270}
271
272/* RC interrupt handling */
273static void
477d3c1c 274rcintr(void *arg, void *frame)
984263bc 275{
477d3c1c 276 int unit = (int)arg;
c9faf524
RG
277 struct rc_softc *rcb = &rc_softc[unit];
278 struct rc_chans *rc;
279 int nec, resid;
280 u_char val, iack, bsr, ucnt, *optr;
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MD
281 int good_data, t_state;
282
283 if (rcb->rcb_probed != RC_ATTACHED) {
e3869ec7 284 kprintf("rc%d: bogus interrupt\n", unit);
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MD
285 return;
286 }
287 nec = rcb->rcb_addr;
288
289 bsr = ~(rcin(RC_BSR));
290
291 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) {
e3869ec7 292 kprintf("rc%d: extra interrupt\n", unit);
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MD
293 rcout(CD180_EOIR, 0);
294 return;
295 }
296
297 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) {
298#ifdef RCDEBUG_DETAILED
e3869ec7 299 kprintf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr,
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MD
300 (bsr & RC_BSR_TOUT)?"TOUT ":"",
301 (bsr & RC_BSR_RXINT)?"RXINT ":"",
302 (bsr & RC_BSR_TXINT)?"TXINT ":"",
303 (bsr & RC_BSR_MOINT)?"MOINT":"");
304#endif
305 if (bsr & RC_BSR_TOUT) {
e3869ec7 306 kprintf("rc%d: hardware failure, reset board\n", unit);
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MD
307 rcout(RC_CTOUT, 0);
308 rc_reinit(rcb);
309 return;
310 }
311 if (bsr & RC_BSR_RXINT) {
312 iack = rcin(RC_PILR_RX);
313 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID));
314 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) {
e3869ec7 315 kprintf("rc%d: fake rxint: %02x\n", unit, iack);
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MD
316 goto more_intrs;
317 }
318 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
319 t_state = rc->rc_tp->t_state;
320 /* Do RTS flow control stuff */
321 if ( (rc->rc_flags & RC_RTSFLOW)
322 || !(t_state & TS_ISOPEN)
323 ) {
324 if ( ( !(t_state & TS_ISOPEN)
325 || (t_state & TS_TBLOCK)
326 )
327 && (rc->rc_msvr & MSVR_RTS)
328 )
329 rcout(CD180_MSVR,
330 rc->rc_msvr &= ~MSVR_RTS);
331 else if (!(rc->rc_msvr & MSVR_RTS))
332 rcout(CD180_MSVR,
333 rc->rc_msvr |= MSVR_RTS);
334 }
335 ucnt = rcin(CD180_RDCR) & 0xF;
336 resid = 0;
337
338 if (t_state & TS_ISOPEN) {
339 /* check for input buffer overflow */
340 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) {
341 resid = ucnt;
342 ucnt = rc->rc_bufend - rc->rc_iptr;
343 resid -= ucnt;
344 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) {
345 rc->rc_flags |= RC_WAS_BUFOVFL;
346 rc_scheduled_event++;
347 }
348 }
349 optr = rc->rc_iptr;
350 /* check foor good data */
351 if (good_data) {
352 while (ucnt-- > 0) {
353 val = rcin(CD180_RDR);
354 optr[0] = val;
355 optr[INPUT_FLAGS_SHIFT] = 0;
356 optr++;
357 rc_scheduled_event++;
358 if (val != 0 && val == rc->rc_hotchar)
359 setsofttty();
360 }
361 } else {
362 /* Store also status data */
363 while (ucnt-- > 0) {
364 iack = rcin(CD180_RCSR);
365 if (iack & RCSR_Timeout)
366 break;
367 if ( (iack & RCSR_OE)
368 && !(rc->rc_flags & RC_WAS_SILOVFL)) {
369 rc->rc_flags |= RC_WAS_SILOVFL;
370 rc_scheduled_event++;
371 }
372 val = rcin(CD180_RDR);
373 /*
374 Don't store PE if IGNPAR and BREAK if IGNBRK,
375 this hack allows "raw" tty optimization
376 works even if IGN* is set.
377 */
378 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break))
379 || ((!(iack & (RCSR_PE|RCSR_FE))
380 || !(rc->rc_tp->t_iflag & IGNPAR))
381 && (!(iack & RCSR_Break)
382 || !(rc->rc_tp->t_iflag & IGNBRK)))) {
383 if ( (iack & (RCSR_PE|RCSR_FE))
384 && (t_state & TS_CAN_BYPASS_L_RINT)
385 && ((iack & RCSR_FE)
386 || ((iack & RCSR_PE)
387 && (rc->rc_tp->t_iflag & INPCK))))
388 val = 0;
389 else if (val != 0 && val == rc->rc_hotchar)
390 setsofttty();
391 optr[0] = val;
392 optr[INPUT_FLAGS_SHIFT] = iack;
393 optr++;
394 rc_scheduled_event++;
395 }
396 }
397 }
398 rc->rc_iptr = optr;
399 rc->rc_flags |= RC_DORXFER;
400 } else
401 resid = ucnt;
402 /* Clear FIFO if necessary */
403 while (resid-- > 0) {
404 if (!good_data)
405 iack = rcin(CD180_RCSR);
406 else
407 iack = 0;
408 if (iack & RCSR_Timeout)
409 break;
410 (void) rcin(CD180_RDR);
411 }
412 goto more_intrs;
413 }
414 if (bsr & RC_BSR_MOINT) {
415 iack = rcin(RC_PILR_MODEM);
416 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) {
e3869ec7 417 kprintf("rc%d: fake moint: %02x\n", unit, iack);
984263bc
MD
418 goto more_intrs;
419 }
420 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
421 iack = rcin(CD180_MCR);
422 rc->rc_msvr = rcin(CD180_MSVR);
423 rcout(CD180_MCR, 0);
424#ifdef RCDEBUG
425 printrcflags(rc, "moint");
426#endif
427 if (rc->rc_flags & RC_CTSFLOW) {
428 if (rc->rc_msvr & MSVR_CTS)
429 rc->rc_flags |= RC_SEND_RDY;
430 else
431 rc->rc_flags &= ~RC_SEND_RDY;
432 } else
433 rc->rc_flags |= RC_SEND_RDY;
434 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) {
435 rc_scheduled_event += LOTS_OF_EVENTS;
436 rc->rc_flags |= RC_MODCHG;
437 setsofttty();
438 }
439 goto more_intrs;
440 }
441 if (bsr & RC_BSR_TXINT) {
442 iack = rcin(RC_PILR_TX);
443 if (iack != (GIVR_IT_TDI | RC_FAKEID)) {
e3869ec7 444 kprintf("rc%d: fake txint: %02x\n", unit, iack);
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MD
445 goto more_intrs;
446 }
447 rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
448 if ( (rc->rc_flags & RC_OSUSP)
449 || !(rc->rc_flags & RC_SEND_RDY)
450 )
451 goto more_intrs;
452 /* Handle breaks and other stuff */
453 if (rc->rc_pendcmd) {
454 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC);
455 rcout(CD180_TDR, CD180_C_ESC);
456 rcout(CD180_TDR, rc->rc_pendcmd);
457 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC);
458 rc->rc_pendcmd = 0;
459 goto more_intrs;
460 }
461 optr = rc->rc_optr;
462 resid = rc->rc_obufend - optr;
463 if (resid > CD180_NFIFO)
464 resid = CD180_NFIFO;
465 while (resid-- > 0)
466 rcout(CD180_TDR, *optr++);
467 rc->rc_optr = optr;
468
469 /* output completed? */
470 if (optr >= rc->rc_obufend) {
471 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy);
472#ifdef RCDEBUG
e3869ec7 473 kprintf("rc%d/%d: output completed\n", unit, rc->rc_chan);
984263bc
MD
474#endif
475 if (!(rc->rc_flags & RC_DOXXFER)) {
476 rc_scheduled_event += LOTS_OF_EVENTS;
477 rc->rc_flags |= RC_DOXXFER;
478 setsofttty();
479 }
480 }
481 }
482 more_intrs:
483 rcout(CD180_EOIR, 0); /* end of interrupt */
484 rcout(RC_CTOUT, 0);
485 bsr = ~(rcin(RC_BSR));
486 }
487}
488
489/* Feed characters to output buffer */
490static void rc_start(tp)
c9faf524 491struct tty *tp;
984263bc 492{
c9faf524 493 struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
8d77660e 494 int nec = rc->rc_rcb->rcb_addr;
984263bc
MD
495
496 if (rc->rc_flags & RC_OSBUSY)
497 return;
8d77660e 498 crit_enter();
984263bc 499 rc->rc_flags |= RC_OSBUSY;
7b95be2a 500 cpu_disable_intr();
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MD
501 if (tp->t_state & TS_TTSTOP)
502 rc->rc_flags |= RC_OSUSP;
503 else
504 rc->rc_flags &= ~RC_OSUSP;
505 /* Do RTS flow control stuff */
506 if ( (rc->rc_flags & RC_RTSFLOW)
507 && (tp->t_state & TS_TBLOCK)
508 && (rc->rc_msvr & MSVR_RTS)
509 ) {
510 rcout(CD180_CAR, rc->rc_chan);
511 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS);
512 } else if (!(rc->rc_msvr & MSVR_RTS)) {
513 rcout(CD180_CAR, rc->rc_chan);
514 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS);
515 }
7b95be2a 516 cpu_enable_intr();
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MD
517 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP))
518 goto out;
519#ifdef RCDEBUG
520 printrcflags(rc, "rcstart");
521#endif
522 ttwwakeup(tp);
523#ifdef RCDEBUG
e3869ec7 524 kprintf("rcstart: outq = %d obuf = %d\n",
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MD
525 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr);
526#endif
527 if (tp->t_state & TS_BUSY)
528 goto out; /* output still in progress ... */
529
530 if (tp->t_outq.c_cc > 0) {
531 u_int ocnt;
532
533 tp->t_state |= TS_BUSY;
534 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf);
7b95be2a 535 cpu_disable_intr();
984263bc
MD
536 rc->rc_optr = rc->rc_obuf;
537 rc->rc_obufend = rc->rc_optr + ocnt;
7b95be2a 538 cpu_enable_intr();
984263bc
MD
539 if (!(rc->rc_ier & IER_TxRdy)) {
540#ifdef RCDEBUG
e3869ec7 541 kprintf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan);
984263bc
MD
542#endif
543 rcout(CD180_CAR, rc->rc_chan);
544 rcout(CD180_IER, rc->rc_ier |= IER_TxRdy);
545 }
546 }
547out:
548 rc->rc_flags &= ~RC_OSBUSY;
8d77660e 549 crit_exit();
984263bc
MD
550}
551
552/* Handle delayed events. */
7b95be2a 553void
477d3c1c 554rcpoll(void *dummy, void *frame)
984263bc 555{
c9faf524
RG
556 struct rc_chans *rc;
557 struct rc_softc *rcb;
558 u_char *tptr, *eptr;
559 struct tty *tp;
560 int chan, icnt, nec, unit;
984263bc
MD
561
562 if (rc_scheduled_event == 0)
563 return;
564repeat:
565 for (unit = 0; unit < NRC; unit++) {
566 rcb = &rc_softc[unit];
567 rc = rcb->rcb_baserc;
568 nec = rc->rc_rcb->rcb_addr;
569 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) {
570 tp = rc->rc_tp;
571#ifdef RCDEBUG
572 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG|
573 RC_WAS_BUFOVFL|RC_WAS_SILOVFL))
574 printrcflags(rc, "rcevent");
575#endif
576 if (rc->rc_flags & RC_WAS_BUFOVFL) {
7b95be2a 577 cpu_disable_intr();
984263bc
MD
578 rc->rc_flags &= ~RC_WAS_BUFOVFL;
579 rc_scheduled_event--;
7b95be2a 580 cpu_enable_intr();
e3869ec7 581 kprintf("rc%d/%d: interrupt-level buffer overflow\n",
984263bc
MD
582 unit, chan);
583 }
584 if (rc->rc_flags & RC_WAS_SILOVFL) {
7b95be2a 585 cpu_disable_intr();
984263bc
MD
586 rc->rc_flags &= ~RC_WAS_SILOVFL;
587 rc_scheduled_event--;
7b95be2a 588 cpu_enable_intr();
e3869ec7 589 kprintf("rc%d/%d: silo overflow\n",
984263bc
MD
590 unit, chan);
591 }
592 if (rc->rc_flags & RC_MODCHG) {
7b95be2a 593 cpu_disable_intr();
984263bc
MD
594 rc->rc_flags &= ~RC_MODCHG;
595 rc_scheduled_event -= LOTS_OF_EVENTS;
7b95be2a 596 cpu_enable_intr();
984263bc
MD
597 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD));
598 }
599 if (rc->rc_flags & RC_DORXFER) {
7b95be2a 600 cpu_disable_intr();
984263bc
MD
601 rc->rc_flags &= ~RC_DORXFER;
602 eptr = rc->rc_iptr;
603 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE])
604 tptr = &rc->rc_ibuf[RC_IBUFSIZE];
605 else
606 tptr = rc->rc_ibuf;
607 icnt = eptr - tptr;
608 if (icnt > 0) {
609 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
610 rc->rc_iptr = rc->rc_ibuf;
611 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
612 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER];
613 } else {
614 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
615 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE];
616 rc->rc_hiwat =
617 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER];
618 }
619 if ( (rc->rc_flags & RC_RTSFLOW)
620 && (tp->t_state & TS_ISOPEN)
621 && !(tp->t_state & TS_TBLOCK)
622 && !(rc->rc_msvr & MSVR_RTS)
623 ) {
624 rcout(CD180_CAR, chan);
625 rcout(CD180_MSVR,
626 rc->rc_msvr |= MSVR_RTS);
627 }
628 rc_scheduled_event -= icnt;
629 }
7b95be2a 630 cpu_enable_intr();
984263bc
MD
631
632 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN))
633 goto done1;
634
635 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT)
636 && !(tp->t_state & TS_LOCAL)) {
637 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER
638 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF))
639 && !(tp->t_state & TS_TBLOCK))
640 ttyblock(tp);
641 tk_nin += icnt;
642 tk_rawcc += icnt;
643 tp->t_rawcc += icnt;
644 if (b_to_q(tptr, icnt, &tp->t_rawq))
e3869ec7 645 kprintf("rc%d/%d: tty-level buffer overflow\n",
984263bc
MD
646 unit, chan);
647 ttwakeup(tp);
648 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY)
649 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) {
650 tp->t_state &= ~TS_TTSTOP;
651 tp->t_lflag &= ~FLUSHO;
652 rc_start(tp);
653 }
654 } else {
655 for (; tptr < eptr; tptr++)
656 (*linesw[tp->t_line].l_rint)
657 (tptr[0] |
658 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp);
659 }
660done1: ;
661 }
662 if (rc->rc_flags & RC_DOXXFER) {
7b95be2a 663 cpu_disable_intr();
984263bc
MD
664 rc_scheduled_event -= LOTS_OF_EVENTS;
665 rc->rc_flags &= ~RC_DOXXFER;
666 rc->rc_tp->t_state &= ~TS_BUSY;
7b95be2a 667 cpu_enable_intr();
984263bc
MD
668 (*linesw[tp->t_line].l_start)(tp);
669 }
670 }
671 if (rc_scheduled_event == 0)
672 break;
673 }
674 if (rc_scheduled_event >= LOTS_OF_EVENTS)
675 goto repeat;
676}
677
678static void
679rc_stop(tp, rw)
c9faf524 680 struct tty *tp;
984263bc
MD
681 int rw;
682{
c9faf524 683 struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
984263bc
MD
684 u_char *tptr, *eptr;
685
686#ifdef RCDEBUG
e3869ec7 687 kprintf("rc%d/%d: rc_stop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan,
984263bc
MD
688 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":"");
689#endif
690 if (rw & FWRITE)
691 rc_discard_output(rc);
7b95be2a 692 cpu_disable_intr();
984263bc
MD
693 if (rw & FREAD) {
694 rc->rc_flags &= ~RC_DORXFER;
695 eptr = rc->rc_iptr;
696 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
697 tptr = &rc->rc_ibuf[RC_IBUFSIZE];
698 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
699 } else {
700 tptr = rc->rc_ibuf;
701 rc->rc_iptr = rc->rc_ibuf;
702 }
703 rc_scheduled_event -= eptr - tptr;
704 }
705 if (tp->t_state & TS_TTSTOP)
706 rc->rc_flags |= RC_OSUSP;
707 else
708 rc->rc_flags &= ~RC_OSUSP;
7b95be2a 709 cpu_enable_intr();
984263bc
MD
710}
711
712static int
fef8985e 713rcopen(struct dev_open_args *ap)
984263bc 714{
b13267a5 715 cdev_t dev = ap->a_head.a_dev;
c9faf524
RG
716 struct rc_chans *rc;
717 struct tty *tp;
8d77660e 718 int unit, nec, error = 0;
984263bc
MD
719
720 unit = GET_UNIT(dev);
721 if (unit >= NRC * CD180_NCHAN)
722 return ENXIO;
723 if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED)
724 return ENXIO;
725 rc = &rc_chans[unit];
726 tp = rc->rc_tp;
727 dev->si_tty = tp;
728 nec = rc->rc_rcb->rcb_addr;
729#ifdef RCDEBUG
e3869ec7 730 kprintf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
984263bc 731#endif
8d77660e 732 crit_enter();
984263bc
MD
733
734again:
735 while (rc->rc_flags & RC_DTR_OFF) {
377d4740 736 error = tsleep(&(rc->rc_dtrwait), PCATCH, "rcdtr", 0);
984263bc
MD
737 if (error != 0)
738 goto out;
739 }
740 if (tp->t_state & TS_ISOPEN) {
741 if (CALLOUT(dev)) {
742 if (!(rc->rc_flags & RC_ACTOUT)) {
743 error = EBUSY;
744 goto out;
745 }
746 } else {
747 if (rc->rc_flags & RC_ACTOUT) {
fef8985e 748 if (ap->a_oflags & O_NONBLOCK) {
984263bc
MD
749 error = EBUSY;
750 goto out;
751 }
377d4740 752 error = tsleep(&rc->rc_rcb, PCATCH, "rcbi", 0);
984263bc
MD
753 if (error)
754 goto out;
755 goto again;
756 }
757 }
758 if (tp->t_state & TS_XCLUDE &&
fef8985e 759 suser_cred(ap->a_cred, 0)) {
984263bc
MD
760 error = EBUSY;
761 goto out;
762 }
763 } else {
764 tp->t_oproc = rc_start;
765 tp->t_param = rc_param;
766 tp->t_stop = rc_stop;
767 tp->t_dev = dev;
768
769 if (CALLOUT(dev))
770 tp->t_cflag |= CLOCAL;
771 else
772 tp->t_cflag &= ~CLOCAL;
773
774 error = rc_param(tp, &tp->t_termios);
775 if (error)
776 goto out;
777 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET);
778
779 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev))
780 (*linesw[tp->t_line].l_modem)(tp, 1);
781 }
782 if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev)
fef8985e 783 && !(tp->t_cflag & CLOCAL) && !(ap->a_oflags & O_NONBLOCK)) {
984263bc 784 rc->rc_dcdwaits++;
377d4740 785 error = tsleep(TSA_CARR_ON(tp), PCATCH, "rcdcd", 0);
984263bc
MD
786 rc->rc_dcdwaits--;
787 if (error != 0)
788 goto out;
789 goto again;
790 }
791 error = (*linesw[tp->t_line].l_open)(dev, tp);
792 disc_optim(tp, &tp->t_termios, rc);
793 if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev))
794 rc->rc_flags |= RC_ACTOUT;
795out:
8d77660e 796 crit_exit();
984263bc
MD
797
798 if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN))
799 rc_hardclose(rc);
800
801 return error;
802}
803
804static int
fef8985e 805rcclose(struct dev_close_args *ap)
984263bc 806{
b13267a5 807 cdev_t dev = ap->a_head.a_dev;
c9faf524
RG
808 struct rc_chans *rc;
809 struct tty *tp;
8d77660e 810 int unit = GET_UNIT(dev);
984263bc
MD
811
812 if (unit >= NRC * CD180_NCHAN)
813 return ENXIO;
814 rc = &rc_chans[unit];
815 tp = rc->rc_tp;
816#ifdef RCDEBUG
e3869ec7 817 kprintf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
984263bc 818#endif
8d77660e 819 crit_enter();
fef8985e 820 (*linesw[tp->t_line].l_close)(tp, ap->a_fflag);
984263bc
MD
821 disc_optim(tp, &tp->t_termios, rc);
822 rc_stop(tp, FREAD | FWRITE);
823 rc_hardclose(rc);
824 ttyclose(tp);
8d77660e 825 crit_exit();
984263bc
MD
826 return 0;
827}
828
829static void rc_hardclose(rc)
c9faf524 830struct rc_chans *rc;
984263bc 831{
8d77660e 832 int nec = rc->rc_rcb->rcb_addr;
c9faf524 833 struct tty *tp = rc->rc_tp;
984263bc 834
8d77660e 835 crit_enter();
984263bc
MD
836 rcout(CD180_CAR, rc->rc_chan);
837
838 /* Disable rx/tx intrs */
839 rcout(CD180_IER, rc->rc_ier = 0);
840 if ( (tp->t_cflag & HUPCL)
841 || (!(rc->rc_flags & RC_ACTOUT)
842 && !(rc->rc_msvr & MSVR_CD)
843 && !(tp->t_cflag & CLOCAL))
844 || !(tp->t_state & TS_ISOPEN)
845 ) {
846 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
847 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
848 (void) rc_modctl(rc, TIOCM_RTS, DMSET);
849 if (rc->rc_dtrwait) {
7a08a71e
MD
850 callout_reset(&rc->rc_dtr_ch, rc->rc_dtrwait,
851 rc_dtrwakeup, rc);
984263bc
MD
852 rc->rc_flags |= RC_DTR_OFF;
853 }
854 }
855 rc->rc_flags &= ~RC_ACTOUT;
856 wakeup((caddr_t) &rc->rc_rcb); /* wake bi */
857 wakeup(TSA_CARR_ON(tp));
8d77660e 858 crit_exit();
984263bc
MD
859}
860
861/* Reset the bastard */
862static void rc_hwreset(unit, nec, chipid)
c9faf524 863 int unit, nec;
984263bc
MD
864 unsigned int chipid;
865{
866 CCRCMD(unit, -1, CCR_HWRESET); /* Hardware reset */
867 DELAY(20000);
868 WAITFORCCR(unit, -1);
869
870 rcout(RC_CTOUT, 0); /* Clear timeout */
871 rcout(CD180_GIVR, chipid);
872 rcout(CD180_GICR, 0);
873
874 /* Set Prescaler Registers (1 msec) */
875 rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF);
876 rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8);
877
878 /* Initialize Priority Interrupt Level Registers */
879 rcout(CD180_PILR1, RC_PILR_MODEM);
880 rcout(CD180_PILR2, RC_PILR_TX);
881 rcout(CD180_PILR3, RC_PILR_RX);
882
883 /* Reset DTR */
884 rcout(RC_DTREG, ~0);
885}
886
887/* Set channel parameters */
888static int rc_param(tp, ts)
c9faf524 889 struct tty *tp;
984263bc
MD
890 struct termios *ts;
891{
c9faf524
RG
892 struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
893 int nec = rc->rc_rcb->rcb_addr;
8d77660e 894 int idivs, odivs, val, cflag, iflag, lflag, inpflow;
984263bc
MD
895
896 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800
897 || ts->c_ispeed < 0 || ts->c_ispeed > 76800
898 )
899 return (EINVAL);
900 if (ts->c_ispeed == 0)
901 ts->c_ispeed = ts->c_ospeed;
902 odivs = RC_BRD(ts->c_ospeed);
903 idivs = RC_BRD(ts->c_ispeed);
904
8d77660e 905 crit_enter();
984263bc
MD
906
907 /* Select channel */
908 rcout(CD180_CAR, rc->rc_chan);
909
910 /* If speed == 0, hangup line */
911 if (ts->c_ospeed == 0) {
912 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
913 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
914 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
915 }
916
917 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
918 cflag = ts->c_cflag;
919 iflag = ts->c_iflag;
920 lflag = ts->c_lflag;
921
922 if (idivs > 0) {
923 rcout(CD180_RBPRL, idivs & 0xFF);
924 rcout(CD180_RBPRH, idivs >> 8);
925 }
926 if (odivs > 0) {
927 rcout(CD180_TBPRL, odivs & 0xFF);
928 rcout(CD180_TBPRH, odivs >> 8);
929 }
930
931 /* set timeout value */
932 if (ts->c_ispeed > 0) {
933 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1;
934
935 if ( !(lflag & ICANON)
936 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0
937 && ts->c_cc[VTIME] * 10 > itm)
938 itm = ts->c_cc[VTIME] * 10;
939
940 rcout(CD180_RTPR, itm <= 255 ? itm : 255);
941 }
942
943 switch (cflag & CSIZE) {
944 case CS5: val = COR1_5BITS; break;
945 case CS6: val = COR1_6BITS; break;
946 case CS7: val = COR1_7BITS; break;
947 default:
948 case CS8: val = COR1_8BITS; break;
949 }
950 if (cflag & PARENB) {
951 val |= COR1_NORMPAR;
952 if (cflag & PARODD)
953 val |= COR1_ODDP;
954 if (!(cflag & INPCK))
955 val |= COR1_Ignore;
956 } else
957 val |= COR1_Ignore;
958 if (cflag & CSTOPB)
959 val |= COR1_2SB;
960 rcout(CD180_COR1, val);
961
962 /* Set FIFO threshold */
963 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2;
964 inpflow = 0;
965 if ( (iflag & IXOFF)
966 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE
967 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE
968 || (iflag & IXANY)
969 )
970 )
971 ) {
972 inpflow = 1;
973 val |= COR3_SCDE|COR3_FCT;
974 }
975 rcout(CD180_COR3, val);
976
977 /* Initialize on-chip automatic flow control */
978 val = 0;
979 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY);
980 if (cflag & CCTS_OFLOW) {
981 rc->rc_flags |= RC_CTSFLOW;
982 val |= COR2_CtsAE;
983 } else
984 rc->rc_flags |= RC_SEND_RDY;
985 if (tp->t_state & TS_TTSTOP)
986 rc->rc_flags |= RC_OSUSP;
987 else
988 rc->rc_flags &= ~RC_OSUSP;
989 if (cflag & CRTS_IFLOW)
990 rc->rc_flags |= RC_RTSFLOW;
991 else
992 rc->rc_flags &= ~RC_RTSFLOW;
993
994 if (inpflow) {
995 if (ts->c_cc[VSTART] != _POSIX_VDISABLE)
996 rcout(CD180_SCHR1, ts->c_cc[VSTART]);
997 rcout(CD180_SCHR2, ts->c_cc[VSTOP]);
998 val |= COR2_TxIBE;
999 if (iflag & IXANY)
1000 val |= COR2_IXM;
1001 }
1002
1003 rcout(CD180_COR2, rc->rc_cor2 = val);
1004
1005 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1006 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1007
1008 disc_optim(tp, ts, rc);
1009
1010 /* modem ctl */
1011 val = cflag & CLOCAL ? 0 : MCOR1_CDzd;
1012 if (cflag & CCTS_OFLOW)
1013 val |= MCOR1_CTSzd;
1014 rcout(CD180_MCOR1, val);
1015
1016 val = cflag & CLOCAL ? 0 : MCOR2_CDod;
1017 if (cflag & CCTS_OFLOW)
1018 val |= MCOR2_CTSod;
1019 rcout(CD180_MCOR2, val);
1020
1021 /* enable i/o and interrupts */
1022 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1023 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS));
1024 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
1025
1026 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD;
1027 if (cflag & CCTS_OFLOW)
1028 rc->rc_ier |= IER_CTS;
1029 if (cflag & CREAD)
1030 rc->rc_ier |= IER_RxData;
1031 if (tp->t_state & TS_BUSY)
1032 rc->rc_ier |= IER_TxRdy;
1033 if (ts->c_ospeed != 0)
1034 rc_modctl(rc, TIOCM_DTR, DMBIS);
1035 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS))
1036 rc->rc_flags |= RC_SEND_RDY;
1037 rcout(CD180_IER, rc->rc_ier);
8d77660e 1038 crit_exit();
984263bc
MD
1039 return 0;
1040}
1041
1042/* Re-initialize board after bogus interrupts */
1043static void rc_reinit(rcb)
1044struct rc_softc *rcb;
1045{
c9faf524
RG
1046 struct rc_chans *rc, *rce;
1047 int nec;
984263bc
MD
1048
1049 nec = rcb->rcb_addr;
1050 rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID);
1051 rc = &rc_chans[rcb->rcb_unit * CD180_NCHAN];
1052 rce = rc + CD180_NCHAN;
1053 for (; rc < rce; rc++)
1054 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios);
1055}
1056
1057static int
fef8985e 1058rcioctl(struct dev_ioctl_args *ap)
984263bc 1059{
b13267a5 1060 cdev_t dev = ap->a_head.a_dev;
c9faf524 1061 struct rc_chans *rc = &rc_chans[GET_UNIT(dev)];
8d77660e 1062 int error;
984263bc
MD
1063 struct tty *tp = rc->rc_tp;
1064
fef8985e
MD
1065 error = (*linesw[tp->t_line].l_ioctl)(tp, ap->a_cmd, ap->a_data,
1066 ap->a_fflag, ap->a_cred);
984263bc
MD
1067 if (error != ENOIOCTL)
1068 return (error);
fef8985e 1069 error = ttioctl(tp, ap->a_cmd, ap->a_data, ap->a_fflag);
984263bc
MD
1070 disc_optim(tp, &tp->t_termios, rc);
1071 if (error != ENOIOCTL)
1072 return (error);
8d77660e 1073 crit_enter();
984263bc 1074
fef8985e 1075 switch (ap->a_cmd) {
984263bc
MD
1076 case TIOCSBRK:
1077 rc->rc_pendcmd = CD180_C_SBRK;
1078 break;
1079
1080 case TIOCCBRK:
1081 rc->rc_pendcmd = CD180_C_EBRK;
1082 break;
1083
1084 case TIOCSDTR:
1085 (void) rc_modctl(rc, TIOCM_DTR, DMBIS);
1086 break;
1087
1088 case TIOCCDTR:
1089 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
1090 break;
1091
1092 case TIOCMGET:
fef8985e 1093 *(int *) ap->a_data = rc_modctl(rc, 0, DMGET);
984263bc
MD
1094 break;
1095
1096 case TIOCMSET:
fef8985e 1097 (void) rc_modctl(rc, *(int *) ap->a_data, DMSET);
984263bc
MD
1098 break;
1099
1100 case TIOCMBIC:
fef8985e 1101 (void) rc_modctl(rc, *(int *) ap->a_data, DMBIC);
984263bc
MD
1102 break;
1103
1104 case TIOCMBIS:
fef8985e 1105 (void) rc_modctl(rc, *(int *) ap->a_data, DMBIS);
984263bc
MD
1106 break;
1107
1108 case TIOCMSDTRWAIT:
fef8985e 1109 error = suser_cred(ap->a_cred, 0);
984263bc 1110 if (error != 0) {
8d77660e 1111 crit_exit();
984263bc
MD
1112 return (error);
1113 }
fef8985e 1114 rc->rc_dtrwait = *(int *)ap->a_data * hz / 100;
984263bc
MD
1115 break;
1116
1117 case TIOCMGDTRWAIT:
fef8985e 1118 *(int *)ap->a_data = rc->rc_dtrwait * 100 / hz;
984263bc
MD
1119 break;
1120
1121 default:
8d77660e 1122 crit_exit();
984263bc
MD
1123 return ENOTTY;
1124 }
8d77660e 1125 crit_exit();
984263bc
MD
1126 return 0;
1127}
1128
1129
1130/* Modem control routines */
1131
1132static int rc_modctl(rc, bits, cmd)
c9faf524 1133struct rc_chans *rc;
984263bc
MD
1134int bits, cmd;
1135{
c9faf524 1136 int nec = rc->rc_rcb->rcb_addr;
984263bc
MD
1137 u_char *dtr = &rc->rc_rcb->rcb_dtr, msvr;
1138
1139 rcout(CD180_CAR, rc->rc_chan);
1140
1141 switch (cmd) {
1142 case DMSET:
1143 rcout(RC_DTREG, (bits & TIOCM_DTR) ?
1144 ~(*dtr |= 1 << rc->rc_chan) :
1145 ~(*dtr &= ~(1 << rc->rc_chan)));
1146 msvr = rcin(CD180_MSVR);
1147 if (bits & TIOCM_RTS)
1148 msvr |= MSVR_RTS;
1149 else
1150 msvr &= ~MSVR_RTS;
1151 if (bits & TIOCM_DTR)
1152 msvr |= MSVR_DTR;
1153 else
1154 msvr &= ~MSVR_DTR;
1155 rcout(CD180_MSVR, msvr);
1156 break;
1157
1158 case DMBIS:
1159 if (bits & TIOCM_DTR)
1160 rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan));
1161 msvr = rcin(CD180_MSVR);
1162 if (bits & TIOCM_RTS)
1163 msvr |= MSVR_RTS;
1164 if (bits & TIOCM_DTR)
1165 msvr |= MSVR_DTR;
1166 rcout(CD180_MSVR, msvr);
1167 break;
1168
1169 case DMGET:
1170 bits = TIOCM_LE;
1171 msvr = rc->rc_msvr = rcin(CD180_MSVR);
1172
1173 if (msvr & MSVR_RTS)
1174 bits |= TIOCM_RTS;
1175 if (msvr & MSVR_CTS)
1176 bits |= TIOCM_CTS;
1177 if (msvr & MSVR_DSR)
1178 bits |= TIOCM_DSR;
1179 if (msvr & MSVR_DTR)
1180 bits |= TIOCM_DTR;
1181 if (msvr & MSVR_CD)
1182 bits |= TIOCM_CD;
1183 if (~rcin(RC_RIREG) & (1 << rc->rc_chan))
1184 bits |= TIOCM_RI;
1185 return bits;
1186
1187 case DMBIC:
1188 if (bits & TIOCM_DTR)
1189 rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan)));
1190 msvr = rcin(CD180_MSVR);
1191 if (bits & TIOCM_RTS)
1192 msvr &= ~MSVR_RTS;
1193 if (bits & TIOCM_DTR)
1194 msvr &= ~MSVR_DTR;
1195 rcout(CD180_MSVR, msvr);
1196 break;
1197 }
1198 rc->rc_msvr = rcin(CD180_MSVR);
1199 return 0;
1200}
1201
1202/* Test the board. */
1203int rc_test(nec, unit)
c9faf524 1204 int nec;
984263bc
MD
1205 int unit;
1206{
1207 int chan = 0;
8d77660e 1208 int i = 0, rcnt;
984263bc
MD
1209 unsigned int iack, chipid;
1210 unsigned short divs;
1211 static u_char ctest[] = "\377\125\252\045\244\0\377";
1212#define CTLEN 8
1213#define ERR(s) { \
e3869ec7 1214 kprintf("rc%d: ", unit); kprintf s ; kprintf("\n"); \
8d77660e 1215 crit_exit(); return 1; }
984263bc
MD
1216
1217 struct rtest {
1218 u_char txbuf[CD180_NFIFO]; /* TX buffer */
1219 u_char rxbuf[CD180_NFIFO]; /* RX buffer */
1220 int rxptr; /* RX pointer */
1221 int txptr; /* TX pointer */
1222 } tchans[CD180_NCHAN];
1223
8d77660e 1224 crit_enter();
984263bc
MD
1225
1226 chipid = RC_FAKEID;
1227
1228 /* First, reset board to inital state */
1229 rc_hwreset(unit, nec, chipid);
1230
1231 divs = RC_BRD(19200);
1232
1233 /* Initialize channels */
1234 for (chan = 0; chan < CD180_NCHAN; chan++) {
1235
1236 /* Select and reset channel */
1237 rcout(CD180_CAR, chan);
1238 CCRCMD(unit, chan, CCR_ResetChan);
1239 WAITFORCCR(unit, chan);
1240
1241 /* Set speed */
1242 rcout(CD180_RBPRL, divs & 0xFF);
1243 rcout(CD180_RBPRH, divs >> 8);
1244 rcout(CD180_TBPRL, divs & 0xFF);
1245 rcout(CD180_TBPRH, divs >> 8);
1246
1247 /* set timeout value */
1248 rcout(CD180_RTPR, 0);
1249
1250 /* Establish local loopback */
1251 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB);
1252 rcout(CD180_COR2, COR2_LLM);
1253 rcout(CD180_COR3, CD180_NFIFO);
1254 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1255 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN);
1256 WAITFORCCR(unit, chan);
1257 rcout(CD180_MSVR, MSVR_RTS);
1258
1259 /* Fill TXBUF with test data */
1260 for (i = 0; i < CD180_NFIFO; i++) {
1261 tchans[chan].txbuf[i] = ctest[i];
1262 tchans[chan].rxbuf[i] = 0;
1263 }
1264 tchans[chan].txptr = tchans[chan].rxptr = 0;
1265
1266 /* Now, start transmit */
1267 rcout(CD180_IER, IER_TxMpty|IER_RxData);
1268 }
1269 /* Pseudo-interrupt poll stuff */
1270 for (rcnt = 10000; rcnt-- > 0; rcnt--) {
1271 i = ~(rcin(RC_BSR));
1272 if (i & RC_BSR_TOUT)
1273 ERR(("BSR timeout bit set\n"))
1274 else if (i & RC_BSR_TXINT) {
1275 iack = rcin(RC_PILR_TX);
1276 if (iack != (GIVR_IT_TDI | chipid))
1277 ERR(("Bad TX intr ack (%02x != %02x)\n",
1278 iack, GIVR_IT_TDI | chipid));
1279 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1280 /* If no more data to transmit, disable TX intr */
1281 if (tchans[chan].txptr >= CD180_NFIFO) {
1282 iack = rcin(CD180_IER);
1283 rcout(CD180_IER, iack & ~IER_TxMpty);
1284 } else {
1285 for (iack = tchans[chan].txptr;
1286 iack < CD180_NFIFO; iack++)
1287 rcout(CD180_TDR,
1288 tchans[chan].txbuf[iack]);
1289 tchans[chan].txptr = iack;
1290 }
1291 rcout(CD180_EOIR, 0);
1292 } else if (i & RC_BSR_RXINT) {
1293 u_char ucnt;
1294
1295 iack = rcin(RC_PILR_RX);
1296 if (iack != (GIVR_IT_RGDI | chipid) &&
1297 iack != (GIVR_IT_REI | chipid))
1298 ERR(("Bad RX intr ack (%02x != %02x)\n",
1299 iack, GIVR_IT_RGDI | chipid))
1300 chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1301 ucnt = rcin(CD180_RDCR) & 0xF;
1302 while (ucnt-- > 0) {
1303 iack = rcin(CD180_RCSR);
1304 if (iack & RCSR_Timeout)
1305 break;
1306 if (iack & 0xF)
1307 ERR(("Bad char chan %d (RCSR = %02X)\n",
1308 chan, iack))
1309 if (tchans[chan].rxptr > CD180_NFIFO)
1310 ERR(("Got extra chars chan %d\n",
1311 chan))
1312 tchans[chan].rxbuf[tchans[chan].rxptr++] =
1313 rcin(CD180_RDR);
1314 }
1315 rcout(CD180_EOIR, 0);
1316 }
1317 rcout(RC_CTOUT, 0);
1318 for (iack = chan = 0; chan < CD180_NCHAN; chan++)
1319 if (tchans[chan].rxptr >= CD180_NFIFO)
1320 iack++;
1321 if (iack == CD180_NCHAN)
1322 break;
1323 }
1324 for (chan = 0; chan < CD180_NCHAN; chan++) {
1325 /* Select and reset channel */
1326 rcout(CD180_CAR, chan);
1327 CCRCMD(unit, chan, CCR_ResetChan);
1328 }
1329
1330 if (!rcnt)
1331 ERR(("looses characters during local loopback\n"))
1332 /* Now, check data */
1333 for (chan = 0; chan < CD180_NCHAN; chan++)
1334 for (i = 0; i < CD180_NFIFO; i++)
1335 if (ctest[i] != tchans[chan].rxbuf[i])
1336 ERR(("data mismatch chan %d ptr %d (%d != %d)\n",
1337 chan, i, ctest[i], tchans[chan].rxbuf[i]))
8d77660e 1338 crit_exit();
984263bc
MD
1339 return 0;
1340}
1341
1342#ifdef RCDEBUG
1343static void printrcflags(rc, comment)
1344struct rc_chans *rc;
1345char *comment;
1346{
1347 u_short f = rc->rc_flags;
c9faf524 1348 int nec = rc->rc_rcb->rcb_addr;
984263bc 1349
e3869ec7 1350 kprintf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n",
984263bc
MD
1351 rc->rc_rcb->rcb_unit, rc->rc_chan, comment,
1352 (f & RC_DTR_OFF)?"DTR_OFF " :"",
1353 (f & RC_ACTOUT) ?"ACTOUT " :"",
1354 (f & RC_RTSFLOW)?"RTSFLOW " :"",
1355 (f & RC_CTSFLOW)?"CTSFLOW " :"",
1356 (f & RC_DORXFER)?"DORXFER " :"",
1357 (f & RC_DOXXFER)?"DOXXFER " :"",
1358 (f & RC_MODCHG) ?"MODCHG " :"",
1359 (f & RC_OSUSP) ?"OSUSP " :"",
1360 (f & RC_OSBUSY) ?"OSBUSY " :"",
1361 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"",
1362 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"",
1363 (f & RC_SEND_RDY) ?"SEND_RDY":"");
1364
1365 rcout(CD180_CAR, rc->rc_chan);
1366
e3869ec7 1367 kprintf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n",
984263bc
MD
1368 rc->rc_rcb->rcb_unit, rc->rc_chan,
1369 rcin(CD180_MSVR),
1370 rcin(CD180_IER),
1371 rcin(CD180_CCSR));
1372}
1373#endif /* RCDEBUG */
1374
1375static void
1376rc_dtrwakeup(chan)
1377 void *chan;
1378{
1379 struct rc_chans *rc;
1380
1381 rc = (struct rc_chans *)chan;
1382 rc->rc_flags &= ~RC_DTR_OFF;
1383 wakeup(&rc->rc_dtrwait);
1384}
1385
1386static void
1387rc_discard_output(rc)
1388 struct rc_chans *rc;
1389{
7b95be2a 1390 cpu_disable_intr();
984263bc
MD
1391 if (rc->rc_flags & RC_DOXXFER) {
1392 rc_scheduled_event -= LOTS_OF_EVENTS;
1393 rc->rc_flags &= ~RC_DOXXFER;
1394 }
1395 rc->rc_optr = rc->rc_obufend;
1396 rc->rc_tp->t_state &= ~TS_BUSY;
7b95be2a 1397 cpu_enable_intr();
984263bc
MD
1398 ttwwakeup(rc->rc_tp);
1399}
1400
1401static void
1402rc_wakeup(chan)
1403 void *chan;
1404{
984263bc 1405 if (rc_scheduled_event != 0) {
8d77660e 1406 crit_enter();
477d3c1c 1407 rcpoll(NULL, NULL);
8d77660e 1408 crit_exit();
984263bc 1409 }
7a08a71e 1410 callout_reset(&rc_wakeup_ch, 1, rc_wakeup, NULL);
984263bc
MD
1411}
1412
1413static void
1414disc_optim(tp, t, rc)
1415 struct tty *tp;
1416 struct termios *t;
1417 struct rc_chans *rc;
1418{
1419
1420 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
1421 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
1422 && (!(t->c_iflag & PARMRK)
1423 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
1424 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
1425 && linesw[tp->t_line].l_rint == ttyinput)
1426 tp->t_state |= TS_CAN_BYPASS_L_RINT;
1427 else
1428 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
1429 rc->rc_hotchar = linesw[tp->t_line].l_hotchar;
1430}
1431
1432static void
1433rc_wait0(nec, unit, chan, line)
1434 int nec, unit, chan, line;
1435{
1436 int rcnt;
1437
1438 for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--)
1439 DELAY(30);
1440 if (rcnt == 0)
e3869ec7 1441 kprintf("rc%d/%d: channel command timeout, rc.c line: %d\n",
984263bc
MD
1442 unit, chan, line);
1443}