Fix whitespace in copyright dates.
[dragonfly.git] / sys / bus / pci / pci.c
CommitLineData
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1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
ed1bd994 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.23 2005/02/04 02:52:15 dillon Exp $
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28 *
29 */
30
31#include "opt_bus.h"
32#include "opt_pci.h"
33
34#include "opt_simos.h"
dc5a7bd2 35#include "opt_compat_oldpci.h"
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36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/malloc.h>
40#include <sys/module.h>
41#include <sys/fcntl.h>
42#include <sys/conf.h>
43#include <sys/kernel.h>
44#include <sys/queue.h>
45#include <sys/types.h>
46#include <sys/buf.h>
47
48#include <vm/vm.h>
49#include <vm/pmap.h>
50#include <vm/vm_extern.h>
51
52#include <sys/bus.h>
53#include <machine/bus.h>
54#include <sys/rman.h>
55#include <machine/resource.h>
56#include <machine/md_var.h> /* For the Alpha */
57#ifdef __i386__
bbca97bc 58#include <bus/pci/i386/pci_cfgreg.h>
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59#endif
60
dc5a7bd2 61#include <sys/pciio.h>
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62#include "pcireg.h"
63#include "pcivar.h"
22457186 64#include "pci_private.h"
984263bc 65
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66#include "pcib_if.h"
67
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68#ifdef __alpha__
69#include <machine/rpb.h>
70#endif
71
72#ifdef APIC_IO
73#include <machine/smp.h>
74#endif /* APIC_IO */
75
e126caf1 76devclass_t pci_devclass;
dc5a7bd2 77
4a5a2d63 78static void pci_read_extcap(device_t dev, pcicfgregs *cfg);
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79
80struct pci_quirk {
81 u_int32_t devid; /* Vendor/device of the card */
82 int type;
3e4db402 83#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
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84 int arg1;
85 int arg2;
86};
87
88struct pci_quirk pci_quirks[] = {
89 /*
90 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
91 */
92 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
93 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
94
95 { 0 }
96};
97
98/* map register information */
99#define PCI_MAPMEM 0x01 /* memory map */
100#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
101#define PCI_MAPPORT 0x04 /* port map */
102
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103static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
104u_int32_t pci_numdevs = 0;
105static u_int32_t pci_generation = 0;
106
107device_t
108pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func)
109{
110 struct pci_devinfo *dinfo;
111
112 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
113 if ((dinfo->cfg.bus == bus) &&
114 (dinfo->cfg.slot == slot) &&
115 (dinfo->cfg.func == func)) {
116 return (dinfo->cfg.dev);
117 }
118 }
119
120 return (NULL);
121}
122
123device_t
124pci_find_device (u_int16_t vendor, u_int16_t device)
125{
126 struct pci_devinfo *dinfo;
127
128 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
129 if ((dinfo->cfg.vendor == vendor) &&
130 (dinfo->cfg.device == device)) {
131 return (dinfo->cfg.dev);
132 }
133 }
134
135 return (NULL);
136}
137
138/* return base address of memory or port map */
139
140static u_int32_t
141pci_mapbase(unsigned mapreg)
142{
143 int mask = 0x03;
144 if ((mapreg & 0x01) == 0)
145 mask = 0x0f;
146 return (mapreg & ~mask);
147}
148
149/* return map type of memory or port map */
150
151static int
152pci_maptype(unsigned mapreg)
153{
154 static u_int8_t maptype[0x10] = {
155 PCI_MAPMEM, PCI_MAPPORT,
156 PCI_MAPMEM, 0,
157 PCI_MAPMEM, PCI_MAPPORT,
158 0, 0,
159 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
160 PCI_MAPMEM|PCI_MAPMEMP, 0,
161 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
162 0, 0,
163 };
164
165 return maptype[mapreg & 0x0f];
166}
167
168/* return log2 of map size decoded for memory or port map */
169
170static int
171pci_mapsize(unsigned testval)
172{
173 int ln2size;
174
175 testval = pci_mapbase(testval);
176 ln2size = 0;
177 if (testval != 0) {
178 while ((testval & 1) == 0)
179 {
180 ln2size++;
181 testval >>= 1;
182 }
183 }
184 return (ln2size);
185}
186
187/* return log2 of address range supported by map register */
188
189static int
190pci_maprange(unsigned mapreg)
191{
192 int ln2range = 0;
193 switch (mapreg & 0x07) {
194 case 0x00:
195 case 0x01:
196 case 0x05:
197 ln2range = 32;
198 break;
199 case 0x02:
200 ln2range = 20;
201 break;
202 case 0x04:
203 ln2range = 64;
204 break;
205 }
206 return (ln2range);
207}
208
209/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
210
211static void
212pci_fixancient(pcicfgregs *cfg)
213{
214 if (cfg->hdrtype != 0)
215 return;
216
217 /* PCI to PCI bridges use header type 1 */
218 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
219 cfg->hdrtype = 1;
220}
221
222/* read config data specific to header type 1 device (PCI to PCI bridge) */
223
224static void *
4a5a2d63 225pci_readppb(device_t pcib, int b, int s, int f)
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226{
227 pcih1cfgregs *p;
228
4a5a2d63 229 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
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230 if (p == NULL)
231 return (NULL);
232
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233 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
234 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
984263bc 235
4a5a2d63 236 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
984263bc 237
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238 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
239 PCIR_IOBASEH_1, 2),
240 PCIB_READ_CONFIG(pcib, b, s, f,
241 PCIR_IOBASEL_1, 1));
242 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
243 PCIR_IOLIMITH_1, 2),
244 PCIB_READ_CONFIG(pcib, b, s, f,
245 PCIR_IOLIMITL_1, 1));
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246
247 p->membase = PCI_PPBMEMBASE (0,
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248 PCIB_READ_CONFIG(pcib, b, s, f,
249 PCIR_MEMBASE_1, 2));
984263bc 250 p->memlimit = PCI_PPBMEMLIMIT (0,
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251 PCIB_READ_CONFIG(pcib, b, s, f,
252 PCIR_MEMLIMIT_1, 2));
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253
254 p->pmembase = PCI_PPBMEMBASE (
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255 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
256 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
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257
258 p->pmemlimit = PCI_PPBMEMLIMIT (
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259 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
260 PCIR_PMLIMITH_1, 4),
261 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
262
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263 return (p);
264}
265
266/* read config data specific to header type 2 device (PCI to CardBus bridge) */
267
268static void *
4a5a2d63 269pci_readpcb(device_t pcib, int b, int s, int f)
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270{
271 pcih2cfgregs *p;
272
4a5a2d63 273 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
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274 if (p == NULL)
275 return (NULL);
276
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277 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
278 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
984263bc 279
4a5a2d63 280 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
984263bc 281
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282 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
283 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
284 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
285 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
984263bc 286
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287 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
288 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
289 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
290 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
984263bc 291
4a5a2d63 292 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
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293 return p;
294}
295
296/* extract header type specific config data */
297
298static void
4a5a2d63 299pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
984263bc 300{
4a5a2d63 301#define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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302 switch (cfg->hdrtype) {
303 case 0:
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304 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
305 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
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306 cfg->nummaps = PCI_MAXMAPS_0;
307 break;
308 case 1:
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309 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
310 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
311 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
312 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
984263bc 313 cfg->nummaps = PCI_MAXMAPS_1;
4a5a2d63 314 cfg->hdrspec = pci_readppb(pcib, b, s, f);
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315 break;
316 case 2:
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317 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
318 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
319 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
320 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
984263bc 321 cfg->nummaps = PCI_MAXMAPS_2;
4a5a2d63 322 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
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323 break;
324 }
4a5a2d63 325#undef REG
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326}
327
328/* read configuration header into pcicfgrect structure */
329
22457186 330struct pci_devinfo *
c01b8d84 331pci_read_device(device_t pcib, int b, int s, int f, size_t size)
984263bc 332{
4a5a2d63 333#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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334
335 pcicfgregs *cfg = NULL;
336 struct pci_devinfo *devlist_entry;
337 struct devlist *devlist_head;
338
339 devlist_head = &pci_devq;
340
341 devlist_entry = NULL;
342
4a5a2d63 343 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
984263bc 344
c01b8d84 345 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
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346 if (devlist_entry == NULL)
347 return (NULL);
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348
349 cfg = &devlist_entry->cfg;
350
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351 cfg->bus = b;
352 cfg->slot = s;
353 cfg->func = f;
354 cfg->vendor = REG(PCIR_VENDOR, 2);
355 cfg->device = REG(PCIR_DEVICE, 2);
356 cfg->cmdreg = REG(PCIR_COMMAND, 2);
357 cfg->statreg = REG(PCIR_STATUS, 2);
358 cfg->baseclass = REG(PCIR_CLASS, 1);
359 cfg->subclass = REG(PCIR_SUBCLASS, 1);
360 cfg->progif = REG(PCIR_PROGIF, 1);
361 cfg->revid = REG(PCIR_REVID, 1);
e126caf1 362 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
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363 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
364 cfg->lattimer = REG(PCIR_LATTIMER, 1);
365 cfg->intpin = REG(PCIR_INTPIN, 1);
366 cfg->intline = REG(PCIR_INTLINE, 1);
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367#ifdef __alpha__
368 alpha_platform_assign_pciintr(cfg);
369#endif
370
371#ifdef APIC_IO
372 if (cfg->intpin != 0) {
373 int airq;
374
375 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
376 if (airq >= 0) {
377 /* PCI specific entry found in MP table */
378 if (airq != cfg->intline) {
379 undirect_pci_irq(cfg->intline);
380 cfg->intline = airq;
381 }
382 } else {
383 /*
384 * PCI interrupts might be redirected to the
385 * ISA bus according to some MP tables. Use the
386 * same methods as used by the ISA devices
387 * devices to find the proper IOAPIC int pin.
388 */
389 airq = isa_apic_irq(cfg->intline);
390 if ((airq >= 0) && (airq != cfg->intline)) {
391 /* XXX: undirect_pci_irq() ? */
392 undirect_isa_irq(cfg->intline);
393 cfg->intline = airq;
394 }
395 }
396 }
397#endif /* APIC_IO */
398
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399 cfg->mingnt = REG(PCIR_MINGNT, 1);
400 cfg->maxlat = REG(PCIR_MAXLAT, 1);
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401
402 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
403 cfg->hdrtype &= ~PCIM_MFDEV;
404
405 pci_fixancient(cfg);
4a5a2d63 406 pci_hdrtypedata(pcib, b, s, f, cfg);
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407
408 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
4a5a2d63 409 pci_read_extcap(pcib, cfg);
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410
411 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
412
413 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
414 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
415 devlist_entry->conf.pc_sel.pc_func = cfg->func;
416 devlist_entry->conf.pc_hdr = cfg->hdrtype;
417
418 devlist_entry->conf.pc_subvendor = cfg->subvendor;
419 devlist_entry->conf.pc_subdevice = cfg->subdevice;
420 devlist_entry->conf.pc_vendor = cfg->vendor;
421 devlist_entry->conf.pc_device = cfg->device;
422
423 devlist_entry->conf.pc_class = cfg->baseclass;
424 devlist_entry->conf.pc_subclass = cfg->subclass;
425 devlist_entry->conf.pc_progif = cfg->progif;
426 devlist_entry->conf.pc_revid = cfg->revid;
427
428 pci_numdevs++;
429 pci_generation++;
430 }
431 return (devlist_entry);
432#undef REG
433}
434
435static void
4a5a2d63 436pci_read_extcap(device_t pcib, pcicfgregs *cfg)
984263bc 437{
4a5a2d63 438#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
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439 int ptr, nextptr, ptrptr;
440
441 switch (cfg->hdrtype) {
442 case 0:
443 ptrptr = 0x34;
444 break;
445 case 2:
446 ptrptr = 0x14;
447 break;
448 default:
449 return; /* no extended capabilities support */
450 }
451 nextptr = REG(ptrptr, 1); /* sanity check? */
452
453 /*
454 * Read capability entries.
455 */
456 while (nextptr != 0) {
457 /* Sanity check */
458 if (nextptr > 255) {
459 printf("illegal PCI extended capability offset %d\n",
460 nextptr);
461 return;
462 }
463 /* Find the next entry */
464 ptr = nextptr;
465 nextptr = REG(ptr + 1, 1);
466
467 /* Process this entry */
468 switch (REG(ptr, 1)) {
469 case 0x01: /* PCI power management */
470 if (cfg->pp_cap == 0) {
471 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
472 cfg->pp_status = ptr + PCIR_POWER_STATUS;
473 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
474 if ((nextptr - ptr) > PCIR_POWER_DATA)
475 cfg->pp_data = ptr + PCIR_POWER_DATA;
476 }
477 break;
478 default:
479 break;
480 }
481 }
482#undef REG
483}
484
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485/* free pcicfgregs structure and all depending data structures */
486
22457186 487int
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488pci_freecfg(struct pci_devinfo *dinfo)
489{
490 struct devlist *devlist_head;
491
492 devlist_head = &pci_devq;
493
494 if (dinfo->cfg.hdrspec != NULL)
495 free(dinfo->cfg.hdrspec, M_DEVBUF);
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496 /* XXX this hasn't been tested */
497 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
498 free(dinfo, M_DEVBUF);
499
500 /* increment the generation count */
501 pci_generation++;
502
503 /* we're losing one device */
504 pci_numdevs--;
505 return (0);
506}
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507
508
509/*
510 * PCI power manangement
511 */
e126caf1 512int
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513pci_set_powerstate_method(device_t dev, device_t child, int state)
514{
515 struct pci_devinfo *dinfo = device_get_ivars(child);
516 pcicfgregs *cfg = &dinfo->cfg;
517 u_int16_t status;
518 int result;
519
520 if (cfg->pp_cap != 0) {
521 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK;
522 result = 0;
523 switch (state) {
524 case PCI_POWERSTATE_D0:
525 status |= PCIM_PSTAT_D0;
526 break;
527 case PCI_POWERSTATE_D1:
528 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) {
529 status |= PCIM_PSTAT_D1;
530 } else {
531 result = EOPNOTSUPP;
532 }
533 break;
534 case PCI_POWERSTATE_D2:
535 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) {
536 status |= PCIM_PSTAT_D2;
537 } else {
538 result = EOPNOTSUPP;
539 }
540 break;
541 case PCI_POWERSTATE_D3:
542 status |= PCIM_PSTAT_D3;
543 break;
544 default:
545 result = EINVAL;
546 }
547 if (result == 0)
548 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2);
549 } else {
550 result = ENXIO;
551 }
552 return(result);
553}
554
e126caf1 555int
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556pci_get_powerstate_method(device_t dev, device_t child)
557{
558 struct pci_devinfo *dinfo = device_get_ivars(child);
559 pcicfgregs *cfg = &dinfo->cfg;
560 u_int16_t status;
561 int result;
562
563 if (cfg->pp_cap != 0) {
564 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2);
565 switch (status & PCIM_PSTAT_DMASK) {
566 case PCIM_PSTAT_D0:
567 result = PCI_POWERSTATE_D0;
568 break;
569 case PCIM_PSTAT_D1:
570 result = PCI_POWERSTATE_D1;
571 break;
572 case PCIM_PSTAT_D2:
573 result = PCI_POWERSTATE_D2;
574 break;
575 case PCIM_PSTAT_D3:
576 result = PCI_POWERSTATE_D3;
577 break;
578 default:
579 result = PCI_POWERSTATE_UNKNOWN;
580 break;
581 }
582 } else {
583 /* No support, device is always at D0 */
584 result = PCI_POWERSTATE_D0;
585 }
586 return(result);
587}
588
589/*
590 * Some convenience functions for PCI device drivers.
591 */
592
593static __inline void
594pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
595{
596 u_int16_t command;
597
598 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
599 command |= bit;
600 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
601}
602
603static __inline void
604pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
605{
606 u_int16_t command;
607
608 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
609 command &= ~bit;
610 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
611}
612
e126caf1 613int
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614pci_enable_busmaster_method(device_t dev, device_t child)
615{
616 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 617 return(0);
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618}
619
e126caf1 620int
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621pci_disable_busmaster_method(device_t dev, device_t child)
622{
623 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 624 return(0);
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625}
626
e126caf1 627int
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628pci_enable_io_method(device_t dev, device_t child, int space)
629{
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630 uint16_t command;
631 uint16_t bit;
632 char *error;
633
634 bit = 0;
635 error = NULL;
636
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637 switch(space) {
638 case SYS_RES_IOPORT:
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639 bit = PCIM_CMD_PORTEN;
640 error = "port";
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641 break;
642 case SYS_RES_MEMORY:
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643 bit = PCIM_CMD_MEMEN;
644 error = "memory";
984263bc 645 break;
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MD
646 default:
647 return(EINVAL);
984263bc 648 }
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649 pci_set_command_bit(dev, child, bit);
650 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
651 if (command & bit)
652 return(0);
653 device_printf(child, "failed to enable %s mapping!\n", error);
654 return(ENXIO);
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655}
656
e126caf1 657int
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658pci_disable_io_method(device_t dev, device_t child, int space)
659{
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660 uint16_t command;
661 uint16_t bit;
662 char *error;
663
664 bit = 0;
665 error = NULL;
666
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667 switch(space) {
668 case SYS_RES_IOPORT:
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669 bit = PCIM_CMD_PORTEN;
670 error = "port";
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671 break;
672 case SYS_RES_MEMORY:
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673 bit = PCIM_CMD_MEMEN;
674 error = "memory";
984263bc 675 break;
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676 default:
677 return (EINVAL);
984263bc 678 }
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679 pci_clear_command_bit(dev, child, bit);
680 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
681 if (command & bit) {
682 device_printf(child, "failed to disable %s mapping!\n", error);
683 return (ENXIO);
684 }
685 return (0);
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686}
687
688/*
689 * This is the user interface to PCI configuration space.
690 */
691
692static int
41c20dac 693pci_open(dev_t dev, int oflags, int devtype, struct thread *td)
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694{
695 if ((oflags & FWRITE) && securelevel > 0) {
696 return EPERM;
697 }
698 return 0;
699}
700
701static int
41c20dac 702pci_close(dev_t dev, int flag, int devtype, struct thread *td)
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703{
704 return 0;
705}
706
707/*
708 * Match a single pci_conf structure against an array of pci_match_conf
709 * structures. The first argument, 'matches', is an array of num_matches
710 * pci_match_conf structures. match_buf is a pointer to the pci_conf
711 * structure that will be compared to every entry in the matches array.
712 * This function returns 1 on failure, 0 on success.
713 */
714static int
715pci_conf_match(struct pci_match_conf *matches, int num_matches,
716 struct pci_conf *match_buf)
717{
718 int i;
719
720 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
721 return(1);
722
723 for (i = 0; i < num_matches; i++) {
724 /*
725 * I'm not sure why someone would do this...but...
726 */
727 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
728 continue;
729
730 /*
731 * Look at each of the match flags. If it's set, do the
732 * comparison. If the comparison fails, we don't have a
733 * match, go on to the next item if there is one.
734 */
735 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
736 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
737 continue;
738
739 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
740 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
741 continue;
742
743 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
744 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
745 continue;
746
747 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
748 && (match_buf->pc_vendor != matches[i].pc_vendor))
749 continue;
750
751 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
752 && (match_buf->pc_device != matches[i].pc_device))
753 continue;
754
755 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
756 && (match_buf->pc_class != matches[i].pc_class))
757 continue;
758
759 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
760 && (match_buf->pd_unit != matches[i].pd_unit))
761 continue;
762
763 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
764 && (strncmp(matches[i].pd_name, match_buf->pd_name,
765 sizeof(match_buf->pd_name)) != 0))
766 continue;
767
768 return(0);
769 }
770
771 return(1);
772}
773
774/*
775 * Locate the parent of a PCI device by scanning the PCI devlist
776 * and return the entry for the parent.
777 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
778 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
779 */
780
781pcicfgregs *
782pci_devlist_get_parent(pcicfgregs *cfg)
783{
784 struct devlist *devlist_head;
785 struct pci_devinfo *dinfo;
786 pcicfgregs *bridge_cfg;
787 int i;
788
789 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
790
791 /* If the device is on PCI bus 0, look for the host */
792 if (cfg->bus == 0) {
793 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
794 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
795 bridge_cfg = &dinfo->cfg;
796 if (bridge_cfg->baseclass == PCIC_BRIDGE
797 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
798 && bridge_cfg->bus == cfg->bus) {
799 return bridge_cfg;
800 }
801 }
802 }
803
804 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
805 if (cfg->bus > 0) {
806 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
807 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
808 bridge_cfg = &dinfo->cfg;
809 if (bridge_cfg->baseclass == PCIC_BRIDGE
810 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
811 && bridge_cfg->secondarybus == cfg->bus) {
812 return bridge_cfg;
813 }
814 }
815 }
816
817 return NULL;
818}
819
820static int
41c20dac 821pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td)
984263bc 822{
4a5a2d63 823 device_t pci, pcib;
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824 struct pci_io *io;
825 const char *name;
826 int error;
827
828 if (!(flag & FWRITE))
829 return EPERM;
830
831
832 switch(cmd) {
833 case PCIOCGETCONF:
834 {
835 struct pci_devinfo *dinfo;
836 struct pci_conf_io *cio;
837 struct devlist *devlist_head;
838 struct pci_match_conf *pattern_buf;
839 int num_patterns;
840 size_t iolen;
841 int ionum, i;
842
843 cio = (struct pci_conf_io *)data;
844
845 num_patterns = 0;
846 dinfo = NULL;
847
848 /*
849 * Hopefully the user won't pass in a null pointer, but it
850 * can't hurt to check.
851 */
852 if (cio == NULL) {
853 error = EINVAL;
854 break;
855 }
856
857 /*
858 * If the user specified an offset into the device list,
859 * but the list has changed since they last called this
860 * ioctl, tell them that the list has changed. They will
861 * have to get the list from the beginning.
862 */
863 if ((cio->offset != 0)
864 && (cio->generation != pci_generation)){
865 cio->num_matches = 0;
866 cio->status = PCI_GETCONF_LIST_CHANGED;
867 error = 0;
868 break;
869 }
870
871 /*
872 * Check to see whether the user has asked for an offset
873 * past the end of our list.
874 */
875 if (cio->offset >= pci_numdevs) {
876 cio->num_matches = 0;
877 cio->status = PCI_GETCONF_LAST_DEVICE;
878 error = 0;
879 break;
880 }
881
882 /* get the head of the device queue */
883 devlist_head = &pci_devq;
884
885 /*
886 * Determine how much room we have for pci_conf structures.
887 * Round the user's buffer size down to the nearest
888 * multiple of sizeof(struct pci_conf) in case the user
889 * didn't specify a multiple of that size.
890 */
891 iolen = min(cio->match_buf_len -
892 (cio->match_buf_len % sizeof(struct pci_conf)),
893 pci_numdevs * sizeof(struct pci_conf));
894
895 /*
896 * Since we know that iolen is a multiple of the size of
897 * the pciconf union, it's okay to do this.
898 */
899 ionum = iolen / sizeof(struct pci_conf);
900
901 /*
902 * If this test is true, the user wants the pci_conf
903 * structures returned to match the supplied entries.
904 */
905 if ((cio->num_patterns > 0)
906 && (cio->pat_buf_len > 0)) {
907 /*
908 * pat_buf_len needs to be:
909 * num_patterns * sizeof(struct pci_match_conf)
910 * While it is certainly possible the user just
911 * allocated a large buffer, but set the number of
912 * matches correctly, it is far more likely that
913 * their kernel doesn't match the userland utility
914 * they're using. It's also possible that the user
915 * forgot to initialize some variables. Yes, this
916 * may be overly picky, but I hazard to guess that
917 * it's far more likely to just catch folks that
918 * updated their kernel but not their userland.
919 */
920 if ((cio->num_patterns *
921 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
922 /* The user made a mistake, return an error*/
923 cio->status = PCI_GETCONF_ERROR;
924 printf("pci_ioctl: pat_buf_len %d != "
925 "num_patterns (%d) * sizeof(struct "
926 "pci_match_conf) (%d)\npci_ioctl: "
927 "pat_buf_len should be = %d\n",
928 cio->pat_buf_len, cio->num_patterns,
929 (int)sizeof(struct pci_match_conf),
930 (int)sizeof(struct pci_match_conf) *
931 cio->num_patterns);
932 printf("pci_ioctl: do your headers match your "
933 "kernel?\n");
934 cio->num_matches = 0;
935 error = EINVAL;
936 break;
937 }
938
939 /*
940 * Check the user's buffer to make sure it's readable.
941 */
942 if (!useracc((caddr_t)cio->patterns,
943 cio->pat_buf_len, VM_PROT_READ)) {
944 printf("pci_ioctl: pattern buffer %p, "
945 "length %u isn't user accessible for"
946 " READ\n", cio->patterns,
947 cio->pat_buf_len);
948 error = EACCES;
949 break;
950 }
951 /*
952 * Allocate a buffer to hold the patterns.
953 */
954 pattern_buf = malloc(cio->pat_buf_len, M_TEMP,
955 M_WAITOK);
956 error = copyin(cio->patterns, pattern_buf,
957 cio->pat_buf_len);
958 if (error != 0)
959 break;
960 num_patterns = cio->num_patterns;
961
962 } else if ((cio->num_patterns > 0)
963 || (cio->pat_buf_len > 0)) {
964 /*
965 * The user made a mistake, spit out an error.
966 */
967 cio->status = PCI_GETCONF_ERROR;
968 cio->num_matches = 0;
969 printf("pci_ioctl: invalid GETCONF arguments\n");
970 error = EINVAL;
971 break;
972 } else
973 pattern_buf = NULL;
974
975 /*
976 * Make sure we can write to the match buffer.
977 */
978 if (!useracc((caddr_t)cio->matches,
979 cio->match_buf_len, VM_PROT_WRITE)) {
980 printf("pci_ioctl: match buffer %p, length %u "
981 "isn't user accessible for WRITE\n",
982 cio->matches, cio->match_buf_len);
983 error = EACCES;
984 break;
985 }
986
987 /*
988 * Go through the list of devices and copy out the devices
989 * that match the user's criteria.
990 */
991 for (cio->num_matches = 0, error = 0, i = 0,
992 dinfo = STAILQ_FIRST(devlist_head);
993 (dinfo != NULL) && (cio->num_matches < ionum)
994 && (error == 0) && (i < pci_numdevs);
995 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
996
997 if (i < cio->offset)
998 continue;
999
1000 /* Populate pd_name and pd_unit */
1001 name = NULL;
1002 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
1003 name = device_get_name(dinfo->cfg.dev);
1004 if (name) {
1005 strncpy(dinfo->conf.pd_name, name,
1006 sizeof(dinfo->conf.pd_name));
1007 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
1008 dinfo->conf.pd_unit =
1009 device_get_unit(dinfo->cfg.dev);
1010 }
1011
1012 if ((pattern_buf == NULL) ||
1013 (pci_conf_match(pattern_buf, num_patterns,
1014 &dinfo->conf) == 0)) {
1015
1016 /*
1017 * If we've filled up the user's buffer,
1018 * break out at this point. Since we've
1019 * got a match here, we'll pick right back
1020 * up at the matching entry. We can also
1021 * tell the user that there are more matches
1022 * left.
1023 */
1024 if (cio->num_matches >= ionum)
1025 break;
1026
1027 error = copyout(&dinfo->conf,
1028 &cio->matches[cio->num_matches],
1029 sizeof(struct pci_conf));
1030 cio->num_matches++;
1031 }
1032 }
1033
1034 /*
1035 * Set the pointer into the list, so if the user is getting
1036 * n records at a time, where n < pci_numdevs,
1037 */
1038 cio->offset = i;
1039
1040 /*
1041 * Set the generation, the user will need this if they make
1042 * another ioctl call with offset != 0.
1043 */
1044 cio->generation = pci_generation;
1045
1046 /*
1047 * If this is the last device, inform the user so he won't
1048 * bother asking for more devices. If dinfo isn't NULL, we
1049 * know that there are more matches in the list because of
1050 * the way the traversal is done.
1051 */
1052 if (dinfo == NULL)
1053 cio->status = PCI_GETCONF_LAST_DEVICE;
1054 else
1055 cio->status = PCI_GETCONF_MORE_DEVS;
1056
1057 if (pattern_buf != NULL)
1058 free(pattern_buf, M_TEMP);
1059
1060 break;
1061 }
1062 case PCIOCREAD:
1063 io = (struct pci_io *)data;
1064 switch(io->pi_width) {
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MD
1065 case 4:
1066 case 2:
1067 case 1:
4a5a2d63
JS
1068 /*
1069 * Assume that the user-level bus number is
1070 * actually the pciN instance number. We map
1071 * from that to the real pcib+bus combination.
1072 */
1073 pci = devclass_get_device(pci_devclass,
1074 io->pi_sel.pc_bus);
1075 if (pci) {
1076 int b = pcib_get_bus(pci);
1077 pcib = device_get_parent(pci);
1078 io->pi_data =
1079 PCIB_READ_CONFIG(pcib,
1080 b,
1081 io->pi_sel.pc_dev,
1082 io->pi_sel.pc_func,
1083 io->pi_reg,
1084 io->pi_width);
1085 error = 0;
1086 } else {
1087 error = ENODEV;
1088 }
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MD
1089 break;
1090 default:
1091 error = ENODEV;
1092 break;
1093 }
1094 break;
1095
1096 case PCIOCWRITE:
1097 io = (struct pci_io *)data;
1098 switch(io->pi_width) {
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1099 case 4:
1100 case 2:
1101 case 1:
4a5a2d63
JS
1102 /*
1103 * Assume that the user-level bus number is
1104 * actually the pciN instance number. We map
1105 * from that to the real pcib+bus combination.
1106 */
1107 pci = devclass_get_device(pci_devclass,
1108 io->pi_sel.pc_bus);
1109 if (pci) {
1110 int b = pcib_get_bus(pci);
1111 pcib = device_get_parent(pci);
1112 PCIB_WRITE_CONFIG(pcib,
1113 b,
1114 io->pi_sel.pc_dev,
1115 io->pi_sel.pc_func,
1116 io->pi_reg,
1117 io->pi_data,
1118 io->pi_width);
1119 error = 0;
1120 } else {
1121 error = ENODEV;
1122 }
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1123 break;
1124 default:
1125 error = ENODEV;
1126 break;
1127 }
1128 break;
1129
1130 default:
1131 error = ENOTTY;
1132 break;
1133 }
1134
1135 return (error);
1136}
1137
1138#define PCI_CDEV 78
1139
1140static struct cdevsw pcicdev = {
fabb8ceb
MD
1141 /* name */ "pci",
1142 /* maj */ PCI_CDEV,
1143 /* flags */ 0,
1144 /* port */ NULL,
455fcd7e 1145 /* clone */ NULL,
fabb8ceb 1146
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1147 /* open */ pci_open,
1148 /* close */ pci_close,
1149 /* read */ noread,
1150 /* write */ nowrite,
1151 /* ioctl */ pci_ioctl,
1152 /* poll */ nopoll,
1153 /* mmap */ nommap,
1154 /* strategy */ nostrategy,
984263bc 1155 /* dump */ nodump,
fabb8ceb 1156 /* psize */ nopsize
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MD
1157};
1158
1159#include "pci_if.h"
1160
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MD
1161/*
1162 * New style pci driver. Parent device is either a pci-host-bridge or a
1163 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1164 */
ed1bd994
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1165const char *
1166pci_class_to_string(int baseclass)
1167{
1168 const char *name;
1169
1170 switch(baseclass) {
1171 case PCIC_OLD:
1172 name = "OLD";
1173 break;
1174 case PCIC_STORAGE:
1175 name = "STORAGE";
1176 break;
1177 case PCIC_NETWORK:
1178 name = "NETWORK";
1179 break;
1180 case PCIC_DISPLAY:
1181 name = "DISPLAY";
1182 break;
1183 case PCIC_MULTIMEDIA:
1184 name = "MULTIMEDIA";
1185 break;
1186 case PCIC_MEMORY:
1187 name = "MEMORY";
1188 break;
1189 case PCIC_BRIDGE:
1190 name = "BRIDGE";
1191 break;
1192 case PCIC_SIMPLECOMM:
1193 name = "SIMPLECOMM";
1194 break;
1195 case PCIC_BASEPERIPH:
1196 name = "BASEPERIPH";
1197 break;
1198 case PCIC_INPUTDEV:
1199 name = "INPUTDEV";
1200 break;
1201 case PCIC_DOCKING:
1202 name = "DOCKING";
1203 break;
1204 case PCIC_PROCESSOR:
1205 name = "PROCESSOR";
1206 break;
1207 case PCIC_SERIALBUS:
1208 name = "SERIALBUS";
1209 break;
1210 case PCIC_WIRELESS:
1211 name = "WIRELESS";
1212 break;
1213 case PCIC_I2O:
1214 name = "I20";
1215 break;
1216 case PCIC_SATELLITE:
1217 name = "SATELLITE";
1218 break;
1219 case PCIC_CRYPTO:
1220 name = "CRYPTO";
1221 break;
1222 case PCIC_SIGPROC:
1223 name = "SIGPROC";
1224 break;
1225 case PCIC_OTHER:
1226 name = "OTHER";
1227 break;
1228 default:
1229 name = "?";
1230 break;
1231 }
1232 return(name);
1233}
984263bc 1234
22457186 1235void
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MD
1236pci_print_verbose(struct pci_devinfo *dinfo)
1237{
1238 if (bootverbose) {
1239 pcicfgregs *cfg = &dinfo->cfg;
1240
1241 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
1242 cfg->vendor, cfg->device, cfg->revid);
4a5a2d63
JS
1243 printf("\tbus=%d, slot=%d, func=%d\n",
1244 cfg->bus, cfg->slot, cfg->func);
ed1bd994
MD
1245 printf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
1246 pci_class_to_string(cfg->baseclass),
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MD
1247 cfg->baseclass, cfg->subclass, cfg->progif,
1248 cfg->hdrtype, cfg->mfdev);
1249 printf("\tsubordinatebus=%x \tsecondarybus=%x\n",
1250 cfg->subordinatebus, cfg->secondarybus);
1251#ifdef PCI_DEBUG
1252 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
1253 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
1254 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
1255 cfg->lattimer, cfg->lattimer * 30,
1256 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1257#endif /* PCI_DEBUG */
1258 if (cfg->intpin > 0)
1259 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
1260 }
1261}
1262
1263static int
4a5a2d63 1264pci_porten(device_t pcib, int b, int s, int f)
984263bc 1265{
4a5a2d63
JS
1266 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1267 & PCIM_CMD_PORTEN) != 0;
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MD
1268}
1269
1270static int
4a5a2d63 1271pci_memen(device_t pcib, int b, int s, int f)
984263bc 1272{
4a5a2d63
JS
1273 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1274 & PCIM_CMD_MEMEN) != 0;
984263bc
MD
1275}
1276
1277/*
1278 * Add a resource based on a pci map register. Return 1 if the map
1279 * register is a 32bit map register or 2 if it is a 64bit register.
1280 */
1281static int
4a5a2d63
JS
1282pci_add_map(device_t pcib, int b, int s, int f, int reg,
1283 struct resource_list *rl)
984263bc 1284{
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MD
1285 u_int32_t map;
1286 u_int64_t base;
1287 u_int8_t ln2size;
1288 u_int8_t ln2range;
1289 u_int32_t testval;
4a5a2d63
JS
1290
1291
1292#ifdef PCI_ENABLE_IO_MODES
1293 u_int16_t cmd;
1294#endif
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MD
1295 int type;
1296
4a5a2d63 1297 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
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MD
1298
1299 if (map == 0 || map == 0xffffffff)
1300 return 1; /* skip invalid entry */
1301
4a5a2d63
JS
1302 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1303 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1304 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
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MD
1305
1306 base = pci_mapbase(map);
1307 if (pci_maptype(map) & PCI_MAPMEM)
1308 type = SYS_RES_MEMORY;
1309 else
1310 type = SYS_RES_IOPORT;
1311 ln2size = pci_mapsize(testval);
1312 ln2range = pci_maprange(testval);
1313 if (ln2range == 64) {
1314 /* Read the other half of a 64bit map register */
4a5a2d63 1315 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
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1316 }
1317
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1318 /*
1319 * This code theoretically does the right thing, but has
1320 * undesirable side effects in some cases where
1321 * peripherals respond oddly to having these bits
1322 * enabled. Leave them alone by default.
1323 */
1324#ifdef PCI_ENABLE_IO_MODES
4a5a2d63
JS
1325 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1326 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1327 cmd |= PCIM_CMD_PORTEN;
1328 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc 1329 }
4a5a2d63
JS
1330 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1331 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1332 cmd |= PCIM_CMD_MEMEN;
1333 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
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MD
1334 }
1335#else
4a5a2d63 1336 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
984263bc 1337 return 1;
4a5a2d63 1338 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
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MD
1339 return 1;
1340#endif
1341
1342 resource_list_add(rl, type, reg,
1343 base, base + (1 << ln2size) - 1,
1344 (1 << ln2size));
1345
1346 if (bootverbose) {
1347 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
1348 reg, pci_maptype(base), ln2range,
1349 (unsigned int) base, ln2size);
1350 }
1351
1352 return (ln2range == 64) ? 2 : 1;
1353}
1354
1355static void
e126caf1 1356pci_add_resources(device_t pcib, device_t bus, device_t dev)
984263bc
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1357{
1358 struct pci_devinfo *dinfo = device_get_ivars(dev);
4a5a2d63 1359 pcicfgregs *cfg = &dinfo->cfg;
984263bc
MD
1360 struct resource_list *rl = &dinfo->resources;
1361 struct pci_quirk *q;
e126caf1
MD
1362 int b, i, f, s;
1363#if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */
1364 int irq;
1365#endif
984263bc 1366
e126caf1
MD
1367 b = cfg->bus;
1368 s = cfg->slot;
1369 f = cfg->func;
984263bc 1370 for (i = 0; i < cfg->nummaps;) {
e126caf1 1371 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl);
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MD
1372 }
1373
1374 for (q = &pci_quirks[0]; q->devid; q++) {
1375 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1376 && q->type == PCI_QUIRK_MAP_REG)
4a5a2d63 1377 pci_add_map(pcib, b, s, f, q->arg1, rl);
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MD
1378 }
1379
1380 if (cfg->intpin > 0 && cfg->intline != 255)
1381 resource_list_add(rl, SYS_RES_IRQ, 0,
1382 cfg->intline, cfg->intline, 1);
1383}
1384
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MD
1385void
1386pci_add_children(device_t dev, int busno, size_t dinfo_size)
984263bc 1387{
e126caf1 1388#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
4a5a2d63 1389 device_t pcib = device_get_parent(dev);
e126caf1 1390 struct pci_devinfo *dinfo;
4a5a2d63 1391 int maxslots;
e126caf1
MD
1392 int s, f, pcifunchigh;
1393 uint8_t hdrtype;
1394
1395 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo));
984263bc 1396
4a5a2d63 1397 maxslots = PCIB_MAXSLOTS(pcib);
984263bc 1398
57e943f7 1399 for (s = 0; s <= maxslots; s++) {
e126caf1
MD
1400 pcifunchigh = 0;
1401 f = 0;
1402 hdrtype = REG(PCIR_HDRTYPE, 1);
1403 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1404 continue;
1405 if (hdrtype & PCIM_MFDEV)
1406 pcifunchigh = PCI_FUNCMAX;
5e658043 1407 for (f = 0; f <= pcifunchigh; f++) {
e126caf1 1408 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
984263bc 1409 if (dinfo != NULL) {
e126caf1 1410 pci_add_child(dev, dinfo);
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MD
1411 }
1412 }
1413 }
e126caf1
MD
1414#undef REG
1415}
1416
1417void
1418pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1419{
1420 device_t pcib;
1421
1422 pcib = device_get_parent(bus);
1423 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1424 device_set_ivars(dinfo->cfg.dev, dinfo);
1425 pci_add_resources(pcib, bus, dinfo->cfg.dev);
1426 pci_print_verbose(dinfo);
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MD
1427}
1428
c01b8d84
MD
1429/*
1430 * Probe the PCI bus. Note: probe code is not supposed to add children
1431 * or call attach.
1432 */
984263bc 1433static int
4a5a2d63 1434pci_probe(device_t dev)
984263bc 1435{
984263bc 1436 device_set_desc(dev, "PCI bus");
4a5a2d63 1437
c01b8d84
MD
1438 /* Allow other subclasses to override this driver */
1439 return(-1000);
984263bc
MD
1440}
1441
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MD
1442static int
1443pci_attach(device_t dev)
1444{
1445 int busno;
e4c9c0c8
MD
1446 int lunit = device_get_unit(dev);
1447
1448 cdevsw_add(&pcicdev, -1, lunit);
1449 make_dev(&pcicdev, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit);
e126caf1
MD
1450
1451 /*
1452 * Since there can be multiple independantly numbered PCI
1453 * busses on some large alpha systems, we can't use the unit
1454 * number to decide what bus we are probing. We ask the parent
1455 * pcib what our bus number is.
1456 */
1457 busno = pcib_get_bus(dev);
1458 if (bootverbose)
ed1bd994 1459 device_printf(dev, "pci_attach() physical bus=%d\n", busno);
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MD
1460
1461 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1462
1463 return (bus_generic_attach(dev));
1464}
1465
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1466static int
1467pci_print_resources(struct resource_list *rl, const char *name, int type,
1468 const char *format)
1469{
1470 struct resource_list_entry *rle;
1471 int printed, retval;
1472
1473 printed = 0;
1474 retval = 0;
1475 /* Yes, this is kinda cheating */
1476 SLIST_FOREACH(rle, rl, link) {
1477 if (rle->type == type) {
1478 if (printed == 0)
1479 retval += printf(" %s ", name);
1480 else if (printed > 0)
1481 retval += printf(",");
1482 printed++;
1483 retval += printf(format, rle->start);
1484 if (rle->count > 1) {
1485 retval += printf("-");
1486 retval += printf(format, rle->start +
1487 rle->count - 1);
1488 }
1489 }
1490 }
1491 return retval;
1492}
1493
e126caf1 1494int
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1495pci_print_child(device_t dev, device_t child)
1496{
1497 struct pci_devinfo *dinfo;
1498 struct resource_list *rl;
1499 pcicfgregs *cfg;
1500 int retval = 0;
1501
1502 dinfo = device_get_ivars(child);
1503 cfg = &dinfo->cfg;
1504 rl = &dinfo->resources;
1505
1506 retval += bus_print_child_header(dev, child);
1507
1508 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1509 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1510 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1511 if (device_get_flags(dev))
1512 retval += printf(" flags %#x", device_get_flags(dev));
1513
1514 retval += printf(" at device %d.%d", pci_get_slot(child),
1515 pci_get_function(child));
1516
1517 retval += bus_print_child_footer(dev, child);
1518
1519 return (retval);
1520}
1521
e126caf1 1522void
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1523pci_probe_nomatch(device_t dev, device_t child)
1524{
1525 struct pci_devinfo *dinfo;
1526 pcicfgregs *cfg;
1527 const char *desc;
1528 int unknown;
1529
1530 unknown = 0;
1531 dinfo = device_get_ivars(child);
1532 cfg = &dinfo->cfg;
1533 desc = pci_ata_match(child);
1534 if (!desc) desc = pci_usb_match(child);
1535 if (!desc) desc = pci_vga_match(child);
27c23c6b 1536 if (!desc) desc = pci_chip_match(child);
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MD
1537 if (!desc) {
1538 desc = "unknown card";
1539 unknown++;
1540 }
1541 device_printf(dev, "<%s>", desc);
1542 if (bootverbose || unknown) {
1543 printf(" (vendor=0x%04x, dev=0x%04x)",
1544 cfg->vendor,
1545 cfg->device);
1546 }
1547 printf(" at %d.%d",
1548 pci_get_slot(child),
1549 pci_get_function(child));
1550 if (cfg->intpin > 0 && cfg->intline != 255) {
1551 printf(" irq %d", cfg->intline);
1552 }
1553 printf("\n");
1554
1555 return;
1556}
1557
22457186 1558int
4a5a2d63 1559pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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MD
1560{
1561 struct pci_devinfo *dinfo;
1562 pcicfgregs *cfg;
1563
1564 dinfo = device_get_ivars(child);
1565 cfg = &dinfo->cfg;
1566
1567 switch (which) {
1568 case PCI_IVAR_SUBVENDOR:
1569 *result = cfg->subvendor;
1570 break;
1571 case PCI_IVAR_SUBDEVICE:
1572 *result = cfg->subdevice;
1573 break;
1574 case PCI_IVAR_VENDOR:
1575 *result = cfg->vendor;
1576 break;
1577 case PCI_IVAR_DEVICE:
1578 *result = cfg->device;
1579 break;
1580 case PCI_IVAR_DEVID:
1581 *result = (cfg->device << 16) | cfg->vendor;
1582 break;
1583 case PCI_IVAR_CLASS:
1584 *result = cfg->baseclass;
1585 break;
1586 case PCI_IVAR_SUBCLASS:
1587 *result = cfg->subclass;
1588 break;
1589 case PCI_IVAR_PROGIF:
1590 *result = cfg->progif;
1591 break;
1592 case PCI_IVAR_REVID:
1593 *result = cfg->revid;
1594 break;
1595 case PCI_IVAR_INTPIN:
1596 *result = cfg->intpin;
1597 break;
1598 case PCI_IVAR_IRQ:
1599 *result = cfg->intline;
1600 break;
1601 case PCI_IVAR_BUS:
1602 *result = cfg->bus;
1603 break;
1604 case PCI_IVAR_SLOT:
1605 *result = cfg->slot;
1606 break;
1607 case PCI_IVAR_FUNCTION:
1608 *result = cfg->func;
1609 break;
1610 case PCI_IVAR_SECONDARYBUS:
1611 *result = cfg->secondarybus;
1612 break;
1613 case PCI_IVAR_SUBORDINATEBUS:
1614 *result = cfg->subordinatebus;
1615 break;
f72d3d23
JS
1616 case PCI_IVAR_ETHADDR:
1617 /*
1618 * The generic accessor doesn't deal with failure, so
1619 * we set the return value, then return an error.
1620 */
1621 *result = NULL;
1622 return (EINVAL);
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MD
1623 default:
1624 return ENOENT;
1625 }
1626 return 0;
1627}
1628
22457186 1629int
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MD
1630pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1631{
1632 struct pci_devinfo *dinfo;
1633 pcicfgregs *cfg;
1634
1635 dinfo = device_get_ivars(child);
1636 cfg = &dinfo->cfg;
1637
1638 switch (which) {
1639 case PCI_IVAR_SUBVENDOR:
1640 case PCI_IVAR_SUBDEVICE:
1641 case PCI_IVAR_VENDOR:
1642 case PCI_IVAR_DEVICE:
1643 case PCI_IVAR_DEVID:
1644 case PCI_IVAR_CLASS:
1645 case PCI_IVAR_SUBCLASS:
1646 case PCI_IVAR_PROGIF:
1647 case PCI_IVAR_REVID:
1648 case PCI_IVAR_INTPIN:
1649 case PCI_IVAR_IRQ:
1650 case PCI_IVAR_BUS:
1651 case PCI_IVAR_SLOT:
1652 case PCI_IVAR_FUNCTION:
f72d3d23 1653 case PCI_IVAR_ETHADDR:
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MD
1654 return EINVAL; /* disallow for now */
1655
1656 case PCI_IVAR_SECONDARYBUS:
1657 cfg->secondarybus = value;
1658 break;
1659 case PCI_IVAR_SUBORDINATEBUS:
1660 cfg->subordinatebus = value;
1661 break;
1662 default:
1663 return ENOENT;
1664 }
1665 return 0;
1666}
1667
261fa16d 1668struct resource *
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MD
1669pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1670 u_long start, u_long end, u_long count, u_int flags)
1671{
1672 struct pci_devinfo *dinfo = device_get_ivars(child);
1673 struct resource_list *rl = &dinfo->resources;
1674
4a5a2d63 1675#ifdef __i386__
984263bc
MD
1676 pcicfgregs *cfg = &dinfo->cfg;
1677 /*
1678 * Perform lazy resource allocation
1679 *
1680 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY
1681 */
1682 if (device_get_parent(child) == dev) {
1683 /*
1684 * If device doesn't have an interrupt routed, and is
1685 * deserving of an interrupt, try to assign it one.
1686 */
1687 if ((type == SYS_RES_IRQ) &&
1688 (cfg->intline == 255 || cfg->intline == 0) &&
1689 (cfg->intpin != 0) && (start == 0) && (end == ~0UL)) {
4a5a2d63 1690 cfg->intline = PCIB_ROUTE_INTERRUPT(
57e943f7 1691 device_get_parent(dev), child,
4a5a2d63 1692 cfg->intpin);
984263bc
MD
1693 if (cfg->intline != 255) {
1694 pci_write_config(child, PCIR_INTLINE,
1695 cfg->intline, 1);
1696 resource_list_add(rl, SYS_RES_IRQ, 0,
1697 cfg->intline, cfg->intline, 1);
1698 }
1699 }
1700 }
1701#endif
1702 return resource_list_alloc(rl, dev, child, type, rid,
1703 start, end, count, flags);
1704}
1705
1706static int
1707pci_release_resource(device_t dev, device_t child, int type, int rid,
1708 struct resource *r)
1709{
1710 struct pci_devinfo *dinfo = device_get_ivars(child);
1711 struct resource_list *rl = &dinfo->resources;
1712
1713 return resource_list_release(rl, dev, child, type, rid, r);
1714}
1715
1716static int
1717pci_set_resource(device_t dev, device_t child, int type, int rid,
1718 u_long start, u_long count)
1719{
1720 struct pci_devinfo *dinfo = device_get_ivars(child);
1721 struct resource_list *rl = &dinfo->resources;
1722
1723 resource_list_add(rl, type, rid, start, start + count - 1, count);
1724 return 0;
1725}
1726
1727static int
1728pci_get_resource(device_t dev, device_t child, int type, int rid,
1729 u_long *startp, u_long *countp)
1730{
1731 struct pci_devinfo *dinfo = device_get_ivars(child);
1732 struct resource_list *rl = &dinfo->resources;
1733 struct resource_list_entry *rle;
1734
1735 rle = resource_list_find(rl, type, rid);
1736 if (!rle)
1737 return ENOENT;
1738
1739 if (startp)
1740 *startp = rle->start;
1741 if (countp)
1742 *countp = rle->count;
1743
1744 return 0;
1745}
1746
e126caf1 1747void
984263bc
MD
1748pci_delete_resource(device_t dev, device_t child, int type, int rid)
1749{
1750 printf("pci_delete_resource: PCI resources can not be deleted\n");
1751}
1752
e126caf1
MD
1753struct resource_list *
1754pci_get_resource_list (device_t dev, device_t child)
1755{
1756 struct pci_devinfo * dinfo = device_get_ivars(child);
1757 struct resource_list * rl = &dinfo->resources;
1758
1759 if (!rl)
1760 return (NULL);
1761
1762 return (rl);
1763}
1764
1765u_int32_t
984263bc
MD
1766pci_read_config_method(device_t dev, device_t child, int reg, int width)
1767{
1768 struct pci_devinfo *dinfo = device_get_ivars(child);
1769 pcicfgregs *cfg = &dinfo->cfg;
4a5a2d63
JS
1770
1771 return PCIB_READ_CONFIG(device_get_parent(dev),
1772 cfg->bus, cfg->slot, cfg->func,
1773 reg, width);
984263bc
MD
1774}
1775
e126caf1 1776void
984263bc
MD
1777pci_write_config_method(device_t dev, device_t child, int reg,
1778 u_int32_t val, int width)
1779{
1780 struct pci_devinfo *dinfo = device_get_ivars(child);
1781 pcicfgregs *cfg = &dinfo->cfg;
4a5a2d63
JS
1782
1783 PCIB_WRITE_CONFIG(device_get_parent(dev),
1784 cfg->bus, cfg->slot, cfg->func,
1785 reg, val, width);
984263bc
MD
1786}
1787
e126caf1
MD
1788int
1789pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
1790 size_t buflen)
1791{
1792 struct pci_devinfo *dinfo;
1793
1794 dinfo = device_get_ivars(child);
1795 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
1796 pci_get_function(child));
1797 return (0);
1798}
1799
1800int
1801pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
1802 size_t buflen)
1803{
1804 struct pci_devinfo *dinfo;
1805 pcicfgregs *cfg;
1806
1807 dinfo = device_get_ivars(child);
1808 cfg = &dinfo->cfg;
1809 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
1810 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
1811 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
1812 cfg->progif);
1813 return (0);
1814}
1815
1816int
1817pci_assign_interrupt_method(device_t dev, device_t child)
1818{
1819 struct pci_devinfo *dinfo = device_get_ivars(child);
1820 pcicfgregs *cfg = &dinfo->cfg;
1821
1822 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
1823 cfg->intpin));
1824}
1825
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MD
1826static int
1827pci_modevent(module_t mod, int what, void *arg)
1828{
1829 switch (what) {
1830 case MOD_LOAD:
1831 STAILQ_INIT(&pci_devq);
1832 break;
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MD
1833 case MOD_UNLOAD:
1834 break;
1835 }
1836
1837 return 0;
1838}
1839
e126caf1
MD
1840int
1841pci_resume(device_t dev)
1842{
1843 int numdevs;
1844 int i;
1845 device_t *children;
1846 device_t child;
1847 struct pci_devinfo *dinfo;
1848 pcicfgregs *cfg;
1849
1850 device_get_children(dev, &children, &numdevs);
1851
1852 for (i = 0; i < numdevs; i++) {
1853 child = children[i];
1854
1855 dinfo = device_get_ivars(child);
1856 cfg = &dinfo->cfg;
1857 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
1858 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
1859 if (PCI_INTERRUPT_VALID(cfg->intline)) {
1860 pci_write_config(child, PCIR_INTLINE,
1861 cfg->intline, 1);
1862 }
1863 }
1864 }
1865
1866 free(children, M_TEMP);
1867
1868 return (bus_generic_resume(dev));
1869}
1870
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MD
1871static device_method_t pci_methods[] = {
1872 /* Device interface */
4a5a2d63 1873 DEVMETHOD(device_probe, pci_probe),
e126caf1 1874 DEVMETHOD(device_attach, pci_attach),
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MD
1875 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1876 DEVMETHOD(device_suspend, bus_generic_suspend),
e126caf1 1877 DEVMETHOD(device_resume, pci_resume),
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MD
1878
1879 /* Bus interface */
1880 DEVMETHOD(bus_print_child, pci_print_child),
1881 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
1882 DEVMETHOD(bus_read_ivar, pci_read_ivar),
1883 DEVMETHOD(bus_write_ivar, pci_write_ivar),
1884 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
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MD
1885 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1886 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
e126caf1
MD
1887
1888 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
984263bc
MD
1889 DEVMETHOD(bus_set_resource, pci_set_resource),
1890 DEVMETHOD(bus_get_resource, pci_get_resource),
1891 DEVMETHOD(bus_delete_resource, pci_delete_resource),
e126caf1
MD
1892 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
1893 DEVMETHOD(bus_release_resource, pci_release_resource),
1894 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1895 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1896 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
1897 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
984263bc
MD
1898
1899 /* PCI interface */
1900 DEVMETHOD(pci_read_config, pci_read_config_method),
1901 DEVMETHOD(pci_write_config, pci_write_config_method),
1902 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
1903 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
1904 DEVMETHOD(pci_enable_io, pci_enable_io_method),
1905 DEVMETHOD(pci_disable_io, pci_disable_io_method),
1906 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
1907 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
e126caf1 1908 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
984263bc
MD
1909
1910 { 0, 0 }
1911};
1912
1913static driver_t pci_driver = {
1914 "pci",
1915 pci_methods,
1916 1, /* no softc */
1917};
1918
1919DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
261fa16d 1920MODULE_VERSION(pci, 1);