note last commit based on evidence supplied by: Paul Herman <pherman@frenchfries...
[dragonfly.git] / sys / bus / pci / pci.c
CommitLineData
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1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
80eff43d 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.6 2003/11/17 00:54:39 asmodai Exp $
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28 *
29 */
30
31#include "opt_bus.h"
32#include "opt_pci.h"
33
34#include "opt_simos.h"
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/malloc.h>
39#include <sys/module.h>
40#include <sys/fcntl.h>
41#include <sys/conf.h>
42#include <sys/kernel.h>
43#include <sys/queue.h>
44#include <sys/types.h>
45#include <sys/buf.h>
46
47#include <vm/vm.h>
48#include <vm/pmap.h>
49#include <vm/vm_extern.h>
50
51#include <sys/bus.h>
52#include <machine/bus.h>
53#include <sys/rman.h>
54#include <machine/resource.h>
55#include <machine/md_var.h> /* For the Alpha */
56#ifdef __i386__
57#include <machine/pci_cfgreg.h>
58#endif
59
1f2de5d4
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60#include "pcireg.h"
61#include "pcivar.h"
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62#include <sys/pciio.h>
63
64#ifdef __alpha__
65#include <machine/rpb.h>
66#endif
67
68#ifdef APIC_IO
69#include <machine/smp.h>
70#endif /* APIC_IO */
71
72static void pci_read_extcap(pcicfgregs *cfg);
73
74struct pci_quirk {
75 u_int32_t devid; /* Vendor/device of the card */
76 int type;
77#define PCI_QUIRK_MAP_REG 1 /* PCI map register in wierd place */
78 int arg1;
79 int arg2;
80};
81
82struct pci_quirk pci_quirks[] = {
83 /*
84 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
85 */
86 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
87 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
88
89 { 0 }
90};
91
92/* map register information */
93#define PCI_MAPMEM 0x01 /* memory map */
94#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
95#define PCI_MAPPORT 0x04 /* port map */
96
97struct pci_devinfo {
98 STAILQ_ENTRY(pci_devinfo) pci_links;
99 struct resource_list resources;
100 pcicfgregs cfg;
101 struct pci_conf conf;
102};
103
104static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
105u_int32_t pci_numdevs = 0;
106static u_int32_t pci_generation = 0;
107
108device_t
109pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func)
110{
111 struct pci_devinfo *dinfo;
112
113 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
114 if ((dinfo->cfg.bus == bus) &&
115 (dinfo->cfg.slot == slot) &&
116 (dinfo->cfg.func == func)) {
117 return (dinfo->cfg.dev);
118 }
119 }
120
121 return (NULL);
122}
123
124device_t
125pci_find_device (u_int16_t vendor, u_int16_t device)
126{
127 struct pci_devinfo *dinfo;
128
129 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
130 if ((dinfo->cfg.vendor == vendor) &&
131 (dinfo->cfg.device == device)) {
132 return (dinfo->cfg.dev);
133 }
134 }
135
136 return (NULL);
137}
138
139/* return base address of memory or port map */
140
141static u_int32_t
142pci_mapbase(unsigned mapreg)
143{
144 int mask = 0x03;
145 if ((mapreg & 0x01) == 0)
146 mask = 0x0f;
147 return (mapreg & ~mask);
148}
149
150/* return map type of memory or port map */
151
152static int
153pci_maptype(unsigned mapreg)
154{
155 static u_int8_t maptype[0x10] = {
156 PCI_MAPMEM, PCI_MAPPORT,
157 PCI_MAPMEM, 0,
158 PCI_MAPMEM, PCI_MAPPORT,
159 0, 0,
160 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
161 PCI_MAPMEM|PCI_MAPMEMP, 0,
162 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
163 0, 0,
164 };
165
166 return maptype[mapreg & 0x0f];
167}
168
169/* return log2 of map size decoded for memory or port map */
170
171static int
172pci_mapsize(unsigned testval)
173{
174 int ln2size;
175
176 testval = pci_mapbase(testval);
177 ln2size = 0;
178 if (testval != 0) {
179 while ((testval & 1) == 0)
180 {
181 ln2size++;
182 testval >>= 1;
183 }
184 }
185 return (ln2size);
186}
187
188/* return log2 of address range supported by map register */
189
190static int
191pci_maprange(unsigned mapreg)
192{
193 int ln2range = 0;
194 switch (mapreg & 0x07) {
195 case 0x00:
196 case 0x01:
197 case 0x05:
198 ln2range = 32;
199 break;
200 case 0x02:
201 ln2range = 20;
202 break;
203 case 0x04:
204 ln2range = 64;
205 break;
206 }
207 return (ln2range);
208}
209
210/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
211
212static void
213pci_fixancient(pcicfgregs *cfg)
214{
215 if (cfg->hdrtype != 0)
216 return;
217
218 /* PCI to PCI bridges use header type 1 */
219 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
220 cfg->hdrtype = 1;
221}
222
223/* read config data specific to header type 1 device (PCI to PCI bridge) */
224
225static void *
226pci_readppb(pcicfgregs *cfg)
227{
228 pcih1cfgregs *p;
229
230 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK);
231 if (p == NULL)
232 return (NULL);
233
234 bzero(p, sizeof *p);
235
236 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_1, 2);
237 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_1, 2);
238
239 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_1, 1);
240
241 p->iobase = PCI_PPBIOBASE (pci_cfgread(cfg, PCIR_IOBASEH_1, 2),
242 pci_cfgread(cfg, PCIR_IOBASEL_1, 1));
243 p->iolimit = PCI_PPBIOLIMIT (pci_cfgread(cfg, PCIR_IOLIMITH_1, 2),
244 pci_cfgread(cfg, PCIR_IOLIMITL_1, 1));
245
246 p->membase = PCI_PPBMEMBASE (0,
247 pci_cfgread(cfg, PCIR_MEMBASE_1, 2));
248 p->memlimit = PCI_PPBMEMLIMIT (0,
249 pci_cfgread(cfg, PCIR_MEMLIMIT_1, 2));
250
251 p->pmembase = PCI_PPBMEMBASE (
252 (pci_addr_t)pci_cfgread(cfg, PCIR_PMBASEH_1, 4),
253 pci_cfgread(cfg, PCIR_PMBASEL_1, 2));
254
255 p->pmemlimit = PCI_PPBMEMLIMIT (
256 (pci_addr_t)pci_cfgread(cfg, PCIR_PMLIMITH_1, 4),
257 pci_cfgread(cfg, PCIR_PMLIMITL_1, 2));
258 return (p);
259}
260
261/* read config data specific to header type 2 device (PCI to CardBus bridge) */
262
263static void *
264pci_readpcb(pcicfgregs *cfg)
265{
266 pcih2cfgregs *p;
267
268 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK);
269 if (p == NULL)
270 return (NULL);
271
272 bzero(p, sizeof *p);
273
274 p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_2, 2);
275 p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_2, 2);
276
277 p->seclat = pci_cfgread(cfg, PCIR_SECLAT_2, 1);
278
279 p->membase0 = pci_cfgread(cfg, PCIR_MEMBASE0_2, 4);
280 p->memlimit0 = pci_cfgread(cfg, PCIR_MEMLIMIT0_2, 4);
281 p->membase1 = pci_cfgread(cfg, PCIR_MEMBASE1_2, 4);
282 p->memlimit1 = pci_cfgread(cfg, PCIR_MEMLIMIT1_2, 4);
283
284 p->iobase0 = pci_cfgread(cfg, PCIR_IOBASE0_2, 4);
285 p->iolimit0 = pci_cfgread(cfg, PCIR_IOLIMIT0_2, 4);
286 p->iobase1 = pci_cfgread(cfg, PCIR_IOBASE1_2, 4);
287 p->iolimit1 = pci_cfgread(cfg, PCIR_IOLIMIT1_2, 4);
288
289 p->pccardif = pci_cfgread(cfg, PCIR_PCCARDIF_2, 4);
290 return p;
291}
292
293/* extract header type specific config data */
294
295static void
296pci_hdrtypedata(pcicfgregs *cfg)
297{
298 switch (cfg->hdrtype) {
299 case 0:
300 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_0, 2);
301 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_0, 2);
302 cfg->nummaps = PCI_MAXMAPS_0;
303 break;
304 case 1:
305 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_1, 2);
306 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_1, 2);
307 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_1, 1);
308 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_1, 1);
309 cfg->nummaps = PCI_MAXMAPS_1;
310 cfg->hdrspec = pci_readppb(cfg);
311 break;
312 case 2:
313 cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_2, 2);
314 cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_2, 2);
315 cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_2, 1);
316 cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_2, 1);
317 cfg->nummaps = PCI_MAXMAPS_2;
318 cfg->hdrspec = pci_readpcb(cfg);
319 break;
320 }
321}
322
323/* read configuration header into pcicfgrect structure */
324
325static struct pci_devinfo *
326pci_readcfg(pcicfgregs *probe)
327{
328#define REG(n, w) pci_cfgread(probe, n, w)
329
330 pcicfgregs *cfg = NULL;
331 struct pci_devinfo *devlist_entry;
332 struct devlist *devlist_head;
333
334 devlist_head = &pci_devq;
335
336 devlist_entry = NULL;
337
338 if (pci_cfgread(probe, PCIR_DEVVENDOR, 4) != -1) {
339
340 devlist_entry = malloc(sizeof(struct pci_devinfo),
341 M_DEVBUF, M_WAITOK);
342 if (devlist_entry == NULL)
343 return (NULL);
344 bzero(devlist_entry, sizeof *devlist_entry);
345
346 cfg = &devlist_entry->cfg;
347
348 cfg->hose = probe->hose;
349 cfg->bus = probe->bus;
350 cfg->slot = probe->slot;
351 cfg->func = probe->func;
352 cfg->vendor = pci_cfgread(cfg, PCIR_VENDOR, 2);
353 cfg->device = pci_cfgread(cfg, PCIR_DEVICE, 2);
354 cfg->cmdreg = pci_cfgread(cfg, PCIR_COMMAND, 2);
355 cfg->statreg = pci_cfgread(cfg, PCIR_STATUS, 2);
356 cfg->baseclass = pci_cfgread(cfg, PCIR_CLASS, 1);
357 cfg->subclass = pci_cfgread(cfg, PCIR_SUBCLASS, 1);
358 cfg->progif = pci_cfgread(cfg, PCIR_PROGIF, 1);
359 cfg->revid = pci_cfgread(cfg, PCIR_REVID, 1);
360 cfg->hdrtype = pci_cfgread(cfg, PCIR_HEADERTYPE, 1);
361 cfg->cachelnsz = pci_cfgread(cfg, PCIR_CACHELNSZ, 1);
362 cfg->lattimer = pci_cfgread(cfg, PCIR_LATTIMER, 1);
363 cfg->intpin = pci_cfgread(cfg, PCIR_INTPIN, 1);
364 cfg->intline = pci_cfgread(cfg, PCIR_INTLINE, 1);
365#ifdef __alpha__
366 alpha_platform_assign_pciintr(cfg);
367#endif
368
369#ifdef APIC_IO
370 if (cfg->intpin != 0) {
371 int airq;
372
373 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
374 if (airq >= 0) {
375 /* PCI specific entry found in MP table */
376 if (airq != cfg->intline) {
377 undirect_pci_irq(cfg->intline);
378 cfg->intline = airq;
379 }
380 } else {
381 /*
382 * PCI interrupts might be redirected to the
383 * ISA bus according to some MP tables. Use the
384 * same methods as used by the ISA devices
385 * devices to find the proper IOAPIC int pin.
386 */
387 airq = isa_apic_irq(cfg->intline);
388 if ((airq >= 0) && (airq != cfg->intline)) {
389 /* XXX: undirect_pci_irq() ? */
390 undirect_isa_irq(cfg->intline);
391 cfg->intline = airq;
392 }
393 }
394 }
395#endif /* APIC_IO */
396
397 cfg->mingnt = pci_cfgread(cfg, PCIR_MINGNT, 1);
398 cfg->maxlat = pci_cfgread(cfg, PCIR_MAXLAT, 1);
399
400 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
401 cfg->hdrtype &= ~PCIM_MFDEV;
402
403 pci_fixancient(cfg);
404 pci_hdrtypedata(cfg);
405
406 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
407 pci_read_extcap(cfg);
408
409 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
410
411 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
412 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
413 devlist_entry->conf.pc_sel.pc_func = cfg->func;
414 devlist_entry->conf.pc_hdr = cfg->hdrtype;
415
416 devlist_entry->conf.pc_subvendor = cfg->subvendor;
417 devlist_entry->conf.pc_subdevice = cfg->subdevice;
418 devlist_entry->conf.pc_vendor = cfg->vendor;
419 devlist_entry->conf.pc_device = cfg->device;
420
421 devlist_entry->conf.pc_class = cfg->baseclass;
422 devlist_entry->conf.pc_subclass = cfg->subclass;
423 devlist_entry->conf.pc_progif = cfg->progif;
424 devlist_entry->conf.pc_revid = cfg->revid;
425
426 pci_numdevs++;
427 pci_generation++;
428 }
429 return (devlist_entry);
430#undef REG
431}
432
433static void
434pci_read_extcap(pcicfgregs *cfg)
435{
436#define REG(n, w) pci_cfgread(cfg, n, w)
437 int ptr, nextptr, ptrptr;
438
439 switch (cfg->hdrtype) {
440 case 0:
441 ptrptr = 0x34;
442 break;
443 case 2:
444 ptrptr = 0x14;
445 break;
446 default:
447 return; /* no extended capabilities support */
448 }
449 nextptr = REG(ptrptr, 1); /* sanity check? */
450
451 /*
452 * Read capability entries.
453 */
454 while (nextptr != 0) {
455 /* Sanity check */
456 if (nextptr > 255) {
457 printf("illegal PCI extended capability offset %d\n",
458 nextptr);
459 return;
460 }
461 /* Find the next entry */
462 ptr = nextptr;
463 nextptr = REG(ptr + 1, 1);
464
465 /* Process this entry */
466 switch (REG(ptr, 1)) {
467 case 0x01: /* PCI power management */
468 if (cfg->pp_cap == 0) {
469 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
470 cfg->pp_status = ptr + PCIR_POWER_STATUS;
471 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
472 if ((nextptr - ptr) > PCIR_POWER_DATA)
473 cfg->pp_data = ptr + PCIR_POWER_DATA;
474 }
475 break;
476 default:
477 break;
478 }
479 }
480#undef REG
481}
482
483#if 0
484/* free pcicfgregs structure and all depending data structures */
485
486static int
487pci_freecfg(struct pci_devinfo *dinfo)
488{
489 struct devlist *devlist_head;
490
491 devlist_head = &pci_devq;
492
493 if (dinfo->cfg.hdrspec != NULL)
494 free(dinfo->cfg.hdrspec, M_DEVBUF);
495 if (dinfo->cfg.map != NULL)
496 free(dinfo->cfg.map, M_DEVBUF);
497 /* XXX this hasn't been tested */
498 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
499 free(dinfo, M_DEVBUF);
500
501 /* increment the generation count */
502 pci_generation++;
503
504 /* we're losing one device */
505 pci_numdevs--;
506 return (0);
507}
508#endif
509
510
511/*
512 * PCI power manangement
513 */
514static int
515pci_set_powerstate_method(device_t dev, device_t child, int state)
516{
517 struct pci_devinfo *dinfo = device_get_ivars(child);
518 pcicfgregs *cfg = &dinfo->cfg;
519 u_int16_t status;
520 int result;
521
522 if (cfg->pp_cap != 0) {
523 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK;
524 result = 0;
525 switch (state) {
526 case PCI_POWERSTATE_D0:
527 status |= PCIM_PSTAT_D0;
528 break;
529 case PCI_POWERSTATE_D1:
530 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) {
531 status |= PCIM_PSTAT_D1;
532 } else {
533 result = EOPNOTSUPP;
534 }
535 break;
536 case PCI_POWERSTATE_D2:
537 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) {
538 status |= PCIM_PSTAT_D2;
539 } else {
540 result = EOPNOTSUPP;
541 }
542 break;
543 case PCI_POWERSTATE_D3:
544 status |= PCIM_PSTAT_D3;
545 break;
546 default:
547 result = EINVAL;
548 }
549 if (result == 0)
550 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2);
551 } else {
552 result = ENXIO;
553 }
554 return(result);
555}
556
557static int
558pci_get_powerstate_method(device_t dev, device_t child)
559{
560 struct pci_devinfo *dinfo = device_get_ivars(child);
561 pcicfgregs *cfg = &dinfo->cfg;
562 u_int16_t status;
563 int result;
564
565 if (cfg->pp_cap != 0) {
566 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2);
567 switch (status & PCIM_PSTAT_DMASK) {
568 case PCIM_PSTAT_D0:
569 result = PCI_POWERSTATE_D0;
570 break;
571 case PCIM_PSTAT_D1:
572 result = PCI_POWERSTATE_D1;
573 break;
574 case PCIM_PSTAT_D2:
575 result = PCI_POWERSTATE_D2;
576 break;
577 case PCIM_PSTAT_D3:
578 result = PCI_POWERSTATE_D3;
579 break;
580 default:
581 result = PCI_POWERSTATE_UNKNOWN;
582 break;
583 }
584 } else {
585 /* No support, device is always at D0 */
586 result = PCI_POWERSTATE_D0;
587 }
588 return(result);
589}
590
591/*
592 * Some convenience functions for PCI device drivers.
593 */
594
595static __inline void
596pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
597{
598 u_int16_t command;
599
600 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
601 command |= bit;
602 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
603}
604
605static __inline void
606pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
607{
608 u_int16_t command;
609
610 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
611 command &= ~bit;
612 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
613}
614
615static void
616pci_enable_busmaster_method(device_t dev, device_t child)
617{
618 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
619}
620
621static void
622pci_disable_busmaster_method(device_t dev, device_t child)
623{
624 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
625}
626
627static void
628pci_enable_io_method(device_t dev, device_t child, int space)
629{
630 switch(space) {
631 case SYS_RES_IOPORT:
632 pci_set_command_bit(dev, child, PCIM_CMD_PORTEN);
633 break;
634 case SYS_RES_MEMORY:
635 pci_set_command_bit(dev, child, PCIM_CMD_MEMEN);
636 break;
637 }
638}
639
640static void
641pci_disable_io_method(device_t dev, device_t child, int space)
642{
643 switch(space) {
644 case SYS_RES_IOPORT:
645 pci_clear_command_bit(dev, child, PCIM_CMD_PORTEN);
646 break;
647 case SYS_RES_MEMORY:
648 pci_clear_command_bit(dev, child, PCIM_CMD_MEMEN);
649 break;
650 }
651}
652
653/*
654 * This is the user interface to PCI configuration space.
655 */
656
657static int
41c20dac 658pci_open(dev_t dev, int oflags, int devtype, struct thread *td)
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659{
660 if ((oflags & FWRITE) && securelevel > 0) {
661 return EPERM;
662 }
663 return 0;
664}
665
666static int
41c20dac 667pci_close(dev_t dev, int flag, int devtype, struct thread *td)
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668{
669 return 0;
670}
671
672/*
673 * Match a single pci_conf structure against an array of pci_match_conf
674 * structures. The first argument, 'matches', is an array of num_matches
675 * pci_match_conf structures. match_buf is a pointer to the pci_conf
676 * structure that will be compared to every entry in the matches array.
677 * This function returns 1 on failure, 0 on success.
678 */
679static int
680pci_conf_match(struct pci_match_conf *matches, int num_matches,
681 struct pci_conf *match_buf)
682{
683 int i;
684
685 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
686 return(1);
687
688 for (i = 0; i < num_matches; i++) {
689 /*
690 * I'm not sure why someone would do this...but...
691 */
692 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
693 continue;
694
695 /*
696 * Look at each of the match flags. If it's set, do the
697 * comparison. If the comparison fails, we don't have a
698 * match, go on to the next item if there is one.
699 */
700 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
701 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
702 continue;
703
704 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
705 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
706 continue;
707
708 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
709 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
710 continue;
711
712 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
713 && (match_buf->pc_vendor != matches[i].pc_vendor))
714 continue;
715
716 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
717 && (match_buf->pc_device != matches[i].pc_device))
718 continue;
719
720 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
721 && (match_buf->pc_class != matches[i].pc_class))
722 continue;
723
724 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
725 && (match_buf->pd_unit != matches[i].pd_unit))
726 continue;
727
728 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
729 && (strncmp(matches[i].pd_name, match_buf->pd_name,
730 sizeof(match_buf->pd_name)) != 0))
731 continue;
732
733 return(0);
734 }
735
736 return(1);
737}
738
739/*
740 * Locate the parent of a PCI device by scanning the PCI devlist
741 * and return the entry for the parent.
742 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
743 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
744 */
745
746pcicfgregs *
747pci_devlist_get_parent(pcicfgregs *cfg)
748{
749 struct devlist *devlist_head;
750 struct pci_devinfo *dinfo;
751 pcicfgregs *bridge_cfg;
752 int i;
753
754 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
755
756 /* If the device is on PCI bus 0, look for the host */
757 if (cfg->bus == 0) {
758 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
759 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
760 bridge_cfg = &dinfo->cfg;
761 if (bridge_cfg->baseclass == PCIC_BRIDGE
762 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
763 && bridge_cfg->bus == cfg->bus) {
764 return bridge_cfg;
765 }
766 }
767 }
768
769 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
770 if (cfg->bus > 0) {
771 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
772 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
773 bridge_cfg = &dinfo->cfg;
774 if (bridge_cfg->baseclass == PCIC_BRIDGE
775 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
776 && bridge_cfg->secondarybus == cfg->bus) {
777 return bridge_cfg;
778 }
779 }
780 }
781
782 return NULL;
783}
784
785static int
41c20dac 786pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td)
984263bc
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787{
788 struct pci_io *io;
789 const char *name;
790 int error;
791
792 if (!(flag & FWRITE))
793 return EPERM;
794
795
796 switch(cmd) {
797 case PCIOCGETCONF:
798 {
799 struct pci_devinfo *dinfo;
800 struct pci_conf_io *cio;
801 struct devlist *devlist_head;
802 struct pci_match_conf *pattern_buf;
803 int num_patterns;
804 size_t iolen;
805 int ionum, i;
806
807 cio = (struct pci_conf_io *)data;
808
809 num_patterns = 0;
810 dinfo = NULL;
811
812 /*
813 * Hopefully the user won't pass in a null pointer, but it
814 * can't hurt to check.
815 */
816 if (cio == NULL) {
817 error = EINVAL;
818 break;
819 }
820
821 /*
822 * If the user specified an offset into the device list,
823 * but the list has changed since they last called this
824 * ioctl, tell them that the list has changed. They will
825 * have to get the list from the beginning.
826 */
827 if ((cio->offset != 0)
828 && (cio->generation != pci_generation)){
829 cio->num_matches = 0;
830 cio->status = PCI_GETCONF_LIST_CHANGED;
831 error = 0;
832 break;
833 }
834
835 /*
836 * Check to see whether the user has asked for an offset
837 * past the end of our list.
838 */
839 if (cio->offset >= pci_numdevs) {
840 cio->num_matches = 0;
841 cio->status = PCI_GETCONF_LAST_DEVICE;
842 error = 0;
843 break;
844 }
845
846 /* get the head of the device queue */
847 devlist_head = &pci_devq;
848
849 /*
850 * Determine how much room we have for pci_conf structures.
851 * Round the user's buffer size down to the nearest
852 * multiple of sizeof(struct pci_conf) in case the user
853 * didn't specify a multiple of that size.
854 */
855 iolen = min(cio->match_buf_len -
856 (cio->match_buf_len % sizeof(struct pci_conf)),
857 pci_numdevs * sizeof(struct pci_conf));
858
859 /*
860 * Since we know that iolen is a multiple of the size of
861 * the pciconf union, it's okay to do this.
862 */
863 ionum = iolen / sizeof(struct pci_conf);
864
865 /*
866 * If this test is true, the user wants the pci_conf
867 * structures returned to match the supplied entries.
868 */
869 if ((cio->num_patterns > 0)
870 && (cio->pat_buf_len > 0)) {
871 /*
872 * pat_buf_len needs to be:
873 * num_patterns * sizeof(struct pci_match_conf)
874 * While it is certainly possible the user just
875 * allocated a large buffer, but set the number of
876 * matches correctly, it is far more likely that
877 * their kernel doesn't match the userland utility
878 * they're using. It's also possible that the user
879 * forgot to initialize some variables. Yes, this
880 * may be overly picky, but I hazard to guess that
881 * it's far more likely to just catch folks that
882 * updated their kernel but not their userland.
883 */
884 if ((cio->num_patterns *
885 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
886 /* The user made a mistake, return an error*/
887 cio->status = PCI_GETCONF_ERROR;
888 printf("pci_ioctl: pat_buf_len %d != "
889 "num_patterns (%d) * sizeof(struct "
890 "pci_match_conf) (%d)\npci_ioctl: "
891 "pat_buf_len should be = %d\n",
892 cio->pat_buf_len, cio->num_patterns,
893 (int)sizeof(struct pci_match_conf),
894 (int)sizeof(struct pci_match_conf) *
895 cio->num_patterns);
896 printf("pci_ioctl: do your headers match your "
897 "kernel?\n");
898 cio->num_matches = 0;
899 error = EINVAL;
900 break;
901 }
902
903 /*
904 * Check the user's buffer to make sure it's readable.
905 */
906 if (!useracc((caddr_t)cio->patterns,
907 cio->pat_buf_len, VM_PROT_READ)) {
908 printf("pci_ioctl: pattern buffer %p, "
909 "length %u isn't user accessible for"
910 " READ\n", cio->patterns,
911 cio->pat_buf_len);
912 error = EACCES;
913 break;
914 }
915 /*
916 * Allocate a buffer to hold the patterns.
917 */
918 pattern_buf = malloc(cio->pat_buf_len, M_TEMP,
919 M_WAITOK);
920 error = copyin(cio->patterns, pattern_buf,
921 cio->pat_buf_len);
922 if (error != 0)
923 break;
924 num_patterns = cio->num_patterns;
925
926 } else if ((cio->num_patterns > 0)
927 || (cio->pat_buf_len > 0)) {
928 /*
929 * The user made a mistake, spit out an error.
930 */
931 cio->status = PCI_GETCONF_ERROR;
932 cio->num_matches = 0;
933 printf("pci_ioctl: invalid GETCONF arguments\n");
934 error = EINVAL;
935 break;
936 } else
937 pattern_buf = NULL;
938
939 /*
940 * Make sure we can write to the match buffer.
941 */
942 if (!useracc((caddr_t)cio->matches,
943 cio->match_buf_len, VM_PROT_WRITE)) {
944 printf("pci_ioctl: match buffer %p, length %u "
945 "isn't user accessible for WRITE\n",
946 cio->matches, cio->match_buf_len);
947 error = EACCES;
948 break;
949 }
950
951 /*
952 * Go through the list of devices and copy out the devices
953 * that match the user's criteria.
954 */
955 for (cio->num_matches = 0, error = 0, i = 0,
956 dinfo = STAILQ_FIRST(devlist_head);
957 (dinfo != NULL) && (cio->num_matches < ionum)
958 && (error == 0) && (i < pci_numdevs);
959 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
960
961 if (i < cio->offset)
962 continue;
963
964 /* Populate pd_name and pd_unit */
965 name = NULL;
966 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
967 name = device_get_name(dinfo->cfg.dev);
968 if (name) {
969 strncpy(dinfo->conf.pd_name, name,
970 sizeof(dinfo->conf.pd_name));
971 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
972 dinfo->conf.pd_unit =
973 device_get_unit(dinfo->cfg.dev);
974 }
975
976 if ((pattern_buf == NULL) ||
977 (pci_conf_match(pattern_buf, num_patterns,
978 &dinfo->conf) == 0)) {
979
980 /*
981 * If we've filled up the user's buffer,
982 * break out at this point. Since we've
983 * got a match here, we'll pick right back
984 * up at the matching entry. We can also
985 * tell the user that there are more matches
986 * left.
987 */
988 if (cio->num_matches >= ionum)
989 break;
990
991 error = copyout(&dinfo->conf,
992 &cio->matches[cio->num_matches],
993 sizeof(struct pci_conf));
994 cio->num_matches++;
995 }
996 }
997
998 /*
999 * Set the pointer into the list, so if the user is getting
1000 * n records at a time, where n < pci_numdevs,
1001 */
1002 cio->offset = i;
1003
1004 /*
1005 * Set the generation, the user will need this if they make
1006 * another ioctl call with offset != 0.
1007 */
1008 cio->generation = pci_generation;
1009
1010 /*
1011 * If this is the last device, inform the user so he won't
1012 * bother asking for more devices. If dinfo isn't NULL, we
1013 * know that there are more matches in the list because of
1014 * the way the traversal is done.
1015 */
1016 if (dinfo == NULL)
1017 cio->status = PCI_GETCONF_LAST_DEVICE;
1018 else
1019 cio->status = PCI_GETCONF_MORE_DEVS;
1020
1021 if (pattern_buf != NULL)
1022 free(pattern_buf, M_TEMP);
1023
1024 break;
1025 }
1026 case PCIOCREAD:
1027 io = (struct pci_io *)data;
1028 switch(io->pi_width) {
1029 pcicfgregs probe;
1030 case 4:
1031 case 2:
1032 case 1:
1033 probe.hose = -1;
1034 probe.bus = io->pi_sel.pc_bus;
1035 probe.slot = io->pi_sel.pc_dev;
1036 probe.func = io->pi_sel.pc_func;
1037 io->pi_data = pci_cfgread(&probe,
1038 io->pi_reg, io->pi_width);
1039 error = 0;
1040 break;
1041 default:
1042 error = ENODEV;
1043 break;
1044 }
1045 break;
1046
1047 case PCIOCWRITE:
1048 io = (struct pci_io *)data;
1049 switch(io->pi_width) {
1050 pcicfgregs probe;
1051 case 4:
1052 case 2:
1053 case 1:
1054 probe.hose = -1;
1055 probe.bus = io->pi_sel.pc_bus;
1056 probe.slot = io->pi_sel.pc_dev;
1057 probe.func = io->pi_sel.pc_func;
1058 pci_cfgwrite(&probe,
1059 io->pi_reg, io->pi_data, io->pi_width);
1060 error = 0;
1061 break;
1062 default:
1063 error = ENODEV;
1064 break;
1065 }
1066 break;
1067
1068 default:
1069 error = ENOTTY;
1070 break;
1071 }
1072
1073 return (error);
1074}
1075
1076#define PCI_CDEV 78
1077
1078static struct cdevsw pcicdev = {
fabb8ceb
MD
1079 /* name */ "pci",
1080 /* maj */ PCI_CDEV,
1081 /* flags */ 0,
1082 /* port */ NULL,
1083 /* autoq */ 0,
1084
984263bc
MD
1085 /* open */ pci_open,
1086 /* close */ pci_close,
1087 /* read */ noread,
1088 /* write */ nowrite,
1089 /* ioctl */ pci_ioctl,
1090 /* poll */ nopoll,
1091 /* mmap */ nommap,
1092 /* strategy */ nostrategy,
984263bc 1093 /* dump */ nodump,
fabb8ceb 1094 /* psize */ nopsize
984263bc
MD
1095};
1096
1097#include "pci_if.h"
1098
1099/*
1100 * A simple driver to wrap the old pci driver mechanism for back-compat.
1101 */
1102
1103static int
1104pci_compat_probe(device_t dev)
1105{
1106 struct pci_device *dvp;
1107 struct pci_devinfo *dinfo;
1108 pcicfgregs *cfg;
1109 const char *name;
1110 int error;
1111
1112 dinfo = device_get_ivars(dev);
1113 cfg = &dinfo->cfg;
1114 dvp = device_get_driver(dev)->priv;
1115
1116 /*
1117 * Do the wrapped probe.
1118 */
1119 error = ENXIO;
1120 if (dvp && dvp->pd_probe) {
1121 name = dvp->pd_probe(cfg, (cfg->device << 16) + cfg->vendor);
1122 if (name) {
1123 device_set_desc_copy(dev, name);
1124 /* Allow newbus drivers to match "better" */
1125 error = -200;
1126 }
1127 }
1128
1129 return error;
1130}
1131
1132static int
1133pci_compat_attach(device_t dev)
1134{
1135 struct pci_device *dvp;
1136 struct pci_devinfo *dinfo;
1137 pcicfgregs *cfg;
1138 int unit;
1139
1140 dinfo = device_get_ivars(dev);
1141 cfg = &dinfo->cfg;
1142 dvp = device_get_driver(dev)->priv;
1143
1144 unit = device_get_unit(dev);
1145 if (unit > *dvp->pd_count)
1146 *dvp->pd_count = unit;
1147 if (dvp->pd_attach)
1148 dvp->pd_attach(cfg, unit);
1149 device_printf(dev, "driver is using old-style compatibility shims\n");
1150 return 0;
1151}
1152
1153static device_method_t pci_compat_methods[] = {
1154 /* Device interface */
1155 DEVMETHOD(device_probe, pci_compat_probe),
1156 DEVMETHOD(device_attach, pci_compat_attach),
1157
1158 { 0, 0 }
1159};
1160
1161static devclass_t pci_devclass;
1162
1163/*
1164 * Create a new style driver around each old pci driver.
1165 */
1166int
1167compat_pci_handler(module_t mod, int type, void *data)
1168{
1169 struct pci_device *dvp = (struct pci_device *)data;
1170 driver_t *driver;
1171
1172 switch (type) {
1173 case MOD_LOAD:
1174 driver = malloc(sizeof(driver_t), M_DEVBUF, M_NOWAIT);
1175 if (!driver)
1176 return ENOMEM;
1177 bzero(driver, sizeof(driver_t));
1178 driver->name = dvp->pd_name;
1179 driver->methods = pci_compat_methods;
80eff43d 1180 driver->size = sizeof(struct pci_devinfo *);
984263bc
MD
1181 driver->priv = dvp;
1182 devclass_add_driver(pci_devclass, driver);
1183 break;
1184 case MOD_UNLOAD:
1185 printf("%s: module unload not supported!\n", dvp->pd_name);
1186 return EOPNOTSUPP;
1187 default:
1188 break;
1189 }
1190 return 0;
1191}
1192
1193/*
1194 * New style pci driver. Parent device is either a pci-host-bridge or a
1195 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1196 */
1197
1198static void
1199pci_print_verbose(struct pci_devinfo *dinfo)
1200{
1201 if (bootverbose) {
1202 pcicfgregs *cfg = &dinfo->cfg;
1203
1204 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
1205 cfg->vendor, cfg->device, cfg->revid);
1206 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
1207 cfg->baseclass, cfg->subclass, cfg->progif,
1208 cfg->hdrtype, cfg->mfdev);
1209 printf("\tsubordinatebus=%x \tsecondarybus=%x\n",
1210 cfg->subordinatebus, cfg->secondarybus);
1211#ifdef PCI_DEBUG
1212 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
1213 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
1214 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
1215 cfg->lattimer, cfg->lattimer * 30,
1216 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1217#endif /* PCI_DEBUG */
1218 if (cfg->intpin > 0)
1219 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
1220 }
1221}
1222
1223static int
1224pci_porten(pcicfgregs *cfg)
1225{
1226 return ((cfg->cmdreg & PCIM_CMD_PORTEN) != 0);
1227}
1228
1229static int
1230pci_memen(pcicfgregs *cfg)
1231{
1232 return ((cfg->cmdreg & PCIM_CMD_MEMEN) != 0);
1233}
1234
1235/*
1236 * Add a resource based on a pci map register. Return 1 if the map
1237 * register is a 32bit map register or 2 if it is a 64bit register.
1238 */
1239static int
1240pci_add_map(device_t dev, pcicfgregs* cfg, int reg)
1241{
1242 struct pci_devinfo *dinfo = device_get_ivars(dev);
1243 struct resource_list *rl = &dinfo->resources;
1244 u_int32_t map;
1245 u_int64_t base;
1246 u_int8_t ln2size;
1247 u_int8_t ln2range;
1248 u_int32_t testval;
1249
1250 int type;
1251
1252 map = pci_cfgread(cfg, reg, 4);
1253
1254 if (map == 0 || map == 0xffffffff)
1255 return 1; /* skip invalid entry */
1256
1257 pci_cfgwrite(cfg, reg, 0xffffffff, 4);
1258 testval = pci_cfgread(cfg, reg, 4);
1259 pci_cfgwrite(cfg, reg, map, 4);
1260
1261 base = pci_mapbase(map);
1262 if (pci_maptype(map) & PCI_MAPMEM)
1263 type = SYS_RES_MEMORY;
1264 else
1265 type = SYS_RES_IOPORT;
1266 ln2size = pci_mapsize(testval);
1267 ln2range = pci_maprange(testval);
1268 if (ln2range == 64) {
1269 /* Read the other half of a 64bit map register */
1270 base |= (u_int64_t) pci_cfgread(cfg, reg + 4, 4) << 32;
1271 }
1272
1273#ifdef __alpha__
1274 /*
1275 * XXX: encode hose number in the base addr,
1276 * This will go away once the bus_space functions
1277 * can deal with multiple hoses
1278 */
1279
1280 if (cfg->hose) {
1281 u_int32_t mask, shift, maxh;
1282
1283 switch (hwrpb->rpb_type) {
1284 case ST_DEC_4100:
1285 case -ST_DEC_4100:
1286 mask = 0xc0000000;
1287 shift = 30;
1288 maxh = 4; /* not a hose. MCPCIA instance # */
1289 break;
1290 case ST_DEC_21000:
1291 mask = 0xf8000000;
1292 shift = 27;
1293 maxh = 32;
1294 break;
1295 case ST_DEC_6600:
1296 mask = 0x80000000;
1297 shift = 31;
1298 maxh = 2;
1299 break;
1300 default:
1301 mask = 0;
1302 shift = 0;
1303 maxh = 0;
1304 break;
1305 }
1306 if (base & mask) {
1307 printf("base addr = 0x%llx\n", (long long) base);
1308 printf("mask addr = 0x%lx\n", (long) mask);
1309 printf("hacked addr = 0x%llx\n", (long long)
1310 (base | ((u_int64_t)cfg->hose << shift)));
1311 panic("hose encoding hack would clobber base addr");
1312 /* NOTREACHED */
1313 }
1314 if (cfg->hose >= maxh) {
1315 panic("Hose %d - can only encode %d hose(s)",
1316 cfg->hose, maxh);
1317 /* NOTREACHED */
1318 }
1319 base |= ((u_int64_t)cfg->hose << shift);
1320 }
1321#endif
1322
1323 /*
1324 * This code theoretically does the right thing, but has
1325 * undesirable side effects in some cases where
1326 * peripherals respond oddly to having these bits
1327 * enabled. Leave them alone by default.
1328 */
1329#ifdef PCI_ENABLE_IO_MODES
1330 if (type == SYS_RES_IOPORT && !pci_porten(cfg)) {
1331 cfg->cmdreg |= PCIM_CMD_PORTEN;
1332 pci_cfgwrite(cfg, PCIR_COMMAND, cfg->cmdreg, 2);
1333 }
1334 if (type == SYS_RES_MEMORY && !pci_memen(cfg)) {
1335 cfg->cmdreg |= PCIM_CMD_MEMEN;
1336 pci_cfgwrite(cfg, PCIR_COMMAND, cfg->cmdreg, 2);
1337 }
1338#else
1339 if (type == SYS_RES_IOPORT && !pci_porten(cfg))
1340 return 1;
1341 if (type == SYS_RES_MEMORY && !pci_memen(cfg))
1342 return 1;
1343#endif
1344
1345 resource_list_add(rl, type, reg,
1346 base, base + (1 << ln2size) - 1,
1347 (1 << ln2size));
1348
1349 if (bootverbose) {
1350 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
1351 reg, pci_maptype(base), ln2range,
1352 (unsigned int) base, ln2size);
1353 }
1354
1355 return (ln2range == 64) ? 2 : 1;
1356}
1357
1358static void
1359pci_add_resources(device_t dev, pcicfgregs* cfg)
1360{
1361 struct pci_devinfo *dinfo = device_get_ivars(dev);
1362 struct resource_list *rl = &dinfo->resources;
1363 struct pci_quirk *q;
1364 int i;
1365
1366 for (i = 0; i < cfg->nummaps;) {
1367 i += pci_add_map(dev, cfg, PCIR_MAPS + i*4);
1368 }
1369
1370 for (q = &pci_quirks[0]; q->devid; q++) {
1371 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1372 && q->type == PCI_QUIRK_MAP_REG)
1373 pci_add_map(dev, cfg, q->arg1);
1374 }
1375
1376 if (cfg->intpin > 0 && cfg->intline != 255)
1377 resource_list_add(rl, SYS_RES_IRQ, 0,
1378 cfg->intline, cfg->intline, 1);
1379}
1380
1381static void
1382pci_add_children(device_t dev, int busno)
1383{
1384 pcicfgregs probe;
1385
1386#ifdef SIMOS
1387#undef PCI_SLOTMAX
1388#define PCI_SLOTMAX 0
1389#endif
1390
1391 bzero(&probe, sizeof probe);
1392#ifdef __alpha__
1393 probe.hose = pcib_get_hose(dev);
1394#endif
1395#ifdef __i386__
1396 probe.hose = 0;
1397#endif
1398 probe.bus = busno;
1399
1400 for (probe.slot = 0; probe.slot <= PCI_SLOTMAX; probe.slot++) {
1401 int pcifunchigh = 0;
1402 for (probe.func = 0; probe.func <= pcifunchigh; probe.func++) {
1403 struct pci_devinfo *dinfo = pci_readcfg(&probe);
1404 if (dinfo != NULL) {
1405 if (dinfo->cfg.mfdev)
1406 pcifunchigh = 7;
1407
1408 pci_print_verbose(dinfo);
1409 dinfo->cfg.dev = device_add_child(dev, NULL, -1);
1410 device_set_ivars(dinfo->cfg.dev, dinfo);
1411 pci_add_resources(dinfo->cfg.dev, &dinfo->cfg);
1412 }
1413 }
1414 }
1415}
1416
1417static int
1418pci_new_probe(device_t dev)
1419{
1420 static int once;
1421
1422 device_set_desc(dev, "PCI bus");
1423 pci_add_children(dev, device_get_unit(dev));
1424 if (!once) {
1425 make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci");
1426 once++;
1427 }
1428
1429 return 0;
1430}
1431
1432static int
1433pci_print_resources(struct resource_list *rl, const char *name, int type,
1434 const char *format)
1435{
1436 struct resource_list_entry *rle;
1437 int printed, retval;
1438
1439 printed = 0;
1440 retval = 0;
1441 /* Yes, this is kinda cheating */
1442 SLIST_FOREACH(rle, rl, link) {
1443 if (rle->type == type) {
1444 if (printed == 0)
1445 retval += printf(" %s ", name);
1446 else if (printed > 0)
1447 retval += printf(",");
1448 printed++;
1449 retval += printf(format, rle->start);
1450 if (rle->count > 1) {
1451 retval += printf("-");
1452 retval += printf(format, rle->start +
1453 rle->count - 1);
1454 }
1455 }
1456 }
1457 return retval;
1458}
1459
1460static int
1461pci_print_child(device_t dev, device_t child)
1462{
1463 struct pci_devinfo *dinfo;
1464 struct resource_list *rl;
1465 pcicfgregs *cfg;
1466 int retval = 0;
1467
1468 dinfo = device_get_ivars(child);
1469 cfg = &dinfo->cfg;
1470 rl = &dinfo->resources;
1471
1472 retval += bus_print_child_header(dev, child);
1473
1474 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1475 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1476 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1477 if (device_get_flags(dev))
1478 retval += printf(" flags %#x", device_get_flags(dev));
1479
1480 retval += printf(" at device %d.%d", pci_get_slot(child),
1481 pci_get_function(child));
1482
1483 retval += bus_print_child_footer(dev, child);
1484
1485 return (retval);
1486}
1487
1488static void
1489pci_probe_nomatch(device_t dev, device_t child)
1490{
1491 struct pci_devinfo *dinfo;
1492 pcicfgregs *cfg;
1493 const char *desc;
1494 int unknown;
1495
1496 unknown = 0;
1497 dinfo = device_get_ivars(child);
1498 cfg = &dinfo->cfg;
1499 desc = pci_ata_match(child);
1500 if (!desc) desc = pci_usb_match(child);
1501 if (!desc) desc = pci_vga_match(child);
1502 if (!desc) {
1503 desc = "unknown card";
1504 unknown++;
1505 }
1506 device_printf(dev, "<%s>", desc);
1507 if (bootverbose || unknown) {
1508 printf(" (vendor=0x%04x, dev=0x%04x)",
1509 cfg->vendor,
1510 cfg->device);
1511 }
1512 printf(" at %d.%d",
1513 pci_get_slot(child),
1514 pci_get_function(child));
1515 if (cfg->intpin > 0 && cfg->intline != 255) {
1516 printf(" irq %d", cfg->intline);
1517 }
1518 printf("\n");
1519
1520 return;
1521}
1522
1523static int
1524pci_read_ivar(device_t dev, device_t child, int which, u_long *result)
1525{
1526 struct pci_devinfo *dinfo;
1527 pcicfgregs *cfg;
1528
1529 dinfo = device_get_ivars(child);
1530 cfg = &dinfo->cfg;
1531
1532 switch (which) {
1533 case PCI_IVAR_SUBVENDOR:
1534 *result = cfg->subvendor;
1535 break;
1536 case PCI_IVAR_SUBDEVICE:
1537 *result = cfg->subdevice;
1538 break;
1539 case PCI_IVAR_VENDOR:
1540 *result = cfg->vendor;
1541 break;
1542 case PCI_IVAR_DEVICE:
1543 *result = cfg->device;
1544 break;
1545 case PCI_IVAR_DEVID:
1546 *result = (cfg->device << 16) | cfg->vendor;
1547 break;
1548 case PCI_IVAR_CLASS:
1549 *result = cfg->baseclass;
1550 break;
1551 case PCI_IVAR_SUBCLASS:
1552 *result = cfg->subclass;
1553 break;
1554 case PCI_IVAR_PROGIF:
1555 *result = cfg->progif;
1556 break;
1557 case PCI_IVAR_REVID:
1558 *result = cfg->revid;
1559 break;
1560 case PCI_IVAR_INTPIN:
1561 *result = cfg->intpin;
1562 break;
1563 case PCI_IVAR_IRQ:
1564 *result = cfg->intline;
1565 break;
1566 case PCI_IVAR_BUS:
1567 *result = cfg->bus;
1568 break;
1569 case PCI_IVAR_SLOT:
1570 *result = cfg->slot;
1571 break;
1572 case PCI_IVAR_FUNCTION:
1573 *result = cfg->func;
1574 break;
1575 case PCI_IVAR_SECONDARYBUS:
1576 *result = cfg->secondarybus;
1577 break;
1578 case PCI_IVAR_SUBORDINATEBUS:
1579 *result = cfg->subordinatebus;
1580 break;
1581 case PCI_IVAR_HOSE:
1582 /*
1583 * Pass up to parent bridge.
1584 */
1585 *result = pcib_get_hose(dev);
1586 break;
1587 default:
1588 return ENOENT;
1589 }
1590 return 0;
1591}
1592
1593static int
1594pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1595{
1596 struct pci_devinfo *dinfo;
1597 pcicfgregs *cfg;
1598
1599 dinfo = device_get_ivars(child);
1600 cfg = &dinfo->cfg;
1601
1602 switch (which) {
1603 case PCI_IVAR_SUBVENDOR:
1604 case PCI_IVAR_SUBDEVICE:
1605 case PCI_IVAR_VENDOR:
1606 case PCI_IVAR_DEVICE:
1607 case PCI_IVAR_DEVID:
1608 case PCI_IVAR_CLASS:
1609 case PCI_IVAR_SUBCLASS:
1610 case PCI_IVAR_PROGIF:
1611 case PCI_IVAR_REVID:
1612 case PCI_IVAR_INTPIN:
1613 case PCI_IVAR_IRQ:
1614 case PCI_IVAR_BUS:
1615 case PCI_IVAR_SLOT:
1616 case PCI_IVAR_FUNCTION:
1617 return EINVAL; /* disallow for now */
1618
1619 case PCI_IVAR_SECONDARYBUS:
1620 cfg->secondarybus = value;
1621 break;
1622 case PCI_IVAR_SUBORDINATEBUS:
1623 cfg->subordinatebus = value;
1624 break;
1625 default:
1626 return ENOENT;
1627 }
1628 return 0;
1629}
1630
1631static struct resource *
1632pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1633 u_long start, u_long end, u_long count, u_int flags)
1634{
1635 struct pci_devinfo *dinfo = device_get_ivars(child);
1636 struct resource_list *rl = &dinfo->resources;
1637
1638#ifdef __i386__ /* Only supported on x86 in stable */
1639 pcicfgregs *cfg = &dinfo->cfg;
1640 /*
1641 * Perform lazy resource allocation
1642 *
1643 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY
1644 */
1645 if (device_get_parent(child) == dev) {
1646 /*
1647 * If device doesn't have an interrupt routed, and is
1648 * deserving of an interrupt, try to assign it one.
1649 */
1650 if ((type == SYS_RES_IRQ) &&
1651 (cfg->intline == 255 || cfg->intline == 0) &&
1652 (cfg->intpin != 0) && (start == 0) && (end == ~0UL)) {
1653 cfg->intline = pci_cfgintr(pci_get_bus(child),
1654 pci_get_slot(child), cfg->intpin);
1655 if (cfg->intline != 255) {
1656 pci_write_config(child, PCIR_INTLINE,
1657 cfg->intline, 1);
1658 resource_list_add(rl, SYS_RES_IRQ, 0,
1659 cfg->intline, cfg->intline, 1);
1660 }
1661 }
1662 }
1663#endif
1664 return resource_list_alloc(rl, dev, child, type, rid,
1665 start, end, count, flags);
1666}
1667
1668static int
1669pci_release_resource(device_t dev, device_t child, int type, int rid,
1670 struct resource *r)
1671{
1672 struct pci_devinfo *dinfo = device_get_ivars(child);
1673 struct resource_list *rl = &dinfo->resources;
1674
1675 return resource_list_release(rl, dev, child, type, rid, r);
1676}
1677
1678static int
1679pci_set_resource(device_t dev, device_t child, int type, int rid,
1680 u_long start, u_long count)
1681{
1682 struct pci_devinfo *dinfo = device_get_ivars(child);
1683 struct resource_list *rl = &dinfo->resources;
1684
1685 resource_list_add(rl, type, rid, start, start + count - 1, count);
1686 return 0;
1687}
1688
1689static int
1690pci_get_resource(device_t dev, device_t child, int type, int rid,
1691 u_long *startp, u_long *countp)
1692{
1693 struct pci_devinfo *dinfo = device_get_ivars(child);
1694 struct resource_list *rl = &dinfo->resources;
1695 struct resource_list_entry *rle;
1696
1697 rle = resource_list_find(rl, type, rid);
1698 if (!rle)
1699 return ENOENT;
1700
1701 if (startp)
1702 *startp = rle->start;
1703 if (countp)
1704 *countp = rle->count;
1705
1706 return 0;
1707}
1708
1709static void
1710pci_delete_resource(device_t dev, device_t child, int type, int rid)
1711{
1712 printf("pci_delete_resource: PCI resources can not be deleted\n");
1713}
1714
1715static u_int32_t
1716pci_read_config_method(device_t dev, device_t child, int reg, int width)
1717{
1718 struct pci_devinfo *dinfo = device_get_ivars(child);
1719 pcicfgregs *cfg = &dinfo->cfg;
1720 return pci_cfgread(cfg, reg, width);
1721}
1722
1723static void
1724pci_write_config_method(device_t dev, device_t child, int reg,
1725 u_int32_t val, int width)
1726{
1727 struct pci_devinfo *dinfo = device_get_ivars(child);
1728 pcicfgregs *cfg = &dinfo->cfg;
1729 pci_cfgwrite(cfg, reg, val, width);
1730}
1731
1732static int
1733pci_modevent(module_t mod, int what, void *arg)
1734{
1735 switch (what) {
1736 case MOD_LOAD:
1737 STAILQ_INIT(&pci_devq);
1738 break;
1739
1740 case MOD_UNLOAD:
1741 break;
1742 }
1743
1744 return 0;
1745}
1746
1747static device_method_t pci_methods[] = {
1748 /* Device interface */
1749 DEVMETHOD(device_probe, pci_new_probe),
1750 DEVMETHOD(device_attach, bus_generic_attach),
1751 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1752 DEVMETHOD(device_suspend, bus_generic_suspend),
1753 DEVMETHOD(device_resume, bus_generic_resume),
1754
1755 /* Bus interface */
1756 DEVMETHOD(bus_print_child, pci_print_child),
1757 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
1758 DEVMETHOD(bus_read_ivar, pci_read_ivar),
1759 DEVMETHOD(bus_write_ivar, pci_write_ivar),
1760 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1761 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
1762 DEVMETHOD(bus_release_resource, pci_release_resource),
1763 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1764 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1765 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1766 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1767 DEVMETHOD(bus_set_resource, pci_set_resource),
1768 DEVMETHOD(bus_get_resource, pci_get_resource),
1769 DEVMETHOD(bus_delete_resource, pci_delete_resource),
1770
1771 /* PCI interface */
1772 DEVMETHOD(pci_read_config, pci_read_config_method),
1773 DEVMETHOD(pci_write_config, pci_write_config_method),
1774 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
1775 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
1776 DEVMETHOD(pci_enable_io, pci_enable_io_method),
1777 DEVMETHOD(pci_disable_io, pci_disable_io_method),
1778 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
1779 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
1780
1781 { 0, 0 }
1782};
1783
1784static driver_t pci_driver = {
1785 "pci",
1786 pci_methods,
1787 1, /* no softc */
1788};
1789
1790DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);