M_MCAST and M_BCAST are set before bridge_input() is executed, so use these
[dragonfly.git] / sys / bus / pci / pci.c
CommitLineData
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1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
c7e4e7eb 27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.49 2007/11/25 10:31:40 sephe Exp $
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28 *
29 */
30
31#include "opt_bus.h"
32#include "opt_pci.h"
33
dc5a7bd2 34#include "opt_compat_oldpci.h"
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35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/malloc.h>
39#include <sys/module.h>
40#include <sys/fcntl.h>
41#include <sys/conf.h>
42#include <sys/kernel.h>
43#include <sys/queue.h>
44#include <sys/types.h>
45#include <sys/buf.h>
46
47#include <vm/vm.h>
48#include <vm/pmap.h>
49#include <vm/vm_extern.h>
50
51#include <sys/bus.h>
984263bc 52#include <sys/rman.h>
97359a5b 53#include <machine/smp.h>
984263bc 54#ifdef __i386__
bbca97bc 55#include <bus/pci/i386/pci_cfgreg.h>
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56#endif
57
dc5a7bd2 58#include <sys/pciio.h>
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59#include "pcireg.h"
60#include "pcivar.h"
22457186 61#include "pci_private.h"
984263bc 62
4a5a2d63
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63#include "pcib_if.h"
64
e126caf1 65devclass_t pci_devclass;
2581072f 66const char *pcib_owner;
dc5a7bd2 67
e9d8f4df 68static void pci_read_capabilities(device_t dev, pcicfgregs *cfg);
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69
70struct pci_quirk {
71 u_int32_t devid; /* Vendor/device of the card */
72 int type;
3e4db402 73#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
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74 int arg1;
75 int arg2;
76};
77
78struct pci_quirk pci_quirks[] = {
79 /*
80 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
81 */
82 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
83 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
f1f0bfb2
JS
84 /* As does the Serverworks OSB4 (the SMBus mapping register) */
85 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
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86
87 { 0 }
88};
89
90/* map register information */
91#define PCI_MAPMEM 0x01 /* memory map */
92#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
93#define PCI_MAPPORT 0x04 /* port map */
94
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95static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
96u_int32_t pci_numdevs = 0;
97static u_int32_t pci_generation = 0;
98
99device_t
c0f16abb 100pci_find_bsf(u_int8_t bus, u_int8_t slot, u_int8_t func)
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101{
102 struct pci_devinfo *dinfo;
103
104 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
105 if ((dinfo->cfg.bus == bus) &&
106 (dinfo->cfg.slot == slot) &&
107 (dinfo->cfg.func == func)) {
108 return (dinfo->cfg.dev);
109 }
110 }
111
112 return (NULL);
113}
114
115device_t
c0f16abb 116pci_find_device(u_int16_t vendor, u_int16_t device)
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117{
118 struct pci_devinfo *dinfo;
119
120 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
121 if ((dinfo->cfg.vendor == vendor) &&
122 (dinfo->cfg.device == device)) {
123 return (dinfo->cfg.dev);
124 }
125 }
126
127 return (NULL);
128}
129
130/* return base address of memory or port map */
131
132static u_int32_t
133pci_mapbase(unsigned mapreg)
134{
135 int mask = 0x03;
136 if ((mapreg & 0x01) == 0)
137 mask = 0x0f;
138 return (mapreg & ~mask);
139}
140
141/* return map type of memory or port map */
142
143static int
144pci_maptype(unsigned mapreg)
145{
146 static u_int8_t maptype[0x10] = {
147 PCI_MAPMEM, PCI_MAPPORT,
148 PCI_MAPMEM, 0,
149 PCI_MAPMEM, PCI_MAPPORT,
150 0, 0,
151 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
152 PCI_MAPMEM|PCI_MAPMEMP, 0,
153 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
154 0, 0,
155 };
156
157 return maptype[mapreg & 0x0f];
158}
159
160/* return log2 of map size decoded for memory or port map */
161
162static int
163pci_mapsize(unsigned testval)
164{
165 int ln2size;
166
167 testval = pci_mapbase(testval);
168 ln2size = 0;
169 if (testval != 0) {
170 while ((testval & 1) == 0)
171 {
172 ln2size++;
173 testval >>= 1;
174 }
175 }
176 return (ln2size);
177}
178
179/* return log2 of address range supported by map register */
180
181static int
182pci_maprange(unsigned mapreg)
183{
184 int ln2range = 0;
185 switch (mapreg & 0x07) {
186 case 0x00:
187 case 0x01:
188 case 0x05:
189 ln2range = 32;
190 break;
191 case 0x02:
192 ln2range = 20;
193 break;
194 case 0x04:
195 ln2range = 64;
196 break;
197 }
198 return (ln2range);
199}
200
201/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
202
203static void
204pci_fixancient(pcicfgregs *cfg)
205{
206 if (cfg->hdrtype != 0)
207 return;
208
209 /* PCI to PCI bridges use header type 1 */
210 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
211 cfg->hdrtype = 1;
212}
213
214/* read config data specific to header type 1 device (PCI to PCI bridge) */
215
216static void *
4a5a2d63 217pci_readppb(device_t pcib, int b, int s, int f)
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218{
219 pcih1cfgregs *p;
220
efda3bd0 221 p = kmalloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
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222 if (p == NULL)
223 return (NULL);
224
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225 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
226 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
984263bc 227
4a5a2d63 228 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
984263bc 229
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230 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
231 PCIR_IOBASEH_1, 2),
232 PCIB_READ_CONFIG(pcib, b, s, f,
233 PCIR_IOBASEL_1, 1));
234 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
235 PCIR_IOLIMITH_1, 2),
236 PCIB_READ_CONFIG(pcib, b, s, f,
237 PCIR_IOLIMITL_1, 1));
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238
239 p->membase = PCI_PPBMEMBASE (0,
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240 PCIB_READ_CONFIG(pcib, b, s, f,
241 PCIR_MEMBASE_1, 2));
984263bc 242 p->memlimit = PCI_PPBMEMLIMIT (0,
4a5a2d63
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243 PCIB_READ_CONFIG(pcib, b, s, f,
244 PCIR_MEMLIMIT_1, 2));
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245
246 p->pmembase = PCI_PPBMEMBASE (
4a5a2d63
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247 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
248 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
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249
250 p->pmemlimit = PCI_PPBMEMLIMIT (
4a5a2d63
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251 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
252 PCIR_PMLIMITH_1, 4),
253 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
254
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255 return (p);
256}
257
258/* read config data specific to header type 2 device (PCI to CardBus bridge) */
259
260static void *
4a5a2d63 261pci_readpcb(device_t pcib, int b, int s, int f)
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262{
263 pcih2cfgregs *p;
264
efda3bd0 265 p = kmalloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
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266 if (p == NULL)
267 return (NULL);
268
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269 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
270 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
984263bc 271
4a5a2d63 272 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
984263bc 273
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274 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
275 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
276 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
277 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
984263bc 278
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279 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
280 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
281 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
282 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
984263bc 283
4a5a2d63 284 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
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285 return p;
286}
287
288/* extract header type specific config data */
289
290static void
4a5a2d63 291pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
984263bc 292{
4a5a2d63 293#define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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294 switch (cfg->hdrtype) {
295 case 0:
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296 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
297 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
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298 cfg->nummaps = PCI_MAXMAPS_0;
299 break;
300 case 1:
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301 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
302 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
303 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
304 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
984263bc 305 cfg->nummaps = PCI_MAXMAPS_1;
4a5a2d63 306 cfg->hdrspec = pci_readppb(pcib, b, s, f);
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307 break;
308 case 2:
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309 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
310 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
311 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
312 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
984263bc 313 cfg->nummaps = PCI_MAXMAPS_2;
4a5a2d63 314 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
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315 break;
316 }
4a5a2d63 317#undef REG
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318}
319
320/* read configuration header into pcicfgrect structure */
321
22457186 322struct pci_devinfo *
c01b8d84 323pci_read_device(device_t pcib, int b, int s, int f, size_t size)
984263bc 324{
4a5a2d63 325#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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326
327 pcicfgregs *cfg = NULL;
328 struct pci_devinfo *devlist_entry;
329 struct devlist *devlist_head;
330
331 devlist_head = &pci_devq;
332
333 devlist_entry = NULL;
334
4a5a2d63 335 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
984263bc 336
efda3bd0 337 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
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338 if (devlist_entry == NULL)
339 return (NULL);
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MD
340
341 cfg = &devlist_entry->cfg;
342
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343 cfg->bus = b;
344 cfg->slot = s;
345 cfg->func = f;
346 cfg->vendor = REG(PCIR_VENDOR, 2);
347 cfg->device = REG(PCIR_DEVICE, 2);
348 cfg->cmdreg = REG(PCIR_COMMAND, 2);
349 cfg->statreg = REG(PCIR_STATUS, 2);
350 cfg->baseclass = REG(PCIR_CLASS, 1);
351 cfg->subclass = REG(PCIR_SUBCLASS, 1);
352 cfg->progif = REG(PCIR_PROGIF, 1);
353 cfg->revid = REG(PCIR_REVID, 1);
e126caf1 354 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
4a5a2d63
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355 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
356 cfg->lattimer = REG(PCIR_LATTIMER, 1);
357 cfg->intpin = REG(PCIR_INTPIN, 1);
358 cfg->intline = REG(PCIR_INTLINE, 1);
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359
360#ifdef APIC_IO
97359a5b
MD
361 /*
362 * If using the APIC the intpin is probably wrong, since it
363 * is often setup by the BIOS with the PIC in mind.
364 */
984263bc
MD
365 if (cfg->intpin != 0) {
366 int airq;
367
368 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
369 if (airq >= 0) {
370 /* PCI specific entry found in MP table */
371 if (airq != cfg->intline) {
372 undirect_pci_irq(cfg->intline);
373 cfg->intline = airq;
374 }
375 } else {
376 /*
377 * PCI interrupts might be redirected to the
378 * ISA bus according to some MP tables. Use the
379 * same methods as used by the ISA devices
380 * devices to find the proper IOAPIC int pin.
381 */
382 airq = isa_apic_irq(cfg->intline);
383 if ((airq >= 0) && (airq != cfg->intline)) {
384 /* XXX: undirect_pci_irq() ? */
385 undirect_isa_irq(cfg->intline);
386 cfg->intline = airq;
387 }
388 }
389 }
390#endif /* APIC_IO */
391
4a5a2d63
JS
392 cfg->mingnt = REG(PCIR_MINGNT, 1);
393 cfg->maxlat = REG(PCIR_MAXLAT, 1);
984263bc
MD
394
395 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
396 cfg->hdrtype &= ~PCIM_MFDEV;
397
398 pci_fixancient(cfg);
4a5a2d63 399 pci_hdrtypedata(pcib, b, s, f, cfg);
e9d8f4df 400 pci_read_capabilities(pcib, cfg);
984263bc
MD
401
402 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
403
404 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
405 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
406 devlist_entry->conf.pc_sel.pc_func = cfg->func;
407 devlist_entry->conf.pc_hdr = cfg->hdrtype;
408
409 devlist_entry->conf.pc_subvendor = cfg->subvendor;
410 devlist_entry->conf.pc_subdevice = cfg->subdevice;
411 devlist_entry->conf.pc_vendor = cfg->vendor;
412 devlist_entry->conf.pc_device = cfg->device;
413
414 devlist_entry->conf.pc_class = cfg->baseclass;
415 devlist_entry->conf.pc_subclass = cfg->subclass;
416 devlist_entry->conf.pc_progif = cfg->progif;
417 devlist_entry->conf.pc_revid = cfg->revid;
418
419 pci_numdevs++;
420 pci_generation++;
421 }
422 return (devlist_entry);
423#undef REG
424}
425
1361c4cd
SZ
426static int
427pci_fixup_nextptr(int *nextptr0)
428{
429 int nextptr = *nextptr0;
430
431 /* "Next pointer" is only one byte */
432 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
433
434 if (nextptr & 0x3) {
435 /*
436 * PCI local bus spec 3.0:
437 *
438 * "... The bottom two bits of all pointers are reserved
439 * and must be implemented as 00b although software must
440 * mask them to allow for future uses of these bits ..."
441 */
442 if (bootverbose) {
443 kprintf("Illegal PCI extended capability "
444 "offset, fixup 0x%02x -> 0x%02x\n",
445 nextptr, nextptr & ~0x3);
446 }
447 nextptr &= ~0x3;
448 }
449 *nextptr0 = nextptr;
450
451 if (nextptr < 0x40) {
452 if (nextptr != 0) {
453 kprintf("Illegal PCI extended capability "
454 "offset 0x%02x", nextptr);
455 }
456 return 0;
457 }
458 return 1;
459}
460
8475d8bb
SZ
461static void
462pci_read_cap_pmgt(device_t pcib, int ptr, pcicfgregs *cfg)
463{
464#define REG(n, w) \
465 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
466
467 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
468
469 if (pmgt->pp_cap)
470 return;
471
472 pmgt->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
473 pmgt->pp_status = ptr + PCIR_POWER_STATUS;
474 pmgt->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
475 /*
476 * XXX
477 * Following way may be used to to test whether
478 * 'data' register exists:
479 * if 'data_select' register of
480 * PCIR_POWER_STATUS(bits[12,9]) is read-only
481 * then 'data' register is _not_ implemented.
482 */
483 pmgt->pp_data = 0;
484
485#undef REG
486}
487
b4c0a845
SZ
488static void
489pci_read_cap_expr(device_t pcib, int ptr, pcicfgregs *cfg)
490{
491#define REG(n, w) \
492 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
493
494 struct pcicfg_expr *expr = &cfg->expr;
495 uint16_t port_type;
496
497 expr->expr_ptr = ptr;
498 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
499
500 /*
501 * Only version 1 can be parsed currently
502 */
503 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
504 return;
505
506 /*
507 * Read slot capabilities
508 *
509 * Slot capabilities exists iff current port is root port or
510 * down stream port, and the slot is implemented.
511 *
512 * - Testing for root port or down stream port is meanningful
513 * iff PCI configure has type 1 header.
514 * - Slot implemented bit is meaningful iff current port is
515 * root port or down stream port.
516 */
517 if (cfg->hdrtype != 1)
518 return;
519
520 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
521 if (port_type != PCIEM_ROOT_PORT &&
522 port_type != PCIEM_DOWN_STREAM_PORT)
523 return;
524
525 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
526 return;
527
528 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
529
530#undef REG
531}
532
984263bc 533static void
e9d8f4df 534pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
984263bc 535{
8475d8bb
SZ
536#define REG(n, w) \
537 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
538
1361c4cd 539 int nextptr, ptrptr;
984263bc 540
0c78fe3f
SZ
541 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
542 /* No capabilities */
543 return;
544 }
545
984263bc
MD
546 switch (cfg->hdrtype) {
547 case 0:
81c29ce4
SZ
548 case 1:
549 ptrptr = PCIR_CAP_PTR;
984263bc
MD
550 break;
551 case 2:
81c29ce4 552 ptrptr = PCIR_CAP_PTR_2;
984263bc
MD
553 break;
554 default:
0c78fe3f 555 return; /* No capabilities support */
984263bc 556 }
0c78fe3f 557 nextptr = REG(ptrptr, 1);
984263bc
MD
558
559 /*
560 * Read capability entries.
561 */
1361c4cd
SZ
562 while (pci_fixup_nextptr(&nextptr)) {
563 int ptr = nextptr;
984263bc
MD
564
565 /* Process this entry */
566 switch (REG(ptr, 1)) {
81c29ce4 567 case PCIY_PMG: /* PCI power management */
8475d8bb 568 pci_read_cap_pmgt(pcib, ptr, cfg);
984263bc 569 break;
c7e4e7eb
SZ
570 case PCIY_PCIX: /* PCI-X */
571 cfg->pcixcap_ptr = ptr;
572 break;
b4c0a845
SZ
573 case PCIY_EXPRESS: /* PCI Express */
574 pci_read_cap_expr(pcib, ptr, cfg);
575 break;
984263bc
MD
576 default:
577 break;
578 }
1361c4cd
SZ
579
580 /* Find the next entry */
581 nextptr = REG(ptr + 1, 1);
984263bc 582 }
8475d8bb 583
984263bc
MD
584#undef REG
585}
586
984263bc
MD
587/* free pcicfgregs structure and all depending data structures */
588
22457186 589int
984263bc
MD
590pci_freecfg(struct pci_devinfo *dinfo)
591{
592 struct devlist *devlist_head;
593
594 devlist_head = &pci_devq;
595
596 if (dinfo->cfg.hdrspec != NULL)
efda3bd0 597 kfree(dinfo->cfg.hdrspec, M_DEVBUF);
984263bc
MD
598 /* XXX this hasn't been tested */
599 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
efda3bd0 600 kfree(dinfo, M_DEVBUF);
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601
602 /* increment the generation count */
603 pci_generation++;
604
605 /* we're losing one device */
606 pci_numdevs--;
607 return (0);
608}
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609
610
611/*
612 * PCI power manangement
613 */
e126caf1 614int
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615pci_set_powerstate_method(device_t dev, device_t child, int state)
616{
617 struct pci_devinfo *dinfo = device_get_ivars(child);
618 pcicfgregs *cfg = &dinfo->cfg;
1f7d9fe0 619 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
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620 u_int16_t status;
621 int result;
622
1f7d9fe0
SZ
623 if (pmgt->pp_cap != 0) {
624 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2) & ~PCIM_PSTAT_DMASK;
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625 result = 0;
626 switch (state) {
627 case PCI_POWERSTATE_D0:
628 status |= PCIM_PSTAT_D0;
629 break;
630 case PCI_POWERSTATE_D1:
1f7d9fe0 631 if (pmgt->pp_cap & PCIM_PCAP_D1SUPP) {
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632 status |= PCIM_PSTAT_D1;
633 } else {
634 result = EOPNOTSUPP;
635 }
636 break;
637 case PCI_POWERSTATE_D2:
1f7d9fe0 638 if (pmgt->pp_cap & PCIM_PCAP_D2SUPP) {
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639 status |= PCIM_PSTAT_D2;
640 } else {
641 result = EOPNOTSUPP;
642 }
643 break;
644 case PCI_POWERSTATE_D3:
645 status |= PCIM_PSTAT_D3;
646 break;
647 default:
648 result = EINVAL;
649 }
650 if (result == 0)
1f7d9fe0 651 PCI_WRITE_CONFIG(dev, child, pmgt->pp_status, status, 2);
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652 } else {
653 result = ENXIO;
654 }
655 return(result);
656}
657
e126caf1 658int
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659pci_get_powerstate_method(device_t dev, device_t child)
660{
661 struct pci_devinfo *dinfo = device_get_ivars(child);
662 pcicfgregs *cfg = &dinfo->cfg;
1f7d9fe0 663 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
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664 u_int16_t status;
665 int result;
666
1f7d9fe0
SZ
667 if (pmgt->pp_cap != 0) {
668 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2);
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669 switch (status & PCIM_PSTAT_DMASK) {
670 case PCIM_PSTAT_D0:
671 result = PCI_POWERSTATE_D0;
672 break;
673 case PCIM_PSTAT_D1:
674 result = PCI_POWERSTATE_D1;
675 break;
676 case PCIM_PSTAT_D2:
677 result = PCI_POWERSTATE_D2;
678 break;
679 case PCIM_PSTAT_D3:
680 result = PCI_POWERSTATE_D3;
681 break;
682 default:
683 result = PCI_POWERSTATE_UNKNOWN;
684 break;
685 }
686 } else {
687 /* No support, device is always at D0 */
688 result = PCI_POWERSTATE_D0;
689 }
690 return(result);
691}
692
693/*
694 * Some convenience functions for PCI device drivers.
695 */
696
697static __inline void
698pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
699{
700 u_int16_t command;
701
702 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
703 command |= bit;
704 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
705}
706
707static __inline void
708pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
709{
710 u_int16_t command;
711
712 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
713 command &= ~bit;
714 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
715}
716
e126caf1 717int
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718pci_enable_busmaster_method(device_t dev, device_t child)
719{
720 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 721 return(0);
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722}
723
e126caf1 724int
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725pci_disable_busmaster_method(device_t dev, device_t child)
726{
727 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
e126caf1 728 return(0);
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MD
729}
730
e126caf1 731int
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732pci_enable_io_method(device_t dev, device_t child, int space)
733{
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MD
734 uint16_t command;
735 uint16_t bit;
736 char *error;
737
738 bit = 0;
739 error = NULL;
740
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741 switch(space) {
742 case SYS_RES_IOPORT:
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MD
743 bit = PCIM_CMD_PORTEN;
744 error = "port";
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745 break;
746 case SYS_RES_MEMORY:
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747 bit = PCIM_CMD_MEMEN;
748 error = "memory";
984263bc 749 break;
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MD
750 default:
751 return(EINVAL);
984263bc 752 }
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MD
753 pci_set_command_bit(dev, child, bit);
754 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
755 if (command & bit)
756 return(0);
757 device_printf(child, "failed to enable %s mapping!\n", error);
758 return(ENXIO);
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759}
760
e126caf1 761int
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762pci_disable_io_method(device_t dev, device_t child, int space)
763{
e126caf1
MD
764 uint16_t command;
765 uint16_t bit;
766 char *error;
767
768 bit = 0;
769 error = NULL;
770
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771 switch(space) {
772 case SYS_RES_IOPORT:
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MD
773 bit = PCIM_CMD_PORTEN;
774 error = "port";
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775 break;
776 case SYS_RES_MEMORY:
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777 bit = PCIM_CMD_MEMEN;
778 error = "memory";
984263bc 779 break;
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MD
780 default:
781 return (EINVAL);
984263bc 782 }
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MD
783 pci_clear_command_bit(dev, child, bit);
784 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
785 if (command & bit) {
786 device_printf(child, "failed to disable %s mapping!\n", error);
787 return (ENXIO);
788 }
789 return (0);
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790}
791
792/*
793 * This is the user interface to PCI configuration space.
794 */
795
796static int
fef8985e 797pci_open(struct dev_open_args *ap)
984263bc 798{
fef8985e 799 if ((ap->a_oflags & FWRITE) && securelevel > 0) {
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800 return EPERM;
801 }
802 return 0;
803}
804
805static int
fef8985e 806pci_close(struct dev_close_args *ap)
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807{
808 return 0;
809}
810
811/*
812 * Match a single pci_conf structure against an array of pci_match_conf
813 * structures. The first argument, 'matches', is an array of num_matches
814 * pci_match_conf structures. match_buf is a pointer to the pci_conf
815 * structure that will be compared to every entry in the matches array.
816 * This function returns 1 on failure, 0 on success.
817 */
818static int
819pci_conf_match(struct pci_match_conf *matches, int num_matches,
820 struct pci_conf *match_buf)
821{
822 int i;
823
824 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
825 return(1);
826
827 for (i = 0; i < num_matches; i++) {
828 /*
829 * I'm not sure why someone would do this...but...
830 */
831 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
832 continue;
833
834 /*
835 * Look at each of the match flags. If it's set, do the
836 * comparison. If the comparison fails, we don't have a
837 * match, go on to the next item if there is one.
838 */
839 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
840 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
841 continue;
842
843 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
844 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
845 continue;
846
847 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
848 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
849 continue;
850
851 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
852 && (match_buf->pc_vendor != matches[i].pc_vendor))
853 continue;
854
855 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
856 && (match_buf->pc_device != matches[i].pc_device))
857 continue;
858
859 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
860 && (match_buf->pc_class != matches[i].pc_class))
861 continue;
862
863 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
864 && (match_buf->pd_unit != matches[i].pd_unit))
865 continue;
866
867 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
868 && (strncmp(matches[i].pd_name, match_buf->pd_name,
869 sizeof(match_buf->pd_name)) != 0))
870 continue;
871
872 return(0);
873 }
874
875 return(1);
876}
877
878/*
879 * Locate the parent of a PCI device by scanning the PCI devlist
880 * and return the entry for the parent.
881 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
882 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
883 */
884
885pcicfgregs *
886pci_devlist_get_parent(pcicfgregs *cfg)
887{
888 struct devlist *devlist_head;
889 struct pci_devinfo *dinfo;
890 pcicfgregs *bridge_cfg;
891 int i;
892
893 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
894
895 /* If the device is on PCI bus 0, look for the host */
896 if (cfg->bus == 0) {
897 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
898 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
899 bridge_cfg = &dinfo->cfg;
900 if (bridge_cfg->baseclass == PCIC_BRIDGE
901 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
902 && bridge_cfg->bus == cfg->bus) {
903 return bridge_cfg;
904 }
905 }
906 }
907
908 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
909 if (cfg->bus > 0) {
910 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
911 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
912 bridge_cfg = &dinfo->cfg;
913 if (bridge_cfg->baseclass == PCIC_BRIDGE
914 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
915 && bridge_cfg->secondarybus == cfg->bus) {
916 return bridge_cfg;
917 }
918 }
919 }
920
921 return NULL;
922}
923
924static int
fef8985e 925pci_ioctl(struct dev_ioctl_args *ap)
984263bc 926{
4a5a2d63 927 device_t pci, pcib;
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MD
928 struct pci_io *io;
929 const char *name;
930 int error;
931
fef8985e 932 if (!(ap->a_fflag & FWRITE))
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MD
933 return EPERM;
934
fef8985e 935 switch(ap->a_cmd) {
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MD
936 case PCIOCGETCONF:
937 {
938 struct pci_devinfo *dinfo;
939 struct pci_conf_io *cio;
940 struct devlist *devlist_head;
941 struct pci_match_conf *pattern_buf;
942 int num_patterns;
943 size_t iolen;
944 int ionum, i;
945
fef8985e 946 cio = (struct pci_conf_io *)ap->a_data;
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947
948 num_patterns = 0;
949 dinfo = NULL;
950
951 /*
952 * Hopefully the user won't pass in a null pointer, but it
953 * can't hurt to check.
954 */
955 if (cio == NULL) {
956 error = EINVAL;
957 break;
958 }
959
960 /*
961 * If the user specified an offset into the device list,
962 * but the list has changed since they last called this
963 * ioctl, tell them that the list has changed. They will
964 * have to get the list from the beginning.
965 */
966 if ((cio->offset != 0)
967 && (cio->generation != pci_generation)){
968 cio->num_matches = 0;
969 cio->status = PCI_GETCONF_LIST_CHANGED;
970 error = 0;
971 break;
972 }
973
974 /*
975 * Check to see whether the user has asked for an offset
976 * past the end of our list.
977 */
978 if (cio->offset >= pci_numdevs) {
979 cio->num_matches = 0;
980 cio->status = PCI_GETCONF_LAST_DEVICE;
981 error = 0;
982 break;
983 }
984
985 /* get the head of the device queue */
986 devlist_head = &pci_devq;
987
988 /*
989 * Determine how much room we have for pci_conf structures.
990 * Round the user's buffer size down to the nearest
991 * multiple of sizeof(struct pci_conf) in case the user
992 * didn't specify a multiple of that size.
993 */
994 iolen = min(cio->match_buf_len -
995 (cio->match_buf_len % sizeof(struct pci_conf)),
996 pci_numdevs * sizeof(struct pci_conf));
997
998 /*
999 * Since we know that iolen is a multiple of the size of
1000 * the pciconf union, it's okay to do this.
1001 */
1002 ionum = iolen / sizeof(struct pci_conf);
1003
1004 /*
1005 * If this test is true, the user wants the pci_conf
1006 * structures returned to match the supplied entries.
1007 */
1008 if ((cio->num_patterns > 0)
1009 && (cio->pat_buf_len > 0)) {
1010 /*
1011 * pat_buf_len needs to be:
1012 * num_patterns * sizeof(struct pci_match_conf)
1013 * While it is certainly possible the user just
1014 * allocated a large buffer, but set the number of
1015 * matches correctly, it is far more likely that
1016 * their kernel doesn't match the userland utility
1017 * they're using. It's also possible that the user
1018 * forgot to initialize some variables. Yes, this
1019 * may be overly picky, but I hazard to guess that
1020 * it's far more likely to just catch folks that
1021 * updated their kernel but not their userland.
1022 */
1023 if ((cio->num_patterns *
1024 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
1025 /* The user made a mistake, return an error*/
1026 cio->status = PCI_GETCONF_ERROR;
85f8e2ea 1027 kprintf("pci_ioctl: pat_buf_len %d != "
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MD
1028 "num_patterns (%d) * sizeof(struct "
1029 "pci_match_conf) (%d)\npci_ioctl: "
1030 "pat_buf_len should be = %d\n",
1031 cio->pat_buf_len, cio->num_patterns,
1032 (int)sizeof(struct pci_match_conf),
1033 (int)sizeof(struct pci_match_conf) *
1034 cio->num_patterns);
85f8e2ea 1035 kprintf("pci_ioctl: do your headers match your "
984263bc
MD
1036 "kernel?\n");
1037 cio->num_matches = 0;
1038 error = EINVAL;
1039 break;
1040 }
1041
1042 /*
1043 * Check the user's buffer to make sure it's readable.
1044 */
1045 if (!useracc((caddr_t)cio->patterns,
1046 cio->pat_buf_len, VM_PROT_READ)) {
85f8e2ea 1047 kprintf("pci_ioctl: pattern buffer %p, "
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MD
1048 "length %u isn't user accessible for"
1049 " READ\n", cio->patterns,
1050 cio->pat_buf_len);
1051 error = EACCES;
1052 break;
1053 }
1054 /*
1055 * Allocate a buffer to hold the patterns.
1056 */
efda3bd0 1057 pattern_buf = kmalloc(cio->pat_buf_len, M_TEMP,
984263bc
MD
1058 M_WAITOK);
1059 error = copyin(cio->patterns, pattern_buf,
1060 cio->pat_buf_len);
1061 if (error != 0)
1062 break;
1063 num_patterns = cio->num_patterns;
1064
1065 } else if ((cio->num_patterns > 0)
1066 || (cio->pat_buf_len > 0)) {
1067 /*
1068 * The user made a mistake, spit out an error.
1069 */
1070 cio->status = PCI_GETCONF_ERROR;
1071 cio->num_matches = 0;
85f8e2ea 1072 kprintf("pci_ioctl: invalid GETCONF arguments\n");
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MD
1073 error = EINVAL;
1074 break;
1075 } else
1076 pattern_buf = NULL;
1077
1078 /*
1079 * Make sure we can write to the match buffer.
1080 */
1081 if (!useracc((caddr_t)cio->matches,
1082 cio->match_buf_len, VM_PROT_WRITE)) {
85f8e2ea 1083 kprintf("pci_ioctl: match buffer %p, length %u "
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MD
1084 "isn't user accessible for WRITE\n",
1085 cio->matches, cio->match_buf_len);
1086 error = EACCES;
1087 break;
1088 }
1089
1090 /*
1091 * Go through the list of devices and copy out the devices
1092 * that match the user's criteria.
1093 */
1094 for (cio->num_matches = 0, error = 0, i = 0,
1095 dinfo = STAILQ_FIRST(devlist_head);
1096 (dinfo != NULL) && (cio->num_matches < ionum)
1097 && (error == 0) && (i < pci_numdevs);
1098 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
1099
1100 if (i < cio->offset)
1101 continue;
1102
1103 /* Populate pd_name and pd_unit */
1104 name = NULL;
1105 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
1106 name = device_get_name(dinfo->cfg.dev);
1107 if (name) {
1108 strncpy(dinfo->conf.pd_name, name,
1109 sizeof(dinfo->conf.pd_name));
1110 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
1111 dinfo->conf.pd_unit =
1112 device_get_unit(dinfo->cfg.dev);
1113 }
1114
1115 if ((pattern_buf == NULL) ||
1116 (pci_conf_match(pattern_buf, num_patterns,
1117 &dinfo->conf) == 0)) {
1118
1119 /*
1120 * If we've filled up the user's buffer,
1121 * break out at this point. Since we've
1122 * got a match here, we'll pick right back
1123 * up at the matching entry. We can also
1124 * tell the user that there are more matches
1125 * left.
1126 */
1127 if (cio->num_matches >= ionum)
1128 break;
1129
1130 error = copyout(&dinfo->conf,
1131 &cio->matches[cio->num_matches],
1132 sizeof(struct pci_conf));
1133 cio->num_matches++;
1134 }
1135 }
1136
1137 /*
1138 * Set the pointer into the list, so if the user is getting
1139 * n records at a time, where n < pci_numdevs,
1140 */
1141 cio->offset = i;
1142
1143 /*
1144 * Set the generation, the user will need this if they make
1145 * another ioctl call with offset != 0.
1146 */
1147 cio->generation = pci_generation;
1148
1149 /*
1150 * If this is the last device, inform the user so he won't
1151 * bother asking for more devices. If dinfo isn't NULL, we
1152 * know that there are more matches in the list because of
1153 * the way the traversal is done.
1154 */
1155 if (dinfo == NULL)
1156 cio->status = PCI_GETCONF_LAST_DEVICE;
1157 else
1158 cio->status = PCI_GETCONF_MORE_DEVS;
1159
1160 if (pattern_buf != NULL)
efda3bd0 1161 kfree(pattern_buf, M_TEMP);
984263bc
MD
1162
1163 break;
1164 }
1165 case PCIOCREAD:
fef8985e 1166 io = (struct pci_io *)ap->a_data;
984263bc 1167 switch(io->pi_width) {
984263bc
MD
1168 case 4:
1169 case 2:
1170 case 1:
4a5a2d63
JS
1171 /*
1172 * Assume that the user-level bus number is
1173 * actually the pciN instance number. We map
1174 * from that to the real pcib+bus combination.
1175 */
1176 pci = devclass_get_device(pci_devclass,
1177 io->pi_sel.pc_bus);
1178 if (pci) {
2581072f
MD
1179 /*
1180 * pci is the pci device and may contain
1181 * several children (for each function code).
1182 * The governing pci bus is the parent to
1183 * the pci device.
1184 */
1185 int b;
1186
4a5a2d63 1187 pcib = device_get_parent(pci);
2581072f 1188 b = pcib_get_bus(pcib);
4a5a2d63
JS
1189 io->pi_data =
1190 PCIB_READ_CONFIG(pcib,
1191 b,
1192 io->pi_sel.pc_dev,
1193 io->pi_sel.pc_func,
1194 io->pi_reg,
1195 io->pi_width);
1196 error = 0;
1197 } else {
1198 error = ENODEV;
1199 }
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MD
1200 break;
1201 default:
1202 error = ENODEV;
1203 break;
1204 }
1205 break;
1206
1207 case PCIOCWRITE:
fef8985e 1208 io = (struct pci_io *)ap->a_data;
984263bc 1209 switch(io->pi_width) {
984263bc
MD
1210 case 4:
1211 case 2:
1212 case 1:
4a5a2d63
JS
1213 /*
1214 * Assume that the user-level bus number is
1215 * actually the pciN instance number. We map
1216 * from that to the real pcib+bus combination.
1217 */
1218 pci = devclass_get_device(pci_devclass,
1219 io->pi_sel.pc_bus);
1220 if (pci) {
2581072f
MD
1221 /*
1222 * pci is the pci device and may contain
1223 * several children (for each function code).
1224 * The governing pci bus is the parent to
1225 * the pci device.
1226 */
1227 int b;
1228
4a5a2d63 1229 pcib = device_get_parent(pci);
2581072f 1230 b = pcib_get_bus(pcib);
4a5a2d63
JS
1231 PCIB_WRITE_CONFIG(pcib,
1232 b,
1233 io->pi_sel.pc_dev,
1234 io->pi_sel.pc_func,
1235 io->pi_reg,
1236 io->pi_data,
1237 io->pi_width);
1238 error = 0;
1239 } else {
1240 error = ENODEV;
1241 }
984263bc
MD
1242 break;
1243 default:
1244 error = ENODEV;
1245 break;
1246 }
1247 break;
1248
1249 default:
1250 error = ENOTTY;
1251 break;
1252 }
1253
1254 return (error);
1255}
1256
1257#define PCI_CDEV 78
1258
fef8985e
MD
1259static struct dev_ops pcic_ops = {
1260 { "pci", PCI_CDEV, 0 },
1261 .d_open = pci_open,
1262 .d_close = pci_close,
1263 .d_ioctl = pci_ioctl,
984263bc
MD
1264};
1265
1266#include "pci_if.h"
1267
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MD
1268/*
1269 * New style pci driver. Parent device is either a pci-host-bridge or a
1270 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1271 */
ed1bd994
MD
1272const char *
1273pci_class_to_string(int baseclass)
1274{
1275 const char *name;
1276
1277 switch(baseclass) {
1278 case PCIC_OLD:
1279 name = "OLD";
1280 break;
1281 case PCIC_STORAGE:
1282 name = "STORAGE";
1283 break;
1284 case PCIC_NETWORK:
1285 name = "NETWORK";
1286 break;
1287 case PCIC_DISPLAY:
1288 name = "DISPLAY";
1289 break;
1290 case PCIC_MULTIMEDIA:
1291 name = "MULTIMEDIA";
1292 break;
1293 case PCIC_MEMORY:
1294 name = "MEMORY";
1295 break;
1296 case PCIC_BRIDGE:
1297 name = "BRIDGE";
1298 break;
1299 case PCIC_SIMPLECOMM:
1300 name = "SIMPLECOMM";
1301 break;
1302 case PCIC_BASEPERIPH:
1303 name = "BASEPERIPH";
1304 break;
1305 case PCIC_INPUTDEV:
1306 name = "INPUTDEV";
1307 break;
1308 case PCIC_DOCKING:
1309 name = "DOCKING";
1310 break;
1311 case PCIC_PROCESSOR:
1312 name = "PROCESSOR";
1313 break;
1314 case PCIC_SERIALBUS:
1315 name = "SERIALBUS";
1316 break;
1317 case PCIC_WIRELESS:
1318 name = "WIRELESS";
1319 break;
1320 case PCIC_I2O:
1321 name = "I20";
1322 break;
1323 case PCIC_SATELLITE:
1324 name = "SATELLITE";
1325 break;
1326 case PCIC_CRYPTO:
1327 name = "CRYPTO";
1328 break;
1329 case PCIC_SIGPROC:
1330 name = "SIGPROC";
1331 break;
1332 case PCIC_OTHER:
1333 name = "OTHER";
1334 break;
1335 default:
1336 name = "?";
1337 break;
1338 }
1339 return(name);
1340}
984263bc 1341
b4c0a845
SZ
1342static void
1343pci_print_verbose_expr(const pcicfgregs *cfg)
1344{
1345 const struct pcicfg_expr *expr = &cfg->expr;
1346 const char *port_name;
1347 uint16_t port_type;
1348
1349 if (!bootverbose)
1350 return;
1351
1352 if (expr->expr_ptr == 0) /* No PCI Express capability */
1353 return;
1354
1355 kprintf("\tPCI Express ver.%d cap=0x%04x",
1356 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
1357 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
1358 goto back;
1359
1360 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
1361
1362 switch (port_type) {
1363 case PCIEM_END_POINT:
1364 port_name = "DEVICE";
1365 break;
1366 case PCIEM_LEG_END_POINT:
1367 port_name = "LEGDEV";
1368 break;
1369 case PCIEM_ROOT_PORT:
1370 port_name = "ROOT";
1371 break;
1372 case PCIEM_UP_STREAM_PORT:
1373 port_name = "UPSTREAM";
1374 break;
1375 case PCIEM_DOWN_STREAM_PORT:
1376 port_name = "DOWNSTRM";
1377 break;
1378 case PCIEM_PCIE2PCI_BRIDGE:
1379 port_name = "PCIE2PCI";
1380 break;
1381 case PCIEM_PCI2PCIE_BRIDGE:
1382 port_name = "PCI2PCIE";
1383 break;
1384 default:
1385 port_name = NULL;
1386 break;
1387 }
1388 if ((port_type == PCIEM_ROOT_PORT ||
1389 port_type == PCIEM_DOWN_STREAM_PORT) &&
1390 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
1391 port_name = NULL;
1392 if (port_name != NULL)
1393 kprintf("[%s]", port_name);
1394
1395 if ((port_type == PCIEM_ROOT_PORT ||
1396 port_type == PCIEM_DOWN_STREAM_PORT) &&
1397 (expr->expr_cap & PCIEM_CAP_SLOT_IMPL)) {
1398 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
1399 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
1400 kprintf("[HOTPLUG]");
1401 }
1402back:
1403 kprintf("\n");
1404}
1405
22457186 1406void
984263bc
MD
1407pci_print_verbose(struct pci_devinfo *dinfo)
1408{
1409 if (bootverbose) {
1410 pcicfgregs *cfg = &dinfo->cfg;
1411
85f8e2ea 1412 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
984263bc 1413 cfg->vendor, cfg->device, cfg->revid);
85f8e2ea 1414 kprintf("\tbus=%d, slot=%d, func=%d\n",
4a5a2d63 1415 cfg->bus, cfg->slot, cfg->func);
85f8e2ea 1416 kprintf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
ed1bd994 1417 pci_class_to_string(cfg->baseclass),
984263bc
MD
1418 cfg->baseclass, cfg->subclass, cfg->progif,
1419 cfg->hdrtype, cfg->mfdev);
85f8e2ea 1420 kprintf("\tsubordinatebus=%x \tsecondarybus=%x\n",
984263bc
MD
1421 cfg->subordinatebus, cfg->secondarybus);
1422#ifdef PCI_DEBUG
85f8e2ea 1423 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
984263bc 1424 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
85f8e2ea 1425 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
984263bc
MD
1426 cfg->lattimer, cfg->lattimer * 30,
1427 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1428#endif /* PCI_DEBUG */
1429 if (cfg->intpin > 0)
85f8e2ea 1430 kprintf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
b4c0a845
SZ
1431
1432 pci_print_verbose_expr(cfg);
984263bc
MD
1433 }
1434}
1435
1436static int
4a5a2d63 1437pci_porten(device_t pcib, int b, int s, int f)
984263bc 1438{
4a5a2d63
JS
1439 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1440 & PCIM_CMD_PORTEN) != 0;
984263bc
MD
1441}
1442
1443static int
4a5a2d63 1444pci_memen(device_t pcib, int b, int s, int f)
984263bc 1445{
4a5a2d63
JS
1446 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1447 & PCIM_CMD_MEMEN) != 0;
984263bc
MD
1448}
1449
1450/*
1451 * Add a resource based on a pci map register. Return 1 if the map
1452 * register is a 32bit map register or 2 if it is a 64bit register.
1453 */
1454static int
4a5a2d63
JS
1455pci_add_map(device_t pcib, int b, int s, int f, int reg,
1456 struct resource_list *rl)
984263bc 1457{
984263bc
MD
1458 u_int32_t map;
1459 u_int64_t base;
1460 u_int8_t ln2size;
1461 u_int8_t ln2range;
1462 u_int32_t testval;
4a5a2d63
JS
1463
1464
1465#ifdef PCI_ENABLE_IO_MODES
1466 u_int16_t cmd;
1467#endif
984263bc
MD
1468 int type;
1469
4a5a2d63 1470 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
984263bc
MD
1471
1472 if (map == 0 || map == 0xffffffff)
1473 return 1; /* skip invalid entry */
1474
4a5a2d63
JS
1475 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1476 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1477 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
984263bc
MD
1478
1479 base = pci_mapbase(map);
1480 if (pci_maptype(map) & PCI_MAPMEM)
1481 type = SYS_RES_MEMORY;
1482 else
1483 type = SYS_RES_IOPORT;
1484 ln2size = pci_mapsize(testval);
1485 ln2range = pci_maprange(testval);
1486 if (ln2range == 64) {
1487 /* Read the other half of a 64bit map register */
4a5a2d63 1488 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
984263bc
MD
1489 }
1490
984263bc
MD
1491 /*
1492 * This code theoretically does the right thing, but has
1493 * undesirable side effects in some cases where
1494 * peripherals respond oddly to having these bits
1495 * enabled. Leave them alone by default.
1496 */
1497#ifdef PCI_ENABLE_IO_MODES
4a5a2d63
JS
1498 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1499 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1500 cmd |= PCIM_CMD_PORTEN;
1501 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc 1502 }
4a5a2d63
JS
1503 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1504 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1505 cmd |= PCIM_CMD_MEMEN;
1506 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
984263bc
MD
1507 }
1508#else
4a5a2d63 1509 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
984263bc 1510 return 1;
4a5a2d63 1511 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
984263bc
MD
1512 return 1;
1513#endif
1514
1515 resource_list_add(rl, type, reg,
1516 base, base + (1 << ln2size) - 1,
1517 (1 << ln2size));
1518
1519 if (bootverbose) {
85f8e2ea 1520 kprintf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
984263bc
MD
1521 reg, pci_maptype(base), ln2range,
1522 (unsigned int) base, ln2size);
1523 }
1524
1525 return (ln2range == 64) ? 2 : 1;
1526}
1527
201eb0a7
TS
1528#ifdef PCI_MAP_FIXUP
1529/*
1530 * For ATA devices we need to decide early on what addressing mode to use.
1531 * Legacy demands that the primary and secondary ATA ports sits on the
1532 * same addresses that old ISA hardware did. This dictates that we use
1533 * those addresses and ignore the BARs if we cannot set PCI native
1534 * addressing mode.
1535 */
1536static void
1537pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, int s, int f,
1538 struct resource_list *rl)
1539{
1540 int rid, type, progif;
1541#if 0
1542 /* if this device supports PCI native addressing use it */
1543 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1544 if ((progif &0x8a) == 0x8a) {
1545 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
1546 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
85f8e2ea 1547 kprintf("Trying ATA native PCI addressing mode\n");
201eb0a7
TS
1548 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
1549 }
1550 }
1551#endif
1552 /*
1553 * Because we return any preallocated resources for lazy
1554 * allocation for PCI devices in pci_alloc_resource(), we can
1555 * allocate our legacy resources here.
1556 */
1557 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1558 type = SYS_RES_IOPORT;
1559 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
1560 pci_add_map(pcib, b, s, f, PCIR_BAR(0), rl);
1561 pci_add_map(pcib, b, s, f, PCIR_BAR(1), rl);
1562 } else {
1563 rid = PCIR_BAR(0);
1564 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
1565 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
1566 0);
1567 rid = PCIR_BAR(1);
1568 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
1569 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
1570 0);
1571 }
1572 if (progif & PCIP_STORAGE_IDE_MODESEC) {
1573 pci_add_map(pcib, b, s, f, PCIR_BAR(2), rl);
1574 pci_add_map(pcib, b, s, f, PCIR_BAR(3), rl);
1575 } else {
1576 rid = PCIR_BAR(2);
1577 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
1578 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
1579 0);
1580 rid = PCIR_BAR(3);
1581 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
1582 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
1583 0);
1584 }
1585 pci_add_map(pcib, b, s, f, PCIR_BAR(4), rl);
1586 pci_add_map(pcib, b, s, f, PCIR_BAR(5), rl);
1587}
1588#endif /* PCI_MAP_FIXUP */
1589
984263bc 1590static void
e126caf1 1591pci_add_resources(device_t pcib, device_t bus, device_t dev)
984263bc
MD
1592{
1593 struct pci_devinfo *dinfo = device_get_ivars(dev);
4a5a2d63 1594 pcicfgregs *cfg = &dinfo->cfg;
984263bc
MD
1595 struct resource_list *rl = &dinfo->resources;
1596 struct pci_quirk *q;
e126caf1
MD
1597 int b, i, f, s;
1598#if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */
1599 int irq;
1600#endif
984263bc 1601
e126caf1
MD
1602 b = cfg->bus;
1603 s = cfg->slot;
1604 f = cfg->func;
201eb0a7
TS
1605#ifdef PCI_MAP_FIXUP
1606 /* atapci devices in legacy mode need special map treatment */
1607 if ((pci_get_class(dev) == PCIC_STORAGE) &&
1608 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
d3d1ea7a
MD
1609 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
1610 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
1611 !pci_read_config(dev, PCIR_BAR(2), 4))) )
201eb0a7
TS
1612 pci_ata_maps(pcib, bus, dev, b, s, f, rl);
1613 else
1614#endif /* PCI_MAP_FIXUP */
1615 for (i = 0; i < cfg->nummaps;) {
1616 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl);
1617 }
984263bc
MD
1618
1619 for (q = &pci_quirks[0]; q->devid; q++) {
1620 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1621 && q->type == PCI_QUIRK_MAP_REG)
4a5a2d63 1622 pci_add_map(pcib, b, s, f, q->arg1, rl);
984263bc
MD
1623 }
1624
1625 if (cfg->intpin > 0 && cfg->intline != 255)
1626 resource_list_add(rl, SYS_RES_IRQ, 0,
1627 cfg->intline, cfg->intline, 1);
1628}
1629
e126caf1
MD
1630void
1631pci_add_children(device_t dev, int busno, size_t dinfo_size)
984263bc 1632{
e126caf1 1633#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
4a5a2d63 1634 device_t pcib = device_get_parent(dev);
e126caf1 1635 struct pci_devinfo *dinfo;
4a5a2d63 1636 int maxslots;
e126caf1
MD
1637 int s, f, pcifunchigh;
1638 uint8_t hdrtype;
1639
1640 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo));
984263bc 1641
4a5a2d63 1642 maxslots = PCIB_MAXSLOTS(pcib);
984263bc 1643
57e943f7 1644 for (s = 0; s <= maxslots; s++) {
e126caf1
MD
1645 pcifunchigh = 0;
1646 f = 0;
1647 hdrtype = REG(PCIR_HDRTYPE, 1);
1648 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1649 continue;
1650 if (hdrtype & PCIM_MFDEV)
1651 pcifunchigh = PCI_FUNCMAX;
5e658043 1652 for (f = 0; f <= pcifunchigh; f++) {
e126caf1 1653 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
984263bc 1654 if (dinfo != NULL) {
e126caf1 1655 pci_add_child(dev, dinfo);
984263bc
MD
1656 }
1657 }
1658 }
e126caf1
MD
1659#undef REG
1660}
1661
2581072f
MD
1662/*
1663 * The actual PCI child that we add has a NULL driver whos parent
1664 * device will be "pci". The child contains the ivars, not the parent.
1665 */
e126caf1
MD
1666void
1667pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1668{
1669 device_t pcib;
1670
1671 pcib = device_get_parent(bus);
1672 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1673 device_set_ivars(dinfo->cfg.dev, dinfo);
1674 pci_add_resources(pcib, bus, dinfo->cfg.dev);
1675 pci_print_verbose(dinfo);
984263bc
MD
1676}
1677
c01b8d84
MD
1678/*
1679 * Probe the PCI bus. Note: probe code is not supposed to add children
1680 * or call attach.
1681 */
984263bc 1682static int
4a5a2d63 1683pci_probe(device_t dev)
984263bc 1684{
984263bc 1685 device_set_desc(dev, "PCI bus");
4a5a2d63 1686
c01b8d84
MD
1687 /* Allow other subclasses to override this driver */
1688 return(-1000);
984263bc
MD
1689}
1690
e126caf1
MD
1691static int
1692pci_attach(device_t dev)
1693{
1694 int busno;
e4c9c0c8
MD
1695 int lunit = device_get_unit(dev);
1696
fef8985e
MD
1697 dev_ops_add(&pcic_ops, -1, lunit);
1698 make_dev(&pcic_ops, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit);
e126caf1
MD
1699
1700 /*
1701 * Since there can be multiple independantly numbered PCI
1702 * busses on some large alpha systems, we can't use the unit
1703 * number to decide what bus we are probing. We ask the parent
1704 * pcib what our bus number is.
2581072f
MD
1705 *
1706 * pcib_get_bus() must act on the pci bus device, not on the pci
1707 * device, because it uses badly hacked nexus-based ivars to
1708 * store and retrieve the physical bus number. XXX
e126caf1 1709 */
2581072f 1710 busno = pcib_get_bus(device_get_parent(dev));
e126caf1 1711 if (bootverbose)
ed1bd994 1712 device_printf(dev, "pci_attach() physical bus=%d\n", busno);
e126caf1
MD
1713
1714 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1715
1716 return (bus_generic_attach(dev));
1717}
1718
984263bc
MD
1719static int
1720pci_print_resources(struct resource_list *rl, const char *name, int type,
1721 const char *format)
1722{
1723 struct resource_list_entry *rle;
1724 int printed, retval;
1725
1726 printed = 0;
1727 retval = 0;
1728 /* Yes, this is kinda cheating */
1729 SLIST_FOREACH(rle, rl, link) {
1730 if (rle->type == type) {
1731 if (printed == 0)
85f8e2ea 1732 retval += kprintf(" %s ", name);
984263bc 1733 else if (printed > 0)
85f8e2ea 1734 retval += kprintf(",");
984263bc 1735 printed++;
85f8e2ea 1736 retval += kprintf(format, rle->start);
984263bc 1737 if (rle->count > 1) {
85f8e2ea
SW
1738 retval += kprintf("-");
1739 retval += kprintf(format, rle->start +
984263bc
MD
1740 rle->count - 1);
1741 }
1742 }
1743 }
1744 return retval;
1745}
1746
e126caf1 1747int
984263bc
MD
1748pci_print_child(device_t dev, device_t child)
1749{
1750 struct pci_devinfo *dinfo;
1751 struct resource_list *rl;
1752 pcicfgregs *cfg;
1753 int retval = 0;
1754
1755 dinfo = device_get_ivars(child);
1756 cfg = &dinfo->cfg;
1757 rl = &dinfo->resources;
1758
1759 retval += bus_print_child_header(dev, child);
1760
1761 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1762 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1763 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1764 if (device_get_flags(dev))
85f8e2ea 1765 retval += kprintf(" flags %#x", device_get_flags(dev));
984263bc 1766
85f8e2ea 1767 retval += kprintf(" at device %d.%d", pci_get_slot(child),
984263bc
MD
1768 pci_get_function(child));
1769
1770 retval += bus_print_child_footer(dev, child);
1771
1772 return (retval);
1773}
1774
e126caf1 1775void
984263bc
MD
1776pci_probe_nomatch(device_t dev, device_t child)
1777{
1778 struct pci_devinfo *dinfo;
1779 pcicfgregs *cfg;
1780 const char *desc;
1781 int unknown;
1782
1783 unknown = 0;
1784 dinfo = device_get_ivars(child);
1785 cfg = &dinfo->cfg;
1786 desc = pci_ata_match(child);
1787 if (!desc) desc = pci_usb_match(child);
1788 if (!desc) desc = pci_vga_match(child);
27c23c6b 1789 if (!desc) desc = pci_chip_match(child);
984263bc
MD
1790 if (!desc) {
1791 desc = "unknown card";
1792 unknown++;
1793 }
1794 device_printf(dev, "<%s>", desc);
1795 if (bootverbose || unknown) {
85f8e2ea 1796 kprintf(" (vendor=0x%04x, dev=0x%04x)",
984263bc
MD
1797 cfg->vendor,
1798 cfg->device);
1799 }
85f8e2ea 1800 kprintf(" at %d.%d",
984263bc
MD
1801 pci_get_slot(child),
1802 pci_get_function(child));
1803 if (cfg->intpin > 0 && cfg->intline != 255) {
85f8e2ea 1804 kprintf(" irq %d", cfg->intline);
984263bc 1805 }
85f8e2ea 1806 kprintf("\n");
984263bc
MD
1807
1808 return;
1809}
1810
22457186 1811int
4a5a2d63 1812pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
984263bc
MD
1813{
1814 struct pci_devinfo *dinfo;
1815 pcicfgregs *cfg;
1816
1817 dinfo = device_get_ivars(child);
1818 cfg = &dinfo->cfg;
1819
1820 switch (which) {
1821 case PCI_IVAR_SUBVENDOR:
1822 *result = cfg->subvendor;
1823 break;
1824 case PCI_IVAR_SUBDEVICE:
1825 *result = cfg->subdevice;
1826 break;
1827 case PCI_IVAR_VENDOR:
1828 *result = cfg->vendor;
1829 break;
1830 case PCI_IVAR_DEVICE:
1831 *result = cfg->device;
1832 break;
1833 case PCI_IVAR_DEVID:
1834 *result = (cfg->device << 16) | cfg->vendor;
1835 break;
1836 case PCI_IVAR_CLASS:
1837 *result = cfg->baseclass;
1838 break;
1839 case PCI_IVAR_SUBCLASS:
1840 *result = cfg->subclass;
1841 break;
1842 case PCI_IVAR_PROGIF:
1843 *result = cfg->progif;
1844 break;
1845 case PCI_IVAR_REVID:
1846 *result = cfg->revid;
1847 break;
1848 case PCI_IVAR_INTPIN:
1849 *result = cfg->intpin;
1850 break;
1851 case PCI_IVAR_IRQ:
1852 *result = cfg->intline;
1853 break;
1854 case PCI_IVAR_BUS:
1855 *result = cfg->bus;
1856 break;
1857 case PCI_IVAR_SLOT:
1858 *result = cfg->slot;
1859 break;
1860 case PCI_IVAR_FUNCTION:
1861 *result = cfg->func;
1862 break;
1863 case PCI_IVAR_SECONDARYBUS:
1864 *result = cfg->secondarybus;
1865 break;
1866 case PCI_IVAR_SUBORDINATEBUS:
1867 *result = cfg->subordinatebus;
1868 break;
f72d3d23
JS
1869 case PCI_IVAR_ETHADDR:
1870 /*
1871 * The generic accessor doesn't deal with failure, so
1872 * we set the return value, then return an error.
1873 */
1874 *result = NULL;
1875 return (EINVAL);
c7e4e7eb
SZ
1876 case PCI_IVAR_PCIXCAP_PTR:
1877 *result = cfg->pcixcap_ptr;
1878 break;
1879 case PCI_IVAR_PCIECAP_PTR:
1880 *result = cfg->expr.expr_ptr;
1881 break;
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MD
1882 default:
1883 return ENOENT;
1884 }
1885 return 0;
1886}
1887
22457186 1888int
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MD
1889pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1890{
1891 struct pci_devinfo *dinfo;
1892 pcicfgregs *cfg;
1893
1894 dinfo = device_get_ivars(child);
1895 cfg = &dinfo->cfg;
1896
1897 switch (which) {
1898 case PCI_IVAR_SUBVENDOR:
1899 case PCI_IVAR_SUBDEVICE:
1900 case PCI_IVAR_VENDOR:
1901 case PCI_IVAR_DEVICE:
1902 case PCI_IVAR_DEVID:
1903 case PCI_IVAR_CLASS:
1904 case PCI_IVAR_SUBCLASS:
1905 case PCI_IVAR_PROGIF:
1906 case PCI_IVAR_REVID:
1907 case PCI_IVAR_INTPIN:
1908 case PCI_IVAR_IRQ:
1909 case PCI_IVAR_BUS:
1910 case PCI_IVAR_SLOT:
1911 case PCI_IVAR_FUNCTION:
f72d3d23 1912 case PCI_IVAR_ETHADDR:
c7e4e7eb
SZ
1913 case PCI_IVAR_PCIXCAP_PTR:
1914 case PCI_IVAR_PCIECAP_PTR:
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MD
1915 return EINVAL; /* disallow for now */
1916
1917 case PCI_IVAR_SECONDARYBUS:
1918 cfg->secondarybus = value;
1919 break;
1920 case PCI_IVAR_SUBORDINATEBUS:
1921 cfg->subordinatebus = value;
1922 break;
1923 default:
1924 return ENOENT;
1925 }
1926 return 0;
1927}
1928
201eb0a7
TS
1929#ifdef PCI_MAP_FIXUP
1930static struct resource *
1931pci_alloc_map(device_t dev, device_t child, int type, int *rid, u_long start,
1932 u_long end, u_long count, u_int flags)
1933{
1934 struct pci_devinfo *dinfo = device_get_ivars(child);
1935 struct resource_list *rl = &dinfo->resources;
1936 struct resource_list_entry *rle;
1937 struct resource *res;
1938 uint32_t map, testval;
1939 int mapsize;
1940
1941 /*
1942 * Weed out the bogons, and figure out how large the BAR/map
1943 * is. BARs that read back 0 here are bogus and unimplemented.
1944 *
1945 * Note: atapci in legacy mode are special and handled elsewhere
1946 * in the code. If you have an atapci device in legacy mode and
1947 * it fails here, that other code is broken.
1948 */
1949 res = NULL;
1950 map = pci_read_config(child, *rid, 4);
1951 pci_write_config(child, *rid, 0xffffffff, 4);
1952 testval = pci_read_config(child, *rid, 4);
1953 if (pci_mapbase(testval) == 0)
1954 goto out;
1955 if (pci_maptype(testval) & PCI_MAPMEM) {
1956 if (type != SYS_RES_MEMORY) {
1957 if (bootverbose)
1958 device_printf(dev, "child %s requested type %d"
1959 " for rid %#x, but the BAR says "
1960 "it is a memio\n",
1961 device_get_nameunit(child), type,
1962 *rid);
1963 goto out;
1964 }
1965 } else {
1966 if (type != SYS_RES_IOPORT) {
1967 if (bootverbose)
1968 device_printf(dev, "child %s requested type %d"
1969 " for rid %#x, but the BAR says "
1970 "it is an ioport\n",
1971 device_get_nameunit(child), type,
1972 *rid);
1973 goto out;
1974 }
1975 }
1976 /*
1977 * For real BARs, we need to override the size that
1978 * the driver requests, because that's what the BAR
1979 * actually uses and we would otherwise have a
1980 * situation where we might allocate the excess to
1981 * another driver, which won't work.
1982 */
1983 mapsize = pci_mapsize(testval);
1984 count = 1 << mapsize;
1985 if (RF_ALIGNMENT(flags) < mapsize)
1986 flags = (flags & ~RF_ALIGNMENT_MASK) |
1987 RF_ALIGNMENT_LOG2(mapsize);
1988 /*
1989 * Allocate enough resource, and then write back the
1990 * appropriate BAR for that resource.
1991 */
1992 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
1993 start, end, count, flags);
1994 if (res == NULL) {
1995 device_printf(child, "%#lx bytes at rid %#x res %d failed "
1996 "(%#lx, %#lx)\n", count, *rid, type, start, end);
1997 goto out;
1998 }
1999 resource_list_add(rl, type, *rid, start, end, count);
2000 rle = resource_list_find(rl, type, *rid);
2001 if (rle == NULL)
2002 panic("pci_alloc_map: unexpectedly can't find resource.");
2003 rle->res = res;
2004 rle->start = rman_get_start(res);
2005 rle->end = rman_get_end(res);
2006 rle->count = count;
2007 if (bootverbose)
2008 device_printf(child, "lazy allocation of %#lx bytes rid %#x "
2009 "type %d at %#lx\n", count, *rid, type,
2010 rman_get_start(res));
2011 map = rman_get_start(res);
2012out:;
2013 pci_write_config(child, *rid, map, 4);
2014 return res;
2015}
2016#endif /* PCI_MAP_FIXUP */
2017
261fa16d 2018struct resource *
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MD
2019pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
2020 u_long start, u_long end, u_long count, u_int flags)
2021{
2022 struct pci_devinfo *dinfo = device_get_ivars(child);
2023 struct resource_list *rl = &dinfo->resources;
201eb0a7
TS
2024#ifdef PCI_MAP_FIXUP
2025 struct resource_list_entry *rle;
2026#endif /* PCI_MAP_FIXUP */
984263bc 2027 pcicfgregs *cfg = &dinfo->cfg;
de67e43b 2028
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MD
2029 /*
2030 * Perform lazy resource allocation
984263bc
MD
2031 */
2032 if (device_get_parent(child) == dev) {
de67e43b
JS
2033 switch (type) {
2034 case SYS_RES_IRQ:
2035#ifdef __i386__
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MD
2036 /*
2037 * If device doesn't have an interrupt routed, and is
2038 * deserving of an interrupt, try to assign it one.
2039 */
de67e43b
JS
2040 if ((cfg->intline == 255 || cfg->intline == 0) &&
2041 (cfg->intpin != 0) &&
2042 (start == 0) && (end == ~0UL)) {
2043 cfg->intline = PCIB_ROUTE_INTERRUPT(
2044 device_get_parent(dev), child,
2045 cfg->intpin);
2046 if (cfg->intline != 255) {
2047 pci_write_config(child, PCIR_INTLINE,
2048 cfg->intline, 1);
2049 resource_list_add(rl, SYS_RES_IRQ, 0,
2050 cfg->intline, cfg->intline, 1);
2051 }
2052 }
820c1612 2053 break;
de67e43b
JS
2054#endif
2055 case SYS_RES_IOPORT:
201eb0a7 2056 /* FALLTHROUGH */
de67e43b
JS
2057 case SYS_RES_MEMORY:
2058 if (*rid < PCIR_BAR(cfg->nummaps)) {
2059 /*
2060 * Enable the I/O mode. We should
2061 * also be assigning resources too
2062 * when none are present. The
2063 * resource_list_alloc kind of sorta does
2064 * this...
2065 */
2066 if (PCI_ENABLE_IO(dev, child, type))
2067 return (NULL);
984263bc 2068 }
201eb0a7
TS
2069#ifdef PCI_MAP_FIXUP
2070 rle = resource_list_find(rl, type, *rid);
2071 if (rle == NULL)
2072 return pci_alloc_map(dev, child, type, rid,
2073 start, end, count, flags);
2074#endif /* PCI_MAP_FIXUP */
820c1612 2075 break;
984263bc 2076 }
201eb0a7
TS
2077#ifdef PCI_MAP_FIXUP
2078 /*
2079 * If we've already allocated the resource, then
2080 * return it now. But first we may need to activate
2081 * it, since we don't allocate the resource as active
2082 * above. Normally this would be done down in the
2083 * nexus, but since we short-circuit that path we have
2084 * to do its job here. Not sure if we should free the
2085 * resource if it fails to activate.
2086 *
2087 * Note: this also finds and returns resources for
2088 * atapci devices in legacy mode as allocated in
2089 * pci_ata_maps().
2090 */
2091 rle = resource_list_find(rl, type, *rid);
2092 if (rle != NULL && rle->res != NULL) {
2093 if (bootverbose)
2094 device_printf(child, "reserved %#lx bytes for "
2095 "rid %#x type %d at %#lx\n",
2096 rman_get_size(rle->res), *rid,
2097 type, rman_get_start(rle->res));
2098 if ((flags & RF_ACTIVE) &&
2099 bus_generic_activate_resource(dev, child, type,
2100 *rid, rle->res) != 0)
2101 return NULL;
2102 return rle->res;
2103 }
2104#endif /* PCI_MAP_FIXUP */
984263bc 2105 }
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MD
2106 return resource_list_alloc(rl, dev, child, type, rid,
2107 start, end, count, flags);
2108}
2109
2110static int
2111pci_release_resource(device_t dev, device_t child, int type, int rid,
2112 struct resource *r)
2113{
2114 struct pci_devinfo *dinfo = device_get_ivars(child);
2115 struct resource_list *rl = &dinfo->resources;
2116
2117 return resource_list_release(rl, dev, child, type, rid, r);
2118}
2119
2120static int
2121pci_set_resource(device_t dev, device_t child, int type, int rid,
2122 u_long start, u_long count)
2123{
2124 struct pci_devinfo *dinfo = device_get_ivars(child);
2125 struct resource_list *rl = &dinfo->resources;
2126
2127 resource_list_add(rl, type, rid, start, start + count - 1, count);
2128 return 0;
2129}
2130
2131static int
2132pci_get_resource(device_t dev, device_t child, int type, int rid,
2133 u_long *startp, u_long *countp)
2134{
2135 struct pci_devinfo *dinfo = device_get_ivars(child);
2136 struct resource_list *rl = &dinfo->resources;
2137 struct resource_list_entry *rle;
2138
2139 rle = resource_list_find(rl, type, rid);
2140 if (!rle)
2141 return ENOENT;
2142
2143 if (startp)
2144 *startp = rle->start;
2145 if (countp)
2146 *countp = rle->count;
2147
2148 return 0;
2149}
2150
e126caf1 2151void
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MD
2152pci_delete_resource(device_t dev, device_t child, int type, int rid)
2153{
85f8e2ea 2154 kprintf("pci_delete_resource: PCI resources can not be deleted\n");
984263bc
MD
2155}
2156
e126caf1
MD
2157struct resource_list *
2158pci_get_resource_list (device_t dev, device_t child)
2159{
b0486c83 2160 struct pci_devinfo *dinfo = device_get_ivars(child);
e126caf1 2161
b0486c83 2162 if (dinfo == NULL)
e126caf1 2163 return (NULL);
b0486c83 2164 return (&dinfo->resources);
e126caf1
MD
2165}
2166
2167u_int32_t
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MD
2168pci_read_config_method(device_t dev, device_t child, int reg, int width)
2169{
2170 struct pci_devinfo *dinfo = device_get_ivars(child);
2171 pcicfgregs *cfg = &dinfo->cfg;
4a5a2d63
JS
2172
2173 return PCIB_READ_CONFIG(device_get_parent(dev),
2174 cfg->bus, cfg->slot, cfg->func,
2175 reg, width);
984263bc
MD
2176}
2177
e126caf1 2178void
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MD
2179pci_write_config_method(device_t dev, device_t child, int reg,
2180 u_int32_t val, int width)
2181{
2182 struct pci_devinfo *dinfo = device_get_ivars(child);
2183 pcicfgregs *cfg = &dinfo->cfg;
4a5a2d63
JS
2184
2185 PCIB_WRITE_CONFIG(device_get_parent(dev),
2186 cfg->bus, cfg->slot, cfg->func,
2187 reg, val, width);
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MD
2188}
2189
e126caf1
MD
2190int
2191pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
2192 size_t buflen)
2193{
2194 struct pci_devinfo *dinfo;
2195
2196 dinfo = device_get_ivars(child);
f8c7a42d 2197 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
e126caf1
MD
2198 pci_get_function(child));
2199 return (0);
2200}
2201
2202int
2203pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
2204 size_t buflen)
2205{
2206 struct pci_devinfo *dinfo;
2207 pcicfgregs *cfg;
2208
2209 dinfo = device_get_ivars(child);
2210 cfg = &dinfo->cfg;
f8c7a42d 2211 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
e126caf1
MD
2212 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
2213 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
2214 cfg->progif);
2215 return (0);
2216}
2217
2218int
2219pci_assign_interrupt_method(device_t dev, device_t child)
2220{
2221 struct pci_devinfo *dinfo = device_get_ivars(child);
2222 pcicfgregs *cfg = &dinfo->cfg;
2223
2224 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
2225 cfg->intpin));
2226}
2227
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MD
2228static int
2229pci_modevent(module_t mod, int what, void *arg)
2230{
2231 switch (what) {
2232 case MOD_LOAD:
2233 STAILQ_INIT(&pci_devq);
2234 break;
984263bc
MD
2235 case MOD_UNLOAD:
2236 break;
2237 }
2238
2239 return 0;
2240}
2241
e126caf1
MD
2242int
2243pci_resume(device_t dev)
2244{
2245 int numdevs;
2246 int i;
2247 device_t *children;
2248 device_t child;
2249 struct pci_devinfo *dinfo;
2250 pcicfgregs *cfg;
2251
2252 device_get_children(dev, &children, &numdevs);
2253
2254 for (i = 0; i < numdevs; i++) {
2255 child = children[i];
2256
2257 dinfo = device_get_ivars(child);
2258 cfg = &dinfo->cfg;
2259 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2260 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
2261 if (PCI_INTERRUPT_VALID(cfg->intline)) {
2262 pci_write_config(child, PCIR_INTLINE,
2263 cfg->intline, 1);
2264 }
2265 }
2266 }
2267
efda3bd0 2268 kfree(children, M_TEMP);
e126caf1
MD
2269
2270 return (bus_generic_resume(dev));
2271}
2272
984263bc
MD
2273static device_method_t pci_methods[] = {
2274 /* Device interface */
4a5a2d63 2275 DEVMETHOD(device_probe, pci_probe),
e126caf1 2276 DEVMETHOD(device_attach, pci_attach),
984263bc
MD
2277 DEVMETHOD(device_shutdown, bus_generic_shutdown),
2278 DEVMETHOD(device_suspend, bus_generic_suspend),
e126caf1 2279 DEVMETHOD(device_resume, pci_resume),
984263bc
MD
2280
2281 /* Bus interface */
2282 DEVMETHOD(bus_print_child, pci_print_child),
2283 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
2284 DEVMETHOD(bus_read_ivar, pci_read_ivar),
2285 DEVMETHOD(bus_write_ivar, pci_write_ivar),
2286 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
984263bc
MD
2287 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
2288 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
e126caf1
MD
2289
2290 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
984263bc
MD
2291 DEVMETHOD(bus_set_resource, pci_set_resource),
2292 DEVMETHOD(bus_get_resource, pci_get_resource),
2293 DEVMETHOD(bus_delete_resource, pci_delete_resource),
e126caf1
MD
2294 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
2295 DEVMETHOD(bus_release_resource, pci_release_resource),
2296 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
2297 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
2298 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
2299 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
984263bc
MD
2300
2301 /* PCI interface */
2302 DEVMETHOD(pci_read_config, pci_read_config_method),
2303 DEVMETHOD(pci_write_config, pci_write_config_method),
2304 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
2305 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
2306 DEVMETHOD(pci_enable_io, pci_enable_io_method),
2307 DEVMETHOD(pci_disable_io, pci_disable_io_method),
2308 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
2309 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
e126caf1 2310 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
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MD
2311
2312 { 0, 0 }
2313};
2314
3aef8050 2315driver_t pci_driver = {
984263bc
MD
2316 "pci",
2317 pci_methods,
2318 1, /* no softc */
2319};
2320
2321DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
261fa16d 2322MODULE_VERSION(pci, 1);