carp: add carp_group_demote_adj()
[dragonfly.git] / sys / bus / pci / pci.c
CommitLineData
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1/*-
2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
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5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83c1faaa
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27 *
28 * $FreeBSD: src/sys/dev/pci/pci.c,v 1.355.2.9.2.1 2009/04/15 03:14:26 kensmith Exp $
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29 */
30
4d28e78f 31#include "opt_bus.h"
92683a33 32#include "opt_acpi.h"
6951547b 33#include "opt_compat_oldpci.h"
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34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/malloc.h>
38#include <sys/module.h>
4d28e78f 39#include <sys/linker.h>
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40#include <sys/fcntl.h>
41#include <sys/conf.h>
42#include <sys/kernel.h>
43#include <sys/queue.h>
638744c5 44#include <sys/sysctl.h>
4d28e78f 45#include <sys/endian.h>
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46
47#include <vm/vm.h>
48#include <vm/pmap.h>
49#include <vm/vm_extern.h>
50
51#include <sys/bus.h>
984263bc 52#include <sys/rman.h>
4d28e78f 53#include <sys/device.h>
984263bc 54
dc5a7bd2 55#include <sys/pciio.h>
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56#include <bus/pci/pcireg.h>
57#include <bus/pci/pcivar.h>
58#include <bus/pci/pci_private.h>
984263bc 59
4a5a2d63 60#include "pcib_if.h"
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61#include "pci_if.h"
62
63#ifdef __HAVE_ACPI
64#include <contrib/dev/acpica/acpi.h>
65#include "acpi_if.h"
66#else
67#define ACPI_PWR_FOR_SLEEP(x, y, z)
68#endif
69
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70extern struct dev_ops pcic_ops; /* XXX */
71
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72typedef void (*pci_read_cap_t)(device_t, int, int, pcicfgregs *);
73
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74static uint32_t pci_mapbase(unsigned mapreg);
75static const char *pci_maptype(unsigned mapreg);
76static int pci_mapsize(unsigned testval);
77static int pci_maprange(unsigned mapreg);
78static void pci_fixancient(pcicfgregs *cfg);
79
80static int pci_porten(device_t pcib, int b, int s, int f);
81static int pci_memen(device_t pcib, int b, int s, int f);
82static void pci_assign_interrupt(device_t bus, device_t dev,
83 int force_route);
84static int pci_add_map(device_t pcib, device_t bus, device_t dev,
85 int b, int s, int f, int reg,
86 struct resource_list *rl, int force, int prefetch);
87static int pci_probe(device_t dev);
88static int pci_attach(device_t dev);
11a49859 89static void pci_child_detached(device_t, device_t);
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90static void pci_load_vendor_data(void);
91static int pci_describe_parse_line(char **ptr, int *vendor,
92 int *device, char **desc);
93static char *pci_describe_device(device_t dev);
94static int pci_modevent(module_t mod, int what, void *arg);
95static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
96 pcicfgregs *cfg);
3a6dc23c 97static void pci_read_capabilities(device_t pcib, pcicfgregs *cfg);
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98static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
99 int reg, uint32_t *data);
100#if 0
101static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
102 int reg, uint32_t data);
103#endif
104static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
105static void pci_disable_msi(device_t dev);
106static void pci_enable_msi(device_t dev, uint64_t address,
107 uint16_t data);
108static void pci_enable_msix(device_t dev, u_int index,
109 uint64_t address, uint32_t data);
110static void pci_mask_msix(device_t dev, u_int index);
111static void pci_unmask_msix(device_t dev, u_int index);
112static int pci_msi_blacklisted(void);
113static void pci_resume_msi(device_t dev);
114static void pci_resume_msix(device_t dev);
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115static int pcie_slotimpl(const pcicfgregs *);
116static void pci_print_verbose_expr(const pcicfgregs *);
4d28e78f 117
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118static void pci_read_cap_pmgt(device_t, int, int, pcicfgregs *);
119static void pci_read_cap_ht(device_t, int, int, pcicfgregs *);
120static void pci_read_cap_msi(device_t, int, int, pcicfgregs *);
121static void pci_read_cap_msix(device_t, int, int, pcicfgregs *);
122static void pci_read_cap_vpd(device_t, int, int, pcicfgregs *);
123static void pci_read_cap_subvendor(device_t, int, int,
124 pcicfgregs *);
125static void pci_read_cap_pcix(device_t, int, int, pcicfgregs *);
d85e7311 126static void pci_read_cap_express(device_t, int, int, pcicfgregs *);
3a6dc23c 127
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128static device_method_t pci_methods[] = {
129 /* Device interface */
130 DEVMETHOD(device_probe, pci_probe),
131 DEVMETHOD(device_attach, pci_attach),
132 DEVMETHOD(device_detach, bus_generic_detach),
133 DEVMETHOD(device_shutdown, bus_generic_shutdown),
134 DEVMETHOD(device_suspend, pci_suspend),
135 DEVMETHOD(device_resume, pci_resume),
136
137 /* Bus interface */
138 DEVMETHOD(bus_print_child, pci_print_child),
139 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
140 DEVMETHOD(bus_read_ivar, pci_read_ivar),
141 DEVMETHOD(bus_write_ivar, pci_write_ivar),
142 DEVMETHOD(bus_driver_added, pci_driver_added),
11a49859 143 DEVMETHOD(bus_child_detached, pci_child_detached),
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144 DEVMETHOD(bus_setup_intr, pci_setup_intr),
145 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
146
147 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
148 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
149 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
150 DEVMETHOD(bus_delete_resource, pci_delete_resource),
151 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
152 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
153 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
154 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
155 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
156 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
157
158 /* PCI interface */
159 DEVMETHOD(pci_read_config, pci_read_config_method),
160 DEVMETHOD(pci_write_config, pci_write_config_method),
161 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
162 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
163 DEVMETHOD(pci_enable_io, pci_enable_io_method),
164 DEVMETHOD(pci_disable_io, pci_disable_io_method),
165 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
166 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
167 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
168 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
169 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
170 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
171 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
172 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
173 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
174 DEVMETHOD(pci_release_msi, pci_release_msi_method),
175 DEVMETHOD(pci_msi_count, pci_msi_count_method),
176 DEVMETHOD(pci_msix_count, pci_msix_count_method),
177
178 { 0, 0 }
179};
180
181DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
4a5a2d63 182
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183static devclass_t pci_devclass;
184DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
185MODULE_VERSION(pci, 1);
186
187static char *pci_vendordata;
188static size_t pci_vendordata_size;
dc5a7bd2 189
984263bc 190
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191static const struct pci_read_cap {
192 int cap;
193 pci_read_cap_t read_cap;
194} pci_read_caps[] = {
195 { PCIY_PMG, pci_read_cap_pmgt },
196 { PCIY_HT, pci_read_cap_ht },
197 { PCIY_MSI, pci_read_cap_msi },
198 { PCIY_MSIX, pci_read_cap_msix },
199 { PCIY_VPD, pci_read_cap_vpd },
200 { PCIY_SUBVENDOR, pci_read_cap_subvendor },
201 { PCIY_PCIX, pci_read_cap_pcix },
d85e7311 202 { PCIY_EXPRESS, pci_read_cap_express },
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203 { 0, NULL } /* required last entry */
204};
205
984263bc 206struct pci_quirk {
4d28e78f 207 uint32_t devid; /* Vendor/device of the card */
984263bc 208 int type;
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209#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
210#define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
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211 int arg1;
212 int arg2;
213};
214
215struct pci_quirk pci_quirks[] = {
4d28e78f 216 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
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217 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
218 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
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219 /* As does the Serverworks OSB4 (the SMBus mapping register) */
220 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
984263bc 221
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222 /*
223 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
224 * or the CMIC-SL (AKA ServerWorks GC_LE).
225 */
226 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
227 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
228
229 /*
230 * MSI doesn't work on earlier Intel chipsets including
231 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
232 */
233 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
234 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
235 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
236 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
237 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
238 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
239 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
240
241 /*
242 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
243 * bridge.
244 */
245 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
246
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247 { 0 }
248};
249
250/* map register information */
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251#define PCI_MAPMEM 0x01 /* memory map */
252#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
253#define PCI_MAPPORT 0x04 /* port map */
254
255struct devlist pci_devq;
256uint32_t pci_generation;
257uint32_t pci_numdevs = 0;
258static int pcie_chipset, pcix_chipset;
259
260/* sysctl vars */
261SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
262
263static int pci_enable_io_modes = 1;
264TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
265SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
266 &pci_enable_io_modes, 1,
267 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
268enable these bits correctly. We'd like to do this all the time, but there\n\
269are some peripherals that this causes problems with.");
984263bc 270
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271static int pci_do_power_nodriver = 0;
272TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
273SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
274 &pci_do_power_nodriver, 0,
275 "Place a function into D3 state when no driver attaches to it. 0 means\n\
276disable. 1 means conservatively place devices into D3 state. 2 means\n\
6699890a 277aggressively place devices into D3 state. 3 means put absolutely everything\n\
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278in D3 state.");
279
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280static int pci_do_power_resume = 1;
281TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
282SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
283 &pci_do_power_resume, 1,
284 "Transition from D3 -> D0 on resume.");
285
286static int pci_do_msi = 1;
287TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
288SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
289 "Enable support for MSI interrupts");
290
291static int pci_do_msix = 1;
292TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
293SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
294 "Enable support for MSI-X interrupts");
295
296static int pci_honor_msi_blacklist = 1;
297TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
298SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
299 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
300
301/* Find a device_t by bus/slot/function in domain 0 */
302
303device_t
304pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
305{
306
307 return (pci_find_dbsf(0, bus, slot, func));
308}
309
310/* Find a device_t by domain/bus/slot/function */
311
984263bc 312device_t
4d28e78f 313pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
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314{
315 struct pci_devinfo *dinfo;
316
317 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
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318 if ((dinfo->cfg.domain == domain) &&
319 (dinfo->cfg.bus == bus) &&
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320 (dinfo->cfg.slot == slot) &&
321 (dinfo->cfg.func == func)) {
322 return (dinfo->cfg.dev);
323 }
324 }
325
326 return (NULL);
327}
328
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329/* Find a device_t by vendor/device ID */
330
984263bc 331device_t
4d28e78f 332pci_find_device(uint16_t vendor, uint16_t device)
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333{
334 struct pci_devinfo *dinfo;
335
336 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
337 if ((dinfo->cfg.vendor == vendor) &&
338 (dinfo->cfg.device == device)) {
339 return (dinfo->cfg.dev);
340 }
341 }
342
343 return (NULL);
344}
345
346/* return base address of memory or port map */
347
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348static uint32_t
349pci_mapbase(uint32_t mapreg)
984263bc 350{
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351
352 if (PCI_BAR_MEM(mapreg))
353 return (mapreg & PCIM_BAR_MEM_BASE);
354 else
355 return (mapreg & PCIM_BAR_IO_BASE);
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356}
357
358/* return map type of memory or port map */
359
4d28e78f 360static const char *
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361pci_maptype(unsigned mapreg)
362{
984263bc 363
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364 if (PCI_BAR_IO(mapreg))
365 return ("I/O Port");
366 if (mapreg & PCIM_BAR_MEM_PREFETCH)
367 return ("Prefetchable Memory");
368 return ("Memory");
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369}
370
371/* return log2 of map size decoded for memory or port map */
372
373static int
4d28e78f 374pci_mapsize(uint32_t testval)
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375{
376 int ln2size;
377
378 testval = pci_mapbase(testval);
379 ln2size = 0;
380 if (testval != 0) {
381 while ((testval & 1) == 0)
382 {
383 ln2size++;
384 testval >>= 1;
385 }
386 }
387 return (ln2size);
388}
389
390/* return log2 of address range supported by map register */
391
392static int
393pci_maprange(unsigned mapreg)
394{
395 int ln2range = 0;
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396
397 if (PCI_BAR_IO(mapreg))
984263bc 398 ln2range = 32;
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399 else
400 switch (mapreg & PCIM_BAR_MEM_TYPE) {
401 case PCIM_BAR_MEM_32:
402 ln2range = 32;
403 break;
404 case PCIM_BAR_MEM_1MB:
405 ln2range = 20;
406 break;
407 case PCIM_BAR_MEM_64:
408 ln2range = 64;
409 break;
410 }
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411 return (ln2range);
412}
413
414/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
415
416static void
417pci_fixancient(pcicfgregs *cfg)
418{
419 if (cfg->hdrtype != 0)
420 return;
421
422 /* PCI to PCI bridges use header type 1 */
423 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
424 cfg->hdrtype = 1;
425}
426
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427/* extract header type specific config data */
428
429static void
4a5a2d63 430pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
984263bc 431{
4d28e78f 432#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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433 switch (cfg->hdrtype) {
434 case 0:
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435 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
436 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
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437 cfg->nummaps = PCI_MAXMAPS_0;
438 break;
439 case 1:
984263bc 440 cfg->nummaps = PCI_MAXMAPS_1;
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441#ifdef COMPAT_OLDPCI
442 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
443#endif
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444 break;
445 case 2:
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446 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
447 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
984263bc 448 cfg->nummaps = PCI_MAXMAPS_2;
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449#ifdef COMPAT_OLDPCI
450 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
451#endif
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452 break;
453 }
4a5a2d63 454#undef REG
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455}
456
4d28e78f 457/* read configuration header into pcicfgregs structure */
22457186 458struct pci_devinfo *
4d28e78f 459pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
984263bc 460{
4d28e78f 461#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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462 pcicfgregs *cfg = NULL;
463 struct pci_devinfo *devlist_entry;
464 struct devlist *devlist_head;
465
466 devlist_head = &pci_devq;
467
468 devlist_entry = NULL;
469
4d28e78f 470 if (REG(PCIR_DEVVENDOR, 4) != -1) {
efda3bd0 471 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
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472
473 cfg = &devlist_entry->cfg;
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474
475 cfg->domain = d;
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476 cfg->bus = b;
477 cfg->slot = s;
478 cfg->func = f;
479 cfg->vendor = REG(PCIR_VENDOR, 2);
480 cfg->device = REG(PCIR_DEVICE, 2);
481 cfg->cmdreg = REG(PCIR_COMMAND, 2);
482 cfg->statreg = REG(PCIR_STATUS, 2);
483 cfg->baseclass = REG(PCIR_CLASS, 1);
484 cfg->subclass = REG(PCIR_SUBCLASS, 1);
485 cfg->progif = REG(PCIR_PROGIF, 1);
486 cfg->revid = REG(PCIR_REVID, 1);
e126caf1 487 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
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488 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
489 cfg->lattimer = REG(PCIR_LATTIMER, 1);
490 cfg->intpin = REG(PCIR_INTPIN, 1);
491 cfg->intline = REG(PCIR_INTLINE, 1);
984263bc 492
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493 cfg->mingnt = REG(PCIR_MINGNT, 1);
494 cfg->maxlat = REG(PCIR_MAXLAT, 1);
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495
496 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
497 cfg->hdrtype &= ~PCIM_MFDEV;
498
499 pci_fixancient(cfg);
4a5a2d63 500 pci_hdrtypedata(pcib, b, s, f, cfg);
4d28e78f 501
3a6dc23c 502 pci_read_capabilities(pcib, cfg);
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503
504 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
505
4d28e78f 506 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
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507 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
508 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
509 devlist_entry->conf.pc_sel.pc_func = cfg->func;
510 devlist_entry->conf.pc_hdr = cfg->hdrtype;
511
512 devlist_entry->conf.pc_subvendor = cfg->subvendor;
513 devlist_entry->conf.pc_subdevice = cfg->subdevice;
514 devlist_entry->conf.pc_vendor = cfg->vendor;
515 devlist_entry->conf.pc_device = cfg->device;
516
517 devlist_entry->conf.pc_class = cfg->baseclass;
518 devlist_entry->conf.pc_subclass = cfg->subclass;
519 devlist_entry->conf.pc_progif = cfg->progif;
520 devlist_entry->conf.pc_revid = cfg->revid;
521
522 pci_numdevs++;
523 pci_generation++;
524 }
525 return (devlist_entry);
526#undef REG
527}
528
3a6dc23c
SZ
529static int
530pci_fixup_nextptr(int *nextptr0)
531{
532 int nextptr = *nextptr0;
533
534 /* "Next pointer" is only one byte */
535 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
536
537 if (nextptr & 0x3) {
538 /*
539 * PCI local bus spec 3.0:
540 *
541 * "... The bottom two bits of all pointers are reserved
542 * and must be implemented as 00b although software must
543 * mask them to allow for future uses of these bits ..."
544 */
545 if (bootverbose) {
546 kprintf("Illegal PCI extended capability "
547 "offset, fixup 0x%02x -> 0x%02x\n",
548 nextptr, nextptr & ~0x3);
549 }
550 nextptr &= ~0x3;
551 }
552 *nextptr0 = nextptr;
553
554 if (nextptr < 0x40) {
555 if (nextptr != 0) {
556 kprintf("Illegal PCI extended capability "
557 "offset 0x%02x", nextptr);
558 }
559 return 0;
560 }
561 return 1;
562}
563
984263bc 564static void
3a6dc23c 565pci_read_cap_pmgt(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
984263bc 566{
3a6dc23c
SZ
567#define REG(n, w) \
568 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
569
570 struct pcicfg_pp *pp = &cfg->pp;
571
572 if (pp->pp_cap)
573 return;
574
575 pp->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
576 pp->pp_status = ptr + PCIR_POWER_STATUS;
577 pp->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
578
579 if ((nextptr - ptr) > PCIR_POWER_DATA) {
580 /*
581 * XXX
582 * We should write to data_select and read back from
583 * data_scale to determine whether data register is
584 * implemented.
585 */
586#ifdef foo
587 pp->pp_data = ptr + PCIR_POWER_DATA;
588#else
589 pp->pp_data = 0;
590#endif
591 }
592
593#undef REG
594}
595
596static void
597pci_read_cap_ht(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
598{
599#ifdef notyet
b2b3ffcd 600#if defined(__i386__) || defined(__x86_64__)
3a6dc23c
SZ
601
602#define REG(n, w) \
603 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
604
605 struct pcicfg_ht *ht = &cfg->ht;
4d28e78f 606 uint64_t addr;
4d28e78f 607 uint32_t val;
3a6dc23c
SZ
608
609 /* Determine HT-specific capability type. */
610 val = REG(ptr + PCIR_HT_COMMAND, 2);
611
612 if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_MSI_MAPPING)
613 return;
614
615 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
616 /* Sanity check the mapping window. */
617 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 4);
618 addr <<= 32;
619 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 4);
620 if (addr != MSI_INTEL_ADDR_BASE) {
621 device_printf(pcib, "HT Bridge at pci%d:%d:%d:%d "
622 "has non-default MSI window 0x%llx\n",
623 cfg->domain, cfg->bus, cfg->slot, cfg->func,
624 (long long)addr);
625 }
626 } else {
627 addr = MSI_INTEL_ADDR_BASE;
628 }
629
630 ht->ht_msimap = ptr;
631 ht->ht_msictrl = val;
632 ht->ht_msiaddr = addr;
633
634#undef REG
635
b2b3ffcd 636#endif /* __i386__ || __x86_64__ */
3a6dc23c
SZ
637#endif /* notyet */
638}
639
640static void
641pci_read_cap_msi(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
642{
643#define REG(n, w) \
644 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
645
646 struct pcicfg_msi *msi = &cfg->msi;
647
648 msi->msi_location = ptr;
649 msi->msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
650 msi->msi_msgnum = 1 << ((msi->msi_ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
651
652#undef REG
653}
654
655static void
656pci_read_cap_msix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
657{
658#define REG(n, w) \
659 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
660
661 struct pcicfg_msix *msix = &cfg->msix;
662 uint32_t val;
663
664 msix->msix_location = ptr;
665 msix->msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
666 msix->msix_msgnum = (msix->msix_ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
667
668 val = REG(ptr + PCIR_MSIX_TABLE, 4);
669 msix->msix_table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
670 msix->msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
671
672 val = REG(ptr + PCIR_MSIX_PBA, 4);
673 msix->msix_pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
674 msix->msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
675
676#undef REG
677}
678
679static void
680pci_read_cap_vpd(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
681{
682 cfg->vpd.vpd_reg = ptr;
683}
684
685static void
686pci_read_cap_subvendor(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
687{
688#define REG(n, w) \
689 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
690
691 /* Should always be true. */
692 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
693 uint32_t val;
694
695 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
696 cfg->subvendor = val & 0xffff;
697 cfg->subdevice = val >> 16;
698 }
699
700#undef REG
701}
702
703static void
704pci_read_cap_pcix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
705{
706 /*
707 * Assume we have a PCI-X chipset if we have
708 * at least one PCI-PCI bridge with a PCI-X
709 * capability. Note that some systems with
710 * PCI-express or HT chipsets might match on
711 * this check as well.
712 */
713 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
714 pcix_chipset = 1;
d85e7311
SZ
715
716 cfg->pcix.pcix_ptr = ptr;
717}
718
719static int
720pcie_slotimpl(const pcicfgregs *cfg)
721{
722 const struct pcicfg_expr *expr = &cfg->expr;
723 uint16_t port_type;
724
725 /*
726 * Only version 1 can be parsed currently
727 */
728 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
729 return 0;
730
731 /*
732 * - Slot implemented bit is meaningful iff current port is
733 * root port or down stream port.
734 * - Testing for root port or down stream port is meanningful
735 * iff PCI configure has type 1 header.
736 */
737
738 if (cfg->hdrtype != 1)
739 return 0;
740
741 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
742 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT)
743 return 0;
744
745 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
746 return 0;
747
748 return 1;
3a6dc23c
SZ
749}
750
751static void
d85e7311 752pci_read_cap_express(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
3a6dc23c 753{
d85e7311
SZ
754#define REG(n, w) \
755 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
756
757 struct pcicfg_expr *expr = &cfg->expr;
758
3a6dc23c
SZ
759 /*
760 * Assume we have a PCI-express chipset if we have
761 * at least one PCI-express device.
762 */
763 pcie_chipset = 1;
d85e7311
SZ
764
765 expr->expr_ptr = ptr;
766 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
767
768 /*
769 * Only version 1 can be parsed currently
770 */
771 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
772 return;
773
774 /*
775 * Read slot capabilities. Slot capabilities exists iff
776 * current port's slot is implemented
777 */
778 if (pcie_slotimpl(cfg))
779 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
780
781#undef REG
3a6dc23c
SZ
782}
783
784static void
785pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
786{
787#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
788#define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
789
790 uint32_t val;
791 int nextptr, ptrptr;
792
793 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
794 /* No capabilities */
795 return;
796 }
0c78fe3f 797
4d28e78f 798 switch (cfg->hdrtype & PCIM_HDRTYPE) {
984263bc 799 case 0:
81c29ce4
SZ
800 case 1:
801 ptrptr = PCIR_CAP_PTR;
984263bc
MD
802 break;
803 case 2:
4d28e78f 804 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
984263bc
MD
805 break;
806 default:
3a6dc23c 807 return; /* no capabilities support */
984263bc 808 }
4d28e78f 809 nextptr = REG(ptrptr, 1); /* sanity check? */
984263bc
MD
810
811 /*
812 * Read capability entries.
813 */
3a6dc23c
SZ
814 while (pci_fixup_nextptr(&nextptr)) {
815 const struct pci_read_cap *rc;
816 int ptr = nextptr;
817
4d28e78f 818 /* Find the next entry */
4d28e78f 819 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
984263bc
MD
820
821 /* Process this entry */
3a6dc23c
SZ
822 val = REG(ptr + PCICAP_ID, 1);
823 for (rc = pci_read_caps; rc->read_cap != NULL; ++rc) {
824 if (rc->cap == val) {
825 rc->read_cap(pcib, ptr, nextptr, cfg);
4d28e78f
SZ
826 break;
827 }
984263bc
MD
828 }
829 }
4d28e78f 830/* REG and WREG use carry through to next functions */
984263bc
MD
831}
832
4d28e78f
SZ
833/*
834 * PCI Vital Product Data
835 */
836
837#define PCI_VPD_TIMEOUT 1000000
984263bc 838
4d28e78f
SZ
839static int
840pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
984263bc 841{
4d28e78f 842 int count = PCI_VPD_TIMEOUT;
984263bc 843
4d28e78f 844 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
984263bc 845
4d28e78f 846 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
984263bc 847
4d28e78f
SZ
848 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
849 if (--count < 0)
850 return (ENXIO);
851 DELAY(1); /* limit looping */
852 }
853 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
984263bc 854
984263bc
MD
855 return (0);
856}
984263bc 857
4d28e78f
SZ
858#if 0
859static int
860pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
984263bc 861{
4d28e78f
SZ
862 int count = PCI_VPD_TIMEOUT;
863
864 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
865
866 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
867 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
868 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
869 if (--count < 0)
870 return (ENXIO);
871 DELAY(1); /* limit looping */
872 }
873
874 return (0);
875}
876#endif
877
878#undef PCI_VPD_TIMEOUT
879
880struct vpd_readstate {
881 device_t pcib;
882 pcicfgregs *cfg;
883 uint32_t val;
884 int bytesinval;
885 int off;
886 uint8_t cksum;
887};
888
889static int
890vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
891{
892 uint32_t reg;
893 uint8_t byte;
894
895 if (vrs->bytesinval == 0) {
896 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, &reg))
897 return (ENXIO);
898 vrs->val = le32toh(reg);
899 vrs->off += 4;
900 byte = vrs->val & 0xff;
901 vrs->bytesinval = 3;
902 } else {
903 vrs->val = vrs->val >> 8;
904 byte = vrs->val & 0xff;
905 vrs->bytesinval--;
906 }
907
908 vrs->cksum += byte;
909 *data = byte;
910 return (0);
911}
912
d85e7311
SZ
913int
914pcie_slot_implemented(device_t dev)
915{
916 struct pci_devinfo *dinfo = device_get_ivars(dev);
917
918 return pcie_slotimpl(&dinfo->cfg);
919}
920
4d28e78f
SZ
921void
922pcie_set_max_readrq(device_t dev, uint16_t rqsize)
923{
d85e7311
SZ
924 uint8_t expr_ptr;
925 uint16_t val;
926
927 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK;
928 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) {
929 panic("%s: invalid max read request size 0x%02x\n",
930 device_get_nameunit(dev), rqsize);
931 }
932
933 expr_ptr = pci_get_pciecap_ptr(dev);
934 if (!expr_ptr)
935 panic("%s: not PCIe device\n", device_get_nameunit(dev));
936
937 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
938 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) {
939 if (bootverbose)
940 device_printf(dev, "adjust device control 0x%04x", val);
941
942 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
943 val |= rqsize;
944 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
945
946 if (bootverbose)
947 kprintf(" -> 0x%04x\n", val);
948 }
4d28e78f
SZ
949}
950
951static void
952pci_read_vpd(device_t pcib, pcicfgregs *cfg)
953{
954 struct vpd_readstate vrs;
955 int state;
956 int name;
957 int remain;
958 int i;
959 int alloc, off; /* alloc/off for RO/W arrays */
960 int cksumvalid;
961 int dflen;
962 uint8_t byte;
963 uint8_t byte2;
964
965 /* init vpd reader */
966 vrs.bytesinval = 0;
967 vrs.off = 0;
968 vrs.pcib = pcib;
969 vrs.cfg = cfg;
970 vrs.cksum = 0;
971
972 state = 0;
973 name = remain = i = 0; /* shut up stupid gcc */
974 alloc = off = 0; /* shut up stupid gcc */
975 dflen = 0; /* shut up stupid gcc */
976 cksumvalid = -1;
977 while (state >= 0) {
978 if (vpd_nextbyte(&vrs, &byte)) {
979 state = -2;
980 break;
981 }
982#if 0
983 kprintf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
984 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
985 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
986#endif
987 switch (state) {
988 case 0: /* item name */
989 if (byte & 0x80) {
990 if (vpd_nextbyte(&vrs, &byte2)) {
991 state = -2;
992 break;
993 }
994 remain = byte2;
995 if (vpd_nextbyte(&vrs, &byte2)) {
996 state = -2;
997 break;
998 }
999 remain |= byte2 << 8;
1000 if (remain > (0x7f*4 - vrs.off)) {
1001 state = -1;
1002 kprintf(
1003 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
1004 cfg->domain, cfg->bus, cfg->slot,
1005 cfg->func, remain);
1006 }
1007 name = byte & 0x7f;
1008 } else {
1009 remain = byte & 0x7;
1010 name = (byte >> 3) & 0xf;
1011 }
1012 switch (name) {
1013 case 0x2: /* String */
1014 cfg->vpd.vpd_ident = kmalloc(remain + 1,
1015 M_DEVBUF, M_WAITOK);
1016 i = 0;
1017 state = 1;
1018 break;
1019 case 0xf: /* End */
1020 state = -1;
1021 break;
1022 case 0x10: /* VPD-R */
1023 alloc = 8;
1024 off = 0;
1025 cfg->vpd.vpd_ros = kmalloc(alloc *
1026 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
1027 M_WAITOK | M_ZERO);
1028 state = 2;
1029 break;
1030 case 0x11: /* VPD-W */
1031 alloc = 8;
1032 off = 0;
1033 cfg->vpd.vpd_w = kmalloc(alloc *
1034 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
1035 M_WAITOK | M_ZERO);
1036 state = 5;
1037 break;
1038 default: /* Invalid data, abort */
1039 state = -1;
1040 break;
1041 }
1042 break;
1043
1044 case 1: /* Identifier String */
1045 cfg->vpd.vpd_ident[i++] = byte;
1046 remain--;
1047 if (remain == 0) {
1048 cfg->vpd.vpd_ident[i] = '\0';
1049 state = 0;
1050 }
1051 break;
1052
1053 case 2: /* VPD-R Keyword Header */
1054 if (off == alloc) {
a68a7edf 1055 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
4d28e78f
SZ
1056 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
1057 M_DEVBUF, M_WAITOK | M_ZERO);
1058 }
1059 cfg->vpd.vpd_ros[off].keyword[0] = byte;
1060 if (vpd_nextbyte(&vrs, &byte2)) {
1061 state = -2;
1062 break;
1063 }
1064 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
1065 if (vpd_nextbyte(&vrs, &byte2)) {
1066 state = -2;
1067 break;
1068 }
1069 dflen = byte2;
1070 if (dflen == 0 &&
1071 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1072 2) == 0) {
1073 /*
1074 * if this happens, we can't trust the rest
1075 * of the VPD.
1076 */
1077 kprintf(
1078 "pci%d:%d:%d:%d: bad keyword length: %d\n",
1079 cfg->domain, cfg->bus, cfg->slot,
1080 cfg->func, dflen);
1081 cksumvalid = 0;
1082 state = -1;
1083 break;
1084 } else if (dflen == 0) {
1085 cfg->vpd.vpd_ros[off].value = kmalloc(1 *
1086 sizeof(*cfg->vpd.vpd_ros[off].value),
1087 M_DEVBUF, M_WAITOK);
1088 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1089 } else
1090 cfg->vpd.vpd_ros[off].value = kmalloc(
1091 (dflen + 1) *
1092 sizeof(*cfg->vpd.vpd_ros[off].value),
1093 M_DEVBUF, M_WAITOK);
1094 remain -= 3;
1095 i = 0;
1096 /* keep in sync w/ state 3's transistions */
1097 if (dflen == 0 && remain == 0)
1098 state = 0;
1099 else if (dflen == 0)
1100 state = 2;
1101 else
1102 state = 3;
1103 break;
1104
1105 case 3: /* VPD-R Keyword Value */
1106 cfg->vpd.vpd_ros[off].value[i++] = byte;
1107 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1108 "RV", 2) == 0 && cksumvalid == -1) {
1109 if (vrs.cksum == 0)
1110 cksumvalid = 1;
1111 else {
1112 if (bootverbose)
1113 kprintf(
1114 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
1115 cfg->domain, cfg->bus,
1116 cfg->slot, cfg->func,
1117 vrs.cksum);
1118 cksumvalid = 0;
1119 state = -1;
1120 break;
1121 }
1122 }
1123 dflen--;
1124 remain--;
1125 /* keep in sync w/ state 2's transistions */
1126 if (dflen == 0)
1127 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1128 if (dflen == 0 && remain == 0) {
1129 cfg->vpd.vpd_rocnt = off;
a68a7edf 1130 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
4d28e78f
SZ
1131 off * sizeof(*cfg->vpd.vpd_ros),
1132 M_DEVBUF, M_WAITOK | M_ZERO);
1133 state = 0;
1134 } else if (dflen == 0)
1135 state = 2;
1136 break;
1137
1138 case 4:
1139 remain--;
1140 if (remain == 0)
1141 state = 0;
1142 break;
1143
1144 case 5: /* VPD-W Keyword Header */
1145 if (off == alloc) {
a68a7edf 1146 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
4d28e78f
SZ
1147 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1148 M_DEVBUF, M_WAITOK | M_ZERO);
1149 }
1150 cfg->vpd.vpd_w[off].keyword[0] = byte;
1151 if (vpd_nextbyte(&vrs, &byte2)) {
1152 state = -2;
1153 break;
1154 }
1155 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1156 if (vpd_nextbyte(&vrs, &byte2)) {
1157 state = -2;
1158 break;
1159 }
1160 cfg->vpd.vpd_w[off].len = dflen = byte2;
1161 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1162 cfg->vpd.vpd_w[off].value = kmalloc((dflen + 1) *
1163 sizeof(*cfg->vpd.vpd_w[off].value),
1164 M_DEVBUF, M_WAITOK);
1165 remain -= 3;
1166 i = 0;
1167 /* keep in sync w/ state 6's transistions */
1168 if (dflen == 0 && remain == 0)
1169 state = 0;
1170 else if (dflen == 0)
1171 state = 5;
1172 else
1173 state = 6;
1174 break;
1175
1176 case 6: /* VPD-W Keyword Value */
1177 cfg->vpd.vpd_w[off].value[i++] = byte;
1178 dflen--;
1179 remain--;
1180 /* keep in sync w/ state 5's transistions */
1181 if (dflen == 0)
1182 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1183 if (dflen == 0 && remain == 0) {
1184 cfg->vpd.vpd_wcnt = off;
a68a7edf 1185 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
4d28e78f
SZ
1186 off * sizeof(*cfg->vpd.vpd_w),
1187 M_DEVBUF, M_WAITOK | M_ZERO);
1188 state = 0;
1189 } else if (dflen == 0)
1190 state = 5;
1191 break;
1192
1193 default:
1194 kprintf("pci%d:%d:%d:%d: invalid state: %d\n",
1195 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1196 state);
1197 state = -1;
1198 break;
1199 }
1200 }
1201
1202 if (cksumvalid == 0 || state < -1) {
1203 /* read-only data bad, clean up */
1204 if (cfg->vpd.vpd_ros != NULL) {
1205 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1206 kfree(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1207 kfree(cfg->vpd.vpd_ros, M_DEVBUF);
1208 cfg->vpd.vpd_ros = NULL;
1209 }
1210 }
1211 if (state < -1) {
1212 /* I/O error, clean up */
1213 kprintf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1214 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1215 if (cfg->vpd.vpd_ident != NULL) {
1216 kfree(cfg->vpd.vpd_ident, M_DEVBUF);
1217 cfg->vpd.vpd_ident = NULL;
1218 }
1219 if (cfg->vpd.vpd_w != NULL) {
1220 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1221 kfree(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1222 kfree(cfg->vpd.vpd_w, M_DEVBUF);
1223 cfg->vpd.vpd_w = NULL;
1224 }
1225 }
1226 cfg->vpd.vpd_cached = 1;
1227#undef REG
1228#undef WREG
1229}
1230
1231int
1232pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1233{
1234 struct pci_devinfo *dinfo = device_get_ivars(child);
1235 pcicfgregs *cfg = &dinfo->cfg;
1236
1237 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1238 pci_read_vpd(device_get_parent(dev), cfg);
1239
1240 *identptr = cfg->vpd.vpd_ident;
1241
1242 if (*identptr == NULL)
1243 return (ENXIO);
1244
1245 return (0);
1246}
1247
1248int
1249pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1250 const char **vptr)
1251{
1252 struct pci_devinfo *dinfo = device_get_ivars(child);
1253 pcicfgregs *cfg = &dinfo->cfg;
1254 int i;
1255
1256 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1257 pci_read_vpd(device_get_parent(dev), cfg);
1258
1259 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1260 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1261 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1262 *vptr = cfg->vpd.vpd_ros[i].value;
1263 }
1264
1265 if (i != cfg->vpd.vpd_rocnt)
1266 return (0);
1267
1268 *vptr = NULL;
1269 return (ENXIO);
1270}
1271
1272/*
1273 * Return the offset in configuration space of the requested extended
1274 * capability entry or 0 if the specified capability was not found.
1275 */
1276int
1277pci_find_extcap_method(device_t dev, device_t child, int capability,
1278 int *capreg)
1279{
1280 struct pci_devinfo *dinfo = device_get_ivars(child);
1281 pcicfgregs *cfg = &dinfo->cfg;
1282 u_int32_t status;
1283 u_int8_t ptr;
1284
1285 /*
1286 * Check the CAP_LIST bit of the PCI status register first.
1287 */
1288 status = pci_read_config(child, PCIR_STATUS, 2);
1289 if (!(status & PCIM_STATUS_CAPPRESENT))
1290 return (ENXIO);
1291
1292 /*
1293 * Determine the start pointer of the capabilities list.
1294 */
1295 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1296 case 0:
1297 case 1:
1298 ptr = PCIR_CAP_PTR;
1299 break;
1300 case 2:
1301 ptr = PCIR_CAP_PTR_2;
1302 break;
1303 default:
1304 /* XXX: panic? */
1305 return (ENXIO); /* no extended capabilities support */
1306 }
1307 ptr = pci_read_config(child, ptr, 1);
1308
1309 /*
1310 * Traverse the capabilities list.
1311 */
1312 while (ptr != 0) {
1313 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1314 if (capreg != NULL)
1315 *capreg = ptr;
1316 return (0);
1317 }
1318 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1319 }
1320
1321 return (ENOENT);
1322}
1323
1324/*
1325 * Support for MSI-X message interrupts.
1326 */
1327void
1328pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1329{
1330 struct pci_devinfo *dinfo = device_get_ivars(dev);
1331 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1332 uint32_t offset;
1333
1334 KASSERT(msix->msix_table_len > index, ("bogus index"));
1335 offset = msix->msix_table_offset + index * 16;
1336 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1337 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1338 bus_write_4(msix->msix_table_res, offset + 8, data);
1339
1340 /* Enable MSI -> HT mapping. */
1341 pci_ht_map_msi(dev, address);
1342}
1343
1344void
1345pci_mask_msix(device_t dev, u_int index)
1346{
1347 struct pci_devinfo *dinfo = device_get_ivars(dev);
1348 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1349 uint32_t offset, val;
1350
1351 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1352 offset = msix->msix_table_offset + index * 16 + 12;
1353 val = bus_read_4(msix->msix_table_res, offset);
1354 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1355 val |= PCIM_MSIX_VCTRL_MASK;
1356 bus_write_4(msix->msix_table_res, offset, val);
1357 }
1358}
1359
1360void
1361pci_unmask_msix(device_t dev, u_int index)
1362{
1363 struct pci_devinfo *dinfo = device_get_ivars(dev);
1364 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1365 uint32_t offset, val;
1366
1367 KASSERT(msix->msix_table_len > index, ("bogus index"));
1368 offset = msix->msix_table_offset + index * 16 + 12;
1369 val = bus_read_4(msix->msix_table_res, offset);
1370 if (val & PCIM_MSIX_VCTRL_MASK) {
1371 val &= ~PCIM_MSIX_VCTRL_MASK;
1372 bus_write_4(msix->msix_table_res, offset, val);
1373 }
1374}
1375
1376int
1377pci_pending_msix(device_t dev, u_int index)
1378{
1379 struct pci_devinfo *dinfo = device_get_ivars(dev);
1380 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1381 uint32_t offset, bit;
1382
1383 KASSERT(msix->msix_table_len > index, ("bogus index"));
1384 offset = msix->msix_pba_offset + (index / 32) * 4;
1385 bit = 1 << index % 32;
1386 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1387}
1388
1389/*
1390 * Restore MSI-X registers and table during resume. If MSI-X is
1391 * enabled then walk the virtual table to restore the actual MSI-X
1392 * table.
1393 */
1394static void
1395pci_resume_msix(device_t dev)
1396{
1397 struct pci_devinfo *dinfo = device_get_ivars(dev);
1398 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1399 struct msix_table_entry *mte;
1400 struct msix_vector *mv;
1401 int i;
1402
1403 if (msix->msix_alloc > 0) {
1404 /* First, mask all vectors. */
1405 for (i = 0; i < msix->msix_msgnum; i++)
1406 pci_mask_msix(dev, i);
1407
1408 /* Second, program any messages with at least one handler. */
1409 for (i = 0; i < msix->msix_table_len; i++) {
1410 mte = &msix->msix_table[i];
1411 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1412 continue;
1413 mv = &msix->msix_vectors[mte->mte_vector - 1];
1414 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1415 pci_unmask_msix(dev, i);
1416 }
1417 }
1418 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1419 msix->msix_ctrl, 2);
1420}
1421
1422/*
1423 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1424 * returned in *count. After this function returns, each message will be
1425 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1426 */
1427int
1428pci_alloc_msix_method(device_t dev, device_t child, int *count)
1429{
1430 struct pci_devinfo *dinfo = device_get_ivars(child);
1431 pcicfgregs *cfg = &dinfo->cfg;
1432 struct resource_list_entry *rle;
1433 int actual, error, i, irq, max;
1434
1435 /* Don't let count == 0 get us into trouble. */
1436 if (*count == 0)
1437 return (EINVAL);
1438
1439 /* If rid 0 is allocated, then fail. */
1440 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1441 if (rle != NULL && rle->res != NULL)
1442 return (ENXIO);
1443
1444 /* Already have allocated messages? */
1445 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1446 return (ENXIO);
1447
1448 /* If MSI is blacklisted for this system, fail. */
1449 if (pci_msi_blacklisted())
1450 return (ENXIO);
1451
1452 /* MSI-X capability present? */
1453 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1454 return (ENODEV);
1455
1456 /* Make sure the appropriate BARs are mapped. */
1457 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1458 cfg->msix.msix_table_bar);
1459 if (rle == NULL || rle->res == NULL ||
1460 !(rman_get_flags(rle->res) & RF_ACTIVE))
1461 return (ENXIO);
1462 cfg->msix.msix_table_res = rle->res;
1463 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1464 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1465 cfg->msix.msix_pba_bar);
1466 if (rle == NULL || rle->res == NULL ||
1467 !(rman_get_flags(rle->res) & RF_ACTIVE))
1468 return (ENXIO);
1469 }
1470 cfg->msix.msix_pba_res = rle->res;
1471
1472 if (bootverbose)
1473 device_printf(child,
1474 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1475 *count, cfg->msix.msix_msgnum);
1476 max = min(*count, cfg->msix.msix_msgnum);
1477 for (i = 0; i < max; i++) {
1478 /* Allocate a message. */
1479 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1480 if (error)
1481 break;
1482 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1483 irq, 1);
1484 }
1485 actual = i;
1486
14ae4dce
MN
1487 if (actual == 0) {
1488 if (bootverbose) {
1489 device_printf(child,
1490 "could not allocate any MSI-X vectors\n");
1491 }
1492 return (ENXIO);
1493 }
1494
4d28e78f
SZ
1495 if (bootverbose) {
1496 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1497 if (actual == 1)
1498 device_printf(child, "using IRQ %lu for MSI-X\n",
1499 rle->start);
1500 else {
1501 int run;
1502
1503 /*
1504 * Be fancy and try to print contiguous runs of
1505 * IRQ values as ranges. 'irq' is the previous IRQ.
1506 * 'run' is true if we are in a range.
1507 */
1508 device_printf(child, "using IRQs %lu", rle->start);
1509 irq = rle->start;
1510 run = 0;
1511 for (i = 1; i < actual; i++) {
1512 rle = resource_list_find(&dinfo->resources,
1513 SYS_RES_IRQ, i + 1);
1514
1515 /* Still in a run? */
1516 if (rle->start == irq + 1) {
1517 run = 1;
1518 irq++;
1519 continue;
1520 }
1521
1522 /* Finish previous range. */
1523 if (run) {
1524 kprintf("-%d", irq);
1525 run = 0;
1526 }
1527
1528 /* Start new range. */
1529 kprintf(",%lu", rle->start);
1530 irq = rle->start;
1531 }
1532
1533 /* Unfinished range? */
1534 if (run)
1535 kprintf("-%d", irq);
1536 kprintf(" for MSI-X\n");
1537 }
1538 }
1539
1540 /* Mask all vectors. */
1541 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1542 pci_mask_msix(child, i);
1543
1544 /* Allocate and initialize vector data and virtual table. */
1545 cfg->msix.msix_vectors = kmalloc(sizeof(struct msix_vector) * actual,
1546 M_DEVBUF, M_WAITOK | M_ZERO);
1547 cfg->msix.msix_table = kmalloc(sizeof(struct msix_table_entry) * actual,
1548 M_DEVBUF, M_WAITOK | M_ZERO);
1549 for (i = 0; i < actual; i++) {
1550 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1551 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1552 cfg->msix.msix_table[i].mte_vector = i + 1;
1553 }
1554
1555 /* Update control register to enable MSI-X. */
1556 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1557 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1558 cfg->msix.msix_ctrl, 2);
1559
1560 /* Update counts of alloc'd messages. */
1561 cfg->msix.msix_alloc = actual;
1562 cfg->msix.msix_table_len = actual;
1563 *count = actual;
1564 return (0);
1565}
1566
1567/*
1568 * By default, pci_alloc_msix() will assign the allocated IRQ
1569 * resources consecutively to the first N messages in the MSI-X table.
1570 * However, device drivers may want to use different layouts if they
1571 * either receive fewer messages than they asked for, or they wish to
1572 * populate the MSI-X table sparsely. This method allows the driver
1573 * to specify what layout it wants. It must be called after a
1574 * successful pci_alloc_msix() but before any of the associated
1575 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1576 *
1577 * The 'vectors' array contains 'count' message vectors. The array
1578 * maps directly to the MSI-X table in that index 0 in the array
1579 * specifies the vector for the first message in the MSI-X table, etc.
1580 * The vector value in each array index can either be 0 to indicate
1581 * that no vector should be assigned to a message slot, or it can be a
1582 * number from 1 to N (where N is the count returned from a
1583 * succcessful call to pci_alloc_msix()) to indicate which message
1584 * vector (IRQ) to be used for the corresponding message.
1585 *
1586 * On successful return, each message with a non-zero vector will have
1587 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1588 * 1. Additionally, if any of the IRQs allocated via the previous
1589 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1590 * will be kfreed back to the system automatically.
1591 *
1592 * For example, suppose a driver has a MSI-X table with 6 messages and
1593 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1594 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1595 * C. After the call to pci_alloc_msix(), the device will be setup to
1596 * have an MSI-X table of ABC--- (where - means no vector assigned).
1597 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 },
1598 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1599 * be kfreed back to the system. This device will also have valid
1600 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1601 *
1602 * In any case, the SYS_RES_IRQ rid X will always map to the message
1603 * at MSI-X table index X - 1 and will only be valid if a vector is
1604 * assigned to that table entry.
1605 */
1606int
1607pci_remap_msix_method(device_t dev, device_t child, int count,
1608 const u_int *vectors)
1609{
1610 struct pci_devinfo *dinfo = device_get_ivars(child);
1611 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1612 struct resource_list_entry *rle;
1613 int i, irq, j, *used;
1614
1615 /*
1616 * Have to have at least one message in the table but the
1617 * table can't be bigger than the actual MSI-X table in the
1618 * device.
1619 */
1620 if (count == 0 || count > msix->msix_msgnum)
1621 return (EINVAL);
1622
1623 /* Sanity check the vectors. */
1624 for (i = 0; i < count; i++)
1625 if (vectors[i] > msix->msix_alloc)
1626 return (EINVAL);
1627
1628 /*
1629 * Make sure there aren't any holes in the vectors to be used.
1630 * It's a big pain to support it, and it doesn't really make
1631 * sense anyway. Also, at least one vector must be used.
1632 */
1633 used = kmalloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1634 M_ZERO);
1635 for (i = 0; i < count; i++)
1636 if (vectors[i] != 0)
1637 used[vectors[i] - 1] = 1;
1638 for (i = 0; i < msix->msix_alloc - 1; i++)
1639 if (used[i] == 0 && used[i + 1] == 1) {
1640 kfree(used, M_DEVBUF);
1641 return (EINVAL);
1642 }
1643 if (used[0] != 1) {
1644 kfree(used, M_DEVBUF);
1645 return (EINVAL);
1646 }
1647
1648 /* Make sure none of the resources are allocated. */
1649 for (i = 0; i < msix->msix_table_len; i++) {
1650 if (msix->msix_table[i].mte_vector == 0)
1651 continue;
1652 if (msix->msix_table[i].mte_handlers > 0)
1653 return (EBUSY);
1654 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1655 KASSERT(rle != NULL, ("missing resource"));
1656 if (rle->res != NULL)
1657 return (EBUSY);
1658 }
1659
1660 /* Free the existing resource list entries. */
1661 for (i = 0; i < msix->msix_table_len; i++) {
1662 if (msix->msix_table[i].mte_vector == 0)
1663 continue;
1664 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1665 }
1666
1667 /*
1668 * Build the new virtual table keeping track of which vectors are
1669 * used.
1670 */
1671 kfree(msix->msix_table, M_DEVBUF);
1672 msix->msix_table = kmalloc(sizeof(struct msix_table_entry) * count,
1673 M_DEVBUF, M_WAITOK | M_ZERO);
1674 for (i = 0; i < count; i++)
1675 msix->msix_table[i].mte_vector = vectors[i];
1676 msix->msix_table_len = count;
1677
1678 /* Free any unused IRQs and resize the vectors array if necessary. */
1679 j = msix->msix_alloc - 1;
1680 if (used[j] == 0) {
1681 struct msix_vector *vec;
1682
1683 while (used[j] == 0) {
1684 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1685 msix->msix_vectors[j].mv_irq);
1686 j--;
1687 }
1688 vec = kmalloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1689 M_WAITOK);
1690 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1691 (j + 1));
1692 kfree(msix->msix_vectors, M_DEVBUF);
1693 msix->msix_vectors = vec;
1694 msix->msix_alloc = j + 1;
1695 }
1696 kfree(used, M_DEVBUF);
1697
1698 /* Map the IRQs onto the rids. */
1699 for (i = 0; i < count; i++) {
1700 if (vectors[i] == 0)
1701 continue;
1702 irq = msix->msix_vectors[vectors[i]].mv_irq;
1703 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1704 irq, 1);
1705 }
1706
1707 if (bootverbose) {
1708 device_printf(child, "Remapped MSI-X IRQs as: ");
1709 for (i = 0; i < count; i++) {
1710 if (i != 0)
1711 kprintf(", ");
1712 if (vectors[i] == 0)
1713 kprintf("---");
1714 else
1715 kprintf("%d",
1716 msix->msix_vectors[vectors[i]].mv_irq);
1717 }
1718 kprintf("\n");
1719 }
1720
1721 return (0);
1722}
1723
1724static int
1725pci_release_msix(device_t dev, device_t child)
1726{
1727 struct pci_devinfo *dinfo = device_get_ivars(child);
1728 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1729 struct resource_list_entry *rle;
1730 int i;
1731
1732 /* Do we have any messages to release? */
1733 if (msix->msix_alloc == 0)
1734 return (ENODEV);
1735
1736 /* Make sure none of the resources are allocated. */
1737 for (i = 0; i < msix->msix_table_len; i++) {
1738 if (msix->msix_table[i].mte_vector == 0)
1739 continue;
1740 if (msix->msix_table[i].mte_handlers > 0)
1741 return (EBUSY);
1742 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1743 KASSERT(rle != NULL, ("missing resource"));
1744 if (rle->res != NULL)
1745 return (EBUSY);
1746 }
1747
1748 /* Update control register to disable MSI-X. */
1749 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1750 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1751 msix->msix_ctrl, 2);
1752
1753 /* Free the resource list entries. */
1754 for (i = 0; i < msix->msix_table_len; i++) {
1755 if (msix->msix_table[i].mte_vector == 0)
1756 continue;
1757 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1758 }
1759 kfree(msix->msix_table, M_DEVBUF);
1760 msix->msix_table_len = 0;
1761
1762 /* Release the IRQs. */
1763 for (i = 0; i < msix->msix_alloc; i++)
1764 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1765 msix->msix_vectors[i].mv_irq);
1766 kfree(msix->msix_vectors, M_DEVBUF);
1767 msix->msix_alloc = 0;
1768 return (0);
1769}
1770
1771/*
1772 * Return the max supported MSI-X messages this device supports.
1773 * Basically, assuming the MD code can alloc messages, this function
1774 * should return the maximum value that pci_alloc_msix() can return.
1775 * Thus, it is subject to the tunables, etc.
1776 */
1777int
1778pci_msix_count_method(device_t dev, device_t child)
1779{
1780 struct pci_devinfo *dinfo = device_get_ivars(child);
1781 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1782
1783 if (pci_do_msix && msix->msix_location != 0)
1784 return (msix->msix_msgnum);
1785 return (0);
1786}
1787
1788/*
1789 * HyperTransport MSI mapping control
1790 */
1791void
1792pci_ht_map_msi(device_t dev, uint64_t addr)
1793{
1794 struct pci_devinfo *dinfo = device_get_ivars(dev);
1795 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1796
1797 if (!ht->ht_msimap)
1798 return;
1799
1800 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1801 ht->ht_msiaddr >> 20 == addr >> 20) {
1802 /* Enable MSI -> HT mapping. */
1803 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1804 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1805 ht->ht_msictrl, 2);
1806 }
1807
1808 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1809 /* Disable MSI -> HT mapping. */
1810 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1811 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1812 ht->ht_msictrl, 2);
1813 }
1814}
1815
1816/*
1817 * Support for MSI message signalled interrupts.
1818 */
1819void
1820pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1821{
1822 struct pci_devinfo *dinfo = device_get_ivars(dev);
1823 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1824
1825 /* Write data and address values. */
1826 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1827 address & 0xffffffff, 4);
1828 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1829 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1830 address >> 32, 4);
1831 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1832 data, 2);
1833 } else
1834 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1835 2);
1836
1837 /* Enable MSI in the control register. */
1838 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1839 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1840 2);
1841
1842 /* Enable MSI -> HT mapping. */
1843 pci_ht_map_msi(dev, address);
1844}
1845
1846void
1847pci_disable_msi(device_t dev)
1848{
1849 struct pci_devinfo *dinfo = device_get_ivars(dev);
1850 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1851
1852 /* Disable MSI -> HT mapping. */
1853 pci_ht_map_msi(dev, 0);
1854
1855 /* Disable MSI in the control register. */
1856 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1857 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1858 2);
1859}
1860
1861/*
1862 * Restore MSI registers during resume. If MSI is enabled then
1863 * restore the data and address registers in addition to the control
1864 * register.
1865 */
1866static void
1867pci_resume_msi(device_t dev)
1868{
1869 struct pci_devinfo *dinfo = device_get_ivars(dev);
1870 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1871 uint64_t address;
1872 uint16_t data;
1873
1874 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1875 address = msi->msi_addr;
1876 data = msi->msi_data;
1877 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1878 address & 0xffffffff, 4);
1879 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1880 pci_write_config(dev, msi->msi_location +
1881 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1882 pci_write_config(dev, msi->msi_location +
1883 PCIR_MSI_DATA_64BIT, data, 2);
1884 } else
1885 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1886 data, 2);
1887 }
1888 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1889 2);
1890}
1891
1892int
1893pci_remap_msi_irq(device_t dev, u_int irq)
1894{
1895 struct pci_devinfo *dinfo = device_get_ivars(dev);
1896 pcicfgregs *cfg = &dinfo->cfg;
1897 struct resource_list_entry *rle;
1898 struct msix_table_entry *mte;
1899 struct msix_vector *mv;
1900 device_t bus;
1901 uint64_t addr;
1902 uint32_t data;
1903 int error, i, j;
1904
1905 bus = device_get_parent(dev);
1906
1907 /*
1908 * Handle MSI first. We try to find this IRQ among our list
1909 * of MSI IRQs. If we find it, we request updated address and
1910 * data registers and apply the results.
1911 */
1912 if (cfg->msi.msi_alloc > 0) {
1913
1914 /* If we don't have any active handlers, nothing to do. */
1915 if (cfg->msi.msi_handlers == 0)
1916 return (0);
1917 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1918 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1919 i + 1);
1920 if (rle->start == irq) {
1921 error = PCIB_MAP_MSI(device_get_parent(bus),
1922 dev, irq, &addr, &data);
1923 if (error)
1924 return (error);
1925 pci_disable_msi(dev);
1926 dinfo->cfg.msi.msi_addr = addr;
1927 dinfo->cfg.msi.msi_data = data;
1928 pci_enable_msi(dev, addr, data);
1929 return (0);
1930 }
1931 }
1932 return (ENOENT);
1933 }
1934
1935 /*
1936 * For MSI-X, we check to see if we have this IRQ. If we do,
1937 * we request the updated mapping info. If that works, we go
1938 * through all the slots that use this IRQ and update them.
1939 */
1940 if (cfg->msix.msix_alloc > 0) {
1941 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1942 mv = &cfg->msix.msix_vectors[i];
1943 if (mv->mv_irq == irq) {
1944 error = PCIB_MAP_MSI(device_get_parent(bus),
1945 dev, irq, &addr, &data);
1946 if (error)
1947 return (error);
1948 mv->mv_address = addr;
1949 mv->mv_data = data;
1950 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1951 mte = &cfg->msix.msix_table[j];
1952 if (mte->mte_vector != i + 1)
1953 continue;
1954 if (mte->mte_handlers == 0)
1955 continue;
1956 pci_mask_msix(dev, j);
1957 pci_enable_msix(dev, j, addr, data);
1958 pci_unmask_msix(dev, j);
1959 }
1960 }
1961 }
1962 return (ENOENT);
1963 }
1964
1965 return (ENOENT);
1966}
1967
1968/*
1969 * Returns true if the specified device is blacklisted because MSI
1970 * doesn't work.
1971 */
1972int
1973pci_msi_device_blacklisted(device_t dev)
1974{
1975 struct pci_quirk *q;
1976
1977 if (!pci_honor_msi_blacklist)
1978 return (0);
1979
1980 for (q = &pci_quirks[0]; q->devid; q++) {
1981 if (q->devid == pci_get_devid(dev) &&
1982 q->type == PCI_QUIRK_DISABLE_MSI)
1983 return (1);
1984 }
1985 return (0);
1986}
1987
1988/*
1989 * Determine if MSI is blacklisted globally on this sytem. Currently,
1990 * we just check for blacklisted chipsets as represented by the
1991 * host-PCI bridge at device 0:0:0. In the future, it may become
1992 * necessary to check other system attributes, such as the kenv values
1993 * that give the motherboard manufacturer and model number.
1994 */
1995static int
1996pci_msi_blacklisted(void)
1997{
1998 device_t dev;
1999
2000 if (!pci_honor_msi_blacklist)
2001 return (0);
2002
2003 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
2004 if (!(pcie_chipset || pcix_chipset))
2005 return (1);
2006
2007 dev = pci_find_bsf(0, 0, 0);
2008 if (dev != NULL)
2009 return (pci_msi_device_blacklisted(dev));
2010 return (0);
2011}
2012
2013/*
2014 * Attempt to allocate *count MSI messages. The actual number allocated is
2015 * returned in *count. After this function returns, each message will be
2016 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
2017 */
2018int
2019pci_alloc_msi_method(device_t dev, device_t child, int *count)
2020{
2021 struct pci_devinfo *dinfo = device_get_ivars(child);
2022 pcicfgregs *cfg = &dinfo->cfg;
2023 struct resource_list_entry *rle;
2024 int actual, error, i, irqs[32];
2025 uint16_t ctrl;
2026
2027 /* Don't let count == 0 get us into trouble. */
2028 if (*count == 0)
2029 return (EINVAL);
2030
2031 /* If rid 0 is allocated, then fail. */
2032 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
2033 if (rle != NULL && rle->res != NULL)
2034 return (ENXIO);
2035
2036 /* Already have allocated messages? */
2037 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
2038 return (ENXIO);
2039
2040 /* If MSI is blacklisted for this system, fail. */
2041 if (pci_msi_blacklisted())
2042 return (ENXIO);
2043
2044 /* MSI capability present? */
2045 if (cfg->msi.msi_location == 0 || !pci_do_msi)
2046 return (ENODEV);
2047
2048 if (bootverbose)
2049 device_printf(child,
2050 "attempting to allocate %d MSI vectors (%d supported)\n",
2051 *count, cfg->msi.msi_msgnum);
2052
2053 /* Don't ask for more than the device supports. */
2054 actual = min(*count, cfg->msi.msi_msgnum);
2055
2056 /* Don't ask for more than 32 messages. */
2057 actual = min(actual, 32);
2058
2059 /* MSI requires power of 2 number of messages. */
2060 if (!powerof2(actual))
2061 return (EINVAL);
2062
2063 for (;;) {
2064 /* Try to allocate N messages. */
2065 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
2066 cfg->msi.msi_msgnum, irqs);
2067 if (error == 0)
2068 break;
2069 if (actual == 1)
2070 return (error);
2071
2072 /* Try N / 2. */
2073 actual >>= 1;
2074 }
2075
2076 /*
2077 * We now have N actual messages mapped onto SYS_RES_IRQ
2078 * resources in the irqs[] array, so add new resources
2079 * starting at rid 1.
2080 */
2081 for (i = 0; i < actual; i++)
2082 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2083 irqs[i], irqs[i], 1);
2084
2085 if (bootverbose) {
2086 if (actual == 1)
2087 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
2088 else {
2089 int run;
2090
2091 /*
2092 * Be fancy and try to print contiguous runs
2093 * of IRQ values as ranges. 'run' is true if
2094 * we are in a range.
2095 */
2096 device_printf(child, "using IRQs %d", irqs[0]);
2097 run = 0;
2098 for (i = 1; i < actual; i++) {
2099
2100 /* Still in a run? */
2101 if (irqs[i] == irqs[i - 1] + 1) {
2102 run = 1;
2103 continue;
2104 }
2105
2106 /* Finish previous range. */
2107 if (run) {
2108 kprintf("-%d", irqs[i - 1]);
2109 run = 0;
2110 }
2111
2112 /* Start new range. */
2113 kprintf(",%d", irqs[i]);
2114 }
2115
2116 /* Unfinished range? */
2117 if (run)
2118 kprintf("-%d", irqs[actual - 1]);
2119 kprintf(" for MSI\n");
2120 }
2121 }
2122
2123 /* Update control register with actual count. */
2124 ctrl = cfg->msi.msi_ctrl;
2125 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2126 ctrl |= (ffs(actual) - 1) << 4;
2127 cfg->msi.msi_ctrl = ctrl;
2128 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2129
2130 /* Update counts of alloc'd messages. */
2131 cfg->msi.msi_alloc = actual;
2132 cfg->msi.msi_handlers = 0;
2133 *count = actual;
2134 return (0);
2135}
2136
2137/* Release the MSI messages associated with this device. */
2138int
2139pci_release_msi_method(device_t dev, device_t child)
2140{
2141 struct pci_devinfo *dinfo = device_get_ivars(child);
2142 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2143 struct resource_list_entry *rle;
2144 int error, i, irqs[32];
2145
2146 /* Try MSI-X first. */
2147 error = pci_release_msix(dev, child);
2148 if (error != ENODEV)
2149 return (error);
2150
2151 /* Do we have any messages to release? */
2152 if (msi->msi_alloc == 0)
2153 return (ENODEV);
2154 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2155
2156 /* Make sure none of the resources are allocated. */
2157 if (msi->msi_handlers > 0)
2158 return (EBUSY);
2159 for (i = 0; i < msi->msi_alloc; i++) {
2160 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2161 KASSERT(rle != NULL, ("missing MSI resource"));
2162 if (rle->res != NULL)
2163 return (EBUSY);
2164 irqs[i] = rle->start;
2165 }
2166
2167 /* Update control register with 0 count. */
2168 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2169 ("%s: MSI still enabled", __func__));
2170 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2171 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2172 msi->msi_ctrl, 2);
2173
2174 /* Release the messages. */
2175 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2176 for (i = 0; i < msi->msi_alloc; i++)
2177 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2178
2179 /* Update alloc count. */
2180 msi->msi_alloc = 0;
2181 msi->msi_addr = 0;
2182 msi->msi_data = 0;
2183 return (0);
2184}
2185
2186/*
2187 * Return the max supported MSI messages this device supports.
2188 * Basically, assuming the MD code can alloc messages, this function
2189 * should return the maximum value that pci_alloc_msi() can return.
2190 * Thus, it is subject to the tunables, etc.
2191 */
2192int
2193pci_msi_count_method(device_t dev, device_t child)
2194{
2195 struct pci_devinfo *dinfo = device_get_ivars(child);
2196 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2197
2198 if (pci_do_msi && msi->msi_location != 0)
2199 return (msi->msi_msgnum);
2200 return (0);
2201}
2202
2203/* kfree pcicfgregs structure and all depending data structures */
2204
2205int
2206pci_freecfg(struct pci_devinfo *dinfo)
2207{
2208 struct devlist *devlist_head;
2209 int i;
2210
2211 devlist_head = &pci_devq;
2212
2213 if (dinfo->cfg.vpd.vpd_reg) {
2214 kfree(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2215 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2216 kfree(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2217 kfree(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2218 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2219 kfree(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2220 kfree(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2221 }
2222 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2223 kfree(dinfo, M_DEVBUF);
2224
2225 /* increment the generation count */
2226 pci_generation++;
2227
2228 /* we're losing one device */
2229 pci_numdevs--;
2230 return (0);
2231}
2232
2233/*
2234 * PCI power manangement
2235 */
2236int
2237pci_set_powerstate_method(device_t dev, device_t child, int state)
2238{
2239 struct pci_devinfo *dinfo = device_get_ivars(child);
2240 pcicfgregs *cfg = &dinfo->cfg;
f4754a59
HT
2241 uint16_t status;
2242 int result, oldstate, highest, delay;
984263bc 2243
4d28e78f 2244 if (cfg->pp.pp_cap == 0)
f4754a59
HT
2245 return (EOPNOTSUPP);
2246
2247 /*
2248 * Optimize a no state change request away. While it would be OK to
2249 * write to the hardware in theory, some devices have shown odd
2250 * behavior when going from D3 -> D3.
2251 */
2252 oldstate = pci_get_powerstate(child);
2253 if (oldstate == state)
2254 return (0);
2255
2256 /*
2257 * The PCI power management specification states that after a state
2258 * transition between PCI power states, system software must
2259 * guarantee a minimal delay before the function accesses the device.
2260 * Compute the worst case delay that we need to guarantee before we
2261 * access the device. Many devices will be responsive much more
2262 * quickly than this delay, but there are some that don't respond
2263 * instantly to state changes. Transitions to/from D3 state require
2264 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2265 * is done below with DELAY rather than a sleeper function because
2266 * this function can be called from contexts where we cannot sleep.
2267 */
2268 highest = (oldstate > state) ? oldstate : state;
2269 if (highest == PCI_POWERSTATE_D3)
2270 delay = 10000;
2271 else if (highest == PCI_POWERSTATE_D2)
2272 delay = 200;
2273 else
2274 delay = 0;
4d28e78f 2275 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
f4754a59
HT
2276 & ~PCIM_PSTAT_DMASK;
2277 result = 0;
2278 switch (state) {
2279 case PCI_POWERSTATE_D0:
2280 status |= PCIM_PSTAT_D0;
2281 break;
2282 case PCI_POWERSTATE_D1:
4d28e78f 2283 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
f4754a59
HT
2284 return (EOPNOTSUPP);
2285 status |= PCIM_PSTAT_D1;
2286 break;
2287 case PCI_POWERSTATE_D2:
4d28e78f 2288 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
f4754a59
HT
2289 return (EOPNOTSUPP);
2290 status |= PCIM_PSTAT_D2;
2291 break;
2292 case PCI_POWERSTATE_D3:
2293 status |= PCIM_PSTAT_D3;
2294 break;
2295 default:
2296 return (EINVAL);
984263bc 2297 }
f4754a59
HT
2298
2299 if (bootverbose)
2300 kprintf(
4d28e78f
SZ
2301 "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
2302 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2303 dinfo->cfg.func, oldstate, state);
f4754a59 2304
4d28e78f 2305 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
f4754a59
HT
2306 if (delay)
2307 DELAY(delay);
2308 return (0);
984263bc
MD
2309}
2310
e126caf1 2311int
984263bc
MD
2312pci_get_powerstate_method(device_t dev, device_t child)
2313{
2314 struct pci_devinfo *dinfo = device_get_ivars(child);
2315 pcicfgregs *cfg = &dinfo->cfg;
f4754a59 2316 uint16_t status;
984263bc
MD
2317 int result;
2318
4d28e78f
SZ
2319 if (cfg->pp.pp_cap != 0) {
2320 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
984263bc
MD
2321 switch (status & PCIM_PSTAT_DMASK) {
2322 case PCIM_PSTAT_D0:
2323 result = PCI_POWERSTATE_D0;
2324 break;
2325 case PCIM_PSTAT_D1:
2326 result = PCI_POWERSTATE_D1;
2327 break;
2328 case PCIM_PSTAT_D2:
2329 result = PCI_POWERSTATE_D2;
2330 break;
2331 case PCIM_PSTAT_D3:
2332 result = PCI_POWERSTATE_D3;
2333 break;
2334 default:
2335 result = PCI_POWERSTATE_UNKNOWN;
2336 break;
2337 }
2338 } else {
2339 /* No support, device is always at D0 */
2340 result = PCI_POWERSTATE_D0;
2341 }
f4754a59 2342 return (result);
984263bc
MD
2343}
2344
2345/*
2346 * Some convenience functions for PCI device drivers.
2347 */
2348
2349static __inline void
4d28e78f 2350pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
984263bc 2351{
4d28e78f 2352 uint16_t command;
984263bc 2353
4d28e78f
SZ
2354 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2355 command |= bit;
2356 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
984263bc
MD
2357}
2358
2359static __inline void
4d28e78f
SZ
2360pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2361{
2362 uint16_t command;
984263bc 2363
4d28e78f
SZ
2364 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2365 command &= ~bit;
2366 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
984263bc
MD
2367}
2368
4d28e78f
SZ
2369int
2370pci_enable_busmaster_method(device_t dev, device_t child)
2371{
2372 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2373 return (0);
2374}
984263bc 2375
4d28e78f
SZ
2376int
2377pci_disable_busmaster_method(device_t dev, device_t child)
2378{
2379 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2380 return (0);
2381}
984263bc 2382
4d28e78f
SZ
2383int
2384pci_enable_io_method(device_t dev, device_t child, int space)
ed1bd994 2385{
4d28e78f
SZ
2386 uint16_t command;
2387 uint16_t bit;
2388 char *error;
ed1bd994 2389
4d28e78f
SZ
2390 bit = 0;
2391 error = NULL;
2392
2393 switch(space) {
2394 case SYS_RES_IOPORT:
2395 bit = PCIM_CMD_PORTEN;
2396 error = "port";
ed1bd994 2397 break;
4d28e78f
SZ
2398 case SYS_RES_MEMORY:
2399 bit = PCIM_CMD_MEMEN;
2400 error = "memory";
ed1bd994
MD
2401 break;
2402 default:
4d28e78f 2403 return (EINVAL);
ed1bd994 2404 }
4d28e78f
SZ
2405 pci_set_command_bit(dev, child, bit);
2406 /* Some devices seem to need a brief stall here, what do to? */
2407 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2408 if (command & bit)
2409 return (0);
2410 device_printf(child, "failed to enable %s mapping!\n", error);
2411 return (ENXIO);
ed1bd994 2412}
984263bc 2413
4d28e78f
SZ
2414int
2415pci_disable_io_method(device_t dev, device_t child, int space)
b4c0a845 2416{
4d28e78f
SZ
2417 uint16_t command;
2418 uint16_t bit;
2419 char *error;
b4c0a845 2420
4d28e78f
SZ
2421 bit = 0;
2422 error = NULL;
b4c0a845 2423
4d28e78f
SZ
2424 switch(space) {
2425 case SYS_RES_IOPORT:
2426 bit = PCIM_CMD_PORTEN;
2427 error = "port";
b4c0a845 2428 break;
4d28e78f
SZ
2429 case SYS_RES_MEMORY:
2430 bit = PCIM_CMD_MEMEN;
2431 error = "memory";
b4c0a845
SZ
2432 break;
2433 default:
4d28e78f 2434 return (EINVAL);
b4c0a845 2435 }
4d28e78f
SZ
2436 pci_clear_command_bit(dev, child, bit);
2437 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2438 if (command & bit) {
2439 device_printf(child, "failed to disable %s mapping!\n", error);
2440 return (ENXIO);
b4c0a845 2441 }
4d28e78f 2442 return (0);
b4c0a845
SZ
2443}
2444
4d28e78f
SZ
2445/*
2446 * New style pci driver. Parent device is either a pci-host-bridge or a
2447 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2448 */
2449
22457186 2450void
984263bc
MD
2451pci_print_verbose(struct pci_devinfo *dinfo)
2452{
4d28e78f 2453
984263bc
MD
2454 if (bootverbose) {
2455 pcicfgregs *cfg = &dinfo->cfg;
2456
4d28e78f
SZ
2457 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2458 cfg->vendor, cfg->device, cfg->revid);
2459 kprintf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2460 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2461 kprintf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2462 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2463 cfg->mfdev);
2464 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2465 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
85f8e2ea 2466 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
4d28e78f
SZ
2467 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2468 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
984263bc 2469 if (cfg->intpin > 0)
4d28e78f
SZ
2470 kprintf("\tintpin=%c, irq=%d\n",
2471 cfg->intpin +'a' -1, cfg->intline);
2472 if (cfg->pp.pp_cap) {
2473 uint16_t status;
2474
2475 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2476 kprintf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2477 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2478 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2479 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2480 status & PCIM_PSTAT_DMASK);
2481 }
2482 if (cfg->msi.msi_location) {
2483 int ctrl;
2484
2485 ctrl = cfg->msi.msi_ctrl;
2486 kprintf("\tMSI supports %d message%s%s%s\n",
2487 cfg->msi.msi_msgnum,
2488 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2489 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2490 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2491 }
2492 if (cfg->msix.msix_location) {
2493 kprintf("\tMSI-X supports %d message%s ",
2494 cfg->msix.msix_msgnum,
2495 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2496 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2497 kprintf("in map 0x%x\n",
2498 cfg->msix.msix_table_bar);
2499 else
2500 kprintf("in maps 0x%x and 0x%x\n",
2501 cfg->msix.msix_table_bar,
2502 cfg->msix.msix_pba_bar);
2503 }
d85e7311 2504 pci_print_verbose_expr(cfg);
984263bc
MD
2505 }
2506}
2507
d85e7311
SZ
2508static void
2509pci_print_verbose_expr(const pcicfgregs *cfg)
2510{
2511 const struct pcicfg_expr *expr = &cfg->expr;
2512 const char *port_name;
2513 uint16_t port_type;
2514
2515 if (!bootverbose)
2516 return;
2517
2518 if (expr->expr_ptr == 0) /* No PCI Express capability */
2519 return;
2520
2521 kprintf("\tPCI Express ver.%d cap=0x%04x",
2522 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
2523 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
2524 goto back;
2525
2526 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
2527
2528 switch (port_type) {
2529 case PCIE_END_POINT:
2530 port_name = "DEVICE";
2531 break;
2532 case PCIE_LEG_END_POINT:
2533 port_name = "LEGDEV";
2534 break;
2535 case PCIE_ROOT_PORT:
2536 port_name = "ROOT";
2537 break;
2538 case PCIE_UP_STREAM_PORT:
2539 port_name = "UPSTREAM";
2540 break;
2541 case PCIE_DOWN_STREAM_PORT:
2542 port_name = "DOWNSTRM";
2543 break;
2544 case PCIE_PCIE2PCI_BRIDGE:
2545 port_name = "PCIE2PCI";
2546 break;
2547 case PCIE_PCI2PCIE_BRIDGE:
2548 port_name = "PCI2PCIE";
2549 break;
2550 default:
2551 port_name = NULL;
2552 break;
2553 }
2554 if ((port_type == PCIE_ROOT_PORT ||
2555 port_type == PCIE_DOWN_STREAM_PORT) &&
2556 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
2557 port_name = NULL;
2558 if (port_name != NULL)
2559 kprintf("[%s]", port_name);
2560
2561 if (pcie_slotimpl(cfg)) {
2562 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
2563 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
2564 kprintf("[HOTPLUG]");
2565 }
2566back:
2567 kprintf("\n");
2568}
2569
984263bc 2570static int
4a5a2d63 2571pci_porten(device_t pcib, int b, int s, int f)
984263bc 2572{
4a5a2d63
JS
2573 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2574 & PCIM_CMD_PORTEN) != 0;
984263bc
MD
2575}
2576
2577static int
4a5a2d63 2578pci_memen(device_t pcib, int b, int s, int f)
984263bc 2579{
4a5a2d63
JS
2580 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2581 & PCIM_CMD_MEMEN) != 0;
984263bc
MD
2582}
2583
2584/*
2585 * Add a resource based on a pci map register. Return 1 if the map
2586 * register is a 32bit map register or 2 if it is a 64bit register.
2587 */
2588static int
4d28e78f
SZ
2589pci_add_map(device_t pcib, device_t bus, device_t dev,
2590 int b, int s, int f, int reg, struct resource_list *rl, int force,
2591 int prefetch)
2592{
2593 uint32_t map;
2594 pci_addr_t base;
2595 pci_addr_t start, end, count;
2596 uint8_t ln2size;
2597 uint8_t ln2range;
2598 uint32_t testval;
2599 uint16_t cmd;
984263bc 2600 int type;
4d28e78f
SZ
2601 int barlen;
2602 struct resource *res;
984263bc 2603
4a5a2d63 2604 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
4a5a2d63
JS
2605 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
2606 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2607 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
984263bc 2608
4d28e78f 2609 if (PCI_BAR_MEM(map)) {
984263bc 2610 type = SYS_RES_MEMORY;
4d28e78f
SZ
2611 if (map & PCIM_BAR_MEM_PREFETCH)
2612 prefetch = 1;
2613 } else
984263bc
MD
2614 type = SYS_RES_IOPORT;
2615 ln2size = pci_mapsize(testval);
2616 ln2range = pci_maprange(testval);
4d28e78f
SZ
2617 base = pci_mapbase(map);
2618 barlen = ln2range == 64 ? 2 : 1;
2619
2620 /*
2621 * For I/O registers, if bottom bit is set, and the next bit up
2622 * isn't clear, we know we have a BAR that doesn't conform to the
2623 * spec, so ignore it. Also, sanity check the size of the data
2624 * areas to the type of memory involved. Memory must be at least
2625 * 16 bytes in size, while I/O ranges must be at least 4.
2626 */
2627 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2628 return (barlen);
2629 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
2630 (type == SYS_RES_IOPORT && ln2size < 2))
2631 return (barlen);
2632
2633 if (ln2range == 64)
984263bc 2634 /* Read the other half of a 64bit map register */
4d28e78f
SZ
2635 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
2636 if (bootverbose) {
2637 kprintf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2638 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
2639 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2640 kprintf(", port disabled\n");
2641 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2642 kprintf(", memory disabled\n");
2643 else
2644 kprintf(", enabled\n");
984263bc
MD
2645 }
2646
984263bc 2647 /*
4d28e78f
SZ
2648 * If base is 0, then we have problems. It is best to ignore
2649 * such entries for the moment. These will be allocated later if
2650 * the driver specifically requests them. However, some
2651 * removable busses look better when all resources are allocated,
2652 * so allow '0' to be overriden.
2653 *
2654 * Similarly treat maps whose values is the same as the test value
2655 * read back. These maps have had all f's written to them by the
2656 * BIOS in an attempt to disable the resources.
984263bc 2657 */
4d28e78f
SZ
2658 if (!force && (base == 0 || map == testval))
2659 return (barlen);
2660 if ((u_long)base != base) {
2661 device_printf(bus,
2662 "pci%d:%d:%d:%d bar %#x too many address bits",
2663 pci_get_domain(dev), b, s, f, reg);
2664 return (barlen);
984263bc 2665 }
984263bc 2666
4d28e78f
SZ
2667 /*
2668 * This code theoretically does the right thing, but has
2669 * undesirable side effects in some cases where peripherals
2670 * respond oddly to having these bits enabled. Let the user
2671 * be able to turn them off (since pci_enable_io_modes is 1 by
2672 * default).
2673 */
2674 if (pci_enable_io_modes) {
2675 /* Turn on resources that have been left off by a lazy BIOS */
2676 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
2677 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2678 cmd |= PCIM_CMD_PORTEN;
2679 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2680 }
2681 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
2682 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2683 cmd |= PCIM_CMD_MEMEN;
2684 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2685 }
2686 } else {
2687 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2688 return (barlen);
2689 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2690 return (barlen);
2691 }
984263bc 2692
4d28e78f
SZ
2693 count = 1 << ln2size;
2694 if (base == 0 || base == pci_mapbase(testval)) {
2695 start = 0; /* Let the parent decide. */
2696 end = ~0ULL;
2697 } else {
2698 start = base;
2699 end = base + (1 << ln2size) - 1;
984263bc 2700 }
4d28e78f 2701 resource_list_add(rl, type, reg, start, end, count);
984263bc 2702
4d28e78f
SZ
2703 /*
2704 * Try to allocate the resource for this BAR from our parent
2705 * so that this resource range is already reserved. The
2706 * driver for this device will later inherit this resource in
2707 * pci_alloc_resource().
2708 */
2709 res = resource_list_alloc(rl, bus, dev, type, &reg, start, end, count,
2710 prefetch ? RF_PREFETCHABLE : 0);
2711 if (res == NULL) {
2712 /*
d0c4beb1
SZ
2713 * If the allocation fails, delete the resource list
2714 * entry to force pci_alloc_resource() to allocate
2715 * resources from the parent.
4d28e78f
SZ
2716 */
2717 resource_list_delete(rl, type, reg);
d0c4beb1
SZ
2718#ifdef PCI_BAR_CLEAR
2719 /* Clear the BAR */
4d28e78f 2720 start = 0;
d0c4beb1
SZ
2721#else /* !PCI_BAR_CLEAR */
2722 /*
2723 * Don't clear BAR here. Some BIOS lists HPET as a
2724 * PCI function, clearing the BAR causes HPET timer
2725 * stop ticking.
2726 */
2727 if (bootverbose) {
2728 kprintf("pci:%d:%d:%d: resource reservation failed "
bfc09ba0
MD
2729 "%#jx - %#jx\n", b, s, f,
2730 (intmax_t)start, (intmax_t)end);
d0c4beb1
SZ
2731 }
2732 return (barlen);
2733#endif /* PCI_BAR_CLEAR */
2734 } else {
4d28e78f 2735 start = rman_get_start(res);
d0c4beb1 2736 }
4d28e78f
SZ
2737 pci_write_config(dev, reg, start, 4);
2738 if (ln2range == 64)
2739 pci_write_config(dev, reg + 4, start >> 32, 4);
2740 return (barlen);
984263bc
MD
2741}
2742
201eb0a7 2743/*
4d28e78f 2744 * For ATA devices we need to decide early what addressing mode to use.
201eb0a7
TS
2745 * Legacy demands that the primary and secondary ATA ports sits on the
2746 * same addresses that old ISA hardware did. This dictates that we use
4d28e78f 2747 * those addresses and ignore the BAR's if we cannot set PCI native
201eb0a7
TS
2748 * addressing mode.
2749 */
2750static void
4d28e78f
SZ
2751pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
2752 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
201eb0a7
TS
2753{
2754 int rid, type, progif;
2755#if 0
2756 /* if this device supports PCI native addressing use it */
2757 progif = pci_read_config(dev, PCIR_PROGIF, 1);
4d28e78f 2758 if ((progif & 0x8a) == 0x8a) {
201eb0a7
TS
2759 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2760 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
85f8e2ea 2761 kprintf("Trying ATA native PCI addressing mode\n");
201eb0a7
TS
2762 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2763 }
2764 }
2765#endif
201eb0a7
TS
2766 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2767 type = SYS_RES_IOPORT;
2768 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
4d28e78f
SZ
2769 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
2770 prefetchmask & (1 << 0));
2771 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
2772 prefetchmask & (1 << 1));
201eb0a7
TS
2773 } else {
2774 rid = PCIR_BAR(0);
2775 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2776 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
4d28e78f 2777 0);
201eb0a7
TS
2778 rid = PCIR_BAR(1);
2779 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2780 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
4d28e78f 2781 0);
201eb0a7
TS
2782 }
2783 if (progif & PCIP_STORAGE_IDE_MODESEC) {
4d28e78f
SZ
2784 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
2785 prefetchmask & (1 << 2));
2786 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
2787 prefetchmask & (1 << 3));
201eb0a7
TS
2788 } else {
2789 rid = PCIR_BAR(2);
2790 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2791 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
4d28e78f 2792 0);
201eb0a7
TS
2793 rid = PCIR_BAR(3);
2794 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2795 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
4d28e78f 2796 0);
201eb0a7 2797 }
4d28e78f
SZ
2798 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
2799 prefetchmask & (1 << 4));
2800 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
2801 prefetchmask & (1 << 5));
201eb0a7 2802}
201eb0a7 2803
984263bc 2804static void
4d28e78f
SZ
2805pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2806{
2807 struct pci_devinfo *dinfo = device_get_ivars(dev);
2808 pcicfgregs *cfg = &dinfo->cfg;
2809 char tunable_name[64];
2810 int irq;
2811
2812 /* Has to have an intpin to have an interrupt. */
2813 if (cfg->intpin == 0)
2814 return;
2815
2816 /* Let the user override the IRQ with a tunable. */
2817 irq = PCI_INVALID_IRQ;
2818 ksnprintf(tunable_name, sizeof(tunable_name),
2819 "hw.pci%d.%d.%d.INT%c.irq",
2820 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2821 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2822 irq = PCI_INVALID_IRQ;
2823
2824 /*
2825 * If we didn't get an IRQ via the tunable, then we either use the
2826 * IRQ value in the intline register or we ask the bus to route an
2827 * interrupt for us. If force_route is true, then we only use the
2828 * value in the intline register if the bus was unable to assign an
2829 * IRQ.
2830 */
2831 if (!PCI_INTERRUPT_VALID(irq)) {
2832 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2833 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2834 if (!PCI_INTERRUPT_VALID(irq))
2835 irq = cfg->intline;
2836 }
2837
2838 /* If after all that we don't have an IRQ, just bail. */
2839 if (!PCI_INTERRUPT_VALID(irq))
2840 return;
2841
2842 /* Update the config register if it changed. */
2843 if (irq != cfg->intline) {
2844 cfg->intline = irq;
2845 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2846 }
2847
2848 /* Add this IRQ as rid 0 interrupt resource. */
2849 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
2850}
2851
2852void
2853pci_add_resources(device_t pcib, device_t bus, device_t dev, int force, uint32_t prefetchmask)
984263bc
MD
2854{
2855 struct pci_devinfo *dinfo = device_get_ivars(dev);
4a5a2d63 2856 pcicfgregs *cfg = &dinfo->cfg;
984263bc
MD
2857 struct resource_list *rl = &dinfo->resources;
2858 struct pci_quirk *q;
e126caf1 2859 int b, i, f, s;
984263bc 2860
e126caf1
MD
2861 b = cfg->bus;
2862 s = cfg->slot;
2863 f = cfg->func;
4d28e78f
SZ
2864
2865 /* ATA devices needs special map treatment */
201eb0a7
TS
2866 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2867 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
d3d1ea7a
MD
2868 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2869 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2870 !pci_read_config(dev, PCIR_BAR(2), 4))) )
4d28e78f 2871 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
201eb0a7 2872 else
4d28e78f
SZ
2873 for (i = 0; i < cfg->nummaps;)
2874 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
2875 rl, force, prefetchmask & (1 << i));
984263bc 2876
4d28e78f
SZ
2877 /*
2878 * Add additional, quirked resources.
2879 */
984263bc
MD
2880 for (q = &pci_quirks[0]; q->devid; q++) {
2881 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2882 && q->type == PCI_QUIRK_MAP_REG)
4d28e78f
SZ
2883 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
2884 force, 0);
984263bc
MD
2885 }
2886
4d28e78f 2887 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
4d28e78f
SZ
2888 /*
2889 * Try to re-route interrupts. Sometimes the BIOS or
2890 * firmware may leave bogus values in these registers.
2891 * If the re-route fails, then just stick with what we
2892 * have.
2893 */
2894 pci_assign_interrupt(bus, dev, 1);
4d28e78f 2895 }
984263bc
MD
2896}
2897
e126caf1 2898void
4d28e78f 2899pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
984263bc 2900{
4d28e78f 2901#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
4a5a2d63 2902 device_t pcib = device_get_parent(dev);
e126caf1 2903 struct pci_devinfo *dinfo;
4a5a2d63 2904 int maxslots;
e126caf1
MD
2905 int s, f, pcifunchigh;
2906 uint8_t hdrtype;
2907
4d28e78f
SZ
2908 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2909 ("dinfo_size too small"));
4a5a2d63 2910 maxslots = PCIB_MAXSLOTS(pcib);
57e943f7 2911 for (s = 0; s <= maxslots; s++) {
e126caf1
MD
2912 pcifunchigh = 0;
2913 f = 0;
4d28e78f 2914 DELAY(1);
e126caf1
MD
2915 hdrtype = REG(PCIR_HDRTYPE, 1);
2916 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2917 continue;
2918 if (hdrtype & PCIM_MFDEV)
2919 pcifunchigh = PCI_FUNCMAX;
5e658043 2920 for (f = 0; f <= pcifunchigh; f++) {
4d28e78f
SZ
2921 dinfo = pci_read_device(pcib, domain, busno, s, f,
2922 dinfo_size);
984263bc 2923 if (dinfo != NULL) {
e126caf1 2924 pci_add_child(dev, dinfo);
984263bc
MD
2925 }
2926 }
2927 }
e126caf1
MD
2928#undef REG
2929}
2930
2931void
2932pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2933{
2934 device_t pcib;
2935
2936 pcib = device_get_parent(bus);
2937 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2938 device_set_ivars(dinfo->cfg.dev, dinfo);
4d28e78f 2939 resource_list_init(&dinfo->resources);
638744c5
HT
2940 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2941 pci_cfg_restore(dinfo->cfg.dev, dinfo);
e126caf1 2942 pci_print_verbose(dinfo);
4d28e78f 2943 pci_add_resources(pcib, bus, dinfo->cfg.dev, 0, 0);
984263bc
MD
2944}
2945
2946static int
4a5a2d63 2947pci_probe(device_t dev)
984263bc 2948{
984263bc 2949 device_set_desc(dev, "PCI bus");
4a5a2d63 2950
4d28e78f
SZ
2951 /* Allow other subclasses to override this driver. */
2952 return (-1000);
984263bc
MD
2953}
2954
e126caf1
MD
2955static int
2956pci_attach(device_t dev)
2957{
4d28e78f
SZ
2958 int busno, domain;
2959
2960 /*
2961 * Since there can be multiple independantly numbered PCI
2962 * busses on systems with multiple PCI domains, we can't use
2963 * the unit number to decide which bus we are probing. We ask
2964 * the parent pcib what our domain and bus numbers are.
2965 */
2966 domain = pcib_get_domain(dev);
2967 busno = pcib_get_bus(dev);
2968 if (bootverbose)
2969 device_printf(dev, "domain=%d, physical bus=%d\n",
2970 domain, busno);
e4c9c0c8 2971
4d28e78f 2972 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
e126caf1 2973
4d28e78f
SZ
2974 return (bus_generic_attach(dev));
2975}
2976
2977int
2978pci_suspend(device_t dev)
2979{
2980 int dstate, error, i, numdevs;
2981 device_t acpi_dev, child, *devlist;
2982 struct pci_devinfo *dinfo;
2983
2984 /*
2985 * Save the PCI configuration space for each child and set the
2986 * device in the appropriate power state for this sleep state.
2987 */
2988 acpi_dev = NULL;
2989 if (pci_do_power_resume)
2990 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2991 device_get_children(dev, &devlist, &numdevs);
2992 for (i = 0; i < numdevs; i++) {
2993 child = devlist[i];
2994 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2995 pci_cfg_save(child, dinfo, 0);
2996 }
e126caf1 2997
4d28e78f
SZ
2998 /* Suspend devices before potentially powering them down. */
2999 error = bus_generic_suspend(dev);
3000 if (error) {
3001 kfree(devlist, M_TEMP);
3002 return (error);
3003 }
e126caf1 3004
4d28e78f
SZ
3005 /*
3006 * Always set the device to D3. If ACPI suggests a different
3007 * power state, use it instead. If ACPI is not present, the
3008 * firmware is responsible for managing device power. Skip
3009 * children who aren't attached since they are powered down
3010 * separately. Only manage type 0 devices for now.
3011 */
3012 for (i = 0; acpi_dev && i < numdevs; i++) {
3013 child = devlist[i];
3014 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3015 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
3016 dstate = PCI_POWERSTATE_D3;
3017 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
3018 pci_set_powerstate(child, dstate);
3019 }
3020 }
3021 kfree(devlist, M_TEMP);
3022 return (0);
e126caf1
MD
3023}
3024
4d28e78f
SZ
3025int
3026pci_resume(device_t dev)
984263bc 3027{
4d28e78f
SZ
3028 int i, numdevs;
3029 device_t acpi_dev, child, *devlist;
3030 struct pci_devinfo *dinfo;
3031
3032 /*
3033 * Set each child to D0 and restore its PCI configuration space.
3034 */
3035 acpi_dev = NULL;
3036 if (pci_do_power_resume)
3037 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
3038 device_get_children(dev, &devlist, &numdevs);
3039 for (i = 0; i < numdevs; i++) {
3040 /*
3041 * Notify ACPI we're going to D0 but ignore the result. If
3042 * ACPI is not present, the firmware is responsible for
3043 * managing device power. Only manage type 0 devices for now.
3044 */
3045 child = devlist[i];
3046 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3047 if (acpi_dev && device_is_attached(child) &&
3048 dinfo->cfg.hdrtype == 0) {
3049 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
3050 pci_set_powerstate(child, PCI_POWERSTATE_D0);
3051 }
3052
3053 /* Now the device is powered up, restore its config space. */
3054 pci_cfg_restore(child, dinfo);
3055 }
3056 kfree(devlist, M_TEMP);
3057 return (bus_generic_resume(dev));
3058}
3059
3060static void
3061pci_load_vendor_data(void)
3062{
3063 caddr_t vendordata, info;
3064
3065 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
3066 info = preload_search_info(vendordata, MODINFO_ADDR);
3067 pci_vendordata = *(char **)info;
3068 info = preload_search_info(vendordata, MODINFO_SIZE);
3069 pci_vendordata_size = *(size_t *)info;
3070 /* terminate the database */
3071 pci_vendordata[pci_vendordata_size] = '\n';
3072 }
3073}
3074
3075void
3076pci_driver_added(device_t dev, driver_t *driver)
3077{
3078 int numdevs;
3079 device_t *devlist;
3080 device_t child;
3081 struct pci_devinfo *dinfo;
3082 int i;
3083
3084 if (bootverbose)
3085 device_printf(dev, "driver added\n");
3086 DEVICE_IDENTIFY(driver, dev);
3087 device_get_children(dev, &devlist, &numdevs);
3088 for (i = 0; i < numdevs; i++) {
3089 child = devlist[i];
3090 if (device_get_state(child) != DS_NOTPRESENT)
3091 continue;
3092 dinfo = device_get_ivars(child);
3093 pci_print_verbose(dinfo);
3094 if (bootverbose)
3095 kprintf("pci%d:%d:%d:%d: reprobing on driver added\n",
3096 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
3097 dinfo->cfg.func);
3098 pci_cfg_restore(child, dinfo);
3099 if (device_probe_and_attach(child) != 0)
3100 pci_cfg_save(child, dinfo, 1);
3101 }
3102 kfree(devlist, M_TEMP);
3103}
3104
11a49859
SZ
3105static void
3106pci_child_detached(device_t parent __unused, device_t child)
3107{
3108 /* Turn child's power off */
3109 pci_cfg_save(child, device_get_ivars(child), 1);
3110}
3111
4d28e78f
SZ
3112int
3113pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
3114 driver_intr_t *intr, void *arg, void **cookiep, lwkt_serialize_t serializer)
3115{
3116#ifdef MSI
3117 struct pci_devinfo *dinfo;
3118 struct msix_table_entry *mte;
3119 struct msix_vector *mv;
3120 uint64_t addr;
3121 uint32_t data;
35b72619 3122 int rid;
4d28e78f 3123#endif
35b72619 3124 int error;
4d28e78f
SZ
3125 void *cookie;
3126 error = bus_generic_setup_intr(dev, child, irq, flags, intr,
3127 arg, &cookie, serializer);
3128 if (error)
3129 return (error);
3130
3131 /* If this is not a direct child, just bail out. */
3132 if (device_get_parent(child) != dev) {
3133 *cookiep = cookie;
3134 return(0);
3135 }
3136
3137 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3138#ifdef MSI
3139 rid = rman_get_rid(irq);
3140 if (rid == 0) {
3141 /* Make sure that INTx is enabled */
3142 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3143 } else {
3144 /*
3145 * Check to see if the interrupt is MSI or MSI-X.
3146 * Ask our parent to map the MSI and give
3147 * us the address and data register values.
3148 * If we fail for some reason, teardown the
3149 * interrupt handler.
3150 */
3151 dinfo = device_get_ivars(child);
3152 if (dinfo->cfg.msi.msi_alloc > 0) {
3153 if (dinfo->cfg.msi.msi_addr == 0) {
3154 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3155 ("MSI has handlers, but vectors not mapped"));
3156 error = PCIB_MAP_MSI(device_get_parent(dev),
3157 child, rman_get_start(irq), &addr, &data);
3158 if (error)
3159 goto bad;
3160 dinfo->cfg.msi.msi_addr = addr;
3161 dinfo->cfg.msi.msi_data = data;
3162 pci_enable_msi(child, addr, data);
984263bc 3163 }
4d28e78f
SZ
3164 dinfo->cfg.msi.msi_handlers++;
3165 } else {
3166 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3167 ("No MSI or MSI-X interrupts allocated"));
3168 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3169 ("MSI-X index too high"));
3170 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3171 KASSERT(mte->mte_vector != 0, ("no message vector"));
3172 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3173 KASSERT(mv->mv_irq == rman_get_start(irq),
3174 ("IRQ mismatch"));
3175 if (mv->mv_address == 0) {
3176 KASSERT(mte->mte_handlers == 0,
3177 ("MSI-X table entry has handlers, but vector not mapped"));
3178 error = PCIB_MAP_MSI(device_get_parent(dev),
3179 child, rman_get_start(irq), &addr, &data);
3180 if (error)
3181 goto bad;
3182 mv->mv_address = addr;
3183 mv->mv_data = data;
3184 }
3185 if (mte->mte_handlers == 0) {
3186 pci_enable_msix(child, rid - 1, mv->mv_address,
3187 mv->mv_data);
3188 pci_unmask_msix(child, rid - 1);
3189 }
3190 mte->mte_handlers++;
3191 }
3192
3193 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3194 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3195 bad:
3196 if (error) {
3197 (void)bus_generic_teardown_intr(dev, child, irq,
3198 cookie);
3199 return (error);
3200 }
3201 }
3202#endif
3203 *cookiep = cookie;
3204 return (0);
3205}
3206
3207int
3208pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3209 void *cookie)
3210{
3211#ifdef MSI
3212 struct msix_table_entry *mte;
3213 struct resource_list_entry *rle;
3214 struct pci_devinfo *dinfo;
35b72619 3215 int rid;
4d28e78f 3216#endif
35b72619 3217 int error;
4d28e78f
SZ
3218
3219 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3220 return (EINVAL);
3221
3222 /* If this isn't a direct child, just bail out */
3223 if (device_get_parent(child) != dev)
3224 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3225
3226 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3227#ifdef MSI
3228 rid = rman_get_rid(irq);
3229 if (rid == 0) {
3230 /* Mask INTx */
3231 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3232 } else {
3233 /*
3234 * Check to see if the interrupt is MSI or MSI-X. If so,
3235 * decrement the appropriate handlers count and mask the
3236 * MSI-X message, or disable MSI messages if the count
3237 * drops to 0.
3238 */
3239 dinfo = device_get_ivars(child);
3240 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3241 if (rle->res != irq)
3242 return (EINVAL);
3243 if (dinfo->cfg.msi.msi_alloc > 0) {
3244 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3245 ("MSI-X index too high"));
3246 if (dinfo->cfg.msi.msi_handlers == 0)
3247 return (EINVAL);
3248 dinfo->cfg.msi.msi_handlers--;
3249 if (dinfo->cfg.msi.msi_handlers == 0)
3250 pci_disable_msi(child);
3251 } else {
3252 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3253 ("No MSI or MSI-X interrupts allocated"));
3254 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3255 ("MSI-X index too high"));
3256 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3257 if (mte->mte_handlers == 0)
3258 return (EINVAL);
3259 mte->mte_handlers--;
3260 if (mte->mte_handlers == 0)
3261 pci_mask_msix(child, rid - 1);
984263bc
MD
3262 }
3263 }
4d28e78f
SZ
3264 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3265 if (rid > 0)
3266 KASSERT(error == 0,
3267 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3268#endif
3269 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3270 return (error);
984263bc
MD
3271}
3272
e126caf1 3273int
984263bc
MD
3274pci_print_child(device_t dev, device_t child)
3275{
3276 struct pci_devinfo *dinfo;
3277 struct resource_list *rl;
984263bc
MD
3278 int retval = 0;
3279
3280 dinfo = device_get_ivars(child);
984263bc
MD
3281 rl = &dinfo->resources;
3282
3283 retval += bus_print_child_header(dev, child);
3284
4d28e78f
SZ
3285 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3286 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3287 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
984263bc 3288 if (device_get_flags(dev))
85f8e2ea 3289 retval += kprintf(" flags %#x", device_get_flags(dev));
984263bc 3290
85f8e2ea 3291 retval += kprintf(" at device %d.%d", pci_get_slot(child),
4d28e78f 3292 pci_get_function(child));
984263bc
MD
3293
3294 retval += bus_print_child_footer(dev, child);
3295
3296 return (retval);
3297}
3298
4d28e78f
SZ
3299static struct
3300{
3301 int class;
3302 int subclass;
3303 char *desc;
3304} pci_nomatch_tab[] = {
3305 {PCIC_OLD, -1, "old"},
3306 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3307 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3308 {PCIC_STORAGE, -1, "mass storage"},
3309 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3310 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3311 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3312 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3313 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3314 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3315 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3316 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3317 {PCIC_NETWORK, -1, "network"},
3318 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3319 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3320 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3321 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3322 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3323 {PCIC_DISPLAY, -1, "display"},
3324 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3325 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3326 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3327 {PCIC_MULTIMEDIA, -1, "multimedia"},
3328 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3329 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3330 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3331 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3332 {PCIC_MEMORY, -1, "memory"},
3333 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3334 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3335 {PCIC_BRIDGE, -1, "bridge"},
3336 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3337 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3338 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3339 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3340 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3341 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3342 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3343 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3344 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3345 {PCIC_SIMPLECOMM, -1, "simple comms"},
3346 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3347 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3348 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3349 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3350 {PCIC_BASEPERIPH, -1, "base peripheral"},
3351 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3352 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3353 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3354 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3355 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3356 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3357 {PCIC_INPUTDEV, -1, "input device"},
3358 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3359 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3360 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3361 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3362 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3363 {PCIC_DOCKING, -1, "docking station"},
3364 {PCIC_PROCESSOR, -1, "processor"},
3365 {PCIC_SERIALBUS, -1, "serial bus"},
3366 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3367 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3368 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3369 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3370 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3371 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3372 {PCIC_WIRELESS, -1, "wireless controller"},
3373 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3374 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3375 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3376 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3377 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3378 {PCIC_SATCOM, -1, "satellite communication"},
3379 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3380 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3381 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3382 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3383 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3384 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3385 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3386 {PCIC_DASP, -1, "dasp"},
3387 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3388 {0, 0, NULL}
3389};
3390
e126caf1 3391void
984263bc
MD
3392pci_probe_nomatch(device_t dev, device_t child)
3393{
4d28e78f
SZ
3394 int i;
3395 char *cp, *scp, *device;
984263bc 3396
4d28e78f
SZ
3397 /*
3398 * Look for a listing for this device in a loaded device database.
3399 */
3400 if ((device = pci_describe_device(child)) != NULL) {
3401 device_printf(dev, "<%s>", device);
3402 kfree(device, M_DEVBUF);
3403 } else {
3404 /*
3405 * Scan the class/subclass descriptions for a general
3406 * description.
3407 */
3408 cp = "unknown";
3409 scp = NULL;
3410 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3411 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3412 if (pci_nomatch_tab[i].subclass == -1) {
3413 cp = pci_nomatch_tab[i].desc;
3414 } else if (pci_nomatch_tab[i].subclass ==
3415 pci_get_subclass(child)) {
3416 scp = pci_nomatch_tab[i].desc;
3417 }
3418 }
3419 }
3420 device_printf(dev, "<%s%s%s>",
3421 cp ? cp : "",
3422 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3423 scp ? scp : "");
3424 }
6a45dbfa
SZ
3425 kprintf(" (vendor 0x%04x, dev 0x%04x) at device %d.%d",
3426 pci_get_vendor(child), pci_get_device(child),
3427 pci_get_slot(child), pci_get_function(child));
3428 if (pci_get_intpin(child) > 0) {
3429 int irq;
3430
3431 irq = pci_get_irq(child);
3432 if (PCI_INTERRUPT_VALID(irq))
3433 kprintf(" irq %d", irq);
3434 }
3435 kprintf("\n");
3436
638744c5 3437 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
984263bc
MD
3438}
3439
4d28e78f
SZ
3440/*
3441 * Parse the PCI device database, if loaded, and return a pointer to a
3442 * description of the device.
3443 *
3444 * The database is flat text formatted as follows:
3445 *
3446 * Any line not in a valid format is ignored.
3447 * Lines are terminated with newline '\n' characters.
3448 *
3449 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3450 * the vendor name.
3451 *
3452 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3453 * - devices cannot be listed without a corresponding VENDOR line.
3454 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3455 * another TAB, then the device name.
3456 */
3457
3458/*
3459 * Assuming (ptr) points to the beginning of a line in the database,
3460 * return the vendor or device and description of the next entry.
3461 * The value of (vendor) or (device) inappropriate for the entry type
3462 * is set to -1. Returns nonzero at the end of the database.
3463 *
3464 * Note that this is slightly unrobust in the face of corrupt data;
3465 * we attempt to safeguard against this by spamming the end of the
3466 * database with a newline when we initialise.
3467 */
3468static int
3469pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3470{
3471 char *cp = *ptr;
3472 int left;
3473
3474 *device = -1;
3475 *vendor = -1;
3476 **desc = '\0';
3477 for (;;) {
3478 left = pci_vendordata_size - (cp - pci_vendordata);
3479 if (left <= 0) {
3480 *ptr = cp;
3481 return(1);
3482 }
3483
3484 /* vendor entry? */
3485 if (*cp != '\t' &&
3486 ksscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3487 break;
3488 /* device entry? */
3489 if (*cp == '\t' &&
3490 ksscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3491 break;
3492
3493 /* skip to next line */
3494 while (*cp != '\n' && left > 0) {
3495 cp++;
3496 left--;
3497 }
3498 if (*cp == '\n') {
3499 cp++;
3500 left--;
3501 }
3502 }
3503 /* skip to next line */
3504 while (*cp != '\n' && left > 0) {
3505 cp++;
3506 left--;
3507 }
3508 if (*cp == '\n' && left > 0)
3509 cp++;
3510 *ptr = cp;
3511 return(0);
3512}
3513
3514static char *
3515pci_describe_device(device_t dev)
3516{
3517 int vendor, device;
3518 char *desc, *vp, *dp, *line;
3519
3520 desc = vp = dp = NULL;
3521
3522 /*
3523 * If we have no vendor data, we can't do anything.
3524 */
3525 if (pci_vendordata == NULL)
3526 goto out;
3527
3528 /*
3529 * Scan the vendor data looking for this device
3530 */
3531 line = pci_vendordata;
3532 if ((vp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3533 goto out;
3534 for (;;) {
3535 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3536 goto out;
3537 if (vendor == pci_get_vendor(dev))
3538 break;
3539 }
3540 if ((dp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3541 goto out;
3542 for (;;) {
3543 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3544 *dp = 0;
3545 break;
3546 }
3547 if (vendor != -1) {
3548 *dp = 0;
3549 break;
3550 }
3551 if (device == pci_get_device(dev))
3552 break;
3553 }
3554 if (dp[0] == '\0')
3555 ksnprintf(dp, 80, "0x%x", pci_get_device(dev));
3556 if ((desc = kmalloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3557 NULL)
3558 ksprintf(desc, "%s, %s", vp, dp);
3559 out:
3560 if (vp != NULL)
3561 kfree(vp, M_DEVBUF);
3562 if (dp != NULL)
3563 kfree(dp, M_DEVBUF);
3564 return(desc);
3565}
3566
22457186 3567int
4a5a2d63 3568pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
984263bc
MD
3569{
3570 struct pci_devinfo *dinfo;
3571 pcicfgregs *cfg;
3572
3573 dinfo = device_get_ivars(child);
3574 cfg = &dinfo->cfg;
3575
3576 switch (which) {
4d28e78f
SZ
3577 case PCI_IVAR_ETHADDR:
3578 /*
3579 * The generic accessor doesn't deal with failure, so
3580 * we set the return value, then return an error.
3581 */
3582 *((uint8_t **) result) = NULL;
3583 return (EINVAL);
984263bc
MD
3584 case PCI_IVAR_SUBVENDOR:
3585 *result = cfg->subvendor;
3586 break;
3587 case PCI_IVAR_SUBDEVICE:
3588 *result = cfg->subdevice;
3589 break;
3590 case PCI_IVAR_VENDOR:
3591 *result = cfg->vendor;
3592 break;
3593 case PCI_IVAR_DEVICE:
3594 *result = cfg->device;
3595 break;
3596 case PCI_IVAR_DEVID:
3597 *result = (cfg->device << 16) | cfg->vendor;
3598 break;
3599 case PCI_IVAR_CLASS:
3600 *result = cfg->baseclass;
3601 break;
3602 case PCI_IVAR_SUBCLASS:
3603 *result = cfg->subclass;
3604 break;
3605 case PCI_IVAR_PROGIF:
3606 *result = cfg->progif;
3607 break;
3608 case PCI_IVAR_REVID:
3609 *result = cfg->revid;
3610 break;
3611 case PCI_IVAR_INTPIN:
3612 *result = cfg->intpin;
3613 break;
3614 case PCI_IVAR_IRQ:
3615 *result = cfg->intline;
3616 break;
4d28e78f
SZ
3617 case PCI_IVAR_DOMAIN:
3618 *result = cfg->domain;
3619 break;
984263bc
MD
3620 case PCI_IVAR_BUS:
3621 *result = cfg->bus;
3622 break;
3623 case PCI_IVAR_SLOT:
3624 *result = cfg->slot;
3625 break;
3626 case PCI_IVAR_FUNCTION:
3627 *result = cfg->func;
3628 break;
4d28e78f
SZ
3629 case PCI_IVAR_CMDREG:
3630 *result = cfg->cmdreg;
984263bc 3631 break;
4d28e78f
SZ
3632 case PCI_IVAR_CACHELNSZ:
3633 *result = cfg->cachelnsz;
984263bc 3634 break;
4d28e78f
SZ
3635 case PCI_IVAR_MINGNT:
3636 *result = cfg->mingnt;
c7e4e7eb 3637 break;
4d28e78f
SZ
3638 case PCI_IVAR_MAXLAT:
3639 *result = cfg->maxlat;
c7e4e7eb 3640 break;
4d28e78f
SZ
3641 case PCI_IVAR_LATTIMER:
3642 *result = cfg->lattimer;
0254566f 3643 break;
d85e7311
SZ
3644 case PCI_IVAR_PCIXCAP_PTR:
3645 *result = cfg->pcix.pcix_ptr;
3646 break;
3647 case PCI_IVAR_PCIECAP_PTR:
3648 *result = cfg->expr.expr_ptr;
3649 break;
3650 case PCI_IVAR_VPDCAP_PTR:
3651 *result = cfg->vpd.vpd_reg;
3652 break;
984263bc 3653 default:
4d28e78f 3654 return (ENOENT);
984263bc 3655 }
4d28e78f 3656 return (0);
984263bc
MD
3657}
3658
22457186 3659int
984263bc
MD
3660pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3661{
3662 struct pci_devinfo *dinfo;
984263bc
MD
3663
3664 dinfo = device_get_ivars(child);
984263bc
MD
3665
3666 switch (which) {
4d28e78f
SZ
3667 case PCI_IVAR_INTPIN:
3668 dinfo->cfg.intpin = value;
3669 return (0);
3670 case PCI_IVAR_ETHADDR:
984263bc
MD
3671 case PCI_IVAR_SUBVENDOR:
3672 case PCI_IVAR_SUBDEVICE:
3673 case PCI_IVAR_VENDOR:
3674 case PCI_IVAR_DEVICE:
3675 case PCI_IVAR_DEVID:
3676 case PCI_IVAR_CLASS:
3677 case PCI_IVAR_SUBCLASS:
3678 case PCI_IVAR_PROGIF:
3679 case PCI_IVAR_REVID:
984263bc 3680 case PCI_IVAR_IRQ:
4d28e78f 3681 case PCI_IVAR_DOMAIN:
984263bc
MD
3682 case PCI_IVAR_BUS:
3683 case PCI_IVAR_SLOT:
3684 case PCI_IVAR_FUNCTION:
4d28e78f 3685 return (EINVAL); /* disallow for now */
984263bc 3686
984263bc 3687 default:
4d28e78f
SZ
3688 return (ENOENT);
3689 }
3690}
3691#ifdef notyet
3692#include "opt_ddb.h"
3693#ifdef DDB
3694#include <ddb/ddb.h>
3695#include <sys/cons.h>
3696
3697/*
3698 * List resources based on pci map registers, used for within ddb
3699 */
3700
3701DB_SHOW_COMMAND(pciregs, db_pci_dump)
3702{
3703 struct pci_devinfo *dinfo;
3704 struct devlist *devlist_head;
3705 struct pci_conf *p;
3706 const char *name;
3707 int i, error, none_count;
3708
3709 none_count = 0;
3710 /* get the head of the device queue */
3711 devlist_head = &pci_devq;
3712
3713 /*
3714 * Go through the list of devices and print out devices
3715 */
3716 for (error = 0, i = 0,
3717 dinfo = STAILQ_FIRST(devlist_head);
3718 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3719 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3720
3721 /* Populate pd_name and pd_unit */
3722 name = NULL;
3723 if (dinfo->cfg.dev)
3724 name = device_get_name(dinfo->cfg.dev);
3725
3726 p = &dinfo->conf;
3727 db_kprintf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3728 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3729 (name && *name) ? name : "none",
3730 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3731 none_count++,
3732 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3733 p->pc_sel.pc_func, (p->pc_class << 16) |
3734 (p->pc_subclass << 8) | p->pc_progif,
3735 (p->pc_subdevice << 16) | p->pc_subvendor,
3736 (p->pc_device << 16) | p->pc_vendor,
3737 p->pc_revid, p->pc_hdr);
984263bc 3738 }
984263bc 3739}
4d28e78f
SZ
3740#endif /* DDB */
3741#endif
984263bc 3742
201eb0a7 3743static struct resource *
4d28e78f
SZ
3744pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3745 u_long start, u_long end, u_long count, u_int flags)
201eb0a7
TS
3746{
3747 struct pci_devinfo *dinfo = device_get_ivars(child);
3748 struct resource_list *rl = &dinfo->resources;
3749 struct resource_list_entry *rle;
3750 struct resource *res;
4d28e78f 3751 pci_addr_t map, testval;
201eb0a7
TS
3752 int mapsize;
3753
3754 /*
3755 * Weed out the bogons, and figure out how large the BAR/map
4d28e78f 3756 * is. Bars that read back 0 here are bogus and unimplemented.
201eb0a7 3757 * Note: atapci in legacy mode are special and handled elsewhere
4d28e78f 3758 * in the code. If you have a atapci device in legacy mode and
201eb0a7
TS
3759 * it fails here, that other code is broken.
3760 */
3761 res = NULL;
3762 map = pci_read_config(child, *rid, 4);
3763 pci_write_config(child, *rid, 0xffffffff, 4);
3764 testval = pci_read_config(child, *rid, 4);
4d28e78f
SZ
3765 if (pci_maprange(testval) == 64)
3766 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
201eb0a7
TS
3767 if (pci_mapbase(testval) == 0)
3768 goto out;
4d28e78f
SZ
3769
3770 /*
3771 * Restore the original value of the BAR. We may have reprogrammed
3772 * the BAR of the low-level console device and when booting verbose,
3773 * we need the console device addressable.
3774 */
3775 pci_write_config(child, *rid, map, 4);
3776
3777 if (PCI_BAR_MEM(testval)) {
201eb0a7
TS
3778 if (type != SYS_RES_MEMORY) {
3779 if (bootverbose)
4d28e78f
SZ
3780 device_printf(dev,
3781 "child %s requested type %d for rid %#x,"
3782 " but the BAR says it is an memio\n",
3783 device_get_nameunit(child), type, *rid);
201eb0a7
TS
3784 goto out;
3785 }
3786 } else {
3787 if (type != SYS_RES_IOPORT) {
3788 if (bootverbose)
4d28e78f
SZ
3789 device_printf(dev,
3790 "child %s requested type %d for rid %#x,"
3791 " but the BAR says it is an ioport\n",
3792 device_get_nameunit(child), type, *rid);
201eb0a7
TS
3793 goto out;
3794 }
3795 }
3796 /*
3797 * For real BARs, we need to override the size that
3798 * the driver requests, because that's what the BAR
3799 * actually uses and we would otherwise have a
3800 * situation where we might allocate the excess to
3801 * another driver, which won't work.
3802 */
3803 mapsize = pci_mapsize(testval);
4d28e78f 3804 count = 1UL << mapsize;
201eb0a7 3805 if (RF_ALIGNMENT(flags) < mapsize)
4d28e78f
SZ
3806 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3807 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3808 flags |= RF_PREFETCHABLE;
3809
201eb0a7
TS
3810 /*
3811 * Allocate enough resource, and then write back the
4d28e78f 3812 * appropriate bar for that resource.
201eb0a7
TS
3813 */
3814 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
4d28e78f 3815 start, end, count, flags);
201eb0a7 3816 if (res == NULL) {
4d28e78f
SZ
3817 device_printf(child,
3818 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3819 count, *rid, type, start, end);
201eb0a7
TS
3820 goto out;
3821 }
3822 resource_list_add(rl, type, *rid, start, end, count);
3823 rle = resource_list_find(rl, type, *rid);
3824 if (rle == NULL)
3825 panic("pci_alloc_map: unexpectedly can't find resource.");
3826 rle->res = res;
3827 rle->start = rman_get_start(res);
3828 rle->end = rman_get_end(res);
3829 rle->count = count;
3830 if (bootverbose)
4d28e78f
SZ
3831 device_printf(child,
3832 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3833 count, *rid, type, rman_get_start(res));
201eb0a7
TS
3834 map = rman_get_start(res);
3835out:;
3836 pci_write_config(child, *rid, map, 4);
4d28e78f
SZ
3837 if (pci_maprange(testval) == 64)
3838 pci_write_config(child, *rid + 4, map >> 32, 4);
3839 return (res);
201eb0a7 3840}
4d28e78f 3841
201eb0a7 3842
261fa16d 3843struct resource *
984263bc
MD
3844pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3845 u_long start, u_long end, u_long count, u_int flags)
3846{
3847 struct pci_devinfo *dinfo = device_get_ivars(child);
3848 struct resource_list *rl = &dinfo->resources;
201eb0a7 3849 struct resource_list_entry *rle;
984263bc 3850 pcicfgregs *cfg = &dinfo->cfg;
09e7d9f3 3851
984263bc
MD
3852 /*
3853 * Perform lazy resource allocation
984263bc
MD
3854 */
3855 if (device_get_parent(child) == dev) {
de67e43b
JS
3856 switch (type) {
3857 case SYS_RES_IRQ:
4d28e78f
SZ
3858 /*
3859 * Can't alloc legacy interrupt once MSI messages
3860 * have been allocated.
3861 */
3862#ifdef MSI
3863 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3864 cfg->msix.msix_alloc > 0))
3865 return (NULL);
de67e43b 3866#endif
4d28e78f
SZ
3867 /*
3868 * If the child device doesn't have an
3869 * interrupt routed and is deserving of an
3870 * interrupt, try to assign it one.
3871 */
3872 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3873 (cfg->intpin != 0))
3874 pci_assign_interrupt(dev, child, 0);
3875 break;
de67e43b
JS
3876 case SYS_RES_IOPORT:
3877 case SYS_RES_MEMORY:
3878 if (*rid < PCIR_BAR(cfg->nummaps)) {
3879 /*
3880 * Enable the I/O mode. We should
3881 * also be assigning resources too
3882 * when none are present. The
3883 * resource_list_alloc kind of sorta does