| 1 | /* |
| 2 | * Copyright (c) 2004 |
| 3 | * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. |
| 4 | * |
| 5 | * Copyright (c) 1997, 1998-2003 |
| 6 | * Bill Paul <wpaul@windriver.com>. All rights reserved. |
| 7 | * |
| 8 | * Redistribution and use in source and binary forms, with or without |
| 9 | * modification, are permitted provided that the following conditions |
| 10 | * are met: |
| 11 | * 1. Redistributions of source code must retain the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer. |
| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer in the |
| 15 | * documentation and/or other materials provided with the distribution. |
| 16 | * 3. All advertising materials mentioning features or use of this software |
| 17 | * must display the following acknowledgement: |
| 18 | * This product includes software developed by Bill Paul. |
| 19 | * 4. Neither the name of the author nor the names of any co-contributors |
| 20 | * may be used to endorse or promote products derived from this software |
| 21 | * without specific prior written permission. |
| 22 | * |
| 23 | * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND |
| 24 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 25 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 26 | * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD |
| 27 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 28 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 29 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 30 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 31 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 32 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 33 | * THE POSSIBILITY OF SUCH DAMAGE. |
| 34 | * |
| 35 | * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $ |
| 36 | * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.94 2008/10/19 06:00:24 sephe Exp $ |
| 37 | */ |
| 38 | |
| 39 | /* |
| 40 | * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver |
| 41 | * |
| 42 | * Written by Bill Paul <wpaul@windriver.com> |
| 43 | * Senior Networking Software Engineer |
| 44 | * Wind River Systems |
| 45 | */ |
| 46 | |
| 47 | /* |
| 48 | * This driver is designed to support RealTek's next generation of |
| 49 | * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently |
| 50 | * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, |
| 51 | * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. |
| 52 | * |
| 53 | * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible |
| 54 | * with the older 8139 family, however it also supports a special |
| 55 | * C+ mode of operation that provides several new performance enhancing |
| 56 | * features. These include: |
| 57 | * |
| 58 | * o Descriptor based DMA mechanism. Each descriptor represents |
| 59 | * a single packet fragment. Data buffers may be aligned on |
| 60 | * any byte boundary. |
| 61 | * |
| 62 | * o 64-bit DMA |
| 63 | * |
| 64 | * o TCP/IP checksum offload for both RX and TX |
| 65 | * |
| 66 | * o High and normal priority transmit DMA rings |
| 67 | * |
| 68 | * o VLAN tag insertion and extraction |
| 69 | * |
| 70 | * o TCP large send (segmentation offload) |
| 71 | * |
| 72 | * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ |
| 73 | * programming API is fairly straightforward. The RX filtering, EEPROM |
| 74 | * access and PHY access is the same as it is on the older 8139 series |
| 75 | * chips. |
| 76 | * |
| 77 | * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the |
| 78 | * same programming API and feature set as the 8139C+ with the following |
| 79 | * differences and additions: |
| 80 | * |
| 81 | * o 1000Mbps mode |
| 82 | * |
| 83 | * o Jumbo frames |
| 84 | * |
| 85 | * o GMII and TBI ports/registers for interfacing with copper |
| 86 | * or fiber PHYs |
| 87 | * |
| 88 | * o RX and TX DMA rings can have up to 1024 descriptors |
| 89 | * (the 8139C+ allows a maximum of 64) |
| 90 | * |
| 91 | * o Slight differences in register layout from the 8139C+ |
| 92 | * |
| 93 | * The TX start and timer interrupt registers are at different locations |
| 94 | * on the 8169 than they are on the 8139C+. Also, the status word in the |
| 95 | * RX descriptor has a slightly different bit layout. The 8169 does not |
| 96 | * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' |
| 97 | * copper gigE PHY. |
| 98 | * |
| 99 | * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs |
| 100 | * (the 'S' stands for 'single-chip'). These devices have the same |
| 101 | * programming API as the older 8169, but also have some vendor-specific |
| 102 | * registers for the on-board PHY. The 8110S is a LAN-on-motherboard |
| 103 | * part designed to be pin-compatible with the RealTek 8100 10/100 chip. |
| 104 | * |
| 105 | * This driver takes advantage of the RX and TX checksum offload and |
| 106 | * VLAN tag insertion/extraction features. It also implements TX |
| 107 | * interrupt moderation using the timer interrupt registers, which |
| 108 | * significantly reduces TX interrupt load. There is also support |
| 109 | * for jumbo frames, however the 8169/8169S/8110S can not transmit |
| 110 | * jumbo frames larger than 7440, so the max MTU possible with this |
| 111 | * driver is 7422 bytes. |
| 112 | */ |
| 113 | |
| 114 | #define _IP_VHL |
| 115 | |
| 116 | #include "opt_polling.h" |
| 117 | |
| 118 | #include <sys/param.h> |
| 119 | #include <sys/bus.h> |
| 120 | #include <sys/endian.h> |
| 121 | #include <sys/kernel.h> |
| 122 | #include <sys/in_cksum.h> |
| 123 | #include <sys/interrupt.h> |
| 124 | #include <sys/malloc.h> |
| 125 | #include <sys/mbuf.h> |
| 126 | #include <sys/rman.h> |
| 127 | #include <sys/serialize.h> |
| 128 | #include <sys/socket.h> |
| 129 | #include <sys/sockio.h> |
| 130 | #include <sys/sysctl.h> |
| 131 | |
| 132 | #include <net/bpf.h> |
| 133 | #include <net/ethernet.h> |
| 134 | #include <net/if.h> |
| 135 | #include <net/ifq_var.h> |
| 136 | #include <net/if_arp.h> |
| 137 | #include <net/if_dl.h> |
| 138 | #include <net/if_media.h> |
| 139 | #include <net/if_types.h> |
| 140 | #include <net/vlan/if_vlan_var.h> |
| 141 | #include <net/vlan/if_vlan_ether.h> |
| 142 | |
| 143 | #include <netinet/ip.h> |
| 144 | |
| 145 | #include <dev/netif/mii_layer/mii.h> |
| 146 | #include <dev/netif/mii_layer/miivar.h> |
| 147 | |
| 148 | #include <bus/pci/pcidevs.h> |
| 149 | #include <bus/pci/pcireg.h> |
| 150 | #include <bus/pci/pcivar.h> |
| 151 | |
| 152 | /* "device miibus" required. See GENERIC if you get errors here. */ |
| 153 | #include "miibus_if.h" |
| 154 | |
| 155 | #include <dev/netif/re/if_rereg.h> |
| 156 | #include <dev/netif/re/if_revar.h> |
| 157 | |
| 158 | #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) |
| 159 | |
| 160 | /* |
| 161 | * Various supported device vendors/types and their names. |
| 162 | */ |
| 163 | static const struct re_type { |
| 164 | uint16_t re_vid; |
| 165 | uint16_t re_did; |
| 166 | const char *re_name; |
| 167 | } re_devs[] = { |
| 168 | { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, |
| 169 | "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, |
| 170 | |
| 171 | { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, |
| 172 | "RealTek 8139C+ 10/100BaseTX" }, |
| 173 | |
| 174 | { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, |
| 175 | "RealTek 810x PCIe 10/100baseTX" }, |
| 176 | |
| 177 | { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, |
| 178 | "RealTek 8111/8168 PCIe Gigabit Ethernet" }, |
| 179 | |
| 180 | { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, |
| 181 | "RealTek 8110/8169 Gigabit Ethernet" }, |
| 182 | |
| 183 | { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, |
| 184 | "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, |
| 185 | |
| 186 | { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, |
| 187 | "Corega CG-LAPCIGT Gigabit Ethernet" }, |
| 188 | |
| 189 | { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, |
| 190 | "Linksys EG1032 Gigabit Ethernet" }, |
| 191 | |
| 192 | { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, |
| 193 | "US Robotics 997902 Gigabit Ethernet" }, |
| 194 | |
| 195 | { 0, 0, NULL } |
| 196 | }; |
| 197 | |
| 198 | static const struct re_hwrev re_hwrevs[] = { |
| 199 | { RE_HWREV_8139CPLUS, RE_MACVER_UNKN, ETHERMTU, |
| 200 | RE_C_HWCSUM | RE_C_8139CP }, |
| 201 | |
| 202 | { RE_HWREV_8169, RE_MACVER_UNKN, RE_MTU_6K, |
| 203 | RE_C_HWCSUM | RE_C_8169 }, |
| 204 | |
| 205 | { RE_HWREV_8110S, RE_MACVER_03, RE_MTU_6K, |
| 206 | RE_C_HWCSUM | RE_C_8169 }, |
| 207 | |
| 208 | { RE_HWREV_8169S, RE_MACVER_03, RE_MTU_6K, |
| 209 | RE_C_HWCSUM | RE_C_8169 }, |
| 210 | |
| 211 | { RE_HWREV_8169SB, RE_MACVER_04, RE_MTU_6K, |
| 212 | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, |
| 213 | |
| 214 | { RE_HWREV_8169SC1, RE_MACVER_05, RE_MTU_6K, |
| 215 | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, |
| 216 | |
| 217 | { RE_HWREV_8169SC2, RE_MACVER_06, RE_MTU_6K, |
| 218 | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 }, |
| 219 | |
| 220 | { RE_HWREV_8168B1, RE_MACVER_21, RE_MTU_6K, |
| 221 | RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT }, |
| 222 | |
| 223 | { RE_HWREV_8168B2, RE_MACVER_23, RE_MTU_6K, |
| 224 | RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD }, |
| 225 | |
| 226 | { RE_HWREV_8168B3, RE_MACVER_23, RE_MTU_6K, |
| 227 | RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD }, |
| 228 | |
| 229 | { RE_HWREV_8168C, RE_MACVER_29, RE_MTU_6K, |
| 230 | RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | |
| 231 | RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, |
| 232 | |
| 233 | { RE_HWREV_8168CP, RE_MACVER_2B, RE_MTU_6K, |
| 234 | RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | |
| 235 | RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, |
| 236 | |
| 237 | { RE_HWREV_8168D, RE_MACVER_2A, RE_MTU_9K, |
| 238 | RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | |
| 239 | RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX }, |
| 240 | |
| 241 | { RE_HWREV_8100E, RE_MACVER_UNKN, ETHERMTU, |
| 242 | RE_C_HWCSUM }, |
| 243 | |
| 244 | { RE_HWREV_8101E1, RE_MACVER_16, ETHERMTU, |
| 245 | RE_C_HWCSUM }, |
| 246 | |
| 247 | { RE_HWREV_8101E2, RE_MACVER_16, ETHERMTU, |
| 248 | RE_C_HWCSUM }, |
| 249 | |
| 250 | { RE_HWREV_8102E, RE_MACVER_15, ETHERMTU, |
| 251 | RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX }, |
| 252 | |
| 253 | { RE_HWREV_8102EL, RE_MACVER_15, ETHERMTU, |
| 254 | RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX }, |
| 255 | |
| 256 | { RE_HWREV_NULL, 0, 0, 0 } |
| 257 | }; |
| 258 | |
| 259 | static int re_probe(device_t); |
| 260 | static int re_attach(device_t); |
| 261 | static int re_detach(device_t); |
| 262 | static int re_suspend(device_t); |
| 263 | static int re_resume(device_t); |
| 264 | static void re_shutdown(device_t); |
| 265 | |
| 266 | static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int); |
| 267 | static void re_dma_map_desc(void *, bus_dma_segment_t *, int, |
| 268 | bus_size_t, int); |
| 269 | static int re_allocmem(device_t); |
| 270 | static void re_freemem(device_t); |
| 271 | static void re_freebufmem(struct re_softc *, int, int); |
| 272 | static int re_encap(struct re_softc *, struct mbuf **, int *); |
| 273 | static int re_newbuf_std(struct re_softc *, int, int); |
| 274 | static int re_newbuf_jumbo(struct re_softc *, int, int); |
| 275 | static void re_setup_rxdesc(struct re_softc *, int); |
| 276 | static int re_rx_list_init(struct re_softc *); |
| 277 | static int re_tx_list_init(struct re_softc *); |
| 278 | static int re_rxeof(struct re_softc *); |
| 279 | static int re_txeof(struct re_softc *); |
| 280 | static int re_tx_collect(struct re_softc *); |
| 281 | static void re_intr(void *); |
| 282 | static void re_tick(void *); |
| 283 | static void re_tick_serialized(void *); |
| 284 | |
| 285 | static void re_start(struct ifnet *); |
| 286 | static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); |
| 287 | static void re_init(void *); |
| 288 | static void re_stop(struct re_softc *); |
| 289 | static void re_watchdog(struct ifnet *); |
| 290 | static int re_ifmedia_upd(struct ifnet *); |
| 291 | static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); |
| 292 | |
| 293 | static void re_eeprom_putbyte(struct re_softc *, int); |
| 294 | static void re_eeprom_getword(struct re_softc *, int, u_int16_t *); |
| 295 | static void re_read_eeprom(struct re_softc *, caddr_t, int, int); |
| 296 | static void re_get_eewidth(struct re_softc *); |
| 297 | |
| 298 | static int re_gmii_readreg(device_t, int, int); |
| 299 | static int re_gmii_writereg(device_t, int, int, int); |
| 300 | |
| 301 | static int re_miibus_readreg(device_t, int, int); |
| 302 | static int re_miibus_writereg(device_t, int, int, int); |
| 303 | static void re_miibus_statchg(device_t); |
| 304 | |
| 305 | static void re_setmulti(struct re_softc *); |
| 306 | static void re_reset(struct re_softc *, int); |
| 307 | static void re_get_eaddr(struct re_softc *, uint8_t *); |
| 308 | static int re_pad_frame(struct mbuf *); |
| 309 | static void re_set_max_readrq(struct re_softc *, uint16_t); |
| 310 | |
| 311 | static void re_setup_hw_im(struct re_softc *); |
| 312 | static void re_setup_sim_im(struct re_softc *); |
| 313 | static void re_disable_hw_im(struct re_softc *); |
| 314 | static void re_disable_sim_im(struct re_softc *); |
| 315 | static void re_config_imtype(struct re_softc *, int); |
| 316 | static void re_setup_intr(struct re_softc *, int, int); |
| 317 | |
| 318 | static int re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *); |
| 319 | static int re_sysctl_rxtime(SYSCTL_HANDLER_ARGS); |
| 320 | static int re_sysctl_txtime(SYSCTL_HANDLER_ARGS); |
| 321 | static int re_sysctl_simtime(SYSCTL_HANDLER_ARGS); |
| 322 | static int re_sysctl_imtype(SYSCTL_HANDLER_ARGS); |
| 323 | |
| 324 | static int re_jpool_alloc(struct re_softc *); |
| 325 | static void re_jpool_free(struct re_softc *); |
| 326 | static struct re_jbuf *re_jbuf_alloc(struct re_softc *); |
| 327 | static void re_jbuf_free(void *); |
| 328 | static void re_jbuf_ref(void *); |
| 329 | |
| 330 | #ifdef RE_DIAG |
| 331 | static int re_diag(struct re_softc *); |
| 332 | #endif |
| 333 | |
| 334 | #ifdef DEVICE_POLLING |
| 335 | static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); |
| 336 | #endif |
| 337 | |
| 338 | static device_method_t re_methods[] = { |
| 339 | /* Device interface */ |
| 340 | DEVMETHOD(device_probe, re_probe), |
| 341 | DEVMETHOD(device_attach, re_attach), |
| 342 | DEVMETHOD(device_detach, re_detach), |
| 343 | DEVMETHOD(device_suspend, re_suspend), |
| 344 | DEVMETHOD(device_resume, re_resume), |
| 345 | DEVMETHOD(device_shutdown, re_shutdown), |
| 346 | |
| 347 | /* bus interface */ |
| 348 | DEVMETHOD(bus_print_child, bus_generic_print_child), |
| 349 | DEVMETHOD(bus_driver_added, bus_generic_driver_added), |
| 350 | |
| 351 | /* MII interface */ |
| 352 | DEVMETHOD(miibus_readreg, re_miibus_readreg), |
| 353 | DEVMETHOD(miibus_writereg, re_miibus_writereg), |
| 354 | DEVMETHOD(miibus_statchg, re_miibus_statchg), |
| 355 | |
| 356 | { 0, 0 } |
| 357 | }; |
| 358 | |
| 359 | static driver_t re_driver = { |
| 360 | "re", |
| 361 | re_methods, |
| 362 | sizeof(struct re_softc) |
| 363 | }; |
| 364 | |
| 365 | static devclass_t re_devclass; |
| 366 | |
| 367 | DECLARE_DUMMY_MODULE(if_re); |
| 368 | DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0); |
| 369 | DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0); |
| 370 | DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); |
| 371 | |
| 372 | static int re_rx_desc_count = RE_RX_DESC_CNT_DEF; |
| 373 | static int re_tx_desc_count = RE_TX_DESC_CNT_DEF; |
| 374 | |
| 375 | TUNABLE_INT("hw.re.rx_desc_count", &re_rx_desc_count); |
| 376 | TUNABLE_INT("hw.re.tx_desc_count", &re_tx_desc_count); |
| 377 | |
| 378 | #define EE_SET(x) \ |
| 379 | CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x)) |
| 380 | |
| 381 | #define EE_CLR(x) \ |
| 382 | CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x)) |
| 383 | |
| 384 | static __inline void |
| 385 | re_free_rxchain(struct re_softc *sc) |
| 386 | { |
| 387 | if (sc->re_head != NULL) { |
| 388 | m_freem(sc->re_head); |
| 389 | sc->re_head = sc->re_tail = NULL; |
| 390 | } |
| 391 | } |
| 392 | |
| 393 | /* |
| 394 | * Send a read command and address to the EEPROM, check for ACK. |
| 395 | */ |
| 396 | static void |
| 397 | re_eeprom_putbyte(struct re_softc *sc, int addr) |
| 398 | { |
| 399 | int d, i; |
| 400 | |
| 401 | d = addr | (RE_9346_READ << sc->re_eewidth); |
| 402 | |
| 403 | /* |
| 404 | * Feed in each bit and strobe the clock. |
| 405 | */ |
| 406 | for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) { |
| 407 | if (d & i) |
| 408 | EE_SET(RE_EE_DATAIN); |
| 409 | else |
| 410 | EE_CLR(RE_EE_DATAIN); |
| 411 | DELAY(100); |
| 412 | EE_SET(RE_EE_CLK); |
| 413 | DELAY(150); |
| 414 | EE_CLR(RE_EE_CLK); |
| 415 | DELAY(100); |
| 416 | } |
| 417 | } |
| 418 | |
| 419 | /* |
| 420 | * Read a word of data stored in the EEPROM at address 'addr.' |
| 421 | */ |
| 422 | static void |
| 423 | re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest) |
| 424 | { |
| 425 | int i; |
| 426 | uint16_t word = 0; |
| 427 | |
| 428 | /* |
| 429 | * Send address of word we want to read. |
| 430 | */ |
| 431 | re_eeprom_putbyte(sc, addr); |
| 432 | |
| 433 | /* |
| 434 | * Start reading bits from EEPROM. |
| 435 | */ |
| 436 | for (i = 0x8000; i != 0; i >>= 1) { |
| 437 | EE_SET(RE_EE_CLK); |
| 438 | DELAY(100); |
| 439 | if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT) |
| 440 | word |= i; |
| 441 | EE_CLR(RE_EE_CLK); |
| 442 | DELAY(100); |
| 443 | } |
| 444 | |
| 445 | *dest = word; |
| 446 | } |
| 447 | |
| 448 | /* |
| 449 | * Read a sequence of words from the EEPROM. |
| 450 | */ |
| 451 | static void |
| 452 | re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt) |
| 453 | { |
| 454 | int i; |
| 455 | uint16_t word = 0, *ptr; |
| 456 | |
| 457 | CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); |
| 458 | DELAY(100); |
| 459 | |
| 460 | for (i = 0; i < cnt; i++) { |
| 461 | CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL); |
| 462 | re_eeprom_getword(sc, off + i, &word); |
| 463 | CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL); |
| 464 | ptr = (uint16_t *)(dest + (i * 2)); |
| 465 | *ptr = word; |
| 466 | } |
| 467 | |
| 468 | CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM); |
| 469 | } |
| 470 | |
| 471 | static void |
| 472 | re_get_eewidth(struct re_softc *sc) |
| 473 | { |
| 474 | uint16_t re_did = 0; |
| 475 | |
| 476 | sc->re_eewidth = 6; |
| 477 | re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); |
| 478 | if (re_did != 0x8129) |
| 479 | sc->re_eewidth = 8; |
| 480 | } |
| 481 | |
| 482 | static int |
| 483 | re_gmii_readreg(device_t dev, int phy, int reg) |
| 484 | { |
| 485 | struct re_softc *sc = device_get_softc(dev); |
| 486 | u_int32_t rval; |
| 487 | int i; |
| 488 | |
| 489 | if (phy != 1) |
| 490 | return(0); |
| 491 | |
| 492 | /* Let the rgephy driver read the GMEDIASTAT register */ |
| 493 | |
| 494 | if (reg == RE_GMEDIASTAT) |
| 495 | return(CSR_READ_1(sc, RE_GMEDIASTAT)); |
| 496 | |
| 497 | CSR_WRITE_4(sc, RE_PHYAR, reg << 16); |
| 498 | DELAY(1000); |
| 499 | |
| 500 | for (i = 0; i < RE_TIMEOUT; i++) { |
| 501 | rval = CSR_READ_4(sc, RE_PHYAR); |
| 502 | if (rval & RE_PHYAR_BUSY) |
| 503 | break; |
| 504 | DELAY(100); |
| 505 | } |
| 506 | |
| 507 | if (i == RE_TIMEOUT) { |
| 508 | device_printf(dev, "PHY read failed\n"); |
| 509 | return(0); |
| 510 | } |
| 511 | |
| 512 | return(rval & RE_PHYAR_PHYDATA); |
| 513 | } |
| 514 | |
| 515 | static int |
| 516 | re_gmii_writereg(device_t dev, int phy, int reg, int data) |
| 517 | { |
| 518 | struct re_softc *sc = device_get_softc(dev); |
| 519 | uint32_t rval; |
| 520 | int i; |
| 521 | |
| 522 | CSR_WRITE_4(sc, RE_PHYAR, |
| 523 | (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY); |
| 524 | DELAY(1000); |
| 525 | |
| 526 | for (i = 0; i < RE_TIMEOUT; i++) { |
| 527 | rval = CSR_READ_4(sc, RE_PHYAR); |
| 528 | if ((rval & RE_PHYAR_BUSY) == 0) |
| 529 | break; |
| 530 | DELAY(100); |
| 531 | } |
| 532 | |
| 533 | if (i == RE_TIMEOUT) |
| 534 | device_printf(dev, "PHY write failed\n"); |
| 535 | |
| 536 | return(0); |
| 537 | } |
| 538 | |
| 539 | static int |
| 540 | re_miibus_readreg(device_t dev, int phy, int reg) |
| 541 | { |
| 542 | struct re_softc *sc = device_get_softc(dev); |
| 543 | uint16_t rval = 0; |
| 544 | uint16_t re8139_reg = 0; |
| 545 | |
| 546 | if (!RE_IS_8139CP(sc)) { |
| 547 | rval = re_gmii_readreg(dev, phy, reg); |
| 548 | return(rval); |
| 549 | } |
| 550 | |
| 551 | /* Pretend the internal PHY is only at address 0 */ |
| 552 | if (phy) |
| 553 | return(0); |
| 554 | |
| 555 | switch(reg) { |
| 556 | case MII_BMCR: |
| 557 | re8139_reg = RE_BMCR; |
| 558 | break; |
| 559 | case MII_BMSR: |
| 560 | re8139_reg = RE_BMSR; |
| 561 | break; |
| 562 | case MII_ANAR: |
| 563 | re8139_reg = RE_ANAR; |
| 564 | break; |
| 565 | case MII_ANER: |
| 566 | re8139_reg = RE_ANER; |
| 567 | break; |
| 568 | case MII_ANLPAR: |
| 569 | re8139_reg = RE_LPAR; |
| 570 | break; |
| 571 | case MII_PHYIDR1: |
| 572 | case MII_PHYIDR2: |
| 573 | return(0); |
| 574 | /* |
| 575 | * Allow the rlphy driver to read the media status |
| 576 | * register. If we have a link partner which does not |
| 577 | * support NWAY, this is the register which will tell |
| 578 | * us the results of parallel detection. |
| 579 | */ |
| 580 | case RE_MEDIASTAT: |
| 581 | return(CSR_READ_1(sc, RE_MEDIASTAT)); |
| 582 | default: |
| 583 | device_printf(dev, "bad phy register\n"); |
| 584 | return(0); |
| 585 | } |
| 586 | rval = CSR_READ_2(sc, re8139_reg); |
| 587 | if (re8139_reg == RE_BMCR) { |
| 588 | /* 8139C+ has different bit layout. */ |
| 589 | rval &= ~(BMCR_LOOP | BMCR_ISO); |
| 590 | } |
| 591 | return(rval); |
| 592 | } |
| 593 | |
| 594 | static int |
| 595 | re_miibus_writereg(device_t dev, int phy, int reg, int data) |
| 596 | { |
| 597 | struct re_softc *sc= device_get_softc(dev); |
| 598 | u_int16_t re8139_reg = 0; |
| 599 | |
| 600 | if (!RE_IS_8139CP(sc)) |
| 601 | return(re_gmii_writereg(dev, phy, reg, data)); |
| 602 | |
| 603 | /* Pretend the internal PHY is only at address 0 */ |
| 604 | if (phy) |
| 605 | return(0); |
| 606 | |
| 607 | switch(reg) { |
| 608 | case MII_BMCR: |
| 609 | re8139_reg = RE_BMCR; |
| 610 | /* 8139C+ has different bit layout. */ |
| 611 | data &= ~(BMCR_LOOP | BMCR_ISO); |
| 612 | break; |
| 613 | case MII_BMSR: |
| 614 | re8139_reg = RE_BMSR; |
| 615 | break; |
| 616 | case MII_ANAR: |
| 617 | re8139_reg = RE_ANAR; |
| 618 | break; |
| 619 | case MII_ANER: |
| 620 | re8139_reg = RE_ANER; |
| 621 | break; |
| 622 | case MII_ANLPAR: |
| 623 | re8139_reg = RE_LPAR; |
| 624 | break; |
| 625 | case MII_PHYIDR1: |
| 626 | case MII_PHYIDR2: |
| 627 | return(0); |
| 628 | default: |
| 629 | device_printf(dev, "bad phy register\n"); |
| 630 | return(0); |
| 631 | } |
| 632 | CSR_WRITE_2(sc, re8139_reg, data); |
| 633 | return(0); |
| 634 | } |
| 635 | |
| 636 | static void |
| 637 | re_miibus_statchg(device_t dev) |
| 638 | { |
| 639 | } |
| 640 | |
| 641 | /* |
| 642 | * Program the 64-bit multicast hash filter. |
| 643 | */ |
| 644 | static void |
| 645 | re_setmulti(struct re_softc *sc) |
| 646 | { |
| 647 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 648 | int h = 0; |
| 649 | uint32_t hashes[2] = { 0, 0 }; |
| 650 | struct ifmultiaddr *ifma; |
| 651 | uint32_t rxfilt; |
| 652 | int mcnt = 0; |
| 653 | |
| 654 | rxfilt = CSR_READ_4(sc, RE_RXCFG); |
| 655 | |
| 656 | if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { |
| 657 | rxfilt |= RE_RXCFG_RX_MULTI; |
| 658 | CSR_WRITE_4(sc, RE_RXCFG, rxfilt); |
| 659 | CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF); |
| 660 | CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF); |
| 661 | return; |
| 662 | } |
| 663 | |
| 664 | /* first, zot all the existing hash bits */ |
| 665 | CSR_WRITE_4(sc, RE_MAR0, 0); |
| 666 | CSR_WRITE_4(sc, RE_MAR4, 0); |
| 667 | |
| 668 | /* now program new ones */ |
| 669 | LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { |
| 670 | if (ifma->ifma_addr->sa_family != AF_LINK) |
| 671 | continue; |
| 672 | h = ether_crc32_be(LLADDR((struct sockaddr_dl *) |
| 673 | ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; |
| 674 | if (h < 32) |
| 675 | hashes[0] |= (1 << h); |
| 676 | else |
| 677 | hashes[1] |= (1 << (h - 32)); |
| 678 | mcnt++; |
| 679 | } |
| 680 | |
| 681 | if (mcnt) |
| 682 | rxfilt |= RE_RXCFG_RX_MULTI; |
| 683 | else |
| 684 | rxfilt &= ~RE_RXCFG_RX_MULTI; |
| 685 | |
| 686 | CSR_WRITE_4(sc, RE_RXCFG, rxfilt); |
| 687 | |
| 688 | /* |
| 689 | * For some unfathomable reason, RealTek decided to reverse |
| 690 | * the order of the multicast hash registers in the PCI Express |
| 691 | * parts. This means we have to write the hash pattern in reverse |
| 692 | * order for those devices. |
| 693 | */ |
| 694 | if (sc->re_caps & RE_C_PCIE) { |
| 695 | CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[0])); |
| 696 | CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[1])); |
| 697 | } else { |
| 698 | CSR_WRITE_4(sc, RE_MAR0, hashes[0]); |
| 699 | CSR_WRITE_4(sc, RE_MAR4, hashes[1]); |
| 700 | } |
| 701 | } |
| 702 | |
| 703 | static void |
| 704 | re_reset(struct re_softc *sc, int running) |
| 705 | { |
| 706 | int i; |
| 707 | |
| 708 | if ((sc->re_caps & RE_C_STOP_RXTX) && running) { |
| 709 | CSR_WRITE_1(sc, RE_COMMAND, |
| 710 | RE_CMD_STOPREQ | RE_CMD_TX_ENB | RE_CMD_RX_ENB); |
| 711 | DELAY(100); |
| 712 | } |
| 713 | |
| 714 | CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET); |
| 715 | |
| 716 | for (i = 0; i < RE_TIMEOUT; i++) { |
| 717 | DELAY(10); |
| 718 | if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0) |
| 719 | break; |
| 720 | } |
| 721 | if (i == RE_TIMEOUT) |
| 722 | if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); |
| 723 | } |
| 724 | |
| 725 | #ifdef RE_DIAG |
| 726 | /* |
| 727 | * The following routine is designed to test for a defect on some |
| 728 | * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# |
| 729 | * lines connected to the bus, however for a 32-bit only card, they |
| 730 | * should be pulled high. The result of this defect is that the |
| 731 | * NIC will not work right if you plug it into a 64-bit slot: DMA |
| 732 | * operations will be done with 64-bit transfers, which will fail |
| 733 | * because the 64-bit data lines aren't connected. |
| 734 | * |
| 735 | * There's no way to work around this (short of talking a soldering |
| 736 | * iron to the board), however we can detect it. The method we use |
| 737 | * here is to put the NIC into digital loopback mode, set the receiver |
| 738 | * to promiscuous mode, and then try to send a frame. We then compare |
| 739 | * the frame data we sent to what was received. If the data matches, |
| 740 | * then the NIC is working correctly, otherwise we know the user has |
| 741 | * a defective NIC which has been mistakenly plugged into a 64-bit PCI |
| 742 | * slot. In the latter case, there's no way the NIC can work correctly, |
| 743 | * so we print out a message on the console and abort the device attach. |
| 744 | */ |
| 745 | |
| 746 | static int |
| 747 | re_diag(struct re_softc *sc) |
| 748 | { |
| 749 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 750 | struct mbuf *m0; |
| 751 | struct ether_header *eh; |
| 752 | struct re_desc *cur_rx; |
| 753 | uint16_t status; |
| 754 | uint32_t rxstat; |
| 755 | int total_len, i, error = 0, phyaddr; |
| 756 | uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; |
| 757 | uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; |
| 758 | |
| 759 | /* Allocate a single mbuf */ |
| 760 | |
| 761 | MGETHDR(m0, MB_DONTWAIT, MT_DATA); |
| 762 | if (m0 == NULL) |
| 763 | return(ENOBUFS); |
| 764 | |
| 765 | /* |
| 766 | * Initialize the NIC in test mode. This sets the chip up |
| 767 | * so that it can send and receive frames, but performs the |
| 768 | * following special functions: |
| 769 | * - Puts receiver in promiscuous mode |
| 770 | * - Enables digital loopback mode |
| 771 | * - Leaves interrupts turned off |
| 772 | */ |
| 773 | |
| 774 | ifp->if_flags |= IFF_PROMISC; |
| 775 | sc->re_flags |= RE_F_TESTMODE; |
| 776 | re_init(sc); |
| 777 | sc->re_flags |= RE_F_LINKED; |
| 778 | if (!RE_IS_8139CP(sc)) |
| 779 | phyaddr = 1; |
| 780 | else |
| 781 | phyaddr = 0; |
| 782 | |
| 783 | re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET); |
| 784 | for (i = 0; i < RE_TIMEOUT; i++) { |
| 785 | status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR); |
| 786 | if (!(status & BMCR_RESET)) |
| 787 | break; |
| 788 | } |
| 789 | |
| 790 | re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP); |
| 791 | CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG); |
| 792 | |
| 793 | DELAY(100000); |
| 794 | |
| 795 | /* Put some data in the mbuf */ |
| 796 | |
| 797 | eh = mtod(m0, struct ether_header *); |
| 798 | bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN); |
| 799 | bcopy (src, eh->ether_shost, ETHER_ADDR_LEN); |
| 800 | eh->ether_type = htons(ETHERTYPE_IP); |
| 801 | m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; |
| 802 | |
| 803 | /* |
| 804 | * Queue the packet, start transmission. |
| 805 | * Note: ifq_handoff() ultimately calls re_start() for us. |
| 806 | */ |
| 807 | |
| 808 | CSR_WRITE_2(sc, RE_ISR, 0xFFFF); |
| 809 | error = ifq_handoff(ifp, m0, NULL); |
| 810 | if (error) { |
| 811 | m0 = NULL; |
| 812 | goto done; |
| 813 | } |
| 814 | m0 = NULL; |
| 815 | |
| 816 | /* Wait for it to propagate through the chip */ |
| 817 | |
| 818 | DELAY(100000); |
| 819 | for (i = 0; i < RE_TIMEOUT; i++) { |
| 820 | status = CSR_READ_2(sc, RE_ISR); |
| 821 | CSR_WRITE_2(sc, RE_ISR, status); |
| 822 | if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) == |
| 823 | (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) |
| 824 | break; |
| 825 | DELAY(10); |
| 826 | } |
| 827 | |
| 828 | if (i == RE_TIMEOUT) { |
| 829 | if_printf(ifp, "diagnostic failed to receive packet " |
| 830 | "in loopback mode\n"); |
| 831 | error = EIO; |
| 832 | goto done; |
| 833 | } |
| 834 | |
| 835 | /* |
| 836 | * The packet should have been dumped into the first |
| 837 | * entry in the RX DMA ring. Grab it from there. |
| 838 | */ |
| 839 | |
| 840 | bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, |
| 841 | sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); |
| 842 | bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0], |
| 843 | BUS_DMASYNC_POSTWRITE); |
| 844 | bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]); |
| 845 | |
| 846 | m0 = sc->re_ldata.re_rx_mbuf[0]; |
| 847 | sc->re_ldata.re_rx_mbuf[0] = NULL; |
| 848 | eh = mtod(m0, struct ether_header *); |
| 849 | |
| 850 | cur_rx = &sc->re_ldata.re_rx_list[0]; |
| 851 | total_len = RE_RXBYTES(cur_rx); |
| 852 | rxstat = le32toh(cur_rx->re_cmdstat); |
| 853 | |
| 854 | if (total_len != ETHER_MIN_LEN) { |
| 855 | if_printf(ifp, "diagnostic failed, received short packet\n"); |
| 856 | error = EIO; |
| 857 | goto done; |
| 858 | } |
| 859 | |
| 860 | /* Test that the received packet data matches what we sent. */ |
| 861 | |
| 862 | if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) || |
| 863 | bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) || |
| 864 | be16toh(eh->ether_type) != ETHERTYPE_IP) { |
| 865 | if_printf(ifp, "WARNING, DMA FAILURE!\n"); |
| 866 | if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n", |
| 867 | dst, ":", src, ":", ETHERTYPE_IP); |
| 868 | if_printf(ifp, "received RX data: %6D/%6D/0x%x\n", |
| 869 | eh->ether_dhost, ":", eh->ether_shost, ":", |
| 870 | ntohs(eh->ether_type)); |
| 871 | if_printf(ifp, "You may have a defective 32-bit NIC plugged " |
| 872 | "into a 64-bit PCI slot.\n"); |
| 873 | if_printf(ifp, "Please re-install the NIC in a 32-bit slot " |
| 874 | "for proper operation.\n"); |
| 875 | if_printf(ifp, "Read the re(4) man page for more details.\n"); |
| 876 | error = EIO; |
| 877 | } |
| 878 | |
| 879 | done: |
| 880 | /* Turn interface off, release resources */ |
| 881 | |
| 882 | sc->re_flags &= ~(RE_F_LINKED | RE_F_TESTMODE); |
| 883 | ifp->if_flags &= ~IFF_PROMISC; |
| 884 | re_stop(sc); |
| 885 | if (m0 != NULL) |
| 886 | m_freem(m0); |
| 887 | |
| 888 | return (error); |
| 889 | } |
| 890 | #endif /* RE_DIAG */ |
| 891 | |
| 892 | /* |
| 893 | * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device |
| 894 | * IDs against our list and return a device name if we find a match. |
| 895 | */ |
| 896 | static int |
| 897 | re_probe(device_t dev) |
| 898 | { |
| 899 | const struct re_type *t; |
| 900 | const struct re_hwrev *hw_rev; |
| 901 | struct re_softc *sc; |
| 902 | int rid; |
| 903 | uint32_t hwrev, macmode, txcfg; |
| 904 | uint16_t vendor, product; |
| 905 | |
| 906 | vendor = pci_get_vendor(dev); |
| 907 | product = pci_get_device(dev); |
| 908 | |
| 909 | /* |
| 910 | * Only attach to rev.3 of the Linksys EG1032 adapter. |
| 911 | * Rev.2 is supported by sk(4). |
| 912 | */ |
| 913 | if (vendor == PCI_VENDOR_LINKSYS && |
| 914 | product == PCI_PRODUCT_LINKSYS_EG1032 && |
| 915 | pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3) |
| 916 | return ENXIO; |
| 917 | |
| 918 | for (t = re_devs; t->re_name != NULL; t++) { |
| 919 | if (product == t->re_did && vendor == t->re_vid) |
| 920 | break; |
| 921 | } |
| 922 | |
| 923 | /* |
| 924 | * Check if we found a RealTek device. |
| 925 | */ |
| 926 | if (t->re_name == NULL) |
| 927 | return ENXIO; |
| 928 | |
| 929 | /* |
| 930 | * Temporarily map the I/O space so we can read the chip ID register. |
| 931 | */ |
| 932 | sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO); |
| 933 | rid = RE_PCI_LOIO; |
| 934 | sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, |
| 935 | RF_ACTIVE); |
| 936 | if (sc->re_res == NULL) { |
| 937 | device_printf(dev, "couldn't map ports/memory\n"); |
| 938 | kfree(sc, M_TEMP); |
| 939 | return ENXIO; |
| 940 | } |
| 941 | |
| 942 | sc->re_btag = rman_get_bustag(sc->re_res); |
| 943 | sc->re_bhandle = rman_get_bushandle(sc->re_res); |
| 944 | |
| 945 | txcfg = CSR_READ_4(sc, RE_TXCFG); |
| 946 | hwrev = txcfg & RE_TXCFG_HWREV; |
| 947 | macmode = txcfg & RE_TXCFG_MACMODE; |
| 948 | bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res); |
| 949 | kfree(sc, M_TEMP); |
| 950 | |
| 951 | /* |
| 952 | * and continue matching for the specific chip... |
| 953 | */ |
| 954 | for (hw_rev = re_hwrevs; hw_rev->re_hwrev != RE_HWREV_NULL; hw_rev++) { |
| 955 | if (hw_rev->re_hwrev == hwrev) { |
| 956 | sc = device_get_softc(dev); |
| 957 | |
| 958 | sc->re_hwrev = hw_rev->re_hwrev; |
| 959 | sc->re_macver = hw_rev->re_macver; |
| 960 | sc->re_caps = hw_rev->re_caps; |
| 961 | sc->re_maxmtu = hw_rev->re_maxmtu; |
| 962 | sc->re_swcsum_lim = RE_SWCSUM_UNLIMITED; |
| 963 | |
| 964 | /* |
| 965 | * Apply chip property fixup |
| 966 | */ |
| 967 | switch (sc->re_hwrev) { |
| 968 | case RE_HWREV_8169: |
| 969 | sc->re_swcsum_lim = RE_SWCSUM_LIM_8169; |
| 970 | break; |
| 971 | case RE_HWREV_8101E1: |
| 972 | case RE_HWREV_8101E2: |
| 973 | if (macmode == 0) |
| 974 | sc->re_macver = RE_MACVER_11; |
| 975 | else if (macmode == 0x200000) |
| 976 | sc->re_macver = RE_MACVER_12; |
| 977 | break; |
| 978 | case RE_HWREV_8102E: |
| 979 | case RE_HWREV_8102EL: |
| 980 | if (macmode == 0) |
| 981 | sc->re_macver = RE_MACVER_13; |
| 982 | else if (macmode == 0x100000) |
| 983 | sc->re_macver = RE_MACVER_14; |
| 984 | break; |
| 985 | case RE_HWREV_8168B2: |
| 986 | case RE_HWREV_8168B3: |
| 987 | if (macmode == 0) |
| 988 | sc->re_macver = RE_MACVER_22; |
| 989 | break; |
| 990 | case RE_HWREV_8168C: |
| 991 | if (macmode == 0) |
| 992 | sc->re_macver = RE_MACVER_24; |
| 993 | else if (macmode == 0x200000) |
| 994 | sc->re_macver = RE_MACVER_25; |
| 995 | else if (macmode == 0x300000) |
| 996 | sc->re_macver = RE_MACVER_27; |
| 997 | break; |
| 998 | case RE_HWREV_8168CP: |
| 999 | if (macmode == 0) |
| 1000 | sc->re_macver = RE_MACVER_26; |
| 1001 | else if (macmode == 0x100000) |
| 1002 | sc->re_macver = RE_MACVER_28; |
| 1003 | break; |
| 1004 | } |
| 1005 | if (pci_get_pciecap_ptr(dev) != 0) |
| 1006 | sc->re_caps |= RE_C_PCIE; |
| 1007 | |
| 1008 | device_set_desc(dev, t->re_name); |
| 1009 | return 0; |
| 1010 | } |
| 1011 | } |
| 1012 | device_printf(dev, "unknown hwrev 0x%08x, macmode 0x%08x\n", |
| 1013 | hwrev, macmode); |
| 1014 | return ENXIO; |
| 1015 | } |
| 1016 | |
| 1017 | static void |
| 1018 | re_dma_map_desc(void *xarg, bus_dma_segment_t *segs, int nsegs, |
| 1019 | bus_size_t mapsize, int error) |
| 1020 | { |
| 1021 | struct re_dmaload_arg *arg = xarg; |
| 1022 | int i; |
| 1023 | |
| 1024 | if (error) |
| 1025 | return; |
| 1026 | |
| 1027 | if (nsegs > arg->re_nsegs) { |
| 1028 | arg->re_nsegs = 0; |
| 1029 | return; |
| 1030 | } |
| 1031 | |
| 1032 | arg->re_nsegs = nsegs; |
| 1033 | for (i = 0; i < nsegs; ++i) |
| 1034 | arg->re_segs[i] = segs[i]; |
| 1035 | } |
| 1036 | |
| 1037 | /* |
| 1038 | * Map a single buffer address. |
| 1039 | */ |
| 1040 | |
| 1041 | static void |
| 1042 | re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) |
| 1043 | { |
| 1044 | uint32_t *addr; |
| 1045 | |
| 1046 | if (error) |
| 1047 | return; |
| 1048 | |
| 1049 | KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); |
| 1050 | addr = arg; |
| 1051 | *addr = segs->ds_addr; |
| 1052 | } |
| 1053 | |
| 1054 | static int |
| 1055 | re_allocmem(device_t dev) |
| 1056 | { |
| 1057 | struct re_softc *sc = device_get_softc(dev); |
| 1058 | int error, i; |
| 1059 | |
| 1060 | /* |
| 1061 | * Allocate list data |
| 1062 | */ |
| 1063 | sc->re_ldata.re_tx_mbuf = |
| 1064 | kmalloc(sc->re_tx_desc_cnt * sizeof(struct mbuf *), |
| 1065 | M_DEVBUF, M_ZERO | M_WAITOK); |
| 1066 | |
| 1067 | sc->re_ldata.re_rx_mbuf = |
| 1068 | kmalloc(sc->re_rx_desc_cnt * sizeof(struct mbuf *), |
| 1069 | M_DEVBUF, M_ZERO | M_WAITOK); |
| 1070 | |
| 1071 | sc->re_ldata.re_rx_paddr = |
| 1072 | kmalloc(sc->re_rx_desc_cnt * sizeof(bus_addr_t), |
| 1073 | M_DEVBUF, M_ZERO | M_WAITOK); |
| 1074 | |
| 1075 | sc->re_ldata.re_tx_dmamap = |
| 1076 | kmalloc(sc->re_tx_desc_cnt * sizeof(bus_dmamap_t), |
| 1077 | M_DEVBUF, M_ZERO | M_WAITOK); |
| 1078 | |
| 1079 | sc->re_ldata.re_rx_dmamap = |
| 1080 | kmalloc(sc->re_rx_desc_cnt * sizeof(bus_dmamap_t), |
| 1081 | M_DEVBUF, M_ZERO | M_WAITOK); |
| 1082 | |
| 1083 | /* |
| 1084 | * Allocate the parent bus DMA tag appropriate for PCI. |
| 1085 | */ |
| 1086 | error = bus_dma_tag_create(NULL, /* parent */ |
| 1087 | 1, 0, /* alignment, boundary */ |
| 1088 | BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ |
| 1089 | BUS_SPACE_MAXADDR, /* highaddr */ |
| 1090 | NULL, NULL, /* filter, filterarg */ |
| 1091 | MAXBSIZE, RE_MAXSEGS, /* maxsize, nsegments */ |
| 1092 | BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ |
| 1093 | BUS_DMA_ALLOCNOW, /* flags */ |
| 1094 | &sc->re_parent_tag); |
| 1095 | if (error) { |
| 1096 | device_printf(dev, "could not allocate parent dma tag\n"); |
| 1097 | return error; |
| 1098 | } |
| 1099 | |
| 1100 | /* Allocate tag for TX descriptor list. */ |
| 1101 | error = bus_dma_tag_create(sc->re_parent_tag, |
| 1102 | RE_RING_ALIGN, 0, |
| 1103 | BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, |
| 1104 | NULL, NULL, |
| 1105 | RE_TX_LIST_SZ(sc), 1, RE_TX_LIST_SZ(sc), |
| 1106 | BUS_DMA_ALLOCNOW, |
| 1107 | &sc->re_ldata.re_tx_list_tag); |
| 1108 | if (error) { |
| 1109 | device_printf(dev, "could not allocate TX ring dma tag\n"); |
| 1110 | return(error); |
| 1111 | } |
| 1112 | |
| 1113 | /* Allocate DMA'able memory for the TX ring */ |
| 1114 | error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag, |
| 1115 | (void **)&sc->re_ldata.re_tx_list, |
| 1116 | BUS_DMA_WAITOK | BUS_DMA_ZERO, |
| 1117 | &sc->re_ldata.re_tx_list_map); |
| 1118 | if (error) { |
| 1119 | device_printf(dev, "could not allocate TX ring\n"); |
| 1120 | bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); |
| 1121 | sc->re_ldata.re_tx_list_tag = NULL; |
| 1122 | return(error); |
| 1123 | } |
| 1124 | |
| 1125 | /* Load the map for the TX ring. */ |
| 1126 | error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag, |
| 1127 | sc->re_ldata.re_tx_list_map, |
| 1128 | sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc), |
| 1129 | re_dma_map_addr, &sc->re_ldata.re_tx_list_addr, |
| 1130 | BUS_DMA_NOWAIT); |
| 1131 | if (error) { |
| 1132 | device_printf(dev, "could not get address of TX ring\n"); |
| 1133 | bus_dmamem_free(sc->re_ldata.re_tx_list_tag, |
| 1134 | sc->re_ldata.re_tx_list, |
| 1135 | sc->re_ldata.re_tx_list_map); |
| 1136 | bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); |
| 1137 | sc->re_ldata.re_tx_list_tag = NULL; |
| 1138 | return(error); |
| 1139 | } |
| 1140 | |
| 1141 | /* Allocate tag for RX descriptor list. */ |
| 1142 | error = bus_dma_tag_create(sc->re_parent_tag, |
| 1143 | RE_RING_ALIGN, 0, |
| 1144 | BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, |
| 1145 | NULL, NULL, |
| 1146 | RE_RX_LIST_SZ(sc), 1, RE_RX_LIST_SZ(sc), |
| 1147 | BUS_DMA_ALLOCNOW, |
| 1148 | &sc->re_ldata.re_rx_list_tag); |
| 1149 | if (error) { |
| 1150 | device_printf(dev, "could not allocate RX ring dma tag\n"); |
| 1151 | return(error); |
| 1152 | } |
| 1153 | |
| 1154 | /* Allocate DMA'able memory for the RX ring */ |
| 1155 | error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag, |
| 1156 | (void **)&sc->re_ldata.re_rx_list, |
| 1157 | BUS_DMA_WAITOK | BUS_DMA_ZERO, |
| 1158 | &sc->re_ldata.re_rx_list_map); |
| 1159 | if (error) { |
| 1160 | device_printf(dev, "could not allocate RX ring\n"); |
| 1161 | bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); |
| 1162 | sc->re_ldata.re_rx_list_tag = NULL; |
| 1163 | return(error); |
| 1164 | } |
| 1165 | |
| 1166 | /* Load the map for the RX ring. */ |
| 1167 | error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag, |
| 1168 | sc->re_ldata.re_rx_list_map, |
| 1169 | sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc), |
| 1170 | re_dma_map_addr, &sc->re_ldata.re_rx_list_addr, |
| 1171 | BUS_DMA_NOWAIT); |
| 1172 | if (error) { |
| 1173 | device_printf(dev, "could not get address of RX ring\n"); |
| 1174 | bus_dmamem_free(sc->re_ldata.re_rx_list_tag, |
| 1175 | sc->re_ldata.re_rx_list, |
| 1176 | sc->re_ldata.re_rx_list_map); |
| 1177 | bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); |
| 1178 | sc->re_ldata.re_rx_list_tag = NULL; |
| 1179 | return(error); |
| 1180 | } |
| 1181 | |
| 1182 | /* Allocate map for RX/TX mbufs. */ |
| 1183 | error = bus_dma_tag_create(sc->re_parent_tag, |
| 1184 | ETHER_ALIGN, 0, |
| 1185 | BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, |
| 1186 | NULL, NULL, |
| 1187 | RE_FRAMELEN_MAX, RE_MAXSEGS, MCLBYTES, |
| 1188 | BUS_DMA_ALLOCNOW, |
| 1189 | &sc->re_ldata.re_mtag); |
| 1190 | if (error) { |
| 1191 | device_printf(dev, "could not allocate buf dma tag\n"); |
| 1192 | return(error); |
| 1193 | } |
| 1194 | |
| 1195 | /* Create spare DMA map for RX */ |
| 1196 | error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, |
| 1197 | &sc->re_ldata.re_rx_spare); |
| 1198 | if (error) { |
| 1199 | device_printf(dev, "can't create spare DMA map for RX\n"); |
| 1200 | bus_dma_tag_destroy(sc->re_ldata.re_mtag); |
| 1201 | sc->re_ldata.re_mtag = NULL; |
| 1202 | return error; |
| 1203 | } |
| 1204 | |
| 1205 | /* Create DMA maps for TX buffers */ |
| 1206 | for (i = 0; i < sc->re_tx_desc_cnt; i++) { |
| 1207 | error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, |
| 1208 | &sc->re_ldata.re_tx_dmamap[i]); |
| 1209 | if (error) { |
| 1210 | device_printf(dev, "can't create DMA map for TX buf\n"); |
| 1211 | re_freebufmem(sc, i, 0); |
| 1212 | return(error); |
| 1213 | } |
| 1214 | } |
| 1215 | |
| 1216 | /* Create DMA maps for RX buffers */ |
| 1217 | for (i = 0; i < sc->re_rx_desc_cnt; i++) { |
| 1218 | error = bus_dmamap_create(sc->re_ldata.re_mtag, 0, |
| 1219 | &sc->re_ldata.re_rx_dmamap[i]); |
| 1220 | if (error) { |
| 1221 | device_printf(dev, "can't create DMA map for RX buf\n"); |
| 1222 | re_freebufmem(sc, sc->re_tx_desc_cnt, i); |
| 1223 | return(error); |
| 1224 | } |
| 1225 | } |
| 1226 | |
| 1227 | /* Create jumbo buffer pool for RX if required */ |
| 1228 | if (sc->re_caps & RE_C_CONTIGRX) { |
| 1229 | error = re_jpool_alloc(sc); |
| 1230 | if (error) { |
| 1231 | re_jpool_free(sc); |
| 1232 | /* Disable jumbo frame support */ |
| 1233 | sc->re_maxmtu = ETHERMTU; |
| 1234 | } |
| 1235 | } |
| 1236 | return(0); |
| 1237 | } |
| 1238 | |
| 1239 | static void |
| 1240 | re_freebufmem(struct re_softc *sc, int tx_cnt, int rx_cnt) |
| 1241 | { |
| 1242 | int i; |
| 1243 | |
| 1244 | /* Destroy all the RX and TX buffer maps */ |
| 1245 | if (sc->re_ldata.re_mtag) { |
| 1246 | for (i = 0; i < tx_cnt; i++) { |
| 1247 | bus_dmamap_destroy(sc->re_ldata.re_mtag, |
| 1248 | sc->re_ldata.re_tx_dmamap[i]); |
| 1249 | } |
| 1250 | for (i = 0; i < rx_cnt; i++) { |
| 1251 | bus_dmamap_destroy(sc->re_ldata.re_mtag, |
| 1252 | sc->re_ldata.re_rx_dmamap[i]); |
| 1253 | } |
| 1254 | bus_dmamap_destroy(sc->re_ldata.re_mtag, |
| 1255 | sc->re_ldata.re_rx_spare); |
| 1256 | bus_dma_tag_destroy(sc->re_ldata.re_mtag); |
| 1257 | sc->re_ldata.re_mtag = NULL; |
| 1258 | } |
| 1259 | } |
| 1260 | |
| 1261 | static void |
| 1262 | re_freemem(device_t dev) |
| 1263 | { |
| 1264 | struct re_softc *sc = device_get_softc(dev); |
| 1265 | |
| 1266 | /* Unload and free the RX DMA ring memory and map */ |
| 1267 | if (sc->re_ldata.re_rx_list_tag) { |
| 1268 | bus_dmamap_unload(sc->re_ldata.re_rx_list_tag, |
| 1269 | sc->re_ldata.re_rx_list_map); |
| 1270 | bus_dmamem_free(sc->re_ldata.re_rx_list_tag, |
| 1271 | sc->re_ldata.re_rx_list, |
| 1272 | sc->re_ldata.re_rx_list_map); |
| 1273 | bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag); |
| 1274 | } |
| 1275 | |
| 1276 | /* Unload and free the TX DMA ring memory and map */ |
| 1277 | if (sc->re_ldata.re_tx_list_tag) { |
| 1278 | bus_dmamap_unload(sc->re_ldata.re_tx_list_tag, |
| 1279 | sc->re_ldata.re_tx_list_map); |
| 1280 | bus_dmamem_free(sc->re_ldata.re_tx_list_tag, |
| 1281 | sc->re_ldata.re_tx_list, |
| 1282 | sc->re_ldata.re_tx_list_map); |
| 1283 | bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag); |
| 1284 | } |
| 1285 | |
| 1286 | /* Free RX/TX buf DMA stuffs */ |
| 1287 | re_freebufmem(sc, sc->re_tx_desc_cnt, sc->re_rx_desc_cnt); |
| 1288 | |
| 1289 | /* Unload and free the stats buffer and map */ |
| 1290 | if (sc->re_ldata.re_stag) { |
| 1291 | bus_dmamap_unload(sc->re_ldata.re_stag, |
| 1292 | sc->re_ldata.re_rx_list_map); |
| 1293 | bus_dmamem_free(sc->re_ldata.re_stag, |
| 1294 | sc->re_ldata.re_stats, |
| 1295 | sc->re_ldata.re_smap); |
| 1296 | bus_dma_tag_destroy(sc->re_ldata.re_stag); |
| 1297 | } |
| 1298 | |
| 1299 | if (sc->re_caps & RE_C_CONTIGRX) |
| 1300 | re_jpool_free(sc); |
| 1301 | |
| 1302 | if (sc->re_parent_tag) |
| 1303 | bus_dma_tag_destroy(sc->re_parent_tag); |
| 1304 | |
| 1305 | if (sc->re_ldata.re_tx_mbuf != NULL) |
| 1306 | kfree(sc->re_ldata.re_tx_mbuf, M_DEVBUF); |
| 1307 | if (sc->re_ldata.re_rx_mbuf != NULL) |
| 1308 | kfree(sc->re_ldata.re_rx_mbuf, M_DEVBUF); |
| 1309 | if (sc->re_ldata.re_rx_paddr != NULL) |
| 1310 | kfree(sc->re_ldata.re_rx_paddr, M_DEVBUF); |
| 1311 | if (sc->re_ldata.re_tx_dmamap != NULL) |
| 1312 | kfree(sc->re_ldata.re_tx_dmamap, M_DEVBUF); |
| 1313 | if (sc->re_ldata.re_rx_dmamap != NULL) |
| 1314 | kfree(sc->re_ldata.re_rx_dmamap, M_DEVBUF); |
| 1315 | } |
| 1316 | |
| 1317 | /* |
| 1318 | * Attach the interface. Allocate softc structures, do ifmedia |
| 1319 | * setup and ethernet/BPF attach. |
| 1320 | */ |
| 1321 | static int |
| 1322 | re_attach(device_t dev) |
| 1323 | { |
| 1324 | struct re_softc *sc = device_get_softc(dev); |
| 1325 | struct ifnet *ifp; |
| 1326 | uint8_t eaddr[ETHER_ADDR_LEN]; |
| 1327 | int error = 0, rid, qlen; |
| 1328 | |
| 1329 | callout_init(&sc->re_timer); |
| 1330 | sc->re_dev = dev; |
| 1331 | |
| 1332 | if (RE_IS_8139CP(sc)) { |
| 1333 | sc->re_rx_desc_cnt = RE_RX_DESC_CNT_8139CP; |
| 1334 | sc->re_tx_desc_cnt = RE_TX_DESC_CNT_8139CP; |
| 1335 | } else { |
| 1336 | sc->re_rx_desc_cnt = re_rx_desc_count; |
| 1337 | if (sc->re_rx_desc_cnt > RE_RX_DESC_CNT_MAX) |
| 1338 | sc->re_rx_desc_cnt = RE_RX_DESC_CNT_MAX; |
| 1339 | |
| 1340 | sc->re_tx_desc_cnt = re_tx_desc_count; |
| 1341 | if (sc->re_tx_desc_cnt > RE_TX_DESC_CNT_MAX) |
| 1342 | sc->re_tx_desc_cnt = RE_TX_DESC_CNT_MAX; |
| 1343 | } |
| 1344 | |
| 1345 | qlen = RE_IFQ_MAXLEN; |
| 1346 | if (sc->re_tx_desc_cnt > qlen) |
| 1347 | qlen = sc->re_tx_desc_cnt; |
| 1348 | |
| 1349 | sc->re_rxbuf_size = MCLBYTES; |
| 1350 | sc->re_newbuf = re_newbuf_std; |
| 1351 | |
| 1352 | sc->re_tx_time = 5; /* 125us */ |
| 1353 | sc->re_rx_time = 2; /* 50us */ |
| 1354 | if (sc->re_caps & RE_C_PCIE) |
| 1355 | sc->re_sim_time = 75; /* 75us */ |
| 1356 | else |
| 1357 | sc->re_sim_time = 125; /* 125us */ |
| 1358 | sc->re_imtype = RE_IMTYPE_SIM; /* simulated interrupt moderation */ |
| 1359 | re_config_imtype(sc, sc->re_imtype); |
| 1360 | |
| 1361 | sysctl_ctx_init(&sc->re_sysctl_ctx); |
| 1362 | sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx, |
| 1363 | SYSCTL_STATIC_CHILDREN(_hw), |
| 1364 | OID_AUTO, |
| 1365 | device_get_nameunit(dev), |
| 1366 | CTLFLAG_RD, 0, ""); |
| 1367 | if (sc->re_sysctl_tree == NULL) { |
| 1368 | device_printf(dev, "can't add sysctl node\n"); |
| 1369 | error = ENXIO; |
| 1370 | goto fail; |
| 1371 | } |
| 1372 | SYSCTL_ADD_INT(&sc->re_sysctl_ctx, |
| 1373 | SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO, |
| 1374 | "rx_desc_count", CTLFLAG_RD, &sc->re_rx_desc_cnt, |
| 1375 | 0, "RX desc count"); |
| 1376 | SYSCTL_ADD_INT(&sc->re_sysctl_ctx, |
| 1377 | SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO, |
| 1378 | "tx_desc_count", CTLFLAG_RD, &sc->re_tx_desc_cnt, |
| 1379 | 0, "TX desc count"); |
| 1380 | SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, |
| 1381 | SYSCTL_CHILDREN(sc->re_sysctl_tree), |
| 1382 | OID_AUTO, "sim_time", |
| 1383 | CTLTYPE_INT | CTLFLAG_RW, |
| 1384 | sc, 0, re_sysctl_simtime, "I", |
| 1385 | "Simulated interrupt moderation time (usec)."); |
| 1386 | SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, |
| 1387 | SYSCTL_CHILDREN(sc->re_sysctl_tree), |
| 1388 | OID_AUTO, "imtype", |
| 1389 | CTLTYPE_INT | CTLFLAG_RW, |
| 1390 | sc, 0, re_sysctl_imtype, "I", |
| 1391 | "Interrupt moderation type -- " |
| 1392 | "0:disable, 1:simulated, " |
| 1393 | "2:hardware(if supported)"); |
| 1394 | if (sc->re_caps & RE_C_HWIM) { |
| 1395 | SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, |
| 1396 | SYSCTL_CHILDREN(sc->re_sysctl_tree), |
| 1397 | OID_AUTO, "hw_rxtime", |
| 1398 | CTLTYPE_INT | CTLFLAG_RW, |
| 1399 | sc, 0, re_sysctl_rxtime, "I", |
| 1400 | "Hardware interrupt moderation time " |
| 1401 | "(unit: 25usec)."); |
| 1402 | SYSCTL_ADD_PROC(&sc->re_sysctl_ctx, |
| 1403 | SYSCTL_CHILDREN(sc->re_sysctl_tree), |
| 1404 | OID_AUTO, "hw_txtime", |
| 1405 | CTLTYPE_INT | CTLFLAG_RW, |
| 1406 | sc, 0, re_sysctl_txtime, "I", |
| 1407 | "Hardware interrupt moderation time " |
| 1408 | "(unit: 25usec)."); |
| 1409 | } |
| 1410 | |
| 1411 | #ifndef BURN_BRIDGES |
| 1412 | /* |
| 1413 | * Handle power management nonsense. |
| 1414 | */ |
| 1415 | |
| 1416 | if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { |
| 1417 | uint32_t membase, irq; |
| 1418 | |
| 1419 | /* Save important PCI config data. */ |
| 1420 | membase = pci_read_config(dev, RE_PCI_LOMEM, 4); |
| 1421 | irq = pci_read_config(dev, PCIR_INTLINE, 4); |
| 1422 | |
| 1423 | /* Reset the power state. */ |
| 1424 | device_printf(dev, "chip is in D%d power mode " |
| 1425 | "-- setting to D0\n", pci_get_powerstate(dev)); |
| 1426 | |
| 1427 | pci_set_powerstate(dev, PCI_POWERSTATE_D0); |
| 1428 | |
| 1429 | /* Restore PCI config data. */ |
| 1430 | pci_write_config(dev, RE_PCI_LOMEM, membase, 4); |
| 1431 | pci_write_config(dev, PCIR_INTLINE, irq, 4); |
| 1432 | } |
| 1433 | #endif |
| 1434 | /* |
| 1435 | * Map control/status registers. |
| 1436 | */ |
| 1437 | pci_enable_busmaster(dev); |
| 1438 | |
| 1439 | rid = RE_PCI_LOIO; |
| 1440 | sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, |
| 1441 | RF_ACTIVE); |
| 1442 | |
| 1443 | if (sc->re_res == NULL) { |
| 1444 | device_printf(dev, "couldn't map ports\n"); |
| 1445 | error = ENXIO; |
| 1446 | goto fail; |
| 1447 | } |
| 1448 | |
| 1449 | sc->re_btag = rman_get_bustag(sc->re_res); |
| 1450 | sc->re_bhandle = rman_get_bushandle(sc->re_res); |
| 1451 | |
| 1452 | /* Allocate interrupt */ |
| 1453 | rid = 0; |
| 1454 | sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, |
| 1455 | RF_SHAREABLE | RF_ACTIVE); |
| 1456 | |
| 1457 | if (sc->re_irq == NULL) { |
| 1458 | device_printf(dev, "couldn't map interrupt\n"); |
| 1459 | error = ENXIO; |
| 1460 | goto fail; |
| 1461 | } |
| 1462 | |
| 1463 | /* Reset the adapter. */ |
| 1464 | re_reset(sc, 0); |
| 1465 | |
| 1466 | if (RE_IS_8139CP(sc)) { |
| 1467 | sc->re_bus_speed = 33; /* XXX */ |
| 1468 | } else if (sc->re_caps & RE_C_PCIE) { |
| 1469 | sc->re_bus_speed = 125; |
| 1470 | } else { |
| 1471 | uint8_t cfg2; |
| 1472 | |
| 1473 | cfg2 = CSR_READ_1(sc, RE_CFG2); |
| 1474 | switch (cfg2 & RE_CFG2_PCICLK_MASK) { |
| 1475 | case RE_CFG2_PCICLK_33MHZ: |
| 1476 | sc->re_bus_speed = 33; |
| 1477 | break; |
| 1478 | case RE_CFG2_PCICLK_66MHZ: |
| 1479 | sc->re_bus_speed = 66; |
| 1480 | break; |
| 1481 | default: |
| 1482 | device_printf(dev, "unknown bus speed, assume 33MHz\n"); |
| 1483 | sc->re_bus_speed = 33; |
| 1484 | break; |
| 1485 | } |
| 1486 | if (cfg2 & RE_CFG2_PCI64) |
| 1487 | sc->re_caps |= RE_C_PCI64; |
| 1488 | } |
| 1489 | device_printf(dev, "Hardware rev. 0x%08x; MAC ver. 0x%02x; " |
| 1490 | "PCI%s %dMHz\n", |
| 1491 | sc->re_hwrev, sc->re_macver, |
| 1492 | (sc->re_caps & RE_C_PCIE) ? |
| 1493 | "-E" : ((sc->re_caps & RE_C_PCI64) ? "64" : "32"), |
| 1494 | sc->re_bus_speed); |
| 1495 | |
| 1496 | /* |
| 1497 | * NOTE: |
| 1498 | * DO NOT try to adjust config1 and config5 which was spotted in |
| 1499 | * Realtek's Linux drivers. It will _permanently_ damage certain |
| 1500 | * cards EEPROM, e.g. one of my 8168B (0x38000000) card ... |
| 1501 | */ |
| 1502 | |
| 1503 | re_get_eaddr(sc, eaddr); |
| 1504 | |
| 1505 | if (!RE_IS_8139CP(sc)) { |
| 1506 | /* Set RX length mask */ |
| 1507 | sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; |
| 1508 | sc->re_txstart = RE_GTXSTART; |
| 1509 | } else { |
| 1510 | /* Set RX length mask */ |
| 1511 | sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; |
| 1512 | sc->re_txstart = RE_TXSTART; |
| 1513 | } |
| 1514 | |
| 1515 | /* Allocate DMA stuffs */ |
| 1516 | error = re_allocmem(dev); |
| 1517 | if (error) |
| 1518 | goto fail; |
| 1519 | |
| 1520 | /* |
| 1521 | * Apply some magic PCI settings from Realtek ... |
| 1522 | */ |
| 1523 | if (RE_IS_8169(sc)) { |
| 1524 | CSR_WRITE_1(sc, 0x82, 1); |
| 1525 | pci_write_config(dev, PCIR_CACHELNSZ, 0x8, 1); |
| 1526 | } |
| 1527 | pci_write_config(dev, PCIR_LATTIMER, 0x40, 1); |
| 1528 | |
| 1529 | if (sc->re_caps & RE_C_MAC2) { |
| 1530 | /* |
| 1531 | * Following part is extracted from Realtek BSD driver v176. |
| 1532 | * However, this does _not_ make much/any sense: |
| 1533 | * 8168C's PCI Express device control is located at 0x78, |
| 1534 | * so the reading from 0x79 (higher part of 0x78) and setting |
| 1535 | * the 4~6bits intend to enlarge the "max read request size" |
| 1536 | * (we will do it). The content of the rest part of this |
| 1537 | * register is not meaningful to other PCI registers, so |
| 1538 | * writing the value to 0x54 could be completely wrong. |
| 1539 | * 0x80 is the lower part of PCI Express device status, non- |
| 1540 | * reserved bits are RW1C, writing 0 to them will not have |
| 1541 | * any effect at all. |
| 1542 | */ |
| 1543 | #ifdef foo |
| 1544 | uint8_t val; |
| 1545 | |
| 1546 | val = pci_read_config(dev, 0x79, 1); |
| 1547 | val = (val & ~0x70) | 0x50; |
| 1548 | pci_write_config(dev, 0x54, val, 1); |
| 1549 | pci_write_config(dev, 0x80, 0, 1); |
| 1550 | #endif |
| 1551 | } |
| 1552 | |
| 1553 | /* |
| 1554 | * Apply some PHY fixup from Realtek ... |
| 1555 | */ |
| 1556 | if (sc->re_hwrev == RE_HWREV_8110S) { |
| 1557 | CSR_WRITE_1(sc, 0x82, 1); |
| 1558 | re_miibus_writereg(dev, 1, 0xb, 0); |
| 1559 | } |
| 1560 | if (sc->re_caps & RE_C_PHYPMGT) { |
| 1561 | /* Power up PHY */ |
| 1562 | re_miibus_writereg(dev, 1, 0x1f, 0); |
| 1563 | re_miibus_writereg(dev, 1, 0xe, 0); |
| 1564 | } |
| 1565 | |
| 1566 | /* Do MII setup */ |
| 1567 | if (mii_phy_probe(dev, &sc->re_miibus, |
| 1568 | re_ifmedia_upd, re_ifmedia_sts)) { |
| 1569 | device_printf(dev, "MII without any phy!\n"); |
| 1570 | error = ENXIO; |
| 1571 | goto fail; |
| 1572 | } |
| 1573 | |
| 1574 | ifp = &sc->arpcom.ac_if; |
| 1575 | ifp->if_softc = sc; |
| 1576 | if_initname(ifp, device_get_name(dev), device_get_unit(dev)); |
| 1577 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; |
| 1578 | ifp->if_ioctl = re_ioctl; |
| 1579 | ifp->if_start = re_start; |
| 1580 | #ifdef DEVICE_POLLING |
| 1581 | ifp->if_poll = re_poll; |
| 1582 | #endif |
| 1583 | ifp->if_watchdog = re_watchdog; |
| 1584 | ifp->if_init = re_init; |
| 1585 | if (!RE_IS_8139CP(sc)) /* XXX */ |
| 1586 | ifp->if_baudrate = 1000000000; |
| 1587 | else |
| 1588 | ifp->if_baudrate = 100000000; |
| 1589 | ifq_set_maxlen(&ifp->if_snd, qlen); |
| 1590 | ifq_set_ready(&ifp->if_snd); |
| 1591 | |
| 1592 | ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; |
| 1593 | if (sc->re_caps & RE_C_HWCSUM) |
| 1594 | ifp->if_capabilities |= IFCAP_HWCSUM; |
| 1595 | |
| 1596 | ifp->if_capenable = ifp->if_capabilities; |
| 1597 | if (ifp->if_capabilities & IFCAP_HWCSUM) |
| 1598 | ifp->if_hwassist = RE_CSUM_FEATURES; |
| 1599 | else |
| 1600 | ifp->if_hwassist = 0; |
| 1601 | |
| 1602 | /* |
| 1603 | * Call MI attach routine. |
| 1604 | */ |
| 1605 | ether_ifattach(ifp, eaddr, NULL); |
| 1606 | |
| 1607 | #ifdef RE_DIAG |
| 1608 | /* |
| 1609 | * Perform hardware diagnostic on the original RTL8169. |
| 1610 | * Some 32-bit cards were incorrectly wired and would |
| 1611 | * malfunction if plugged into a 64-bit slot. |
| 1612 | */ |
| 1613 | if (sc->re_hwrev == RE_HWREV_8169) { |
| 1614 | lwkt_serialize_enter(ifp->if_serializer); |
| 1615 | error = re_diag(sc); |
| 1616 | lwkt_serialize_exit(ifp->if_serializer); |
| 1617 | |
| 1618 | if (error) { |
| 1619 | device_printf(dev, "hardware diagnostic failure\n"); |
| 1620 | ether_ifdetach(ifp); |
| 1621 | goto fail; |
| 1622 | } |
| 1623 | } |
| 1624 | #endif /* RE_DIAG */ |
| 1625 | |
| 1626 | /* Hook interrupt last to avoid having to lock softc */ |
| 1627 | error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc, |
| 1628 | &sc->re_intrhand, ifp->if_serializer); |
| 1629 | |
| 1630 | if (error) { |
| 1631 | device_printf(dev, "couldn't set up irq\n"); |
| 1632 | ether_ifdetach(ifp); |
| 1633 | goto fail; |
| 1634 | } |
| 1635 | |
| 1636 | ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->re_irq)); |
| 1637 | KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); |
| 1638 | |
| 1639 | fail: |
| 1640 | if (error) |
| 1641 | re_detach(dev); |
| 1642 | |
| 1643 | return (error); |
| 1644 | } |
| 1645 | |
| 1646 | /* |
| 1647 | * Shutdown hardware and free up resources. This can be called any |
| 1648 | * time after the mutex has been initialized. It is called in both |
| 1649 | * the error case in attach and the normal detach case so it needs |
| 1650 | * to be careful about only freeing resources that have actually been |
| 1651 | * allocated. |
| 1652 | */ |
| 1653 | static int |
| 1654 | re_detach(device_t dev) |
| 1655 | { |
| 1656 | struct re_softc *sc = device_get_softc(dev); |
| 1657 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 1658 | |
| 1659 | /* These should only be active if attach succeeded */ |
| 1660 | if (device_is_attached(dev)) { |
| 1661 | lwkt_serialize_enter(ifp->if_serializer); |
| 1662 | re_stop(sc); |
| 1663 | bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand); |
| 1664 | lwkt_serialize_exit(ifp->if_serializer); |
| 1665 | |
| 1666 | ether_ifdetach(ifp); |
| 1667 | } |
| 1668 | if (sc->re_miibus) |
| 1669 | device_delete_child(dev, sc->re_miibus); |
| 1670 | bus_generic_detach(dev); |
| 1671 | |
| 1672 | if (sc->re_sysctl_tree != NULL) |
| 1673 | sysctl_ctx_free(&sc->re_sysctl_ctx); |
| 1674 | |
| 1675 | if (sc->re_irq) |
| 1676 | bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq); |
| 1677 | if (sc->re_res) { |
| 1678 | bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, |
| 1679 | sc->re_res); |
| 1680 | } |
| 1681 | |
| 1682 | /* Free DMA stuffs */ |
| 1683 | re_freemem(dev); |
| 1684 | |
| 1685 | return(0); |
| 1686 | } |
| 1687 | |
| 1688 | static void |
| 1689 | re_setup_rxdesc(struct re_softc *sc, int idx) |
| 1690 | { |
| 1691 | bus_addr_t paddr; |
| 1692 | uint32_t cmdstat; |
| 1693 | struct re_desc *d; |
| 1694 | |
| 1695 | paddr = sc->re_ldata.re_rx_paddr[idx]; |
| 1696 | d = &sc->re_ldata.re_rx_list[idx]; |
| 1697 | |
| 1698 | d->re_bufaddr_lo = htole32(RE_ADDR_LO(paddr)); |
| 1699 | d->re_bufaddr_hi = htole32(RE_ADDR_HI(paddr)); |
| 1700 | |
| 1701 | cmdstat = sc->re_rxbuf_size | RE_RDESC_CMD_OWN; |
| 1702 | if (idx == (sc->re_rx_desc_cnt - 1)) |
| 1703 | cmdstat |= RE_RDESC_CMD_EOR; |
| 1704 | d->re_cmdstat = htole32(cmdstat); |
| 1705 | } |
| 1706 | |
| 1707 | static int |
| 1708 | re_newbuf_std(struct re_softc *sc, int idx, int init) |
| 1709 | { |
| 1710 | struct re_dmaload_arg arg; |
| 1711 | bus_dma_segment_t seg; |
| 1712 | bus_dmamap_t map; |
| 1713 | struct mbuf *m; |
| 1714 | int error; |
| 1715 | |
| 1716 | m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR); |
| 1717 | if (m == NULL) { |
| 1718 | error = ENOBUFS; |
| 1719 | |
| 1720 | if (init) { |
| 1721 | if_printf(&sc->arpcom.ac_if, "m_getcl failed\n"); |
| 1722 | return error; |
| 1723 | } else { |
| 1724 | goto back; |
| 1725 | } |
| 1726 | } |
| 1727 | m->m_len = m->m_pkthdr.len = MCLBYTES; |
| 1728 | |
| 1729 | /* |
| 1730 | * NOTE: |
| 1731 | * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer |
| 1732 | * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here. |
| 1733 | */ |
| 1734 | |
| 1735 | arg.re_nsegs = 1; |
| 1736 | arg.re_segs = &seg; |
| 1737 | error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, |
| 1738 | sc->re_ldata.re_rx_spare, m, |
| 1739 | re_dma_map_desc, &arg, BUS_DMA_NOWAIT); |
| 1740 | if (error || arg.re_nsegs == 0) { |
| 1741 | if (!error) { |
| 1742 | if_printf(&sc->arpcom.ac_if, "too many segments?!\n"); |
| 1743 | bus_dmamap_unload(sc->re_ldata.re_mtag, |
| 1744 | sc->re_ldata.re_rx_spare); |
| 1745 | error = EFBIG; |
| 1746 | } |
| 1747 | m_freem(m); |
| 1748 | |
| 1749 | if (init) { |
| 1750 | if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n"); |
| 1751 | return error; |
| 1752 | } else { |
| 1753 | goto back; |
| 1754 | } |
| 1755 | } |
| 1756 | |
| 1757 | if (!init) { |
| 1758 | bus_dmamap_sync(sc->re_ldata.re_mtag, |
| 1759 | sc->re_ldata.re_rx_dmamap[idx], |
| 1760 | BUS_DMASYNC_POSTREAD); |
| 1761 | bus_dmamap_unload(sc->re_ldata.re_mtag, |
| 1762 | sc->re_ldata.re_rx_dmamap[idx]); |
| 1763 | } |
| 1764 | sc->re_ldata.re_rx_mbuf[idx] = m; |
| 1765 | sc->re_ldata.re_rx_paddr[idx] = seg.ds_addr; |
| 1766 | |
| 1767 | map = sc->re_ldata.re_rx_dmamap[idx]; |
| 1768 | sc->re_ldata.re_rx_dmamap[idx] = sc->re_ldata.re_rx_spare; |
| 1769 | sc->re_ldata.re_rx_spare = map; |
| 1770 | back: |
| 1771 | re_setup_rxdesc(sc, idx); |
| 1772 | return error; |
| 1773 | } |
| 1774 | |
| 1775 | static int |
| 1776 | re_newbuf_jumbo(struct re_softc *sc, int idx, int init) |
| 1777 | { |
| 1778 | struct mbuf *m; |
| 1779 | struct re_jbuf *jbuf; |
| 1780 | int error = 0; |
| 1781 | |
| 1782 | MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA); |
| 1783 | if (m == NULL) { |
| 1784 | error = ENOBUFS; |
| 1785 | if (init) { |
| 1786 | if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n"); |
| 1787 | return error; |
| 1788 | } else { |
| 1789 | goto back; |
| 1790 | } |
| 1791 | } |
| 1792 | |
| 1793 | jbuf = re_jbuf_alloc(sc); |
| 1794 | if (jbuf == NULL) { |
| 1795 | m_freem(m); |
| 1796 | |
| 1797 | error = ENOBUFS; |
| 1798 | if (init) { |
| 1799 | if_printf(&sc->arpcom.ac_if, "jpool is empty\n"); |
| 1800 | return error; |
| 1801 | } else { |
| 1802 | goto back; |
| 1803 | } |
| 1804 | } |
| 1805 | |
| 1806 | m->m_ext.ext_arg = jbuf; |
| 1807 | m->m_ext.ext_buf = jbuf->re_buf; |
| 1808 | m->m_ext.ext_free = re_jbuf_free; |
| 1809 | m->m_ext.ext_ref = re_jbuf_ref; |
| 1810 | m->m_ext.ext_size = sc->re_rxbuf_size; |
| 1811 | |
| 1812 | m->m_data = m->m_ext.ext_buf; |
| 1813 | m->m_flags |= M_EXT; |
| 1814 | m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; |
| 1815 | |
| 1816 | /* |
| 1817 | * NOTE: |
| 1818 | * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer |
| 1819 | * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here. |
| 1820 | */ |
| 1821 | |
| 1822 | sc->re_ldata.re_rx_mbuf[idx] = m; |
| 1823 | sc->re_ldata.re_rx_paddr[idx] = jbuf->re_paddr; |
| 1824 | back: |
| 1825 | re_setup_rxdesc(sc, idx); |
| 1826 | return error; |
| 1827 | } |
| 1828 | |
| 1829 | static int |
| 1830 | re_tx_list_init(struct re_softc *sc) |
| 1831 | { |
| 1832 | bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); |
| 1833 | |
| 1834 | /* Flush the TX descriptors */ |
| 1835 | bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, |
| 1836 | sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE); |
| 1837 | |
| 1838 | sc->re_ldata.re_tx_prodidx = 0; |
| 1839 | sc->re_ldata.re_tx_considx = 0; |
| 1840 | sc->re_ldata.re_tx_free = sc->re_tx_desc_cnt; |
| 1841 | |
| 1842 | return(0); |
| 1843 | } |
| 1844 | |
| 1845 | static int |
| 1846 | re_rx_list_init(struct re_softc *sc) |
| 1847 | { |
| 1848 | int i, error; |
| 1849 | |
| 1850 | bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc)); |
| 1851 | |
| 1852 | for (i = 0; i < sc->re_rx_desc_cnt; i++) { |
| 1853 | error = sc->re_newbuf(sc, i, 1); |
| 1854 | if (error) |
| 1855 | return(error); |
| 1856 | } |
| 1857 | |
| 1858 | /* Flush the RX descriptors */ |
| 1859 | bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, |
| 1860 | sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE); |
| 1861 | |
| 1862 | sc->re_ldata.re_rx_prodidx = 0; |
| 1863 | sc->re_head = sc->re_tail = NULL; |
| 1864 | |
| 1865 | return(0); |
| 1866 | } |
| 1867 | |
| 1868 | #define RE_IP4_PACKET 0x1 |
| 1869 | #define RE_TCP_PACKET 0x2 |
| 1870 | #define RE_UDP_PACKET 0x4 |
| 1871 | |
| 1872 | static __inline uint8_t |
| 1873 | re_packet_type(struct re_softc *sc, uint32_t rxstat, uint32_t rxctrl) |
| 1874 | { |
| 1875 | uint8_t packet_type = 0; |
| 1876 | |
| 1877 | if (sc->re_caps & RE_C_MAC2) { |
| 1878 | if (rxctrl & RE_RDESC_CTL_PROTOIP4) |
| 1879 | packet_type |= RE_IP4_PACKET; |
| 1880 | } else { |
| 1881 | if (rxstat & RE_RDESC_STAT_PROTOID) |
| 1882 | packet_type |= RE_IP4_PACKET; |
| 1883 | } |
| 1884 | if (RE_TCPPKT(rxstat)) |
| 1885 | packet_type |= RE_TCP_PACKET; |
| 1886 | else if (RE_UDPPKT(rxstat)) |
| 1887 | packet_type |= RE_UDP_PACKET; |
| 1888 | return packet_type; |
| 1889 | } |
| 1890 | |
| 1891 | /* |
| 1892 | * RX handler for C+ and 8169. For the gigE chips, we support |
| 1893 | * the reception of jumbo frames that have been fragmented |
| 1894 | * across multiple 2K mbuf cluster buffers. |
| 1895 | */ |
| 1896 | static int |
| 1897 | re_rxeof(struct re_softc *sc) |
| 1898 | { |
| 1899 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 1900 | struct mbuf *m; |
| 1901 | struct re_desc *cur_rx; |
| 1902 | uint32_t rxstat, rxctrl; |
| 1903 | int i, total_len, rx = 0; |
| 1904 | struct mbuf_chain chain[MAXCPU]; |
| 1905 | |
| 1906 | /* Invalidate the descriptor memory */ |
| 1907 | |
| 1908 | bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, |
| 1909 | sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD); |
| 1910 | |
| 1911 | ether_input_chain_init(chain); |
| 1912 | |
| 1913 | for (i = sc->re_ldata.re_rx_prodidx; |
| 1914 | RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0; RE_RXDESC_INC(sc, i)) { |
| 1915 | cur_rx = &sc->re_ldata.re_rx_list[i]; |
| 1916 | m = sc->re_ldata.re_rx_mbuf[i]; |
| 1917 | total_len = RE_RXBYTES(cur_rx); |
| 1918 | rxstat = le32toh(cur_rx->re_cmdstat); |
| 1919 | rxctrl = le32toh(cur_rx->re_control); |
| 1920 | |
| 1921 | rx = 1; |
| 1922 | |
| 1923 | #ifdef INVARIANTS |
| 1924 | if (sc->re_flags & RE_F_USE_JPOOL) |
| 1925 | KKASSERT(rxstat & RE_RDESC_STAT_EOF); |
| 1926 | #endif |
| 1927 | |
| 1928 | if ((rxstat & RE_RDESC_STAT_EOF) == 0) { |
| 1929 | if (sc->re_flags & RE_F_DROP_RXFRAG) { |
| 1930 | re_setup_rxdesc(sc, i); |
| 1931 | continue; |
| 1932 | } |
| 1933 | |
| 1934 | if (sc->re_newbuf(sc, i, 0)) { |
| 1935 | /* Drop upcoming fragments */ |
| 1936 | sc->re_flags |= RE_F_DROP_RXFRAG; |
| 1937 | continue; |
| 1938 | } |
| 1939 | |
| 1940 | m->m_len = MCLBYTES; |
| 1941 | if (sc->re_head == NULL) { |
| 1942 | sc->re_head = sc->re_tail = m; |
| 1943 | } else { |
| 1944 | sc->re_tail->m_next = m; |
| 1945 | sc->re_tail = m; |
| 1946 | } |
| 1947 | continue; |
| 1948 | } else if (sc->re_flags & RE_F_DROP_RXFRAG) { |
| 1949 | /* |
| 1950 | * Last fragment of a multi-fragment packet. |
| 1951 | * |
| 1952 | * Since error already happened, this fragment |
| 1953 | * must be dropped as well as the fragment chain. |
| 1954 | */ |
| 1955 | re_setup_rxdesc(sc, i); |
| 1956 | re_free_rxchain(sc); |
| 1957 | sc->re_flags &= ~RE_F_DROP_RXFRAG; |
| 1958 | continue; |
| 1959 | } |
| 1960 | |
| 1961 | /* |
| 1962 | * NOTE: for the 8139C+, the frame length field |
| 1963 | * is always 12 bits in size, but for the gigE chips, |
| 1964 | * it is 13 bits (since the max RX frame length is 16K). |
| 1965 | * Unfortunately, all 32 bits in the status word |
| 1966 | * were already used, so to make room for the extra |
| 1967 | * length bit, RealTek took out the 'frame alignment |
| 1968 | * error' bit and shifted the other status bits |
| 1969 | * over one slot. The OWN, EOR, FS and LS bits are |
| 1970 | * still in the same places. We have already extracted |
| 1971 | * the frame length and checked the OWN bit, so rather |
| 1972 | * than using an alternate bit mapping, we shift the |
| 1973 | * status bits one space to the right so we can evaluate |
| 1974 | * them using the 8169 status as though it was in the |
| 1975 | * same format as that of the 8139C+. |
| 1976 | */ |
| 1977 | if (!RE_IS_8139CP(sc)) |
| 1978 | rxstat >>= 1; |
| 1979 | |
| 1980 | if (rxstat & RE_RDESC_STAT_RXERRSUM) { |
| 1981 | ifp->if_ierrors++; |
| 1982 | /* |
| 1983 | * If this is part of a multi-fragment packet, |
| 1984 | * discard all the pieces. |
| 1985 | */ |
| 1986 | re_free_rxchain(sc); |
| 1987 | re_setup_rxdesc(sc, i); |
| 1988 | continue; |
| 1989 | } |
| 1990 | |
| 1991 | /* |
| 1992 | * If allocating a replacement mbuf fails, |
| 1993 | * reload the current one. |
| 1994 | */ |
| 1995 | |
| 1996 | if (sc->re_newbuf(sc, i, 0)) { |
| 1997 | ifp->if_ierrors++; |
| 1998 | continue; |
| 1999 | } |
| 2000 | |
| 2001 | if (sc->re_head != NULL) { |
| 2002 | m->m_len = total_len % MCLBYTES; |
| 2003 | /* |
| 2004 | * Special case: if there's 4 bytes or less |
| 2005 | * in this buffer, the mbuf can be discarded: |
| 2006 | * the last 4 bytes is the CRC, which we don't |
| 2007 | * care about anyway. |
| 2008 | */ |
| 2009 | if (m->m_len <= ETHER_CRC_LEN) { |
| 2010 | sc->re_tail->m_len -= |
| 2011 | (ETHER_CRC_LEN - m->m_len); |
| 2012 | m_freem(m); |
| 2013 | } else { |
| 2014 | m->m_len -= ETHER_CRC_LEN; |
| 2015 | sc->re_tail->m_next = m; |
| 2016 | } |
| 2017 | m = sc->re_head; |
| 2018 | sc->re_head = sc->re_tail = NULL; |
| 2019 | m->m_pkthdr.len = total_len - ETHER_CRC_LEN; |
| 2020 | } else { |
| 2021 | m->m_pkthdr.len = m->m_len = |
| 2022 | (total_len - ETHER_CRC_LEN); |
| 2023 | } |
| 2024 | |
| 2025 | ifp->if_ipackets++; |
| 2026 | m->m_pkthdr.rcvif = ifp; |
| 2027 | |
| 2028 | /* Do RX checksumming if enabled */ |
| 2029 | |
| 2030 | if (ifp->if_capenable & IFCAP_RXCSUM) { |
| 2031 | uint8_t packet_type; |
| 2032 | |
| 2033 | packet_type = re_packet_type(sc, rxstat, rxctrl); |
| 2034 | |
| 2035 | /* Check IP header checksum */ |
| 2036 | if (packet_type & RE_IP4_PACKET) { |
| 2037 | m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; |
| 2038 | if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0) |
| 2039 | m->m_pkthdr.csum_flags |= CSUM_IP_VALID; |
| 2040 | } |
| 2041 | |
| 2042 | /* Check TCP/UDP checksum */ |
| 2043 | if (((packet_type & RE_TCP_PACKET) && |
| 2044 | (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) || |
| 2045 | ((packet_type & RE_UDP_PACKET) && |
| 2046 | (rxstat & RE_RDESC_STAT_UDPSUMBAD) == 0)) { |
| 2047 | m->m_pkthdr.csum_flags |= |
| 2048 | CSUM_DATA_VALID|CSUM_PSEUDO_HDR| |
| 2049 | CSUM_FRAG_NOT_CHECKED; |
| 2050 | m->m_pkthdr.csum_data = 0xffff; |
| 2051 | } |
| 2052 | } |
| 2053 | |
| 2054 | if (rxctrl & RE_RDESC_CTL_HASTAG) { |
| 2055 | m->m_flags |= M_VLANTAG; |
| 2056 | m->m_pkthdr.ether_vlantag = |
| 2057 | be16toh((rxctrl & RE_RDESC_CTL_TAGDATA)); |
| 2058 | } |
| 2059 | ether_input_chain(ifp, m, chain); |
| 2060 | } |
| 2061 | |
| 2062 | ether_input_dispatch(chain); |
| 2063 | |
| 2064 | /* Flush the RX DMA ring */ |
| 2065 | |
| 2066 | bus_dmamap_sync(sc->re_ldata.re_rx_list_tag, |
| 2067 | sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE); |
| 2068 | |
| 2069 | sc->re_ldata.re_rx_prodidx = i; |
| 2070 | |
| 2071 | return rx; |
| 2072 | } |
| 2073 | |
| 2074 | #undef RE_IP4_PACKET |
| 2075 | #undef RE_TCP_PACKET |
| 2076 | #undef RE_UDP_PACKET |
| 2077 | |
| 2078 | static int |
| 2079 | re_tx_collect(struct re_softc *sc) |
| 2080 | { |
| 2081 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 2082 | uint32_t txstat; |
| 2083 | int idx, tx = 0; |
| 2084 | |
| 2085 | /* Invalidate the TX descriptor list */ |
| 2086 | bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, |
| 2087 | sc->re_ldata.re_tx_list_map, BUS_DMASYNC_POSTREAD); |
| 2088 | |
| 2089 | for (idx = sc->re_ldata.re_tx_considx; |
| 2090 | sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt; |
| 2091 | RE_TXDESC_INC(sc, idx)) { |
| 2092 | txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat); |
| 2093 | if (txstat & RE_TDESC_CMD_OWN) |
| 2094 | break; |
| 2095 | |
| 2096 | tx = 1; |
| 2097 | |
| 2098 | sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0; |
| 2099 | |
| 2100 | /* |
| 2101 | * We only stash mbufs in the last descriptor |
| 2102 | * in a fragment chain, which also happens to |
| 2103 | * be the only place where the TX status bits |
| 2104 | * are valid. |
| 2105 | */ |
| 2106 | if (txstat & RE_TDESC_CMD_EOF) { |
| 2107 | m_freem(sc->re_ldata.re_tx_mbuf[idx]); |
| 2108 | sc->re_ldata.re_tx_mbuf[idx] = NULL; |
| 2109 | bus_dmamap_unload(sc->re_ldata.re_mtag, |
| 2110 | sc->re_ldata.re_tx_dmamap[idx]); |
| 2111 | if (txstat & (RE_TDESC_STAT_EXCESSCOL| |
| 2112 | RE_TDESC_STAT_COLCNT)) |
| 2113 | ifp->if_collisions++; |
| 2114 | if (txstat & RE_TDESC_STAT_TXERRSUM) |
| 2115 | ifp->if_oerrors++; |
| 2116 | else |
| 2117 | ifp->if_opackets++; |
| 2118 | } |
| 2119 | sc->re_ldata.re_tx_free++; |
| 2120 | } |
| 2121 | sc->re_ldata.re_tx_considx = idx; |
| 2122 | |
| 2123 | return tx; |
| 2124 | } |
| 2125 | |
| 2126 | static int |
| 2127 | re_txeof(struct re_softc *sc) |
| 2128 | { |
| 2129 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 2130 | int tx; |
| 2131 | |
| 2132 | tx = re_tx_collect(sc); |
| 2133 | |
| 2134 | /* There is enough free TX descs */ |
| 2135 | if (sc->re_ldata.re_tx_free > RE_TXDESC_SPARE) |
| 2136 | ifp->if_flags &= ~IFF_OACTIVE; |
| 2137 | |
| 2138 | /* |
| 2139 | * Some chips will ignore a second TX request issued while an |
| 2140 | * existing transmission is in progress. If the transmitter goes |
| 2141 | * idle but there are still packets waiting to be sent, we need |
| 2142 | * to restart the channel here to flush them out. This only seems |
| 2143 | * to be required with the PCIe devices. |
| 2144 | */ |
| 2145 | if (sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt) |
| 2146 | CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); |
| 2147 | else |
| 2148 | ifp->if_timer = 0; |
| 2149 | |
| 2150 | return tx; |
| 2151 | } |
| 2152 | |
| 2153 | static void |
| 2154 | re_tick(void *xsc) |
| 2155 | { |
| 2156 | struct re_softc *sc = xsc; |
| 2157 | |
| 2158 | lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer); |
| 2159 | re_tick_serialized(xsc); |
| 2160 | lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer); |
| 2161 | } |
| 2162 | |
| 2163 | static void |
| 2164 | re_tick_serialized(void *xsc) |
| 2165 | { |
| 2166 | struct re_softc *sc = xsc; |
| 2167 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 2168 | struct mii_data *mii; |
| 2169 | |
| 2170 | ASSERT_SERIALIZED(ifp->if_serializer); |
| 2171 | |
| 2172 | mii = device_get_softc(sc->re_miibus); |
| 2173 | mii_tick(mii); |
| 2174 | if (sc->re_flags & RE_F_LINKED) { |
| 2175 | if (!(mii->mii_media_status & IFM_ACTIVE)) |
| 2176 | sc->re_flags &= ~RE_F_LINKED; |
| 2177 | } else { |
| 2178 | if (mii->mii_media_status & IFM_ACTIVE && |
| 2179 | IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { |
| 2180 | sc->re_flags |= RE_F_LINKED; |
| 2181 | if (!ifq_is_empty(&ifp->if_snd)) |
| 2182 | if_devstart(ifp); |
| 2183 | } |
| 2184 | } |
| 2185 | |
| 2186 | callout_reset(&sc->re_timer, hz, re_tick, sc); |
| 2187 | } |
| 2188 | |
| 2189 | #ifdef DEVICE_POLLING |
| 2190 | |
| 2191 | static void |
| 2192 | re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) |
| 2193 | { |
| 2194 | struct re_softc *sc = ifp->if_softc; |
| 2195 | |
| 2196 | ASSERT_SERIALIZED(ifp->if_serializer); |
| 2197 | |
| 2198 | switch(cmd) { |
| 2199 | case POLL_REGISTER: |
| 2200 | /* disable interrupts */ |
| 2201 | re_setup_intr(sc, 0, RE_IMTYPE_NONE); |
| 2202 | break; |
| 2203 | |
| 2204 | case POLL_DEREGISTER: |
| 2205 | /* enable interrupts */ |
| 2206 | re_setup_intr(sc, 1, sc->re_imtype); |
| 2207 | break; |
| 2208 | |
| 2209 | default: |
| 2210 | sc->rxcycles = count; |
| 2211 | re_rxeof(sc); |
| 2212 | re_txeof(sc); |
| 2213 | |
| 2214 | if (!ifq_is_empty(&ifp->if_snd)) |
| 2215 | if_devstart(ifp); |
| 2216 | |
| 2217 | if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ |
| 2218 | uint16_t status; |
| 2219 | |
| 2220 | status = CSR_READ_2(sc, RE_ISR); |
| 2221 | if (status == 0xffff) |
| 2222 | return; |
| 2223 | if (status) |
| 2224 | CSR_WRITE_2(sc, RE_ISR, status); |
| 2225 | |
| 2226 | /* |
| 2227 | * XXX check behaviour on receiver stalls. |
| 2228 | */ |
| 2229 | |
| 2230 | if (status & RE_ISR_SYSTEM_ERR) |
| 2231 | re_init(sc); |
| 2232 | } |
| 2233 | break; |
| 2234 | } |
| 2235 | } |
| 2236 | #endif /* DEVICE_POLLING */ |
| 2237 | |
| 2238 | static void |
| 2239 | re_intr(void *arg) |
| 2240 | { |
| 2241 | struct re_softc *sc = arg; |
| 2242 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 2243 | uint16_t status; |
| 2244 | int rx, tx; |
| 2245 | |
| 2246 | ASSERT_SERIALIZED(ifp->if_serializer); |
| 2247 | |
| 2248 | if ((sc->re_flags & RE_F_SUSPENDED) || |
| 2249 | (ifp->if_flags & IFF_RUNNING) == 0) |
| 2250 | return; |
| 2251 | |
| 2252 | rx = tx = 0; |
| 2253 | for (;;) { |
| 2254 | status = CSR_READ_2(sc, RE_ISR); |
| 2255 | /* If the card has gone away the read returns 0xffff. */ |
| 2256 | if (status == 0xffff) |
| 2257 | break; |
| 2258 | if (status) |
| 2259 | CSR_WRITE_2(sc, RE_ISR, status); |
| 2260 | |
| 2261 | if ((status & sc->re_intrs) == 0) |
| 2262 | break; |
| 2263 | |
| 2264 | if (status & (sc->re_rx_ack | RE_ISR_RX_ERR)) |
| 2265 | rx |= re_rxeof(sc); |
| 2266 | |
| 2267 | if (status & (sc->re_tx_ack | RE_ISR_TX_ERR)) |
| 2268 | tx |= re_txeof(sc); |
| 2269 | |
| 2270 | if (status & RE_ISR_SYSTEM_ERR) |
| 2271 | re_init(sc); |
| 2272 | |
| 2273 | if (status & RE_ISR_LINKCHG) { |
| 2274 | callout_stop(&sc->re_timer); |
| 2275 | re_tick_serialized(sc); |
| 2276 | } |
| 2277 | } |
| 2278 | |
| 2279 | if (sc->re_imtype == RE_IMTYPE_SIM) { |
| 2280 | if ((sc->re_flags & RE_F_TIMER_INTR)) { |
| 2281 | if ((tx | rx) == 0) |
| 2282 | re_setup_intr(sc, 1, RE_IMTYPE_NONE); |
| 2283 | else |
| 2284 | CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */ |
| 2285 | } else if (tx | rx) { |
| 2286 | re_setup_intr(sc, 1, RE_IMTYPE_SIM); |
| 2287 | } |
| 2288 | } |
| 2289 | |
| 2290 | if (tx && !ifq_is_empty(&ifp->if_snd)) |
| 2291 | if_devstart(ifp); |
| 2292 | } |
| 2293 | |
| 2294 | static int |
| 2295 | re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx0) |
| 2296 | { |
| 2297 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 2298 | struct mbuf *m; |
| 2299 | struct re_dmaload_arg arg; |
| 2300 | bus_dma_segment_t segs[RE_MAXSEGS]; |
| 2301 | bus_dmamap_t map; |
| 2302 | int error, maxsegs, idx, i; |
| 2303 | struct re_desc *d, *tx_ring; |
| 2304 | uint32_t cmd_csum, ctl_csum, vlantag; |
| 2305 | |
| 2306 | KASSERT(sc->re_ldata.re_tx_free > RE_TXDESC_SPARE, |
| 2307 | ("not enough free TX desc\n")); |
| 2308 | |
| 2309 | m = *m_head; |
| 2310 | map = sc->re_ldata.re_tx_dmamap[*idx0]; |
| 2311 | |
| 2312 | /* |
| 2313 | * Set up checksum offload. Note: checksum offload bits must |
| 2314 | * appear in all descriptors of a multi-descriptor transmit |
| 2315 | * attempt. (This is according to testing done with an 8169 |
| 2316 | * chip. I'm not sure if this is a requirement or a bug.) |
| 2317 | */ |
| 2318 | cmd_csum = ctl_csum = 0; |
| 2319 | if (m->m_pkthdr.csum_flags & CSUM_IP) { |
| 2320 | cmd_csum |= RE_TDESC_CMD_IPCSUM; |
| 2321 | ctl_csum |= RE_TDESC_CTL_IPCSUM; |
| 2322 | } |
| 2323 | if (m->m_pkthdr.csum_flags & CSUM_TCP) { |
| 2324 | cmd_csum |= RE_TDESC_CMD_TCPCSUM; |
| 2325 | ctl_csum |= RE_TDESC_CTL_TCPCSUM; |
| 2326 | } |
| 2327 | if (m->m_pkthdr.csum_flags & CSUM_UDP) { |
| 2328 | cmd_csum |= RE_TDESC_CMD_UDPCSUM; |
| 2329 | ctl_csum |= RE_TDESC_CTL_UDPCSUM; |
| 2330 | } |
| 2331 | |
| 2332 | /* For MAC2 chips, csum flags are set on re_control */ |
| 2333 | if (sc->re_caps & RE_C_MAC2) |
| 2334 | cmd_csum = 0; |
| 2335 | else |
| 2336 | ctl_csum = 0; |
| 2337 | |
| 2338 | if (m->m_pkthdr.len > sc->re_swcsum_lim && |
| 2339 | (m->m_pkthdr.csum_flags & (CSUM_DELAY_IP | CSUM_DELAY_DATA))) { |
| 2340 | struct ether_header *eh; |
| 2341 | struct ip *ip; |
| 2342 | u_short offset; |
| 2343 | |
| 2344 | m = m_pullup(m, sizeof(struct ether_header *)); |
| 2345 | if (m == NULL) { |
| 2346 | *m_head = NULL; |
| 2347 | return ENOBUFS; |
| 2348 | } |
| 2349 | eh = mtod(m, struct ether_header *); |
| 2350 | |
| 2351 | /* XXX */ |
| 2352 | if (eh->ether_type == ETHERTYPE_VLAN) |
| 2353 | offset = sizeof(struct ether_vlan_header); |
| 2354 | else |
| 2355 | offset = sizeof(struct ether_header); |
| 2356 | |
| 2357 | m = m_pullup(m, offset + sizeof(struct ip *)); |
| 2358 | if (m == NULL) { |
| 2359 | *m_head = NULL; |
| 2360 | return ENOBUFS; |
| 2361 | } |
| 2362 | ip = (struct ip *)(mtod(m, uint8_t *) + offset); |
| 2363 | |
| 2364 | if (m->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { |
| 2365 | u_short csum; |
| 2366 | |
| 2367 | offset += IP_VHL_HL(ip->ip_vhl) << 2; |
| 2368 | csum = in_cksum_skip(m, ntohs(ip->ip_len), offset); |
| 2369 | if (m->m_pkthdr.csum_flags & CSUM_UDP && csum == 0) |
| 2370 | csum = 0xffff; |
| 2371 | offset += m->m_pkthdr.csum_data; /* checksum offset */ |
| 2372 | *(u_short *)(m->m_data + offset) = csum; |
| 2373 | |
| 2374 | m->m_pkthdr.csum_flags &= ~CSUM_DELAY_DATA; |
| 2375 | } |
| 2376 | if (m->m_pkthdr.csum_flags & CSUM_DELAY_IP) { |
| 2377 | ip->ip_sum = 0; |
| 2378 | if (ip->ip_vhl == IP_VHL_BORING) { |
| 2379 | ip->ip_sum = in_cksum_hdr(ip); |
| 2380 | } else { |
| 2381 | ip->ip_sum = |
| 2382 | in_cksum(m, IP_VHL_HL(ip->ip_vhl) << 2); |
| 2383 | } |
| 2384 | m->m_pkthdr.csum_flags &= ~CSUM_DELAY_IP; |
| 2385 | } |
| 2386 | *m_head = m; /* 'm' may be changed by above two m_pullup() */ |
| 2387 | |
| 2388 | /* Clear hardware CSUM flags */ |
| 2389 | cmd_csum = ctl_csum = 0; |
| 2390 | } |
| 2391 | |
| 2392 | if ((sc->re_caps & RE_C_AUTOPAD) == 0) { |
| 2393 | /* |
| 2394 | * With some of the RealTek chips, using the checksum offload |
| 2395 | * support in conjunction with the autopadding feature results |
| 2396 | * in the transmission of corrupt frames. For example, if we |
| 2397 | * need to send a really small IP fragment that's less than 60 |
| 2398 | * bytes in size, and IP header checksumming is enabled, the |
| 2399 | * resulting ethernet frame that appears on the wire will |
| 2400 | * have garbled payload. To work around this, if TX checksum |
| 2401 | * offload is enabled, we always manually pad short frames out |
| 2402 | * to the minimum ethernet frame size. |
| 2403 | * |
| 2404 | * Note: this appears unnecessary for TCP, and doing it for TCP |
| 2405 | * with PCIe adapters seems to result in bad checksums. |
| 2406 | */ |
| 2407 | if ((m->m_pkthdr.csum_flags & |
| 2408 | (CSUM_DELAY_IP | CSUM_DELAY_DATA)) && |
| 2409 | (m->m_pkthdr.csum_flags & CSUM_TCP) == 0 && |
| 2410 | m->m_pkthdr.len < RE_MIN_FRAMELEN) { |
| 2411 | error = re_pad_frame(m); |
| 2412 | if (error) |
| 2413 | goto back; |
| 2414 | } |
| 2415 | } |
| 2416 | |
| 2417 | vlantag = 0; |
| 2418 | if (m->m_flags & M_VLANTAG) { |
| 2419 | vlantag = htobe16(m->m_pkthdr.ether_vlantag) | |
| 2420 | RE_TDESC_CTL_INSTAG; |
| 2421 | } |
| 2422 | |
| 2423 | maxsegs = sc->re_ldata.re_tx_free; |
| 2424 | if (maxsegs > RE_MAXSEGS) |
| 2425 | maxsegs = RE_MAXSEGS; |
| 2426 | |
| 2427 | arg.re_nsegs = maxsegs; |
| 2428 | arg.re_segs = segs; |
| 2429 | error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, m, |
| 2430 | re_dma_map_desc, &arg, BUS_DMA_NOWAIT); |
| 2431 | if (error && error != EFBIG) { |
| 2432 | if_printf(ifp, "can't map mbuf (error %d)\n", error); |
| 2433 | goto back; |
| 2434 | } |
| 2435 | |
| 2436 | /* |
| 2437 | * Too many segments to map, coalesce into a single mbuf |
| 2438 | */ |
| 2439 | if (!error && arg.re_nsegs == 0) { |
| 2440 | bus_dmamap_unload(sc->re_ldata.re_mtag, map); |
| 2441 | error = EFBIG; |
| 2442 | } |
| 2443 | if (error) { |
| 2444 | struct mbuf *m_new; |
| 2445 | |
| 2446 | m_new = m_defrag(m, MB_DONTWAIT); |
| 2447 | if (m_new == NULL) { |
| 2448 | if_printf(ifp, "can't defrag TX mbuf\n"); |
| 2449 | error = ENOBUFS; |
| 2450 | goto back; |
| 2451 | } else { |
| 2452 | *m_head = m = m_new; |
| 2453 | } |
| 2454 | |
| 2455 | arg.re_nsegs = maxsegs; |
| 2456 | arg.re_segs = segs; |
| 2457 | error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, m, |
| 2458 | re_dma_map_desc, &arg, |
| 2459 | BUS_DMA_NOWAIT); |
| 2460 | if (error || arg.re_nsegs == 0) { |
| 2461 | if (!error) { |
| 2462 | bus_dmamap_unload(sc->re_ldata.re_mtag, map); |
| 2463 | error = EFBIG; |
| 2464 | } |
| 2465 | if_printf(ifp, "can't map mbuf (error %d)\n", error); |
| 2466 | goto back; |
| 2467 | } |
| 2468 | } |
| 2469 | bus_dmamap_sync(sc->re_ldata.re_mtag, map, BUS_DMASYNC_PREWRITE); |
| 2470 | |
| 2471 | /* |
| 2472 | * Map the segment array into descriptors. We also keep track |
| 2473 | * of the end of the ring and set the end-of-ring bits as needed, |
| 2474 | * and we set the ownership bits in all except the very first |
| 2475 | * descriptor, whose ownership bits will be turned on later. |
| 2476 | */ |
| 2477 | tx_ring = sc->re_ldata.re_tx_list; |
| 2478 | idx = *idx0; |
| 2479 | i = 0; |
| 2480 | for (;;) { |
| 2481 | uint32_t cmdstat; |
| 2482 | |
| 2483 | d = &tx_ring[idx]; |
| 2484 | |
| 2485 | cmdstat = segs[i].ds_len; |
| 2486 | d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr)); |
| 2487 | d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr)); |
| 2488 | if (i == 0) |
| 2489 | cmdstat |= RE_TDESC_CMD_SOF; |
| 2490 | else |
| 2491 | cmdstat |= RE_TDESC_CMD_OWN; |
| 2492 | if (idx == (sc->re_tx_desc_cnt - 1)) |
| 2493 | cmdstat |= RE_TDESC_CMD_EOR; |
| 2494 | d->re_cmdstat = htole32(cmdstat | cmd_csum); |
| 2495 | d->re_control = htole32(ctl_csum | vlantag); |
| 2496 | |
| 2497 | i++; |
| 2498 | if (i == arg.re_nsegs) |
| 2499 | break; |
| 2500 | RE_TXDESC_INC(sc, idx); |
| 2501 | } |
| 2502 | d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF); |
| 2503 | |
| 2504 | /* Transfer ownership of packet to the chip. */ |
| 2505 | d->re_cmdstat |= htole32(RE_TDESC_CMD_OWN); |
| 2506 | if (*idx0 != idx) |
| 2507 | tx_ring[*idx0].re_cmdstat |= htole32(RE_TDESC_CMD_OWN); |
| 2508 | |
| 2509 | /* |
| 2510 | * Insure that the map for this transmission |
| 2511 | * is placed at the array index of the last descriptor |
| 2512 | * in this chain. |
| 2513 | */ |
| 2514 | sc->re_ldata.re_tx_dmamap[*idx0] = sc->re_ldata.re_tx_dmamap[idx]; |
| 2515 | sc->re_ldata.re_tx_dmamap[idx] = map; |
| 2516 | |
| 2517 | sc->re_ldata.re_tx_mbuf[idx] = m; |
| 2518 | sc->re_ldata.re_tx_free -= arg.re_nsegs; |
| 2519 | |
| 2520 | RE_TXDESC_INC(sc, idx); |
| 2521 | *idx0 = idx; |
| 2522 | back: |
| 2523 | if (error) { |
| 2524 | m_freem(m); |
| 2525 | *m_head = NULL; |
| 2526 | } |
| 2527 | return error; |
| 2528 | } |
| 2529 | |
| 2530 | /* |
| 2531 | * Main transmit routine for C+ and gigE NICs. |
| 2532 | */ |
| 2533 | |
| 2534 | static void |
| 2535 | re_start(struct ifnet *ifp) |
| 2536 | { |
| 2537 | struct re_softc *sc = ifp->if_softc; |
| 2538 | struct mbuf *m_head; |
| 2539 | int idx, need_trans, oactive, error; |
| 2540 | |
| 2541 | ASSERT_SERIALIZED(ifp->if_serializer); |
| 2542 | |
| 2543 | if ((sc->re_flags & RE_F_LINKED) == 0) { |
| 2544 | ifq_purge(&ifp->if_snd); |
| 2545 | return; |
| 2546 | } |
| 2547 | |
| 2548 | if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) |
| 2549 | return; |
| 2550 | |
| 2551 | idx = sc->re_ldata.re_tx_prodidx; |
| 2552 | |
| 2553 | need_trans = 0; |
| 2554 | oactive = 0; |
| 2555 | while (sc->re_ldata.re_tx_mbuf[idx] == NULL) { |
| 2556 | if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) { |
| 2557 | if (!oactive) { |
| 2558 | if (re_tx_collect(sc)) { |
| 2559 | oactive = 1; |
| 2560 | continue; |
| 2561 | } |
| 2562 | } |
| 2563 | ifp->if_flags |= IFF_OACTIVE; |
| 2564 | break; |
| 2565 | } |
| 2566 | |
| 2567 | m_head = ifq_dequeue(&ifp->if_snd, NULL); |
| 2568 | if (m_head == NULL) |
| 2569 | break; |
| 2570 | |
| 2571 | error = re_encap(sc, &m_head, &idx); |
| 2572 | if (error) { |
| 2573 | /* m_head is freed by re_encap(), if we reach here */ |
| 2574 | ifp->if_oerrors++; |
| 2575 | |
| 2576 | if (error == EFBIG && !oactive) { |
| 2577 | if (re_tx_collect(sc)) { |
| 2578 | oactive = 1; |
| 2579 | continue; |
| 2580 | } |
| 2581 | } |
| 2582 | ifp->if_flags |= IFF_OACTIVE; |
| 2583 | break; |
| 2584 | } |
| 2585 | |
| 2586 | oactive = 0; |
| 2587 | need_trans = 1; |
| 2588 | |
| 2589 | /* |
| 2590 | * If there's a BPF listener, bounce a copy of this frame |
| 2591 | * to him. |
| 2592 | */ |
| 2593 | ETHER_BPF_MTAP(ifp, m_head); |
| 2594 | } |
| 2595 | |
| 2596 | if (!need_trans) |
| 2597 | return; |
| 2598 | |
| 2599 | /* Flush the TX descriptors */ |
| 2600 | bus_dmamap_sync(sc->re_ldata.re_tx_list_tag, |
| 2601 | sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE); |
| 2602 | |
| 2603 | sc->re_ldata.re_tx_prodidx = idx; |
| 2604 | |
| 2605 | /* |
| 2606 | * RealTek put the TX poll request register in a different |
| 2607 | * location on the 8169 gigE chip. I don't know why. |
| 2608 | */ |
| 2609 | CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START); |
| 2610 | |
| 2611 | /* |
| 2612 | * Set a timeout in case the chip goes out to lunch. |
| 2613 | */ |
| 2614 | ifp->if_timer = 5; |
| 2615 | } |
| 2616 | |
| 2617 | static void |
| 2618 | re_init(void *xsc) |
| 2619 | { |
| 2620 | struct re_softc *sc = xsc; |
| 2621 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 2622 | struct mii_data *mii; |
| 2623 | uint32_t rxcfg = 0; |
| 2624 | int error, framelen; |
| 2625 | |
| 2626 | ASSERT_SERIALIZED(ifp->if_serializer); |
| 2627 | |
| 2628 | mii = device_get_softc(sc->re_miibus); |
| 2629 | |
| 2630 | /* |
| 2631 | * Cancel pending I/O and free all RX/TX buffers. |
| 2632 | */ |
| 2633 | re_stop(sc); |
| 2634 | |
| 2635 | if (sc->re_caps & RE_C_CONTIGRX) { |
| 2636 | if (ifp->if_mtu > ETHERMTU) { |
| 2637 | KKASSERT(sc->re_ldata.re_jbuf != NULL); |
| 2638 | sc->re_flags |= RE_F_USE_JPOOL; |
| 2639 | sc->re_rxbuf_size = RE_FRAMELEN_MAX; |
| 2640 | sc->re_newbuf = re_newbuf_jumbo; |
| 2641 | } else { |
| 2642 | sc->re_flags &= ~RE_F_USE_JPOOL; |
| 2643 | sc->re_rxbuf_size = MCLBYTES; |
| 2644 | sc->re_newbuf = re_newbuf_std; |
| 2645 | } |
| 2646 | } |
| 2647 | |
| 2648 | /* |
| 2649 | * Adjust max read request size according to MTU. |
| 2650 | * Mainly to improve TX performance for common case (ETHERMTU). |
| 2651 | */ |
| 2652 | if (sc->re_caps & RE_C_PCIE) { |
| 2653 | if (ifp->if_mtu > ETHERMTU) { |
| 2654 | /* |
| 2655 | * 512 seems to be the only value that works |
| 2656 | * reliably with jumbo frame |
| 2657 | */ |
| 2658 | re_set_max_readrq(sc, PCIEM_DEVCTL_MAX_READRQ_512); |
| 2659 | } else { |
| 2660 | re_set_max_readrq(sc, PCIEM_DEVCTL_MAX_READRQ_4096); |
| 2661 | } |
| 2662 | } |
| 2663 | |
| 2664 | /* |
| 2665 | * Enable C+ RX and TX mode, as well as VLAN stripping and |
| 2666 | * RX checksum offload. We must configure the C+ register |
| 2667 | * before all others. |
| 2668 | */ |
| 2669 | CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB | |
| 2670 | RE_CPLUSCMD_PCI_MRW | |
| 2671 | (ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? |
| 2672 | RE_CPLUSCMD_VLANSTRIP : 0) | |
| 2673 | (ifp->if_capenable & IFCAP_RXCSUM ? |
| 2674 | RE_CPLUSCMD_RXCSUM_ENB : 0)); |
| 2675 | |
| 2676 | /* |
| 2677 | * Init our MAC address. Even though the chipset |
| 2678 | * documentation doesn't mention it, we need to enter "Config |
| 2679 | * register write enable" mode to modify the ID registers. |
| 2680 | */ |
| 2681 | CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG); |
| 2682 | CSR_WRITE_4(sc, RE_IDR0, |
| 2683 | htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0]))); |
| 2684 | CSR_WRITE_2(sc, RE_IDR4, |
| 2685 | htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4]))); |
| 2686 | CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF); |
| 2687 | |
| 2688 | /* |
| 2689 | * For C+ mode, initialize the RX descriptors and mbufs. |
| 2690 | */ |
| 2691 | error = re_rx_list_init(sc); |
| 2692 | if (error) { |
| 2693 | re_stop(sc); |
| 2694 | return; |
| 2695 | } |
| 2696 | error = re_tx_list_init(sc); |
| 2697 | if (error) { |
| 2698 | re_stop(sc); |
| 2699 | return; |
| 2700 | } |
| 2701 | |
| 2702 | /* |
| 2703 | * Load the addresses of the RX and TX lists into the chip. |
| 2704 | */ |
| 2705 | CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI, |
| 2706 | RE_ADDR_HI(sc->re_ldata.re_rx_list_addr)); |
| 2707 | CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO, |
| 2708 | RE_ADDR_LO(sc->re_ldata.re_rx_list_addr)); |
| 2709 | |
| 2710 | CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI, |
| 2711 | RE_ADDR_HI(sc->re_ldata.re_tx_list_addr)); |
| 2712 | CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO, |
| 2713 | RE_ADDR_LO(sc->re_ldata.re_tx_list_addr)); |
| 2714 | |
| 2715 | /* |
| 2716 | * Enable transmit and receive. |
| 2717 | */ |
| 2718 | CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); |
| 2719 | |
| 2720 | /* |
| 2721 | * Set the initial TX and RX configuration. |
| 2722 | */ |
| 2723 | if (sc->re_flags & RE_F_TESTMODE) { |
| 2724 | if (!RE_IS_8139CP(sc)) |
| 2725 | CSR_WRITE_4(sc, RE_TXCFG, |
| 2726 | RE_TXCFG_CONFIG | RE_LOOPTEST_ON); |
| 2727 | else |
| 2728 | CSR_WRITE_4(sc, RE_TXCFG, |
| 2729 | RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS); |
| 2730 | } else |
| 2731 | CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG); |
| 2732 | |
| 2733 | framelen = RE_FRAMELEN(ifp->if_mtu); |
| 2734 | if (framelen < MCLBYTES) |
| 2735 | CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(MCLBYTES, 128)); |
| 2736 | else |
| 2737 | CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(framelen, 128)); |
| 2738 | |
| 2739 | CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG); |
| 2740 | |
| 2741 | /* Set the individual bit to receive frames for this host only. */ |
| 2742 | rxcfg = CSR_READ_4(sc, RE_RXCFG); |
| 2743 | rxcfg |= RE_RXCFG_RX_INDIV; |
| 2744 | |
| 2745 | /* If we want promiscuous mode, set the allframes bit. */ |
| 2746 | if (ifp->if_flags & IFF_PROMISC) { |
| 2747 | rxcfg |= RE_RXCFG_RX_ALLPHYS; |
| 2748 | CSR_WRITE_4(sc, RE_RXCFG, rxcfg); |
| 2749 | } else { |
| 2750 | rxcfg &= ~RE_RXCFG_RX_ALLPHYS; |
| 2751 | CSR_WRITE_4(sc, RE_RXCFG, rxcfg); |
| 2752 | } |
| 2753 | |
| 2754 | /* |
| 2755 | * Set capture broadcast bit to capture broadcast frames. |
| 2756 | */ |
| 2757 | if (ifp->if_flags & IFF_BROADCAST) { |
| 2758 | rxcfg |= RE_RXCFG_RX_BROAD; |
| 2759 | CSR_WRITE_4(sc, RE_RXCFG, rxcfg); |
| 2760 | } else { |
| 2761 | rxcfg &= ~RE_RXCFG_RX_BROAD; |
| 2762 | CSR_WRITE_4(sc, RE_RXCFG, rxcfg); |
| 2763 | } |
| 2764 | |
| 2765 | /* |
| 2766 | * Program the multicast filter, if necessary. |
| 2767 | */ |
| 2768 | re_setmulti(sc); |
| 2769 | |
| 2770 | #ifdef DEVICE_POLLING |
| 2771 | /* |
| 2772 | * Disable interrupts if we are polling. |
| 2773 | */ |
| 2774 | if (ifp->if_flags & IFF_POLLING) |
| 2775 | re_setup_intr(sc, 0, RE_IMTYPE_NONE); |
| 2776 | else /* otherwise ... */ |
| 2777 | #endif /* DEVICE_POLLING */ |
| 2778 | /* |
| 2779 | * Enable interrupts. |
| 2780 | */ |
| 2781 | if (sc->re_flags & RE_F_TESTMODE) |
| 2782 | CSR_WRITE_2(sc, RE_IMR, 0); |
| 2783 | else |
| 2784 | re_setup_intr(sc, 1, sc->re_imtype); |
| 2785 | CSR_WRITE_2(sc, RE_ISR, sc->re_intrs); |
| 2786 | |
| 2787 | /* Start RX/TX process. */ |
| 2788 | CSR_WRITE_4(sc, RE_MISSEDPKT, 0); |
| 2789 | |
| 2790 | #ifdef notdef |
| 2791 | /* Enable receiver and transmitter. */ |
| 2792 | CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB); |
| 2793 | #endif |
| 2794 | |
| 2795 | /* |
| 2796 | * For 8169 gigE NICs, set the max allowed RX packet |
| 2797 | * size so we can receive jumbo frames. |
| 2798 | */ |
| 2799 | if (!RE_IS_8139CP(sc)) { |
| 2800 | if (sc->re_caps & RE_C_CONTIGRX) |
| 2801 | CSR_WRITE_2(sc, RE_MAXRXPKTLEN, sc->re_rxbuf_size); |
| 2802 | else |
| 2803 | CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383); |
| 2804 | } |
| 2805 | |
| 2806 | if (sc->re_flags & RE_F_TESTMODE) |
| 2807 | return; |
| 2808 | |
| 2809 | mii_mediachg(mii); |
| 2810 | |
| 2811 | CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX); |
| 2812 | |
| 2813 | ifp->if_flags |= IFF_RUNNING; |
| 2814 | ifp->if_flags &= ~IFF_OACTIVE; |
| 2815 | |
| 2816 | callout_reset(&sc->re_timer, hz, re_tick, sc); |
| 2817 | } |
| 2818 | |
| 2819 | /* |
| 2820 | * Set media options. |
| 2821 | */ |
| 2822 | static int |
| 2823 | re_ifmedia_upd(struct ifnet *ifp) |
| 2824 | { |
| 2825 | struct re_softc *sc = ifp->if_softc; |
| 2826 | struct mii_data *mii; |
| 2827 | |
| 2828 | ASSERT_SERIALIZED(ifp->if_serializer); |
| 2829 | |
| 2830 | mii = device_get_softc(sc->re_miibus); |
| 2831 | mii_mediachg(mii); |
| 2832 | |
| 2833 | return(0); |
| 2834 | } |
| 2835 | |
| 2836 | /* |
| 2837 | * Report current media status. |
| 2838 | */ |
| 2839 | static void |
| 2840 | re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) |
| 2841 | { |
| 2842 | struct re_softc *sc = ifp->if_softc; |
| 2843 | struct mii_data *mii; |
| 2844 | |
| 2845 | ASSERT_SERIALIZED(ifp->if_serializer); |
| 2846 | |
| 2847 | mii = device_get_softc(sc->re_miibus); |
| 2848 | |
| 2849 | mii_pollstat(mii); |
| 2850 | ifmr->ifm_active = mii->mii_media_active; |
| 2851 | ifmr->ifm_status = mii->mii_media_status; |
| 2852 | } |
| 2853 | |
| 2854 | static int |
| 2855 | re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) |
| 2856 | { |
| 2857 | struct re_softc *sc = ifp->if_softc; |
| 2858 | struct ifreq *ifr = (struct ifreq *) data; |
| 2859 | struct mii_data *mii; |
| 2860 | int error = 0, mask; |
| 2861 | |
| 2862 | ASSERT_SERIALIZED(ifp->if_serializer); |
| 2863 | |
| 2864 | switch(command) { |
| 2865 | case SIOCSIFMTU: |
| 2866 | if (ifr->ifr_mtu > sc->re_maxmtu) { |
| 2867 | error = EINVAL; |
| 2868 | } else if (ifp->if_mtu != ifr->ifr_mtu) { |
| 2869 | ifp->if_mtu = ifr->ifr_mtu; |
| 2870 | if (ifp->if_flags & IFF_RUNNING) |
| 2871 | ifp->if_init(sc); |
| 2872 | } |
| 2873 | break; |
| 2874 | |
| 2875 | case SIOCSIFFLAGS: |
| 2876 | if (ifp->if_flags & IFF_UP) |
| 2877 | re_init(sc); |
| 2878 | else if (ifp->if_flags & IFF_RUNNING) |
| 2879 | re_stop(sc); |
| 2880 | break; |
| 2881 | case SIOCADDMULTI: |
| 2882 | case SIOCDELMULTI: |
| 2883 | re_setmulti(sc); |
| 2884 | error = 0; |
| 2885 | break; |
| 2886 | case SIOCGIFMEDIA: |
| 2887 | case SIOCSIFMEDIA: |
| 2888 | mii = device_get_softc(sc->re_miibus); |
| 2889 | error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); |
| 2890 | break; |
| 2891 | case SIOCSIFCAP: |
| 2892 | mask = (ifr->ifr_reqcap ^ ifp->if_capenable) & |
| 2893 | ifp->if_capabilities; |
| 2894 | ifp->if_capenable ^= mask; |
| 2895 | |
| 2896 | if (mask & IFCAP_HWCSUM) { |
| 2897 | if (ifp->if_capenable & IFCAP_TXCSUM) |
| 2898 | ifp->if_hwassist = RE_CSUM_FEATURES; |
| 2899 | else |
| 2900 | ifp->if_hwassist = 0; |
| 2901 | } |
| 2902 | if (mask && (ifp->if_flags & IFF_RUNNING)) |
| 2903 | re_init(sc); |
| 2904 | break; |
| 2905 | default: |
| 2906 | error = ether_ioctl(ifp, command, data); |
| 2907 | break; |
| 2908 | } |
| 2909 | return(error); |
| 2910 | } |
| 2911 | |
| 2912 | static void |
| 2913 | re_watchdog(struct ifnet *ifp) |
| 2914 | { |
| 2915 | struct re_softc *sc = ifp->if_softc; |
| 2916 | |
| 2917 | ASSERT_SERIALIZED(ifp->if_serializer); |
| 2918 | |
| 2919 | if_printf(ifp, "watchdog timeout\n"); |
| 2920 | |
| 2921 | ifp->if_oerrors++; |
| 2922 | |
| 2923 | re_txeof(sc); |
| 2924 | re_rxeof(sc); |
| 2925 | |
| 2926 | re_init(sc); |
| 2927 | |
| 2928 | if (!ifq_is_empty(&ifp->if_snd)) |
| 2929 | if_devstart(ifp); |
| 2930 | } |
| 2931 | |
| 2932 | /* |
| 2933 | * Stop the adapter and free any mbufs allocated to the |
| 2934 | * RX and TX lists. |
| 2935 | */ |
| 2936 | static void |
| 2937 | re_stop(struct re_softc *sc) |
| 2938 | { |
| 2939 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 2940 | int i; |
| 2941 | |
| 2942 | ASSERT_SERIALIZED(ifp->if_serializer); |
| 2943 | |
| 2944 | /* Reset the adapter. */ |
| 2945 | re_reset(sc, ifp->if_flags & IFF_RUNNING); |
| 2946 | |
| 2947 | ifp->if_timer = 0; |
| 2948 | callout_stop(&sc->re_timer); |
| 2949 | |
| 2950 | ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); |
| 2951 | sc->re_flags &= ~(RE_F_TIMER_INTR | RE_F_DROP_RXFRAG | RE_F_LINKED); |
| 2952 | |
| 2953 | CSR_WRITE_1(sc, RE_COMMAND, 0x00); |
| 2954 | CSR_WRITE_2(sc, RE_IMR, 0x0000); |
| 2955 | CSR_WRITE_2(sc, RE_ISR, 0xFFFF); |
| 2956 | |
| 2957 | re_free_rxchain(sc); |
| 2958 | |
| 2959 | /* Free the TX list buffers. */ |
| 2960 | for (i = 0; i < sc->re_tx_desc_cnt; i++) { |
| 2961 | if (sc->re_ldata.re_tx_mbuf[i] != NULL) { |
| 2962 | bus_dmamap_unload(sc->re_ldata.re_mtag, |
| 2963 | sc->re_ldata.re_tx_dmamap[i]); |
| 2964 | m_freem(sc->re_ldata.re_tx_mbuf[i]); |
| 2965 | sc->re_ldata.re_tx_mbuf[i] = NULL; |
| 2966 | } |
| 2967 | } |
| 2968 | |
| 2969 | /* Free the RX list buffers. */ |
| 2970 | for (i = 0; i < sc->re_rx_desc_cnt; i++) { |
| 2971 | if (sc->re_ldata.re_rx_mbuf[i] != NULL) { |
| 2972 | if ((sc->re_flags & RE_F_USE_JPOOL) == 0) { |
| 2973 | bus_dmamap_unload(sc->re_ldata.re_mtag, |
| 2974 | sc->re_ldata.re_rx_dmamap[i]); |
| 2975 | } |
| 2976 | m_freem(sc->re_ldata.re_rx_mbuf[i]); |
| 2977 | sc->re_ldata.re_rx_mbuf[i] = NULL; |
| 2978 | } |
| 2979 | } |
| 2980 | } |
| 2981 | |
| 2982 | /* |
| 2983 | * Device suspend routine. Stop the interface and save some PCI |
| 2984 | * settings in case the BIOS doesn't restore them properly on |
| 2985 | * resume. |
| 2986 | */ |
| 2987 | static int |
| 2988 | re_suspend(device_t dev) |
| 2989 | { |
| 2990 | #ifndef BURN_BRIDGES |
| 2991 | int i; |
| 2992 | #endif |
| 2993 | struct re_softc *sc = device_get_softc(dev); |
| 2994 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 2995 | |
| 2996 | lwkt_serialize_enter(ifp->if_serializer); |
| 2997 | |
| 2998 | re_stop(sc); |
| 2999 | |
| 3000 | #ifndef BURN_BRIDGES |
| 3001 | for (i = 0; i < 5; i++) |
| 3002 | sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); |
| 3003 | sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); |
| 3004 | sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); |
| 3005 | sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); |
| 3006 | sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); |
| 3007 | #endif |
| 3008 | |
| 3009 | sc->re_flags |= RE_F_SUSPENDED; |
| 3010 | |
| 3011 | lwkt_serialize_exit(ifp->if_serializer); |
| 3012 | |
| 3013 | return (0); |
| 3014 | } |
| 3015 | |
| 3016 | /* |
| 3017 | * Device resume routine. Restore some PCI settings in case the BIOS |
| 3018 | * doesn't, re-enable busmastering, and restart the interface if |
| 3019 | * appropriate. |
| 3020 | */ |
| 3021 | static int |
| 3022 | re_resume(device_t dev) |
| 3023 | { |
| 3024 | struct re_softc *sc = device_get_softc(dev); |
| 3025 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 3026 | #ifndef BURN_BRIDGES |
| 3027 | int i; |
| 3028 | #endif |
| 3029 | |
| 3030 | lwkt_serialize_enter(ifp->if_serializer); |
| 3031 | |
| 3032 | #ifndef BURN_BRIDGES |
| 3033 | /* better way to do this? */ |
| 3034 | for (i = 0; i < 5; i++) |
| 3035 | pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); |
| 3036 | pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); |
| 3037 | pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); |
| 3038 | pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); |
| 3039 | pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); |
| 3040 | |
| 3041 | /* reenable busmastering */ |
| 3042 | pci_enable_busmaster(dev); |
| 3043 | pci_enable_io(dev, SYS_RES_IOPORT); |
| 3044 | #endif |
| 3045 | |
| 3046 | /* reinitialize interface if necessary */ |
| 3047 | if (ifp->if_flags & IFF_UP) |
| 3048 | re_init(sc); |
| 3049 | |
| 3050 | sc->re_flags &= ~RE_F_SUSPENDED; |
| 3051 | |
| 3052 | lwkt_serialize_exit(ifp->if_serializer); |
| 3053 | |
| 3054 | return (0); |
| 3055 | } |
| 3056 | |
| 3057 | /* |
| 3058 | * Stop all chip I/O so that the kernel's probe routines don't |
| 3059 | * get confused by errant DMAs when rebooting. |
| 3060 | */ |
| 3061 | static void |
| 3062 | re_shutdown(device_t dev) |
| 3063 | { |
| 3064 | struct re_softc *sc = device_get_softc(dev); |
| 3065 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 3066 | |
| 3067 | lwkt_serialize_enter(ifp->if_serializer); |
| 3068 | re_stop(sc); |
| 3069 | lwkt_serialize_exit(ifp->if_serializer); |
| 3070 | } |
| 3071 | |
| 3072 | static int |
| 3073 | re_pad_frame(struct mbuf *pkt) |
| 3074 | { |
| 3075 | struct mbuf *last = NULL; |
| 3076 | int padlen; |
| 3077 | |
| 3078 | padlen = RE_MIN_FRAMELEN - pkt->m_pkthdr.len; |
| 3079 | |
| 3080 | /* if there's only the packet-header and we can pad there, use it. */ |
| 3081 | if (pkt->m_pkthdr.len == pkt->m_len && |
| 3082 | M_TRAILINGSPACE(pkt) >= padlen) { |
| 3083 | last = pkt; |
| 3084 | } else { |
| 3085 | /* |
| 3086 | * Walk packet chain to find last mbuf. We will either |
| 3087 | * pad there, or append a new mbuf and pad it |
| 3088 | */ |
| 3089 | for (last = pkt; last->m_next != NULL; last = last->m_next) |
| 3090 | ; /* EMPTY */ |
| 3091 | |
| 3092 | /* `last' now points to last in chain. */ |
| 3093 | if (M_TRAILINGSPACE(last) < padlen) { |
| 3094 | struct mbuf *n; |
| 3095 | |
| 3096 | /* Allocate new empty mbuf, pad it. Compact later. */ |
| 3097 | MGET(n, MB_DONTWAIT, MT_DATA); |
| 3098 | if (n == NULL) |
| 3099 | return ENOBUFS; |
| 3100 | n->m_len = 0; |
| 3101 | last->m_next = n; |
| 3102 | last = n; |
| 3103 | } |
| 3104 | } |
| 3105 | KKASSERT(M_TRAILINGSPACE(last) >= padlen); |
| 3106 | KKASSERT(M_WRITABLE(last)); |
| 3107 | |
| 3108 | /* Now zero the pad area, to avoid the re cksum-assist bug */ |
| 3109 | bzero(mtod(last, char *) + last->m_len, padlen); |
| 3110 | last->m_len += padlen; |
| 3111 | pkt->m_pkthdr.len += padlen; |
| 3112 | return 0; |
| 3113 | } |
| 3114 | |
| 3115 | static int |
| 3116 | re_sysctl_rxtime(SYSCTL_HANDLER_ARGS) |
| 3117 | { |
| 3118 | struct re_softc *sc = arg1; |
| 3119 | |
| 3120 | return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_rx_time); |
| 3121 | } |
| 3122 | |
| 3123 | static int |
| 3124 | re_sysctl_txtime(SYSCTL_HANDLER_ARGS) |
| 3125 | { |
| 3126 | struct re_softc *sc = arg1; |
| 3127 | |
| 3128 | return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_tx_time); |
| 3129 | } |
| 3130 | |
| 3131 | static int |
| 3132 | re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *hwtime) |
| 3133 | { |
| 3134 | struct re_softc *sc = arg1; |
| 3135 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 3136 | int error, v; |
| 3137 | |
| 3138 | lwkt_serialize_enter(ifp->if_serializer); |
| 3139 | |
| 3140 | v = *hwtime; |
| 3141 | error = sysctl_handle_int(oidp, &v, 0, req); |
| 3142 | if (error || req->newptr == NULL) |
| 3143 | goto back; |
| 3144 | |
| 3145 | if (v <= 0) { |
| 3146 | error = EINVAL; |
| 3147 | goto back; |
| 3148 | } |
| 3149 | |
| 3150 | if (v != *hwtime) { |
| 3151 | *hwtime = v; |
| 3152 | |
| 3153 | if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) == |
| 3154 | IFF_RUNNING && sc->re_imtype == RE_IMTYPE_HW) |
| 3155 | re_setup_hw_im(sc); |
| 3156 | } |
| 3157 | back: |
| 3158 | lwkt_serialize_exit(ifp->if_serializer); |
| 3159 | return error; |
| 3160 | } |
| 3161 | |
| 3162 | static int |
| 3163 | re_sysctl_simtime(SYSCTL_HANDLER_ARGS) |
| 3164 | { |
| 3165 | struct re_softc *sc = arg1; |
| 3166 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 3167 | int error, v; |
| 3168 | |
| 3169 | lwkt_serialize_enter(ifp->if_serializer); |
| 3170 | |
| 3171 | v = sc->re_sim_time; |
| 3172 | error = sysctl_handle_int(oidp, &v, 0, req); |
| 3173 | if (error || req->newptr == NULL) |
| 3174 | goto back; |
| 3175 | |
| 3176 | if (v <= 0) { |
| 3177 | error = EINVAL; |
| 3178 | goto back; |
| 3179 | } |
| 3180 | |
| 3181 | if (v != sc->re_sim_time) { |
| 3182 | sc->re_sim_time = v; |
| 3183 | |
| 3184 | if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) == |
| 3185 | IFF_RUNNING && sc->re_imtype == RE_IMTYPE_SIM) { |
| 3186 | #ifdef foo |
| 3187 | int reg; |
| 3188 | |
| 3189 | /* |
| 3190 | * Following code causes various strange |
| 3191 | * performance problems. Hmm ... |
| 3192 | */ |
| 3193 | CSR_WRITE_2(sc, RE_IMR, 0); |
| 3194 | if (!RE_IS_8139CP(sc)) |
| 3195 | reg = RE_TIMERINT_8169; |
| 3196 | else |
| 3197 | reg = RE_TIMERINT; |
| 3198 | CSR_WRITE_4(sc, reg, 0); |
| 3199 | CSR_READ_4(sc, reg); /* flush */ |
| 3200 | |
| 3201 | CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); |
| 3202 | re_setup_sim_im(sc); |
| 3203 | #else |
| 3204 | re_setup_intr(sc, 0, RE_IMTYPE_NONE); |
| 3205 | DELAY(10); |
| 3206 | re_setup_intr(sc, 1, RE_IMTYPE_SIM); |
| 3207 | #endif |
| 3208 | } |
| 3209 | } |
| 3210 | back: |
| 3211 | lwkt_serialize_exit(ifp->if_serializer); |
| 3212 | return error; |
| 3213 | } |
| 3214 | |
| 3215 | static int |
| 3216 | re_sysctl_imtype(SYSCTL_HANDLER_ARGS) |
| 3217 | { |
| 3218 | struct re_softc *sc = arg1; |
| 3219 | struct ifnet *ifp = &sc->arpcom.ac_if; |
| 3220 | int error, v; |
| 3221 | |
| 3222 | lwkt_serialize_enter(ifp->if_serializer); |
| 3223 | |
| 3224 | v = sc->re_imtype; |
| 3225 | error = sysctl_handle_int(oidp, &v, 0, req); |
| 3226 | if (error || req->newptr == NULL) |
| 3227 | goto back; |
| 3228 | |
| 3229 | if (v != RE_IMTYPE_HW && v != RE_IMTYPE_SIM && v != RE_IMTYPE_NONE) { |
| 3230 | error = EINVAL; |
| 3231 | goto back; |
| 3232 | } |
| 3233 | if (v == RE_IMTYPE_HW && (sc->re_caps & RE_C_HWIM) == 0) { |
| 3234 | /* Can't do hardware interrupt moderation */ |
| 3235 | error = EOPNOTSUPP; |
| 3236 | goto back; |
| 3237 | } |
| 3238 | |
| 3239 | if (v != sc->re_imtype) { |
| 3240 | sc->re_imtype = v; |
| 3241 | if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) == |
| 3242 | IFF_RUNNING) |
| 3243 | re_setup_intr(sc, 1, sc->re_imtype); |
| 3244 | } |
| 3245 | back: |
| 3246 | lwkt_serialize_exit(ifp->if_serializer); |
| 3247 | return error; |
| 3248 | } |
| 3249 | |
| 3250 | static void |
| 3251 | re_setup_hw_im(struct re_softc *sc) |
| 3252 | { |
| 3253 | KKASSERT(sc->re_caps & RE_C_HWIM); |
| 3254 | |
| 3255 | /* |
| 3256 | * Interrupt moderation |
| 3257 | * |
| 3258 | * 0xABCD |
| 3259 | * A - unknown (maybe TX related) |
| 3260 | * B - TX timer (unit: 25us) |
| 3261 | * C - unknown (maybe RX related) |
| 3262 | * D - RX timer (unit: 25us) |
| 3263 | * |
| 3264 | * |
| 3265 | * re(4)'s interrupt moderation is actually controlled by |
| 3266 | * two variables, like most other NICs (bge, bce etc.) |
| 3267 | * o timer |
| 3268 | * o number of packets [P] |
| 3269 | * |
| 3270 | * The logic relationship between these two variables is |
| 3271 | * similar to other NICs too: |
| 3272 | * if (timer expire || packets > [P]) |
| 3273 | * Interrupt is delivered |
| 3274 | * |
| 3275 | * Currently we only know how to set 'timer', but not |
| 3276 | * 'number of packets', which should be ~30, as far as I |
| 3277 | * tested (sink ~900Kpps, interrupt rate is 30KHz) |
| 3278 | */ |
| 3279 | CSR_WRITE_2(sc, RE_IM, |
| 3280 | RE_IM_RXTIME(sc->re_rx_time) | |
| 3281 | RE_IM_TXTIME(sc->re_tx_time) | |
| 3282 | RE_IM_MAGIC); |
| 3283 | } |
| 3284 | |
| 3285 | static void |
| 3286 | re_disable_hw_im(struct re_softc *sc) |
| 3287 | { |
| 3288 | if (sc->re_caps & RE_C_HWIM) |
| 3289 | CSR_WRITE_2(sc, RE_IM, 0); |
| 3290 | } |
| 3291 | |
| 3292 | static void |
| 3293 | re_setup_sim_im(struct re_softc *sc) |
| 3294 | { |
| 3295 | if (!RE_IS_8139CP(sc)) { |
| 3296 | uint32_t ticks; |
| 3297 | |
| 3298 | /* |
| 3299 | * Datasheet says tick decreases at bus speed, |
| 3300 | * but it seems the clock runs a little bit |
| 3301 | * faster, so we do some compensation here. |
| 3302 | */ |
| 3303 | ticks = (sc->re_sim_time * sc->re_bus_speed * 8) / 5; |
| 3304 | CSR_WRITE_4(sc, RE_TIMERINT_8169, ticks); |
| 3305 | } else { |
| 3306 | CSR_WRITE_4(sc, RE_TIMERINT, 0x400); /* XXX */ |
| 3307 | } |
| 3308 | CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */ |
| 3309 | sc->re_flags |= RE_F_TIMER_INTR; |
| 3310 | } |
| 3311 | |
| 3312 | static void |
| 3313 | re_disable_sim_im(struct re_softc *sc) |
| 3314 | { |
| 3315 | if (!RE_IS_8139CP(sc)) |
| 3316 | CSR_WRITE_4(sc, RE_TIMERINT_8169, 0); |
| 3317 | else |
| 3318 | CSR_WRITE_4(sc, RE_TIMERINT, 0); |
| 3319 | sc->re_flags &= ~RE_F_TIMER_INTR; |
| 3320 | } |
| 3321 | |
| 3322 | static void |
| 3323 | re_config_imtype(struct re_softc *sc, int imtype) |
| 3324 | { |
| 3325 | switch (imtype) { |
| 3326 | case RE_IMTYPE_HW: |
| 3327 | KKASSERT(sc->re_caps & RE_C_HWIM); |
| 3328 | /* FALL THROUGH */ |
| 3329 | case RE_IMTYPE_NONE: |
| 3330 | sc->re_intrs = RE_INTRS; |
| 3331 | sc->re_rx_ack = RE_ISR_RX_OK | RE_ISR_FIFO_OFLOW | |
| 3332 | RE_ISR_RX_OVERRUN; |
| 3333 | sc->re_tx_ack = RE_ISR_TX_OK; |
| 3334 | break; |
| 3335 | |
| 3336 | case RE_IMTYPE_SIM: |
| 3337 | sc->re_intrs = RE_INTRS_TIMER; |
| 3338 | sc->re_rx_ack = RE_ISR_TIMEOUT_EXPIRED; |
| 3339 | sc->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED; |
| 3340 | break; |
| 3341 | |
| 3342 | default: |
| 3343 | panic("%s: unknown imtype %d\n", |
| 3344 | sc->arpcom.ac_if.if_xname, imtype); |
| 3345 | } |
| 3346 | } |
| 3347 | |
| 3348 | static void |
| 3349 | re_setup_intr(struct re_softc *sc, int enable_intrs, int imtype) |
| 3350 | { |
| 3351 | re_config_imtype(sc, imtype); |
| 3352 | |
| 3353 | if (enable_intrs) |
| 3354 | CSR_WRITE_2(sc, RE_IMR, sc->re_intrs); |
| 3355 | else |
| 3356 | CSR_WRITE_2(sc, RE_IMR, 0); |
| 3357 | |
| 3358 | switch (imtype) { |
| 3359 | case RE_IMTYPE_NONE: |
| 3360 | re_disable_sim_im(sc); |
| 3361 | re_disable_hw_im(sc); |
| 3362 | break; |
| 3363 | |
| 3364 | case RE_IMTYPE_HW: |
| 3365 | KKASSERT(sc->re_caps & RE_C_HWIM); |
| 3366 | re_disable_sim_im(sc); |
| 3367 | re_setup_hw_im(sc); |
| 3368 | break; |
| 3369 | |
| 3370 | case RE_IMTYPE_SIM: |
| 3371 | re_disable_hw_im(sc); |
| 3372 | re_setup_sim_im(sc); |
| 3373 | break; |
| 3374 | |
| 3375 | default: |
| 3376 | panic("%s: unknown imtype %d\n", |
| 3377 | sc->arpcom.ac_if.if_xname, imtype); |
| 3378 | } |
| 3379 | } |
| 3380 | |
| 3381 | static void |
| 3382 | re_get_eaddr(struct re_softc *sc, uint8_t *eaddr) |
| 3383 | { |
| 3384 | int i; |
| 3385 | |
| 3386 | if (sc->re_macver == RE_MACVER_11 || sc->re_macver == RE_MACVER_12) { |
| 3387 | uint16_t re_did; |
| 3388 | |
| 3389 | re_get_eewidth(sc); |
| 3390 | re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); |
| 3391 | if (re_did == 0x8128) { |
| 3392 | uint16_t as[ETHER_ADDR_LEN / 2]; |
| 3393 | |
| 3394 | /* |
| 3395 | * Get station address from the EEPROM. |
| 3396 | */ |
| 3397 | re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3); |
| 3398 | for (i = 0; i < ETHER_ADDR_LEN / 2; i++) |
| 3399 | as[i] = le16toh(as[i]); |
| 3400 | bcopy(as, eaddr, sizeof(eaddr)); |
| 3401 | return; |
| 3402 | } |
| 3403 | } |
| 3404 | |
| 3405 | /* |
| 3406 | * Get station address from IDRx. |
| 3407 | */ |
| 3408 | for (i = 0; i < ETHER_ADDR_LEN; ++i) |
| 3409 | eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i); |
| 3410 | } |
| 3411 | |
| 3412 | static void |
| 3413 | re_set_max_readrq(struct re_softc *sc, uint16_t size) |
| 3414 | { |
| 3415 | device_t dev = sc->re_dev; |
| 3416 | uint8_t expr_ptr; |
| 3417 | uint16_t val, rqsize; |
| 3418 | |
| 3419 | rqsize = size & PCIEM_DEVCTL_MAX_READRQ_MASK; |
| 3420 | if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) |
| 3421 | panic("invalid read request size %02x\n", rqsize); |
| 3422 | |
| 3423 | expr_ptr = pci_get_pciecap_ptr(dev); |
| 3424 | KKASSERT(expr_ptr != 0); |
| 3425 | |
| 3426 | val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2); |
| 3427 | if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) { |
| 3428 | device_printf(dev, "adjust device control " |
| 3429 | "0x%04x ", val); |
| 3430 | |
| 3431 | val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK; |
| 3432 | val |= rqsize; |
| 3433 | pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2); |
| 3434 | |
| 3435 | kprintf("-> 0x%04x\n", val); |
| 3436 | } |
| 3437 | } |
| 3438 | |
| 3439 | static int |
| 3440 | re_jpool_alloc(struct re_softc *sc) |
| 3441 | { |
| 3442 | struct re_list_data *ldata = &sc->re_ldata; |
| 3443 | struct re_jbuf *jbuf; |
| 3444 | bus_addr_t paddr; |
| 3445 | bus_size_t jpool_size; |
| 3446 | caddr_t buf; |
| 3447 | int i, error; |
| 3448 | |
| 3449 | lwkt_serialize_init(&ldata->re_jbuf_serializer); |
| 3450 | |
| 3451 | ldata->re_jbuf = kmalloc(sizeof(struct re_jbuf) * RE_JBUF_COUNT(sc), |
| 3452 | M_DEVBUF, M_WAITOK | M_ZERO); |
| 3453 | |
| 3454 | jpool_size = RE_JBUF_COUNT(sc) * RE_JBUF_SIZE; |
| 3455 | |
| 3456 | error = bus_dma_tag_create(sc->re_parent_tag, |
| 3457 | RE_BUF_ALIGN, 0, /* alignment, boundary */ |
| 3458 | BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ |
| 3459 | BUS_SPACE_MAXADDR, /* highaddr */ |
| 3460 | NULL, NULL, /* filter, filterarg */ |
| 3461 | jpool_size, 1, /* nsegments, maxsize */ |
| 3462 | BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ |
| 3463 | BUS_DMA_ALLOCNOW, /* flags */ |
| 3464 | &ldata->re_jpool_tag); |
| 3465 | if (error) { |
| 3466 | device_printf(sc->re_dev, "could not allocate jumbo dma tag\n"); |
| 3467 | return error; |
| 3468 | } |
| 3469 | |
| 3470 | error = bus_dmamem_alloc(ldata->re_jpool_tag, (void **)&ldata->re_jpool, |
| 3471 | BUS_DMA_WAITOK, &ldata->re_jpool_map); |
| 3472 | if (error) { |
| 3473 | device_printf(sc->re_dev, |
| 3474 | "could not allocate jumbo dma memory\n"); |
| 3475 | bus_dma_tag_destroy(ldata->re_jpool_tag); |
| 3476 | ldata->re_jpool_tag = NULL; |
| 3477 | return error; |
| 3478 | } |
| 3479 | |
| 3480 | error = bus_dmamap_load(ldata->re_jpool_tag, ldata->re_jpool_map, |
| 3481 | ldata->re_jpool, jpool_size, |
| 3482 | re_dma_map_addr, &paddr, BUS_DMA_WAITOK); |
| 3483 | if (error) { |
| 3484 | device_printf(sc->re_dev, "could not load jumbo dma map\n"); |
| 3485 | bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool, |
| 3486 | ldata->re_jpool_map); |
| 3487 | bus_dma_tag_destroy(ldata->re_jpool_tag); |
| 3488 | ldata->re_jpool_tag = NULL; |
| 3489 | return error; |
| 3490 | } |
| 3491 | |
| 3492 | /* ..and split it into 9KB chunks */ |
| 3493 | SLIST_INIT(&ldata->re_jbuf_free); |
| 3494 | |
| 3495 | buf = ldata->re_jpool; |
| 3496 | for (i = 0; i < RE_JBUF_COUNT(sc); i++) { |
| 3497 | jbuf = &ldata->re_jbuf[i]; |
| 3498 | |
| 3499 | jbuf->re_sc = sc; |
| 3500 | jbuf->re_inuse = 0; |
| 3501 | jbuf->re_slot = i; |
| 3502 | jbuf->re_buf = buf; |
| 3503 | jbuf->re_paddr = paddr; |
| 3504 | |
| 3505 | SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link); |
| 3506 | |
| 3507 | buf += RE_JBUF_SIZE; |
| 3508 | paddr += RE_JBUF_SIZE; |
| 3509 | } |
| 3510 | return 0; |
| 3511 | } |
| 3512 | |
| 3513 | static void |
| 3514 | re_jpool_free(struct re_softc *sc) |
| 3515 | { |
| 3516 | struct re_list_data *ldata = &sc->re_ldata; |
| 3517 | |
| 3518 | if (ldata->re_jpool_tag != NULL) { |
| 3519 | bus_dmamap_unload(ldata->re_jpool_tag, ldata->re_jpool_map); |
| 3520 | bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool, |
| 3521 | ldata->re_jpool_map); |
| 3522 | bus_dma_tag_destroy(ldata->re_jpool_tag); |
| 3523 | ldata->re_jpool_tag = NULL; |
| 3524 | } |
| 3525 | |
| 3526 | if (ldata->re_jbuf != NULL) { |
| 3527 | kfree(ldata->re_jbuf, M_DEVBUF); |
| 3528 | ldata->re_jbuf = NULL; |
| 3529 | } |
| 3530 | } |
| 3531 | |
| 3532 | static struct re_jbuf * |
| 3533 | re_jbuf_alloc(struct re_softc *sc) |
| 3534 | { |
| 3535 | struct re_list_data *ldata = &sc->re_ldata; |
| 3536 | struct re_jbuf *jbuf; |
| 3537 | |
| 3538 | lwkt_serialize_enter(&ldata->re_jbuf_serializer); |
| 3539 | |
| 3540 | jbuf = SLIST_FIRST(&ldata->re_jbuf_free); |
| 3541 | if (jbuf != NULL) { |
| 3542 | SLIST_REMOVE_HEAD(&ldata->re_jbuf_free, re_link); |
| 3543 | jbuf->re_inuse = 1; |
| 3544 | } |
| 3545 | |
| 3546 | lwkt_serialize_exit(&ldata->re_jbuf_serializer); |
| 3547 | |
| 3548 | return jbuf; |
| 3549 | } |
| 3550 | |
| 3551 | static void |
| 3552 | re_jbuf_free(void *arg) |
| 3553 | { |
| 3554 | struct re_jbuf *jbuf = arg; |
| 3555 | struct re_softc *sc = jbuf->re_sc; |
| 3556 | struct re_list_data *ldata = &sc->re_ldata; |
| 3557 | |
| 3558 | if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) { |
| 3559 | panic("%s: free wrong jumbo buffer\n", |
| 3560 | sc->arpcom.ac_if.if_xname); |
| 3561 | } else if (jbuf->re_inuse == 0) { |
| 3562 | panic("%s: jumbo buffer already freed\n", |
| 3563 | sc->arpcom.ac_if.if_xname); |
| 3564 | } |
| 3565 | |
| 3566 | lwkt_serialize_enter(&ldata->re_jbuf_serializer); |
| 3567 | atomic_subtract_int(&jbuf->re_inuse, 1); |
| 3568 | if (jbuf->re_inuse == 0) |
| 3569 | SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link); |
| 3570 | lwkt_serialize_exit(&ldata->re_jbuf_serializer); |
| 3571 | } |
| 3572 | |
| 3573 | static void |
| 3574 | re_jbuf_ref(void *arg) |
| 3575 | { |
| 3576 | struct re_jbuf *jbuf = arg; |
| 3577 | struct re_softc *sc = jbuf->re_sc; |
| 3578 | struct re_list_data *ldata = &sc->re_ldata; |
| 3579 | |
| 3580 | if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) { |
| 3581 | panic("%s: ref wrong jumbo buffer\n", |
| 3582 | sc->arpcom.ac_if.if_xname); |
| 3583 | } else if (jbuf->re_inuse == 0) { |
| 3584 | panic("%s: jumbo buffer already freed\n", |
| 3585 | sc->arpcom.ac_if.if_xname); |
| 3586 | } |
| 3587 | atomic_add_int(&jbuf->re_inuse, 1); |
| 3588 | } |