| 1 | /* |
| 2 | * Copyright (c) 2004 |
| 3 | * Joerg Sonnenberger <joerg@bec.de>. All rights reserved. |
| 4 | * |
| 5 | * Copyright (c) 1997, 1998-2003 |
| 6 | * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. |
| 7 | * |
| 8 | * Redistribution and use in source and binary forms, with or without |
| 9 | * modification, are permitted provided that the following conditions |
| 10 | * are met: |
| 11 | * 1. Redistributions of source code must retain the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer. |
| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer in the |
| 15 | * documentation and/or other materials provided with the distribution. |
| 16 | * 3. All advertising materials mentioning features or use of this software |
| 17 | * must display the following acknowledgement: |
| 18 | * This product includes software developed by Bill Paul. |
| 19 | * 4. Neither the name of the author nor the names of any co-contributors |
| 20 | * may be used to endorse or promote products derived from this software |
| 21 | * without specific prior written permission. |
| 22 | * |
| 23 | * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND |
| 24 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 25 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 26 | * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD |
| 27 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 28 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 29 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 30 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 31 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 32 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 33 | * THE POSSIBILITY OF SUCH DAMAGE. |
| 34 | * |
| 35 | * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.42 2004/05/24 19:39:23 jhb Exp $ |
| 36 | * $DragonFly: src/sys/dev/netif/re/if_rereg.h,v 1.24 2008/10/19 06:00:24 sephe Exp $ |
| 37 | */ |
| 38 | |
| 39 | /* |
| 40 | * RealTek 8129/8139 register offsets |
| 41 | */ |
| 42 | #define RE_IDR0 0x0000 /* ID register 0 (station addr) */ |
| 43 | #define RE_IDR1 0x0001 /* Must use 32-bit accesses (?) */ |
| 44 | #define RE_IDR2 0x0002 |
| 45 | #define RE_IDR3 0x0003 |
| 46 | #define RE_IDR4 0x0004 |
| 47 | #define RE_IDR5 0x0005 |
| 48 | /* 0006-0007 reserved */ |
| 49 | #define RE_MAR0 0x0008 /* Multicast hash table */ |
| 50 | #define RE_MAR1 0x0009 |
| 51 | #define RE_MAR2 0x000A |
| 52 | #define RE_MAR3 0x000B |
| 53 | #define RE_MAR4 0x000C |
| 54 | #define RE_MAR5 0x000D |
| 55 | #define RE_MAR6 0x000E |
| 56 | #define RE_MAR7 0x000F |
| 57 | |
| 58 | #define RE_RXADDR 0x0030 /* RX ring start address */ |
| 59 | #define RE_RX_EARLY_BYTES 0x0034 /* RX early byte count */ |
| 60 | #define RE_RX_EARLY_STAT 0x0036 /* RX early status */ |
| 61 | #define RE_COMMAND 0x0037 /* command register */ |
| 62 | #define RE_CURRXADDR 0x0038 /* current address of packet read */ |
| 63 | #define RE_CURRXBUF 0x003A /* current RX buffer address */ |
| 64 | #define RE_IMR 0x003C /* interrupt mask register */ |
| 65 | #define RE_ISR 0x003E /* interrupt status register */ |
| 66 | #define RE_TXCFG 0x0040 /* transmit config */ |
| 67 | #define RE_RXCFG 0x0044 /* receive config */ |
| 68 | #define RE_TIMERCNT 0x0048 /* timer count register */ |
| 69 | #define RE_MISSEDPKT 0x004C /* missed packet counter */ |
| 70 | #define RE_EECMD 0x0050 /* EEPROM command register */ |
| 71 | #define RE_CFG0 0x0051 /* config register #0 */ |
| 72 | #define RE_CFG1 0x0052 /* config register #1 */ |
| 73 | #define RE_CFG2 0x0053 /* config register #2 */ |
| 74 | /* 0054-0057 reserved */ |
| 75 | #define RE_MEDIASTAT 0x0058 /* media status register (8139) */ |
| 76 | /* 0059-005A reserved */ |
| 77 | #define RE_MII 0x005A /* 8129 chip only */ |
| 78 | #define RE_HALTCLK 0x005B |
| 79 | #define RE_MULTIINTR 0x005C /* multiple interrupt */ |
| 80 | #define RE_PCIREV 0x005E /* PCI revision value */ |
| 81 | /* 005F reserved */ |
| 82 | #define RE_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ |
| 83 | |
| 84 | /* Direct PHY access registers only available on 8139 */ |
| 85 | #define RE_BMCR 0x0062 /* PHY basic mode control */ |
| 86 | #define RE_BMSR 0x0064 /* PHY basic mode status */ |
| 87 | #define RE_ANAR 0x0066 /* PHY autoneg advert */ |
| 88 | #define RE_LPAR 0x0068 /* PHY link partner ability */ |
| 89 | #define RE_ANER 0x006A /* PHY autoneg expansion */ |
| 90 | |
| 91 | #define RE_DISCCNT 0x006C /* disconnect counter */ |
| 92 | #define RE_FALSECAR 0x006E /* false carrier counter */ |
| 93 | #define RE_NWAYTST 0x0070 /* NWAY test register */ |
| 94 | #define RE_RX_ER 0x0072 /* RX_ER counter */ |
| 95 | #define RE_CSCFG 0x0074 /* CS configuration register */ |
| 96 | |
| 97 | /* |
| 98 | * When operating in special C+ mode, some of the registers in an |
| 99 | * 8139C+ chip have different definitions. These are also used for |
| 100 | * the 8169 gigE chip. |
| 101 | */ |
| 102 | #define RE_DUMPSTATS_LO 0x0010 /* counter dump command register */ |
| 103 | #define RE_DUMPSTATS_HI 0x0014 /* counter dump command register */ |
| 104 | #define RE_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ |
| 105 | #define RE_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ |
| 106 | #define RE_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ |
| 107 | #define RE_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ |
| 108 | #define RE_CFG2 0x0053 |
| 109 | #define RE_TIMERINT 0x0054 /* interrupt on timer expire */ |
| 110 | #define RE_TXSTART 0x00D9 /* 8 bits */ |
| 111 | #define RE_CPLUS_CMD 0x00E0 /* 16 bits */ |
| 112 | #define RE_IM 0x00E2 /* 16 bits */ |
| 113 | #define RE_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ |
| 114 | #define RE_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ |
| 115 | #define RE_EARLY_TX_THRESH 0x00EC /* 8 bits */ |
| 116 | |
| 117 | /* |
| 118 | * Registers specific to the 8169 gigE chip |
| 119 | */ |
| 120 | #define RE_TIMERINT_8169 0x0058 /* different offset than 8139 */ |
| 121 | #define RE_PHYAR 0x0060 |
| 122 | #define RE_TBICSR 0x0064 |
| 123 | #define RE_TBI_ANAR 0x0068 |
| 124 | #define RE_TBI_LPAR 0x006A |
| 125 | #define RE_GMEDIASTAT 0x006C /* 8 bits */ |
| 126 | #define RE_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ |
| 127 | #define RE_GTXSTART 0x0038 /* 16 bits */ |
| 128 | |
| 129 | /* |
| 130 | * TX config register bits |
| 131 | */ |
| 132 | #define RE_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ |
| 133 | #define RE_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ |
| 134 | #define RE_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ |
| 135 | #define RE_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ |
| 136 | #define RE_TXCFG_IFG2 0x00080000 /* 8169 only */ |
| 137 | #define RE_TXCFG_IFG 0x03000000 /* interframe gap */ |
| 138 | #define RE_TXCFG_HWREV 0xFC800000 |
| 139 | #define RE_TXCFG_MACMODE 0x00700000 |
| 140 | |
| 141 | /* |
| 142 | * Config 2 register bits |
| 143 | */ |
| 144 | #define RE_CFG2_PCICLK_MASK 0x07 |
| 145 | #define RE_CFG2_PCICLK_33MHZ 0x00 |
| 146 | #define RE_CFG2_PCICLK_66MHZ 0x01 |
| 147 | #define RE_CFG2_PCI64 0x08 |
| 148 | |
| 149 | #define RE_LOOPTEST_OFF 0x00000000 |
| 150 | #define RE_LOOPTEST_ON 0x00020000 |
| 151 | #define RE_LOOPTEST_ON_CPLUS 0x00060000 |
| 152 | |
| 153 | #define RE_HWREV_8169 0x00000000 |
| 154 | #define RE_HWREV_8110S 0x00800000 |
| 155 | #define RE_HWREV_8169S 0x04000000 |
| 156 | #define RE_HWREV_8169SB 0x10000000 |
| 157 | #define RE_HWREV_8169SC1 0x18000000 |
| 158 | #define RE_HWREV_8102EL 0x24800000 |
| 159 | #define RE_HWREV_8168D 0x28000000 |
| 160 | #define RE_HWREV_8168B1 0x30000000 |
| 161 | #define RE_HWREV_8100E 0x30800000 |
| 162 | #define RE_HWREV_8101E1 0x34000000 |
| 163 | #define RE_HWREV_8102E 0x34800000 |
| 164 | #define RE_HWREV_8168B2 0x38000000 |
| 165 | #define RE_HWREV_8168C 0x3C000000 |
| 166 | #define RE_HWREV_8168CP 0x3C800000 |
| 167 | #define RE_HWREV_8139CPLUS 0x74800000 |
| 168 | #define RE_HWREV_8169SC2 0x98000000 |
| 169 | #define RE_HWREV_8101E2 0xB4000000 |
| 170 | #define RE_HWREV_8168B3 0xB8000000 |
| 171 | #define RE_HWREV_NULL 0xffffffff |
| 172 | |
| 173 | #define RE_TXDMA_16BYTES 0x00000000 |
| 174 | #define RE_TXDMA_32BYTES 0x00000100 |
| 175 | #define RE_TXDMA_64BYTES 0x00000200 |
| 176 | #define RE_TXDMA_128BYTES 0x00000300 |
| 177 | #define RE_TXDMA_256BYTES 0x00000400 |
| 178 | #define RE_TXDMA_512BYTES 0x00000500 |
| 179 | #define RE_TXDMA_1024BYTES 0x00000600 |
| 180 | #define RE_TXDMA_2048BYTES 0x00000700 |
| 181 | |
| 182 | /* |
| 183 | * Transmit descriptor status register bits. |
| 184 | */ |
| 185 | #define RE_TXSTAT_LENMASK 0x00001FFF |
| 186 | #define RE_TXSTAT_OWN 0x00002000 |
| 187 | #define RE_TXSTAT_TX_UNDERRUN 0x00004000 |
| 188 | #define RE_TXSTAT_TX_OK 0x00008000 |
| 189 | #define RE_TXSTAT_EARLY_THRESH 0x003F0000 |
| 190 | #define RE_TXSTAT_COLLCNT 0x0F000000 |
| 191 | #define RE_TXSTAT_CARR_HBEAT 0x10000000 |
| 192 | #define RE_TXSTAT_OUTOFWIN 0x20000000 |
| 193 | #define RE_TXSTAT_TXABRT 0x40000000 |
| 194 | #define RE_TXSTAT_CARRLOSS 0x80000000 |
| 195 | |
| 196 | /* |
| 197 | * Interrupt status register bits. |
| 198 | */ |
| 199 | #define RE_ISR_RX_OK 0x0001 |
| 200 | #define RE_ISR_RX_ERR 0x0002 |
| 201 | #define RE_ISR_TX_OK 0x0004 |
| 202 | #define RE_ISR_TX_ERR 0x0008 |
| 203 | #define RE_ISR_RX_OVERRUN 0x0010 |
| 204 | #define RE_ISR_LINKCHG 0x0020 /* 8169 only */ |
| 205 | #define RE_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ |
| 206 | #define RE_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ |
| 207 | #define RE_ISR_SWI 0x0100 /* C+ only */ |
| 208 | #define RE_ISR_CABLE_LEN_CHGD 0x2000 |
| 209 | #define RE_ISR_TIMEOUT_EXPIRED 0x4000 |
| 210 | #define RE_ISR_SYSTEM_ERR 0x8000 |
| 211 | |
| 212 | #define RE_INTRS \ |
| 213 | (RE_ISR_RX_OK|RE_ISR_RX_ERR|RE_ISR_TX_ERR| \ |
| 214 | RE_ISR_RX_OVERRUN|RE_ISR_FIFO_OFLOW|RE_ISR_LINKCHG| \ |
| 215 | RE_ISR_SYSTEM_ERR|RE_ISR_TX_OK) |
| 216 | |
| 217 | #define RE_INTRS_TIMER \ |
| 218 | (RE_ISR_RX_ERR|RE_ISR_TX_ERR| \ |
| 219 | RE_ISR_LINKCHG|RE_ISR_SYSTEM_ERR| \ |
| 220 | RE_ISR_TIMEOUT_EXPIRED) |
| 221 | |
| 222 | #ifdef RE_DIAG |
| 223 | #define RE_INTRS_DIAG \ |
| 224 | (RE_ISR_TX_OK|RE_ISR_RX_OK|RE_ISR_RX_ERR|RE_ISR_TX_ERR| \ |
| 225 | RE_ISR_RX_OVERRUN|RE_ISR_FIFO_OFLOW|RE_ISR_LINKCHG| \ |
| 226 | RE_ISR_SYSTEM_ERR) |
| 227 | #endif |
| 228 | |
| 229 | /* |
| 230 | * Media status register. (8139 only) |
| 231 | */ |
| 232 | #define RE_MEDIASTAT_RXPAUSE 0x01 |
| 233 | #define RE_MEDIASTAT_TXPAUSE 0x02 |
| 234 | #define RE_MEDIASTAT_LINK 0x04 |
| 235 | #define RE_MEDIASTAT_SPEED10 0x08 |
| 236 | #define RE_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ |
| 237 | #define RE_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ |
| 238 | |
| 239 | /* |
| 240 | * Receive config register. |
| 241 | */ |
| 242 | #define RE_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ |
| 243 | #define RE_RXCFG_RX_INDIV 0x00000002 /* match filter */ |
| 244 | #define RE_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ |
| 245 | #define RE_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ |
| 246 | #define RE_RXCFG_RX_RUNT 0x00000010 |
| 247 | #define RE_RXCFG_RX_ERRPKT 0x00000020 |
| 248 | #define RE_RXCFG_WRAP 0x00000080 |
| 249 | #define RE_RXCFG_MAXDMA 0x00000700 |
| 250 | #define RE_RXCFG_BUFSZ 0x00001800 |
| 251 | #define RE_RXCFG_FIFOTHRESH 0x0000E000 |
| 252 | #define RE_RXCFG_EARLYTHRESH 0x07000000 |
| 253 | |
| 254 | #define RE_RXDMA_16BYTES 0x00000000 |
| 255 | #define RE_RXDMA_32BYTES 0x00000100 |
| 256 | #define RE_RXDMA_64BYTES 0x00000200 |
| 257 | #define RE_RXDMA_128BYTES 0x00000300 |
| 258 | #define RE_RXDMA_256BYTES 0x00000400 |
| 259 | #define RE_RXDMA_512BYTES 0x00000500 |
| 260 | #define RE_RXDMA_1024BYTES 0x00000600 |
| 261 | #define RE_RXDMA_UNLIMITED 0x00000700 |
| 262 | |
| 263 | #define RE_RXBUF_8 0x00000000 |
| 264 | #define RE_RXBUF_16 0x00000800 |
| 265 | #define RE_RXBUF_32 0x00001000 |
| 266 | #define RE_RXBUF_64 0x00001800 |
| 267 | |
| 268 | #define RE_RXFIFO_16BYTES 0x00000000 |
| 269 | #define RE_RXFIFO_32BYTES 0x00002000 |
| 270 | #define RE_RXFIFO_64BYTES 0x00004000 |
| 271 | #define RE_RXFIFO_128BYTES 0x00006000 |
| 272 | #define RE_RXFIFO_256BYTES 0x00008000 |
| 273 | #define RE_RXFIFO_512BYTES 0x0000A000 |
| 274 | #define RE_RXFIFO_1024BYTES 0x0000C000 |
| 275 | #define RE_RXFIFO_NOTHRESH 0x0000E000 |
| 276 | |
| 277 | /* |
| 278 | * Bits in RX status header (included with RX'ed packet |
| 279 | * in ring buffer). |
| 280 | */ |
| 281 | #define RE_RXSTAT_RXOK 0x00000001 |
| 282 | #define RE_RXSTAT_ALIGNERR 0x00000002 |
| 283 | #define RE_RXSTAT_CRCERR 0x00000004 |
| 284 | #define RE_RXSTAT_GIANT 0x00000008 |
| 285 | #define RE_RXSTAT_RUNT 0x00000010 |
| 286 | #define RE_RXSTAT_BADSYM 0x00000020 |
| 287 | #define RE_RXSTAT_BROAD 0x00002000 |
| 288 | #define RE_RXSTAT_INDIV 0x00004000 |
| 289 | #define RE_RXSTAT_MULTI 0x00008000 |
| 290 | #define RE_RXSTAT_LENMASK 0xFFFF0000 |
| 291 | |
| 292 | #define RE_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ |
| 293 | /* |
| 294 | * Command register. |
| 295 | */ |
| 296 | #define RE_CMD_EMPTY_RXBUF 0x0001 |
| 297 | #define RE_CMD_TX_ENB 0x0004 |
| 298 | #define RE_CMD_RX_ENB 0x0008 |
| 299 | #define RE_CMD_RESET 0x0010 |
| 300 | #define RE_CMD_STOPREQ 0x0080 |
| 301 | |
| 302 | /* |
| 303 | * EEPROM control register |
| 304 | */ |
| 305 | #define RE_EE_DATAOUT 0x01 /* Data out */ |
| 306 | #define RE_EE_DATAIN 0x02 /* Data in */ |
| 307 | #define RE_EE_CLK 0x04 /* clock */ |
| 308 | #define RE_EE_SEL 0x08 /* chip select */ |
| 309 | #define RE_EE_MODE (0x40|0x80) |
| 310 | |
| 311 | #define RE_EEMODE_OFF 0x00 |
| 312 | #define RE_EEMODE_AUTOLOAD 0x40 |
| 313 | #define RE_EEMODE_PROGRAM 0x80 |
| 314 | #define RE_EEMODE_WRITECFG (0x80|0x40) |
| 315 | |
| 316 | /* 9346 EEPROM commands */ |
| 317 | #define RE_9346_READ 0x6 |
| 318 | #define RE_EECMD_WRITE 0x140 |
| 319 | #define RE_EECMD_READ_6BIT 0x180 |
| 320 | #define RE_EECMD_READ_8BIT 0x600 |
| 321 | #define RE_EECMD_ERASE 0x1c0 |
| 322 | |
| 323 | #define RE_EE_ID 0x00 |
| 324 | #define RE_EE_PCI_VID 0x01 |
| 325 | #define RE_EE_PCI_DID 0x02 |
| 326 | /* Location of station address inside EEPROM */ |
| 327 | #define RE_EE_EADDR 0x07 |
| 328 | |
| 329 | /* |
| 330 | * Config 0 register |
| 331 | */ |
| 332 | #define RE_CFG0_ROM0 0x01 |
| 333 | #define RE_CFG0_ROM1 0x02 |
| 334 | #define RE_CFG0_ROM2 0x04 |
| 335 | #define RE_CFG0_PL0 0x08 |
| 336 | #define RE_CFG0_PL1 0x10 |
| 337 | #define RE_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ |
| 338 | #define RE_CFG0_PCS 0x40 |
| 339 | #define RE_CFG0_SCR 0x80 |
| 340 | |
| 341 | /* |
| 342 | * Config 1 register |
| 343 | */ |
| 344 | #define RE_CFG1_PWRDWN 0x01 |
| 345 | #define RE_CFG1_SLEEP 0x02 |
| 346 | #define RE_CFG1_IOMAP 0x04 |
| 347 | #define RE_CFG1_MEMMAP 0x08 |
| 348 | #define RE_CFG1_RSVD 0x10 |
| 349 | #define RE_CFG1_DRVLOAD 0x20 |
| 350 | #define RE_CFG1_LED0 0x40 |
| 351 | #define RE_CFG1_FULLDUPLEX 0x40 /* 8129 only */ |
| 352 | #define RE_CFG1_LED1 0x80 |
| 353 | |
| 354 | /* |
| 355 | * 8139C+ register definitions |
| 356 | */ |
| 357 | |
| 358 | /* RE_DUMPSTATS_LO register */ |
| 359 | |
| 360 | #define RE_DUMPSTATS_START 0x00000008 |
| 361 | |
| 362 | /* Transmit start register */ |
| 363 | |
| 364 | #define RE_TXSTART_SWI 0x01 /* generate TX interrupt */ |
| 365 | #define RE_TXSTART_START 0x40 /* start normal queue transmit */ |
| 366 | #define RE_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ |
| 367 | |
| 368 | /* |
| 369 | * Config 2 register, 8139C+/8169/8169S/8110S only |
| 370 | */ |
| 371 | #define RE_CFG2_BUSFREQ 0x07 |
| 372 | #define RE_CFG2_BUSWIDTH 0x08 |
| 373 | #define RE_CFG2_AUXPWRSTS 0x10 |
| 374 | |
| 375 | #define RE_BUSFREQ_33MHZ 0x00 |
| 376 | #define RE_BUSFREQ_66MHZ 0x01 |
| 377 | |
| 378 | #define RE_BUSWIDTH_32BITS 0x00 |
| 379 | #define RE_BUSWIDTH_64BITS 0x08 |
| 380 | |
| 381 | /* C+ mode command register */ |
| 382 | |
| 383 | #define RE_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ |
| 384 | #define RE_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ |
| 385 | #define RE_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ |
| 386 | #define RE_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ |
| 387 | #define RE_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ |
| 388 | #define RE_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ |
| 389 | |
| 390 | /* C+ early transmit threshold */ |
| 391 | |
| 392 | #define RE_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ |
| 393 | |
| 394 | /* |
| 395 | * Gigabit PHY access register (8169 only) |
| 396 | */ |
| 397 | |
| 398 | #define RE_PHYAR_PHYDATA 0x0000FFFF |
| 399 | #define RE_PHYAR_PHYREG 0x001F0000 |
| 400 | #define RE_PHYAR_BUSY 0x80000000 |
| 401 | |
| 402 | /* |
| 403 | * Gigabit media status (8169 only) |
| 404 | */ |
| 405 | #define RE_GMEDIASTAT_FDX 0x01 /* full duplex */ |
| 406 | #define RE_GMEDIASTAT_LINK 0x02 /* link up */ |
| 407 | #define RE_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ |
| 408 | #define RE_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ |
| 409 | #define RE_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ |
| 410 | #define RE_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ |
| 411 | #define RE_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ |
| 412 | #define RE_GMEDIASTAT_TBI 0x80 /* TBI enabled */ |
| 413 | |
| 414 | /* |
| 415 | * The RealTek doesn't use a fragment-based descriptor mechanism. |
| 416 | * Instead, there are only four register sets, each or which represents |
| 417 | * one 'descriptor.' Basically, each TX descriptor is just a contiguous |
| 418 | * packet buffer (32-bit aligned!) and we place the buffer addresses in |
| 419 | * the registers so the chip knows where they are. |
| 420 | * |
| 421 | * We can sort of kludge together the same kind of buffer management |
| 422 | * used in previous drivers, but we have to do buffer copies almost all |
| 423 | * the time, so it doesn't really buy us much. |
| 424 | * |
| 425 | * For reception, there's just one large buffer where the chip stores |
| 426 | * all received packets. |
| 427 | */ |
| 428 | |
| 429 | #define RE_RX_BUF_SZ RE_RXBUF_64 |
| 430 | #define RE_RXBUFLEN (1 << ((RE_RX_BUF_SZ >> 11) + 13)) |
| 431 | #define RE_TX_LIST_CNT 4 |
| 432 | #define RE_MIN_FRAMELEN 60 |
| 433 | #define RE_TXTHRESH(x) ((x) << 11) |
| 434 | #define RE_TX_THRESH_INIT 96 |
| 435 | #define RE_RX_FIFOTHRESH RE_RXFIFO_NOTHRESH |
| 436 | #define RE_RX_MAXDMA RE_RXDMA_UNLIMITED |
| 437 | #define RE_TX_MAXDMA RE_TXDMA_2048BYTES |
| 438 | |
| 439 | #define RE_RXCFG_CONFIG (RE_RX_FIFOTHRESH|RE_RX_MAXDMA|RE_RX_BUF_SZ) |
| 440 | #define RE_TXCFG_CONFIG (RE_TXCFG_IFG|RE_TX_MAXDMA) |
| 441 | |
| 442 | #define RE_IM_MAGIC 0x5050 |
| 443 | #define RE_IM_RXTIME(t) ((t) & 0xf) |
| 444 | #define RE_IM_TXTIME(t) (((t) & 0xf) << 8) |
| 445 | |
| 446 | #if 0 |
| 447 | struct re_mii_frame { |
| 448 | uint8_t mii_stdelim; |
| 449 | uint8_t mii_opcode; |
| 450 | uint8_t mii_phyaddr; |
| 451 | uint8_t mii_regaddr; |
| 452 | uint8_t mii_turnaround; |
| 453 | uint16_t mii_data; |
| 454 | }; |
| 455 | #endif |
| 456 | |
| 457 | /* |
| 458 | * MII constants |
| 459 | */ |
| 460 | #define RE_MII_STARTDELIM 0x01 |
| 461 | #define RE_MII_READOP 0x02 |
| 462 | #define RE_MII_WRITEOP 0x01 |
| 463 | #define RE_MII_TURNAROUND 0x02 |
| 464 | |
| 465 | /* |
| 466 | * The 8139C+ and 8160 gigE chips support descriptor-based TX |
| 467 | * and RX. In fact, they even support TCP large send. Descriptors |
| 468 | * must be allocated in contiguous blocks that are aligned on a |
| 469 | * 256-byte boundary. The rings can hold a maximum of 64 descriptors. |
| 470 | */ |
| 471 | |
| 472 | /* |
| 473 | * RX/TX descriptor definition. When large send mode is enabled, the |
| 474 | * lower 11 bits of the TX re_cmd word are used to hold the MSS, and |
| 475 | * the checksum offload bits are disabled. The structure layout is |
| 476 | * the same for RX and TX descriptors |
| 477 | */ |
| 478 | |
| 479 | struct re_desc { |
| 480 | uint32_t re_cmdstat; |
| 481 | uint32_t re_control; |
| 482 | uint32_t re_bufaddr_lo; |
| 483 | uint32_t re_bufaddr_hi; |
| 484 | }; |
| 485 | |
| 486 | #define RE_TDESC_CMD_FRAGLEN 0x0000FFFF |
| 487 | #define RE_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ |
| 488 | #define RE_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ |
| 489 | #define RE_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ |
| 490 | #define RE_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ |
| 491 | #define RE_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ |
| 492 | #define RE_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ |
| 493 | #define RE_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ |
| 494 | #define RE_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ |
| 495 | #define RE_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ |
| 496 | |
| 497 | #define RE_TDESC_CTL_INSTAG 0x00020000 /* Insert VLAN tag */ |
| 498 | #define RE_TDESC_CTL_TAGDATA 0x0000FFFF /* TAG data */ |
| 499 | #define RE_TDESC_CTL_IPCSUM 0x20000000 /* IP header csum, MAC2 only */ |
| 500 | #define RE_TDESC_CTL_TCPCSUM 0x60000000 /* TCP csum, MAC2 only */ |
| 501 | #define RE_TDESC_CTL_UDPCSUM 0xa0000000 /* UDP csum, MAC2 only */ |
| 502 | |
| 503 | /* |
| 504 | * Error bits are valid only on the last descriptor of a frame |
| 505 | * (i.e. RE_TDESC_CMD_EOF == 1) |
| 506 | */ |
| 507 | |
| 508 | #define RE_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ |
| 509 | #define RE_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ |
| 510 | #define RE_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ |
| 511 | #define RE_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ |
| 512 | #define RE_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ |
| 513 | #define RE_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ |
| 514 | #define RE_TDESC_STAT_OWN 0x80000000 |
| 515 | |
| 516 | /* |
| 517 | * RX descriptor cmd/vlan definitions |
| 518 | */ |
| 519 | |
| 520 | #define RE_RDESC_CMD_EOR 0x40000000 |
| 521 | #define RE_RDESC_CMD_OWN 0x80000000 |
| 522 | #define RE_RDESC_CMD_BUFLEN 0x00001FFF |
| 523 | |
| 524 | #define RE_RDESC_STAT_OWN 0x80000000 |
| 525 | #define RE_RDESC_STAT_EOR 0x40000000 |
| 526 | #define RE_RDESC_STAT_SOF 0x20000000 |
| 527 | #define RE_RDESC_STAT_EOF 0x10000000 |
| 528 | #define RE_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ |
| 529 | #define RE_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ |
| 530 | #define RE_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ |
| 531 | #define RE_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ |
| 532 | #define RE_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ |
| 533 | #define RE_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ |
| 534 | #define RE_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ |
| 535 | #define RE_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ |
| 536 | #define RE_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ |
| 537 | #define RE_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ |
| 538 | #define RE_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ |
| 539 | #define RE_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ |
| 540 | #define RE_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ |
| 541 | #define RE_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ |
| 542 | #define RE_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ |
| 543 | #define RE_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ |
| 544 | |
| 545 | #define RE_RDESC_CTL_HASTAG 0x00010000 /* VLAN tag available |
| 546 | (TAG data valid) */ |
| 547 | #define RE_RDESC_CTL_TAGDATA 0x0000FFFF /* TAG data */ |
| 548 | #define RE_RDESC_CTL_PROTOIP4 0x40000000 /* IPv4 packet, MAC2 only */ |
| 549 | #define RE_RDESC_CTL_PROTOIP6 0x80000000 /* IPv6 packet, MAC2 only */ |
| 550 | |
| 551 | #define RE_PROTOID_NONIP 0x00000000 |
| 552 | #define RE_PROTOID_TCPIP 0x00010000 |
| 553 | #define RE_PROTOID_UDPIP 0x00020000 |
| 554 | #define RE_PROTOID_IP 0x00030000 |
| 555 | #define RE_TCPPKT(x) (((x) & RE_RDESC_STAT_PROTOID) == \ |
| 556 | RE_PROTOID_TCPIP) |
| 557 | #define RE_UDPPKT(x) (((x) & RE_RDESC_STAT_PROTOID) == \ |
| 558 | RE_PROTOID_UDPIP) |
| 559 | |
| 560 | /* |
| 561 | * Statistics counter structure (8139C+ and 8169 only) |
| 562 | */ |
| 563 | struct re_stats { |
| 564 | uint32_t re_tx_pkts_lo; |
| 565 | uint32_t re_tx_pkts_hi; |
| 566 | uint32_t re_tx_errs_lo; |
| 567 | uint32_t re_tx_errs_hi; |
| 568 | uint32_t re_tx_errs; |
| 569 | uint16_t re_missed_pkts; |
| 570 | uint16_t re_rx_framealign_errs; |
| 571 | uint32_t re_tx_onecoll; |
| 572 | uint32_t re_tx_multicolls; |
| 573 | uint32_t re_rx_ucasts_hi; |
| 574 | uint32_t re_rx_ucasts_lo; |
| 575 | uint32_t re_rx_bcasts_lo; |
| 576 | uint32_t re_rx_bcasts_hi; |
| 577 | uint32_t re_rx_mcasts; |
| 578 | uint16_t re_tx_aborts; |
| 579 | uint16_t re_rx_underruns; |
| 580 | }; |
| 581 | |
| 582 | /* |
| 583 | * General constants that are fun to know. |
| 584 | * |
| 585 | * PCI low memory base and low I/O base register, and |
| 586 | * other PCI registers. |
| 587 | */ |
| 588 | |
| 589 | #define RE_PCI_LOMEM 0x14 |
| 590 | #define RE_PCI_LOIO 0x10 |
| 591 | |
| 592 | #define PCI_SUBDEVICE_LINKSYS_EG1032_REV3 0x0024 |