3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.42 2004/05/24 19:39:23 jhb Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_revar.h,v 1.19 2008/10/12 04:08:59 sephe Exp $
39 #define RE_RX_DESC_CNT_DEF 256
40 #define RE_TX_DESC_CNT_DEF 256
41 #define RE_RX_DESC_CNT_MAX 1024
42 #define RE_TX_DESC_CNT_MAX 1024
44 #define RE_RX_LIST_SZ(sc) ((sc)->re_rx_desc_cnt * sizeof(struct re_desc))
45 #define RE_TX_LIST_SZ(sc) ((sc)->re_tx_desc_cnt * sizeof(struct re_desc))
46 #define RE_RING_ALIGN 256
47 #define RE_IFQ_MAXLEN 512
49 #define RE_TXDESC_SPARE 4
51 #define RE_RXDESC_INC(sc, x) (x = (x + 1) % (sc)->re_rx_desc_cnt)
52 #define RE_TXDESC_INC(sc, x) (x = (x + 1) % (sc)->re_tx_desc_cnt)
53 #define RE_OWN(x) (le32toh((x)->re_cmdstat) & RE_RDESC_STAT_OWN)
54 #define RE_RXBYTES(x) (le32toh((x)->re_cmdstat) & sc->re_rxlenmask)
55 #define RE_PKTSZ(x) ((x)/* >> 3*/)
57 #define RE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
58 #define RE_ADDR_HI(y) ((uint64_t) (y) >> 32)
60 #define RE_JUMBO_FRAMELEN 7440
61 #define RE_JUMBO_MTU (RE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
62 #define RE_FRAMELEN_2K 2048
63 #define RE_FRAMELEN(mtu) (mtu + ETHER_HDR_LEN + ETHER_CRC_LEN)
64 #define RE_SWCSUM_LIM_8169 2038
66 #define RE_TIMEOUT 1000
70 int re_type; /* RE_{8139CPLUS,8169} */
71 uint32_t re_caps; /* see RE_C_ */
76 #define RE_8139CPLUS 3
79 struct re_dmaload_arg {
81 bus_dma_segment_t *re_segs;
85 struct mbuf **re_tx_mbuf;
86 struct mbuf **re_rx_mbuf;
87 bus_addr_t *re_rx_paddr;
92 bus_dmamap_t *re_tx_dmamap;
93 bus_dmamap_t *re_rx_dmamap;
94 bus_dmamap_t re_rx_spare;
95 bus_dma_tag_t re_mtag; /* mbuf mapping tag */
96 bus_dma_tag_t re_stag; /* stats mapping tag */
97 bus_dmamap_t re_smap; /* stats map */
98 struct re_stats *re_stats;
99 bus_addr_t re_stats_addr;
100 bus_dma_tag_t re_rx_list_tag;
101 bus_dmamap_t re_rx_list_map;
102 struct re_desc *re_rx_list;
103 bus_addr_t re_rx_list_addr;
104 bus_dma_tag_t re_tx_list_tag;
105 bus_dmamap_t re_tx_list_map;
106 struct re_desc *re_tx_list;
107 bus_addr_t re_tx_list_addr;
111 struct arpcom arpcom; /* interface info */
115 bus_space_handle_t re_bhandle; /* bus space handle */
116 bus_space_tag_t re_btag; /* bus space tag */
117 struct resource *re_res;
118 struct resource *re_irq;
121 bus_dma_tag_t re_parent_tag;
122 bus_dma_tag_t re_tag;
125 uint8_t re_stats_no_timeout;
128 struct re_list_data re_ldata;
129 struct callout re_timer;
130 struct mbuf *re_head;
131 struct mbuf *re_tail;
133 uint32_t re_caps; /* see RE_C_ */
134 uint32_t re_rxlenmask;
137 int suspended; /* 0 = normal 1 = suspended */
145 #ifdef DEVICE_POLLING
149 uint32_t re_flags; /* see RE_F_ */
151 struct sysctl_ctx_list re_sysctl_ctx;
152 struct sysctl_oid *re_sysctl_tree;
159 int re_imtype; /* see RE_IMTYPE_ */
162 uint32_t saved_maps[5]; /* pci data */
163 uint32_t saved_biosaddr;
164 uint8_t saved_intline;
165 uint8_t saved_cachelnsz;
166 uint8_t saved_lattimer;
170 #define RE_C_PCIE 0x1
171 #define RE_C_PCI64 0x2
172 #define RE_C_HWIM 0x4 /* hardware interrupt moderation */
173 #define RE_C_HWCSUM 0x8
175 /* Interrupt moderation types */
176 #define RE_IMTYPE_NONE 0
177 #define RE_IMTYPE_SIM 1 /* simulated */
178 #define RE_IMTYPE_HW 2 /* hardware based */
180 #define RE_F_TIMER_INTR 0x1
183 * register space access macros
185 #define CSR_WRITE_STREAM_4(sc, reg, val) \
186 bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val)
187 #define CSR_WRITE_4(sc, reg, val) \
188 bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val)
189 #define CSR_WRITE_2(sc, reg, val) \
190 bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val)
191 #define CSR_WRITE_1(sc, reg, val) \
192 bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val)
194 #define CSR_READ_4(sc, reg) \
195 bus_space_read_4(sc->re_btag, sc->re_bhandle, reg)
196 #define CSR_READ_2(sc, reg) \
197 bus_space_read_2(sc->re_btag, sc->re_bhandle, reg)
198 #define CSR_READ_1(sc, reg) \
199 bus_space_read_1(sc->re_btag, sc->re_bhandle, reg)
201 #define CSR_SETBIT_1(sc, reg, val) \
202 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (val))
203 #define CSR_CLRBIT_1(sc, reg, val) \
204 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(val))