2 * Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the author may not be used to endorse or promote products
11 * derived from this software withough specific prior written permission
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 * $FreeBSD: src/sys/dev/pdq/pdqreg.h,v 1.2 1999/08/28 00:42:20 peter Exp $
25 * $DragonFly: src/sys/dev/netif/pdq_layer/Attic/pdqreg.h,v 1.2 2003/06/17 04:28:29 dillon Exp $
30 * DEC PDQ FDDI Controller; PDQ port driver definitions
38 #if defined(PDQTEST) && !defined(PDQ_NDEBUG)
40 #define PDQ_ASSERT assert
42 #define PDQ_ASSERT(x) do { } while(0)
45 #define PDQ_RING_SIZE(array) ((sizeof(array) / sizeof(array[0])))
46 #define PDQ_ARRAY_SIZE(array) ((sizeof(array) / sizeof(array[0])))
47 #define PDQ_RING_MASK(array) (PDQ_RING_SIZE(array) - 1)
48 #define PDQ_BITMASK(n) (1L << (pdq_uint32_t) (n))
50 #define PDQ_FDDI_MAX 4495
51 #define PDQ_FDDI_LLC_MIN 20
52 #define PDQ_FDDI_SMT_MIN 37
54 #define PDQ_FDDI_SMT 0x40
55 #define PDQ_FDDI_LLC_ASYNC 0x50
56 #define PDQ_FDDI_LLC_SYNC 0xD0
57 #define PDQ_FDDI_IMP_ASYNC 0x60
58 #define PDQ_FDDI_IMP_SYNC 0xE0
60 #define PDQ_FDDIFC_C 0x80
61 #define PDQ_FDDIFC_L 0x40
62 #define PDQ_FDDIFC_F 0x30
63 #define PDQ_FDDIFC_Z 0x0F
65 #define PDQ_FDDI_PH0 0x20
66 #define PDQ_FDDI_PH1 0x38
67 #define PDQ_FDDI_PH2 0x00
69 typedef pdq_uint32_t pdq_physaddr_t;
71 struct _pdq_lanaddr_t {
72 pdq_uint8_t lanaddr_bytes[8];
76 pdq_uint8_t fwrev_bytes[4];
82 PDQS_DMA_UNAVAILABLE=2,
84 PDQS_LINK_AVAILABLE=4,
85 PDQS_LINK_UNAVAILABLE=5,
91 pdq_bus_memoffset_t csr_port_reset; /* 0x00 [RW] */
92 pdq_bus_memoffset_t csr_host_data; /* 0x04 [R] */
93 pdq_bus_memoffset_t csr_port_control; /* 0x08 [RW] */
94 pdq_bus_memoffset_t csr_port_data_a; /* 0x0C [RW] */
95 pdq_bus_memoffset_t csr_port_data_b; /* 0x10 [RW] */
96 pdq_bus_memoffset_t csr_port_status; /* 0x14 [R] */
97 pdq_bus_memoffset_t csr_host_int_type_0; /* 0x18 [RW] */
98 pdq_bus_memoffset_t csr_host_int_enable; /* 0x1C [RW] */
99 pdq_bus_memoffset_t csr_type_2_producer; /* 0x20 [RW] */
100 pdq_bus_memoffset_t csr_cmd_response_producer; /* 0x28 [RW] */
101 pdq_bus_memoffset_t csr_cmd_request_producer; /* 0x2C [RW] */
102 pdq_bus_memoffset_t csr_host_smt_producer; /* 0x30 [RW] */
103 pdq_bus_memoffset_t csr_unsolicited_producer; /* 0x34 [RW] */
105 pdq_bus_memaddr_t csr_base;
108 struct _pdq_pci_csrs_t {
109 pdq_bus_memoffset_t csr_pfi_mode_control; /* 0x40 [RW] */
110 pdq_bus_memoffset_t csr_pfi_status; /* 0x44 [RW] */
111 pdq_bus_memoffset_t csr_fifo_write; /* 0x48 [RW] */
112 pdq_bus_memoffset_t csr_fifo_read; /* 0x4C [RW] */
114 pdq_bus_memaddr_t csr_base;
117 #define PDQ_PFI_MODE_DMA_ENABLE 0x01 /* DMA Enable */
118 #define PDQ_PFI_MODE_PFI_PCI_INTR 0x02 /* PFI-to-PCI Int Enable */
119 #define PDQ_PFI_MODE_PDQ_PCI_INTR 0x04 /* PDQ-to-PCI Int Enable */
121 #define PDQ_PFI_STATUS_PDQ_INTR 0x10 /* PDQ Int received */
122 #define PDQ_PFI_STATUS_DMA_ABORT 0x08 /* PDQ DMA Abort asserted */
124 #define PDQ_EISA_BURST_HOLDOFF 0x0040
125 #define PDQ_EISA_SLOT_ID 0x0C80
126 #define PDQ_EISA_SLOT_CTRL 0x0C84
127 #define PDQ_EISA_MEM_ADD_CMP_0 0x0C85
128 #define PDQ_EISA_MEM_ADD_CMP_1 0x0C86
129 #define PDQ_EISA_MEM_ADD_CMP_2 0x0C87
130 #define PDQ_EISA_MEM_ADD_HI_CMP_0 0x0C88
131 #define PDQ_EISA_MEM_ADD_HI_CMP_1 0x0C89
132 #define PDQ_EISA_MEM_ADD_HI_CMP_2 0x0C8A
133 #define PDQ_EISA_MEM_ADD_MASK_0 0x0C8B
134 #define PDQ_EISA_MEM_ADD_MASK_1 0x0C8C
135 #define PDQ_EISA_MEM_ADD_MASK_2 0x0C8D
136 #define PDQ_EISA_MEM_ADD_LO_CMP_0 0x0C8E
137 #define PDQ_EISA_MEM_ADD_LO_CMP_1 0x0C8F
138 #define PDQ_EISA_MEM_ADD_LO_CMP_2 0x0C90
139 #define PDQ_EISA_IO_CMP_0_0 0x0C91
140 #define PDQ_EISA_IO_CMP_0_1 0x0C92
141 #define PDQ_EISA_IO_CMP_1_0 0x0C93
142 #define PDQ_EISA_IO_CMP_1_1 0x0C94
143 #define PDQ_EISA_IO_CMP_2_0 0x0C95
144 #define PDQ_EISA_IO_CMP_2_1 0x0C96
145 #define PDQ_EISA_IO_CMP_3_0 0x0C97
146 #define PDQ_EISA_IO_CMP_3_1 0x0C98
147 #define PDQ_EISA_IO_ADD_MASK_0_0 0x0C99
148 #define PDQ_EISA_IO_ADD_MASK_0_1 0x0C9A
149 #define PDQ_EISA_IO_ADD_MASK_1_0 0x0C9B
150 #define PDQ_EISA_IO_ADD_MASK_1_1 0x0C9C
151 #define PDQ_EISA_IO_ADD_MASK_2_0 0x0C9D
152 #define PDQ_EISA_IO_ADD_MASK_2_1 0x0C9E
153 #define PDQ_EISA_IO_ADD_MASK_3_0 0x0C9F
154 #define PDQ_EISA_IO_ADD_MASK_3_1 0x0CA0
155 #define PDQ_EISA_MOD_CONFIG_1 0x0CA1
156 #define PDQ_EISA_MOD_CONFIG_2 0x0CA2
157 #define PDQ_EISA_MOD_CONFIG_3 0x0CA3
158 #define PDQ_EISA_MOD_CONFIG_4 0x0CA4
159 #define PDQ_EISA_MOD_CONFIG_5 0x0CA5
160 #define PDQ_EISA_MOD_CONFIG_6 0x0CA6
161 #define PDQ_EISA_MOD_CONFIG_7 0x0CA7
162 #define PDQ_EISA_DIP_SWITCH 0x0CA8
163 #define PDQ_EISA_IO_CONFIG_STAT_0 0x0CA9
164 #define PDQ_EISA_IO_CONFIG_STAT_1 0x0CAA
165 #define PDQ_EISA_DMA_CONFIG 0x0CAB
166 #define PDQ_EISA_INPUT_PORT 0x0CAC
167 #define PDQ_EISA_OUTPUT_PORT 0x0CAD
168 #define PDQ_EISA_FUNCTION_CTRL 0x0CAE
170 #define PDQ_TC_CSR_OFFSET 0x00100000
171 #define PDQ_TC_CSR_SPACE 0x0040
172 #define PDQ_FBUS_CSR_OFFSET 0x00200000
173 #define PDQ_FBUS_CSR_SPACE 0x0080
176 * Port Reset Data A Definitions
178 #define PDQ_PRESET_SKIP_SELFTEST 0x0004
179 #define PDQ_PRESET_SOFT_RESET 0x0002
180 #define PDQ_PRESET_UPGRADE 0x0001
182 * Port Control Register Definitions
184 #define PDQ_PCTL_CMD_ERROR 0x8000
185 #define PDQ_PCTL_FLASH_BLAST 0x4000
186 #define PDQ_PCTL_HALT 0x2000
187 #define PDQ_PCTL_COPY_DATA 0x1000
188 #define PDQ_PCTL_ERROR_LOG_START 0x0800
189 #define PDQ_PCTL_ERROR_LOG_READ 0x0400
190 #define PDQ_PCTL_XMT_DATA_FLUSH_DONE 0x0200
191 #define PDQ_PCTL_DMA_INIT 0x0100
192 #define PDQ_DMA_INIT_LW_BSWAP_DATA 0x02
193 #define PDQ_DMA_INIT_LW_BSWAP_LITERAL 0x01
194 #define PDQ_PCTL_INIT_START 0x0080
195 #define PDQ_PCTL_CONSUMER_BLOCK 0x0040
196 #define PDQ_PCTL_DMA_UNINIT 0x0020
197 #define PDQ_PCTL_RING_MEMBER 0x0010
198 #define PDQ_PCTL_MLA_READ 0x0008
199 #define PDQ_PCTL_FW_REV_READ 0x0004
200 #define PDQ_PCTL_DEVICE_SPECIFIC 0x0002
201 #define PDQ_PCTL_SUB_CMD 0x0001
204 PDQ_SUB_CMD_LINK_UNINIT=1,
205 PDQ_SUB_CMD_DMA_BURST_SIZE_SET=2,
206 PDQ_SUB_CMD_PDQ_REV_GET=4
212 PDQ_DMA_BURST_16LW=2,
214 } pdq_dma_burst_size_t;
217 PDQ_CHIP_REV_A_B_OR_C=0,
222 * Port Status Register Definitions
224 #define PDQ_PSTS_RCV_DATA_PENDING 0x80000000ul
225 #define PDQ_PSTS_XMT_DATA_PENDING 0x40000000ul
226 #define PDQ_PSTS_HOST_SMT_PENDING 0x20000000ul
227 #define PDQ_PSTS_UNSOL_PENDING 0x10000000ul
228 #define PDQ_PSTS_CMD_RSP_PENDING 0x08000000ul
229 #define PDQ_PSTS_CMD_REQ_PENDING 0x04000000ul
230 #define PDQ_PSTS_TYPE_0_PENDING 0x02000000ul
231 #define PDQ_PSTS_INTR_PENDING 0xFE000000ul
232 #define PDQ_PSTS_ADAPTER_STATE(sts) ((pdq_state_t) (((sts) >> 8) & 0x07))
233 #define PDQ_PSTS_HALT_ID(sts) ((pdq_halt_code_t) ((sts) & 0xFF))
235 * Host Interrupt Register Definitions
237 #define PDQ_HOST_INT_TX_ENABLE 0x80000000ul
238 #define PDQ_HOST_INT_RX_ENABLE 0x40000000ul
239 #define PDQ_HOST_INT_UNSOL_ENABLE 0x20000000ul
240 #define PDQ_HOST_INT_HOST_SMT_ENABLE 0x10000000ul
241 #define PDQ_HOST_INT_CMD_RSP_ENABLE 0x08000000ul
242 #define PDQ_HOST_INT_CMD_RQST_ENABLE 0x04000000ul
244 #define PDQ_HOST_INT_1MS 0x80
245 #define PDQ_HOST_INT_20MS 0x40
246 #define PDQ_HOST_INT_CSR_CMD_DONE 0x20
247 #define PDQ_HOST_INT_STATE_CHANGE 0x10
248 #define PDQ_HOST_INT_XMT_DATA_FLUSH 0x08
249 #define PDQ_HOST_INT_NXM 0x04
250 #define PDQ_HOST_INT_PM_PARITY_ERROR 0x02
251 #define PDQ_HOST_INT_HOST_BUS_PARITY_ERROR 0x01
252 #define PDQ_HOST_INT_FATAL_ERROR 0x07
255 PDQH_SELFTEST_TIMEOUT=0,
256 PDQH_HOST_BUS_PARITY_ERROR=1,
257 PDQH_HOST_DIRECTED_HALT=2,
258 PDQH_SOFTWARE_FAULT=3,
259 PDQH_HARDWARE_FAULT=4,
260 PDQH_PC_TRACE_PATH_TEST=5,
262 PDQH_IMAGE_CRC_ERROR=7,
263 PDQH_ADAPTER_PROCESSOR_ERROR=8,
268 pdq_uint16_t pdqcb_receives;
269 pdq_uint16_t pdqcb_transmits;
270 pdq_uint32_t pdqcb__filler1;
271 pdq_uint32_t pdqcb_host_smt;
272 pdq_uint32_t pdqcb__filler2;
273 pdq_uint32_t pdqcb_unsolicited_event;
274 pdq_uint32_t pdqcb__filler3;
275 pdq_uint32_t pdqcb_command_response;
276 pdq_uint32_t pdqcb__filler4;
277 pdq_uint32_t pdqcb_command_request;
278 pdq_uint32_t pdqcb__filler5[7];
279 } pdq_consumer_block_t;
281 #if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN
282 #define PDQ_BITFIELD2(a, b) b, a
283 #define PDQ_BITFIELD3(a, b, c) c, b, a
284 #define PDQ_BITFIELD4(a, b, c, d) d, c, b, a
285 #define PDQ_BITFIELD5(a, b, c, d, e) e, d, c, b, a
286 #define PDQ_BITFIELD12(a, b, c, d, e, f, g, h, i, j, k, l) \
287 l, k, j, i, h, g, f, e, d, c, b, a
289 #define PDQ_BITFIELD2(a, b) a, b
290 #define PDQ_BITFIELD3(a, b, c) a, b, c
291 #define PDQ_BITFIELD4(a, b, c, d) a, b, c, d
292 #define PDQ_BITFIELD5(a, b, c, d, e) a, b, c, d, e
293 #define PDQ_BITFIELD12(a, b, c, d, e, f, g, h, i, j, k, l) \
294 a, b, c, d, e, f, g, h, i, j, k, l
298 pdq_uint32_t PDQ_BITFIELD5(rxd_pa_hi : 16,
303 pdq_uint32_t rxd_pa_lo;
307 pdq_uint32_t rxs_status;
308 pdq_uint32_t PDQ_BITFIELD12(rxs_len : 13,
314 rxs_fsb__reserved : 2,
323 pdq_uint32_t PDQ_BITFIELD5(txd_pa_hi : 16,
328 pdq_uint32_t txd_pa_lo;
332 pdq_rxdesc_t pdqdb_receives[256]; /* 2048; 0x0000..0x07FF */
333 pdq_txdesc_t pdqdb_transmits[256]; /* 2048; 0x0800..0x0FFF */
334 pdq_rxdesc_t pdqdb_host_smt[64]; /* 512; 0x1000..0x11FF */
335 pdq_rxdesc_t pdqdb_unsolicited_events[16]; /* 128; 0x1200..0x127F */
336 pdq_rxdesc_t pdqdb_command_responses[16]; /* 128; 0x1280..0x12FF */
337 pdq_txdesc_t pdqdb_command_requests[16]; /* 128; 0x1300..0x137F */
339 * The rest of the descriptor block is unused.
340 * As such we could use it for other things.
342 pdq_consumer_block_t pdqdb_consumer; /* 64; 0x1380..0x13BF */
343 void *pdqdb_receive_buffers[256]; /* 1024/2048; 0x13C0..0x17BF 0x13C0..0x1BBF */
344 void *pdqdb_host_smt_buffers[64]; /* 256/ 512; 0x17C0..0x18BF 0x1BC0..0x1DBF */
346 * The maximum command size is 512 so as long as thes
347 * command is at least that long all will be fine.
349 #if defined(__alpha) || defined(__alpha__)
350 pdq_uint32_t pdqdb_command_pool[144];
352 pdq_uint32_t pdqdb_command_pool[464];
354 } pdq_descriptor_block_t;
358 * These value manage the available space in command/response
361 pdq_physaddr_t ci_pa_bufstart;
362 pdq_uint8_t *ci_bufstart;
364 * Bitmask of commands to sent to the PDQ
366 pdq_uint32_t ci_pending_commands;
368 * Variables to maintain the PDQ queues.
370 pdq_uint32_t ci_command_active;
371 pdq_uint32_t ci_request_producer;
372 pdq_uint32_t ci_response_producer;
373 pdq_uint32_t ci_request_completion;
374 pdq_uint32_t ci_response_completion;
375 } pdq_command_info_t;
377 #define PDQ_SIZE_UNSOLICITED_EVENT 512
378 #define PDQ_NUM_UNSOLICITED_EVENTS (PDQ_OS_PAGESIZE / PDQ_SIZE_UNSOLICITED_EVENT)
380 typedef struct _pdq_unsolicited_event_t pdq_unsolicited_event_t;
383 pdq_physaddr_t ui_pa_bufstart;
384 pdq_unsolicited_event_t *ui_events;
386 pdq_uint32_t ui_free;
387 pdq_uint32_t ui_producer;
388 pdq_uint32_t ui_completion;
389 } pdq_unsolicited_info_t;
391 #define PDQ_RX_FC_OFFSET (sizeof(pdq_rxstatus_t) + 3)
392 #define PDQ_RX_SEGCNT ((PDQ_FDDI_MAX + PDQ_OS_DATABUF_SIZE - 1) / PDQ_OS_DATABUF_SIZE)
393 #define PDQ_DO_TYPE2_PRODUCER(pdq) \
394 PDQ_CSR_WRITE(&(pdq)->pdq_csrs, csr_type_2_producer, \
395 ((pdq)->pdq_rx_info.rx_producer << 0) \
396 | ((pdq)->pdq_tx_info.tx_producer << 8) \
397 | ((pdq)->pdq_rx_info.rx_completion << 16) \
398 | ((pdq)->pdq_tx_info.tx_completion << 24))
400 #define PDQ_DO_HOST_SMT_PRODUCER(pdq) \
401 PDQ_CSR_WRITE(&(pdq)->pdq_csrs, csr_host_smt_producer, \
402 ((pdq)->pdq_host_smt_info.rx_producer << 0) \
403 | ((pdq)->pdq_host_smt_info.rx_completion << 8))\
405 #define PDQ_ADVANCE(n, a, m) ((n) = ((n) + (a)) & (m))
410 } pdq_databuf_queue_t;
415 pdq_uint32_t rx_target;
416 pdq_uint32_t rx_free;
417 pdq_uint32_t rx_producer;
418 pdq_uint32_t rx_completion;
422 pdq_databuf_queue_t tx_txq;
423 pdq_txdesc_t tx_hdrdesc;
424 pdq_uint8_t tx_descriptor_count[256];
426 pdq_uint32_t tx_free;
427 pdq_uint32_t tx_producer;
428 pdq_uint32_t tx_completion;
433 pdq_pci_csrs_t pdq_pci_csrs;
435 pdq_chip_rev_t pdq_chip_rev;
436 pdq_lanaddr_t pdq_hwaddr;
437 pdq_fwrev_t pdq_fwrev;
438 pdq_descriptor_block_t *pdq_dbp;
439 volatile pdq_consumer_block_t *pdq_cbp;
440 pdq_uint32_t pdq_flags;
441 #define PDQ_PROMISC 0x0001
442 #define PDQ_ALLMULTI 0x0002
443 #define PDQ_PASS_SMT 0x0004
444 #define PDQ_RUNNING 0x0008
445 #define PDQ_PRINTCHARS 0x0010
446 #define PDQ_TXOK 0x0020
447 const char *pdq_os_name;
449 pdq_uint32_t pdq_unit;
450 pdq_command_info_t pdq_command_info;
451 pdq_unsolicited_info_t pdq_unsolicited_info;
452 pdq_tx_info_t pdq_tx_info;
453 pdq_rx_info_t pdq_rx_info;
454 pdq_rx_info_t pdq_host_smt_info;
455 pdq_uint8_t pdq_tx_hdr[3];
463 PDQC_STATUS_CHARS_GET=4,
466 PDQC_ADDR_FILTER_SET=7,
467 PDQC_ADDR_FILTER_GET=8,
468 PDQC_ERROR_LOG_CLEAR=9,
469 PDQC_ERROR_LOG_GET=10,
470 PDQC_FDDI_MIB_GET=11,
471 PDQC_DEC_EXT_MIB_GET=12,
472 PDQC_DEV_SPECIFIC_GET=13,
482 PDQR_LOOP_MODE_BAD=3,
483 PDQR_ITEM_CODE_BAD=4,
486 PDQR_RESTRICTED_TOKEN_BAD=7,
488 PDQR_FILTER_STATE_BAD=13,
489 PDQR_CMD_TYPE_BAD=14,
490 PDQR_ADAPTER_STATE_BAD=15,
491 PDQR_RING_PURGER_BAD=16,
492 PDQR_LEM_THRESHOLD_BAD=17,
493 PDQR_LOOP_NOT_SUPPORTED=18,
494 PDQR_FLUSH_TIME_BAD=19,
495 PDQR_NOT_YET_IMPLEMENTED=20,
496 PDQR_CONFIG_POLICY_BAD=21,
497 PDQR_STATION_ACTION_BAD=22,
498 PDQR_MAC_ACTION_BAD=23,
499 PDQR_CON_POLICIES_BAD=24,
500 PDQR_MAC_LOOP_TIME_BAD=25,
502 PDQR_LER_CUTOFF_BAD=27,
503 PDQR_LER_ALARM_BAD=28,
504 PDQR_MAC_PATHS_REQ_BAD=29,
505 PDQR_MAC_T_REQ_BAD=30,
506 PDQR_EMAC_RING_PURGER_BAD=31,
507 PDQR_EMAC_RTOKEN_TIMOUT_AD=32,
508 PDQR_NO_SUCH_ENTRY=33,
509 PDQR_T_NOTIFY_BAD=34,
510 PDQR_TR_MAX_EXP_BAD=35,
511 PDQR_FRAME_ERR_THRESHOLD_BAD=36,
512 PDQR_MAX_TREQ_BAD=37,
513 PDQR_FULL_DUPLEX_ENABLE_BAD=38,
514 PDQR_ITEM_INDEX_BAD=39
515 } pdq_response_code_t;
521 PDQI_RESTRICTED_TOKEN=3,
522 PDQI_LEM_THRESHOLD=4,
524 PDQI_COUNTER_INTERVAL=6,
525 PDQI_IND_GROUP_PROM=7,
532 PDQI_LOOPBACK_MODE=14,
533 PDQI_SMT_CONFIG_POLICY=16,
534 PDQI_SMT_CONNECTION_POLICY=17,
535 PDQI_SMT_T_NOTIFY=18,
536 PDQI_SMT_STATION_ACTION=19,
537 PDQI_MAC_PATHS_REQUESTED=21,
539 PDQI_PORT_CONNECTION_POLICIES=24,
540 PDQI_PORT_PATHS_REQUESTED=25,
541 PDQI_PORT_MAC_LOOP_TIME=26,
543 PDQI_PORT_LER_CUTOFF=28,
544 PDQI_PORT_LER_ALARM=29,
547 PDQI_SMT_USER_DATA=33,
548 PDQI_SMT_STATUS_REPORT_POLICY=34,
549 PDQI_SMT_TRACE_MAX_EXPIRATION=35,
550 PDQI_MAC_FRAME_ERR_THRESHOLD=36,
551 PDQI_MAC_UNIT_DATA_ENABLE=37,
552 PDQI_PATH_TVX_LOWER_BOUND=38,
553 PDQI_PATH_TMAX_LOWER_BOUND=39,
554 PDQI_PATH_MAX_TREQ=40,
556 PDQI_EMAC_RING_PURGER=42,
557 PDQI_EMAC_RTOKEN_TIMEOUT=43,
558 PDQI_FULL_DUPLEX_ENABLE=44
561 enum _pdq_boolean_t {
569 } pdq_filter_state_t;
572 PDQ_STATION_TYPE_SAS=0,
573 PDQ_STATION_TYPE_DAC=1,
574 PDQ_STATION_TYPE_SAC=2,
575 PDQ_STATION_TYPE_NAC=3,
576 PDQ_STATION_TYPE_DAS=4
577 } pdq_station_type_t;
580 PDQ_STATION_STATE_OFF=0,
581 PDQ_STATION_STATE_ON=1,
582 PDQ_STATION_STATE_LOOPBACK=2
583 } pdq_station_state_t;
586 PDQ_LINK_STATE_OFF_READY=1,
587 PDQ_LINK_STATE_OFF_FAULT_RECOVERY=2,
588 PDQ_LINK_STATE_ON_RING_INIT=3,
589 PDQ_LINK_STATE_ON_RING_RUN=4,
590 PDQ_LINK_STATE_BROKEN=5
594 PDQ_DA_TEST_STATE_UNKNOWN=0,
595 PDQ_DA_TEST_STATE_SUCCESS=1,
596 PDQ_DA_TEST_STATE_DUPLICATE=2
597 } pdq_da_test_state_t;
600 PDQ_RING_PURGER_STATE_OFF=0,
601 PDQ_RING_PURGER_STATE_CANDIDATE=1,
602 PDQ_RING_PURGER_STATE_NON_PURGER=2,
603 PDQ_RING_PURGER_STATE_PURGER=3
604 } pdq_ring_purger_state_t;
607 PDQ_FRAME_STRING_MODE_SA_MATCH=0,
608 PDQ_FRAME_STRING_MODE_FCI_STRIP=1
609 } pdq_frame_strip_mode_t;
612 PDQ_RING_ERROR_REASON_NO_ERROR=0,
613 PDQ_RING_ERROR_REASON_RING_INIT_INITIATED=5,
614 PDQ_RING_ERROR_REASON_RING_INIT_RECEIVED=6,
615 PDQ_RING_ERROR_REASON_RING_BEACONING_INITIATED=7,
616 PDQ_RING_ERROR_REASON_DUPLICATE_ADDRESS_DETECTED=8,
617 PDQ_RING_ERROR_REASON_DUPLICATE_TOKEN_DETECTED=9,
618 PDQ_RING_ERROR_REASON_RING_PURGER_ERROR=10,
619 PDQ_RING_ERROR_REASON_FCI_STRIP_ERROR=11,
620 PDQ_RING_ERROR_REASON_RING_OP_OSCILLATION=12,
621 PDQ_RING_ERROR_REASON_DIRECTED_BEACON_RECEVIED=13,
622 PDQ_RING_ERROR_REASON_PC_TRACE_INITIATED=14,
623 PDQ_RING_ERROR_REASON_PC_TRACE_RECEVIED=15
624 } pdq_ring_error_reason_t;
627 PDQ_STATION_MODE_NORMAL=0,
628 PDQ_STATION_MODE_INTERNAL_LOOPBACK=1
629 } pdq_station_mode_t;
636 PDQ_PHY_TYPE_UNKNOWN=4
640 PDQ_PMD_TYPE_ANSI_MUTLI_MODE=0,
641 PDQ_PMD_TYPE_ANSI_SINGLE_MODE_TYPE_1=1,
642 PDQ_PMD_TYPE_ANSI_SIGNLE_MODE_TYPE_2=2,
643 PDQ_PMD_TYPE_ANSI_SONET=3,
644 PDQ_PMD_TYPE_LOW_POWER=100,
645 PDQ_PMD_TYPE_THINWIRE=101,
646 PDQ_PMD_TYPE_SHIELDED_TWISTED_PAIR=102,
647 PDQ_PMD_TYPE_UNSHIELDED_TWISTED_PAIR=103
651 PDQ_PMD_CLASS_ANSI_MULTI_MODE=0,
652 PDQ_PMD_CLASS_SINGLE_MODE_TYPE_1=1,
653 PDQ_PMD_CLASS_SINGLE_MODE_TYPE_2=2,
654 PDQ_PMD_CLASS_SONET=3,
655 PDQ_PMD_CLASS_LOW_COST_POWER_FIBER=4,
656 PDQ_PMD_CLASS_TWISTED_PAIR=5,
657 PDQ_PMD_CLASS_UNKNOWN=6,
658 PDQ_PMD_CLASS_UNSPECIFIED=7
662 PDQ_PHY_STATE_INTERNAL_LOOPBACK=0,
663 PDQ_PHY_STATE_BROKEN=1,
664 PDQ_PHY_STATE_OFF_READY=2,
665 PDQ_PHY_STATE_WAITING=3,
666 PDQ_PHY_STATE_STARTING=4,
667 PDQ_PHY_STATE_FAILED=5,
668 PDQ_PHY_STATE_WATCH=6,
669 PDQ_PHY_STATE_INUSE=7
673 PDQ_REJECT_REASON_NONE=0,
674 PDQ_REJECT_REASON_LOCAL_LCT=1,
675 PDQ_REJECT_REASON_REMOTE_LCT=2,
676 PDQ_REJECT_REASON_LCT_BOTH_SIDES=3,
677 PDQ_REJECT_REASON_LEM_REJECT=4,
678 PDQ_REJECT_REASON_TOPOLOGY_ERROR=5,
679 PDQ_REJECT_REASON_NOISE_REJECT=6,
680 PDQ_REJECT_REASON_REMOTE_REJECT=7,
681 PDQ_REJECT_REASON_TRACE_IN_PROGRESS=8,
682 PDQ_REJECT_REASON_TRACE_RECEIVED_DISABLED=9,
683 PDQ_REJECT_REASON_STANDBY=10,
684 PDQ_REJECT_REASON_LCT_PROTOCOL_ERROR=11
685 } pdq_reject_reason_t;
688 PDQ_BROKEN_REASON_NONE=0
689 } pdq_broken_reason_t;
692 PDQ_RI_REASON_TVX_EXPIRED=0,
693 PDQ_RI_REASON_TRT_EXPIRED=1,
694 PDQ_RI_REASON_RING_PURGER_ELECTION_ATTEMPT_LIMIT_EXCEEDED=2,
695 PDQ_RI_REASON_PURGE_ERROR_LIMIT_EXCEEDED=3,
696 PDQ_RI_REASON_RESTRICTED_TOKEN_TIMEOUT=4
700 PDQ_LCT_DIRECTION_LOCAL_LCT=0,
701 PDQ_LCT_DIRECTION_REMOTE_LCT=1,
702 PDQ_LCT_DIRECTION_LCT_BOTH_SIDES=2
703 } pdq_lct_direction_t;
711 pdq_uint8_t station_id_bytes[8];
714 typedef pdq_uint32_t pdq_fdditimer_t;
716 * Command format for Start, Filter_Get, ... commands
719 pdq_cmd_code_t generic_op;
723 * Response format for Start, Filter_Set, ... commands
726 pdq_uint32_t generic_reserved;
727 pdq_cmd_code_t generic_op;
728 pdq_response_code_t generic_status;
729 } pdq_response_generic_t;
732 * Command format for Filter_Set command
735 pdq_cmd_code_t filter_set_op;
737 pdq_item_code_t item_code;
738 pdq_filter_state_t filter_state;
739 } filter_set_items[7];
740 pdq_item_code_t filter_set_eol_item_code;
741 } pdq_cmd_filter_set_t;
744 * Response format for Filter_Get command.
747 pdq_uint32_t filter_get_reserved;
748 pdq_cmd_code_t filter_get_op;
749 pdq_response_code_t filter_get_status;
750 pdq_filter_state_t filter_get_ind_group_prom;
751 pdq_filter_state_t filter_get_group_prom;
752 pdq_filter_state_t filter_get_broadcast_all;
753 pdq_filter_state_t filter_get_smt_prom;
754 pdq_filter_state_t filter_get_smt_user;
755 pdq_filter_state_t filter_get_reserved_all;
756 pdq_filter_state_t filter_get_implementor_all;
757 } pdq_response_filter_get_t;
759 #define PDQ_SIZE_RESPONSE_FILTER_GET 0x28
762 pdq_cmd_code_t chars_set_op;
764 pdq_item_code_t item_code;
765 pdq_uint32_t item_value;
766 pdq_port_type_t item_port;
767 } chars_set_items[1];
768 pdq_item_code_t chars_set_eol_item_code;
769 } pdq_cmd_chars_set_t;
772 pdq_cmd_code_t addr_filter_set_op;
773 pdq_lanaddr_t addr_filter_set_addresses[62];
774 } pdq_cmd_addr_filter_set_t;
776 #define PDQ_SIZE_CMD_ADDR_FILTER_SET 0x1F4
779 pdq_uint32_t addr_filter_get_reserved;
780 pdq_cmd_code_t addr_filter_get_op;
781 pdq_response_code_t addr_filter_get_status;
782 pdq_lanaddr_t addr_filter_get_addresses[62];
783 } pdq_response_addr_filter_get_t;
785 #define PDQ_SIZE_RESPONSE_ADDR_FILTER_GET 0x1FC
788 pdq_uint32_t status_chars_get_reserved;
789 pdq_cmd_code_t status_chars_get_op;
790 pdq_response_code_t status_chars_get_status;
792 /* Station Characteristic Attributes */
793 pdq_station_id_t station_id;
794 pdq_station_type_t station_type;
795 pdq_uint32_t smt_version_id;
796 pdq_uint32_t smt_max_version_id;
797 pdq_uint32_t smt_min_version_id;
798 /* Station Status Attributes */
799 pdq_station_state_t station_state;
800 /* Link Characteristic Attributes */
801 pdq_lanaddr_t link_address;
802 pdq_fdditimer_t t_req;
804 pdq_fdditimer_t restricted_token_timeout;
805 pdq_boolean_t ring_purger_enable;
806 pdq_link_state_t link_state;
807 pdq_fdditimer_t negotiated_trt;
808 pdq_da_test_state_t dup_addr_flag;
809 /* Link Status Attributes */
810 pdq_lanaddr_t upstream_neighbor;
811 pdq_lanaddr_t old_upstream_neighbor;
812 pdq_boolean_t upstream_neighbor_dup_addr_flag;
813 pdq_lanaddr_t downstream_neighbor;
814 pdq_lanaddr_t old_downstream_neighbor;
815 pdq_ring_purger_state_t ring_purger_state;
816 pdq_frame_strip_mode_t frame_strip_mode;
817 pdq_ring_error_reason_t ring_error_reason;
818 pdq_boolean_t loopback;
819 pdq_fdditimer_t ring_latency;
820 pdq_lanaddr_t last_dir_beacon_sa;
821 pdq_lanaddr_t last_dir_beacon_una;
822 /* Phy Characteristic Attributes */
823 pdq_phy_type_t phy_type[2];
824 pdq_pmd_type_t pmd_type[2];
825 pdq_uint32_t lem_threshold[2];
826 /* Phy Status Attributes */
827 pdq_phy_state_t phy_state[2];
828 pdq_phy_type_t neighbor_phy_type[2];
829 pdq_uint32_t link_error_estimate[2];
830 pdq_broken_reason_t broken_reason[2];
831 pdq_reject_reason_t reject_reason[2];
833 pdq_uint32_t counter_interval;
834 pdq_fwrev_t module_rev;
835 pdq_fwrev_t firmware_rev;
836 pdq_uint32_t mop_device_type;
837 pdq_uint32_t fddi_led[2];
840 } pdq_response_status_chars_get_t;
842 #define PDQ_SIZE_RESPONSE_STATUS_CHARS_GET 0xF0
845 pdq_uint32_t fddi_mib_get_reserved;
846 pdq_cmd_code_t fddi_mib_get_op;
847 pdq_response_code_t fddi_mib_get_status;
850 pdq_station_id_t smt_station_id;
851 pdq_uint32_t smt_op_version_id;
852 pdq_uint32_t smt_hi_version_id;
853 pdq_uint32_t smt_lo_version_id;
854 pdq_uint32_t smt_mac_ct;
855 pdq_uint32_t smt_non_master_ct;
856 pdq_uint32_t smt_master_ct;
857 pdq_uint32_t smt_paths_available;
858 pdq_uint32_t smt_config_capabilities;
859 pdq_uint32_t smt_config_policy;
860 pdq_uint32_t smt_connection_policy;
861 pdq_uint32_t smt_t_notify;
862 pdq_uint32_t smt_status_reporting;
863 pdq_uint32_t smt_ecm_state;
864 pdq_uint32_t smt_cf_state;
865 pdq_uint32_t smt_hold_state;
866 pdq_uint32_t smt_remote_disconnect_flag;
867 pdq_uint32_t smt_station_action;
869 pdq_uint32_t mac_frame_status_capabilities;
870 pdq_uint32_t mac_t_max_greatest_lower_bound;
871 pdq_uint32_t mac_tvx_greatest_lower_bound;
872 pdq_uint32_t mac_paths_available;
873 pdq_uint32_t mac_current_path;
874 pdq_lanaddr_t mac_upstream_neighbor;
875 pdq_lanaddr_t mac_old_upstream_neighbor;
876 pdq_uint32_t mac_dup_addr_test;
877 pdq_uint32_t mac_paths_requested;
878 pdq_uint32_t mac_downstream_port_type;
879 pdq_lanaddr_t mac_smt_address;
880 pdq_uint32_t mac_t_req;
881 pdq_uint32_t mac_t_neg;
882 pdq_uint32_t mac_t_max;
883 pdq_uint32_t mac_tvx_value;
884 pdq_uint32_t mac_t_min;
885 pdq_uint32_t mac_current_frame_status;
886 pdq_uint32_t mac_frame_error_threshold;
887 pdq_uint32_t mac_frame_error_ratio;
888 pdq_uint32_t mac_rmt_state;
889 pdq_uint32_t mac_da_flag;
890 pdq_uint32_t mac_una_da_flag;
891 pdq_uint32_t mac_frame_condition;
892 pdq_uint32_t mac_chip_set;
893 pdq_uint32_t mac_action;
895 pdq_uint32_t port_pc_type[2];
896 pdq_uint32_t port_pc_neighbor[2];
897 pdq_uint32_t port_connection_policies[2];
898 pdq_uint32_t port_remote_mac_indicated[2];
899 pdq_uint32_t port_ce_state[2];
900 pdq_uint32_t port_paths_requested[2];
901 pdq_uint32_t port_mac_placement[2];
902 pdq_uint32_t port_available_paths[2];
903 pdq_uint32_t port_mac_loop_time[2];
904 pdq_uint32_t port_tb_max[2];
905 pdq_uint32_t port_bs_flag[2];
906 pdq_uint32_t port_ler_estimate[2];
907 pdq_uint32_t port_ler_cutoff[2];
908 pdq_uint32_t port_ler_alarm[2];
909 pdq_uint32_t port_connect_state[2];
910 pdq_uint32_t port_pcm_state[2];
911 pdq_uint32_t port_pc_withhold[2];
912 pdq_uint32_t port_ler_condition[2];
913 pdq_uint32_t port_chip_set[2];
914 pdq_uint32_t port_action[2];
915 /* Attachment Objects */
916 pdq_uint32_t attachment_class;
917 pdq_uint32_t attachment_optical_bypass_present;
918 pdq_uint32_t attachment_imax_expiration;
919 pdq_uint32_t attachment_inserted_status;
920 pdq_uint32_t attachment_insert_policy;
922 } pdq_response_fddi_mib_get_t;
924 #define PDQ_SIZE_RESPONSE_FDDI_MIB_GET 0x17C
927 PDQ_FDX_STATE_IDLE=0,
928 PDQ_FDX_STATE_REQUEST=1,
929 PDQ_FDX_STATE_CONFIRM=2,
930 PDQ_FDX_STATE_OPERATION=3
934 pdq_uint32_t dec_ext_mib_get_reserved;
935 pdq_cmd_code_t dec_ext_mib_get_op;
936 pdq_response_code_t dec_ext_mib_get_response;
939 pdq_uint32_t esmt_station_type;
941 pdq_uint32_t emac_link_state;
942 pdq_uint32_t emac_ring_purger_state;
943 pdq_uint32_t emac_ring_purger_enable;
944 pdq_uint32_t emac_frame_strip_mode;
945 pdq_uint32_t emac_ring_error_reason;
946 pdq_uint32_t emac_upstream_nbr_dupl_address_flag;
947 pdq_uint32_t emac_restricted_token_timeout;
949 pdq_uint32_t eport_pmd_type[2];
950 pdq_uint32_t eport_phy_state[2];
951 pdq_uint32_t eport_reject_reason[2];
952 /* Full Duplex Objects */
953 pdq_boolean_t fdx_enable;
954 pdq_boolean_t fdx_operational;
955 pdq_fdx_state_t fdx_state;
957 } pdq_response_dec_ext_mib_get_t;
959 #define PDQ_SIZE_RESPONSE_DEC_EXT_MIB_GET 0x50
962 PDQ_CALLER_ID_NONE=0,
963 PDQ_CALLER_ID_SELFTEST=1,
965 PDQ_CALLER_ID_FIRMWARE=5,
966 PDQ_CALLER_ID_CONSOLE=8
970 pdq_uint32_t error_log_get__reserved;
971 pdq_cmd_code_t error_log_get_op;
972 pdq_response_code_t error_log_get_status;
974 pdq_uint32_t error_log_get_event_status;
975 /* Event Information Block */
976 pdq_caller_id_t error_log_get_caller_id;
977 pdq_uint32_t error_log_get_timestamp[2];
978 pdq_uint32_t error_log_get_write_count;
979 /* Diagnostic Information */
980 pdq_uint32_t error_log_get_fru_implication_mask;
981 pdq_uint32_t error_log_get_test_id;
982 pdq_uint32_t error_log_get_diag_reserved[6];
983 /* Firmware Information */
984 pdq_uint32_t error_log_get_fw_reserved[112];
985 } pdq_response_error_log_get_t;
989 * Definitions for the Unsolicited Event Queue.
992 PDQ_UNSOLICITED_EVENT=0,
993 PDQ_UNSOLICITED_COUNTERS=1
997 PDQ_ENTITY_STATION=0,
999 PDQ_ENTITY_PHY_PORT=2
1003 PDQ_STATION_EVENT_TRACE_RECEIVED=1
1004 } pdq_station_event_t;
1007 PDQ_STATION_EVENT_ARGUMENT_REASON=0, /* pdq_uint32_t */
1008 PDQ_STATION_EVENT_ARGUMENT_EOL=0xFF
1009 } pdq_station_event_argument_t;
1012 PDQ_LINK_EVENT_TRANSMIT_UNDERRUN=0,
1013 PDQ_LINK_EVENT_TRANSMIT_FAILED=1,
1014 PDQ_LINK_EVENT_BLOCK_CHECK_ERROR=2,
1015 PDQ_LINK_EVENT_FRAME_STATUS_ERROR=3,
1016 PDQ_LINK_EVENT_PDU_LENGTH_ERROR=4,
1017 PDQ_LINK_EVENT_RECEIVE_DATA_OVERRUN=7,
1018 PDQ_LINK_EVENT_NO_USER_BUFFER=9,
1019 PDQ_LINK_EVENT_RING_INITIALIZATION_INITIATED=10,
1020 PDQ_LINK_EVENT_RING_INITIALIZATION_RECEIVED=11,
1021 PDQ_LINK_EVENT_RING_BEACON_INITIATED=12,
1022 PDQ_LINK_EVENT_DUPLICATE_ADDRESS_FAILURE=13,
1023 PDQ_LINK_EVENT_DUPLICATE_TOKEN_DETECTED=14,
1024 PDQ_LINK_EVENT_RING_PURGE_ERROR=15,
1025 PDQ_LINK_EVENT_FCI_STRIP_ERROR=16,
1026 PDQ_LINK_EVENT_TRACE_INITIATED=17,
1027 PDQ_LINK_EVENT_DIRECTED_BEACON_RECEIVED=18
1031 PDQ_LINK_EVENT_ARGUMENT_REASON=0, /* pdq_rireason_t */
1032 PDQ_LINK_EVENT_ARGUMENT_DATA_LINK_HEADER=1, /* pdq_dlhdr_t */
1033 PDQ_LINK_EVENT_ARGUMENT_SOURCE=2, /* pdq_lanaddr_t */
1034 PDQ_LINK_EVENT_ARGUMENT_UPSTREAM_NEIGHBOR=3,/* pdq_lanaddr_t */
1035 PDQ_LINK_EVENT_ARGUMENT_EOL=0xFF
1036 } pdq_link_event_argument_t;
1039 PDQ_PHY_EVENT_LEM_ERROR_MONITOR_REJECT=0,
1040 PDQ_PHY_EVENT_ELASTICITY_BUFFER_ERROR=1,
1041 PDQ_PHY_EVENT_LINK_CONFIDENCE_TEST_REJECT=2
1045 PDQ_PHY_EVENT_ARGUMENT_DIRECTION=0, /* pdq_lct_direction_t */
1046 PDQ_PHY_EVENT_ARGUMENT_EOL=0xFF
1047 } pdq_phy_event_arguments;
1049 struct _pdq_unsolicited_event_t {
1050 pdq_uint32_t rvent_reserved;
1051 pdq_event_t event_type;
1052 pdq_entity_t event_entity;
1053 pdq_uint32_t event_index;
1055 pdq_station_event_t station_event;
1056 pdq_link_event_t link_event;
1057 pdq_phy_event_t phy_event;
1061 * The remainder of this event is an argument list.
1063 pdq_uint32_t event__filler[123];
1066 #endif /* _PDQREG_H */