sys/net/i4b/layer1/isic/i4b_dynalink.c

   1 /*
   2  *   Copyright (c) 1998 Martijn Plak. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *
  33  *      isdn4bsd layer1 driver for Dynalink IS64PH isdn TA
  34  *      ==================================================
  35  *
  36  * $FreeBSD: src/sys/i4b/layer1/isic/i4b_dynalink.c,v 1.5.2.1 2001/08/10 14:08:38 obrien Exp $
  37  * $DragonFly: src/sys/net/i4b/layer1/isic/i4b_dynalink.c,v 1.3 2003/08/07 21:17:26 dillon Exp $
  38  *
  39  *      last edit-date: [Wed Jan 24 09:08:03 2001]
  40  *
  41  *---------------------------------------------------------------------------*/
  42
  43 /*      NOTES:
  44
  45         This driver was written for the Dynalink IS64PH ISDN TA, based on two
  46         Siemens chips (HSCX 21525 and ISAC 2186). It is sold in the Netherlands.
  47
  48         model numbers found on (my) card:
  49                 IS64PH, TAS100H-N, P/N:89590555, TA200S100045521
  50
  51         chips:
  52                 Siemens PSB 21525N, HSCX TE V2.1
  53                 Siemens PSB 2186N, ISAC-S TE V1.1
  54                 95MS14, PNP
  55
  56         plug-and-play info:
  57                 device id       "ASU1688"
  58                 vendor id       0x88167506
  59                 serial          0x00000044
  60                 i/o port        4 byte alignment, 4 bytes requested,
  61                                 10 bit i/o decoding, 0x100-0x3f8 (?)
  62                 irq             3,4,5,9,10,11,12,15, high true, edge sensitive
  63
  64         At the moment I'm writing this Dynalink is replacing this card with
  65         one based on a single Siemens chip (IPAC). It will apparently be sold
  66         under the same model name.
  67
  68         This driver might also work for Asuscom cards.
  69 */
  70
  71 #include "use_isic.h"
  72 #include "opt_i4b.h"
  73
  74 #if (NISIC > 0) && defined(DYNALINK)
  75
  76 #include <sys/param.h>
  77 #include <sys/systm.h>
  78 #include <sys/socket.h>
  79 #include <net/if.h>
  80
  81 #include <net/i4b/include/machine/i4b_ioctl.h>
  82 #include <net/i4b/include/machine/i4b_trace.h>
  83
  84 #include "../i4b_l1.h"
  85 #include "i4b_isic.h"
  86 #include "i4b_hscx.h"
  87
  88 /* io address mapping */
  89 #define ISAC            0
  90 #define HSCX            1
  91 #define ADDR            2
  92
  93 /* ADDR bits */
  94 #define ADDRMASK        0x7F
  95 #define RESET           0x80
  96
  97 /* HSCX register offsets */
  98 #define HSCXA           0x00
  99 #define HSCXB           0x40
 100
 101 /*      LOW-LEVEL DEVICE ACCESS
 102 */
 103
 104 static void
 105 dynalink_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 106 {
 107         bus_space_tag_t    t = rman_get_bustag(sc->sc_resources.io_base[0]);
 108         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
 109
 110         switch (what) {
 111                 case ISIC_WHAT_ISAC:
 112                         bus_space_write_1(t, h, ADDR, 0);
 113                         bus_space_read_multi_1(t, h, ISAC, buf, size);
 114                         break;
 115                 case ISIC_WHAT_HSCXA:
 116                         bus_space_write_1(t, h, ADDR, HSCXA);
 117                         bus_space_read_multi_1(t, h, HSCX, buf, size);
 118                         break;
 119                 case ISIC_WHAT_HSCXB:
 120                         bus_space_write_1(t, h, ADDR, HSCXB);
 121                         bus_space_read_multi_1(t, h, HSCX, buf, size);
 122                         break;
 123         }
 124 }
 125
 126 static void
 127 dynalink_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 128 {
 129         bus_space_tag_t    t = rman_get_bustag(sc->sc_resources.io_base[0]);
 130         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
 131
 132         switch (what) {
 133                 case ISIC_WHAT_ISAC:
 134                         bus_space_write_1(t, h, ADDR, 0);
 135                         bus_space_write_multi_1(t, h, ISAC, (u_int8_t*)buf, size);
 136                         break;
 137                 case ISIC_WHAT_HSCXA:
 138                         bus_space_write_1(t, h, ADDR, HSCXA);
 139                         bus_space_write_multi_1(t, h, HSCX, (u_int8_t*)buf, size);
 140                         break;
 141                 case ISIC_WHAT_HSCXB:
 142                         bus_space_write_1(t, h, ADDR, HSCXB);
 143                         bus_space_write_multi_1(t, h, HSCX, (u_int8_t*)buf, size);
 144                         break;
 145         }
 146 }
 147
 148 static void
 149 dynalink_write_reg(struct l1_softc *sc, int what, bus_size_t reg, u_int8_t data)
 150 {
 151         bus_space_tag_t    t = rman_get_bustag(sc->sc_resources.io_base[0]);
 152         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
 153
 154         switch (what) {
 155                 case ISIC_WHAT_ISAC:
 156                         bus_space_write_1(t, h, ADDR, reg);
 157                         bus_space_write_1(t, h, ISAC, data);
 158                         break;
 159                 case ISIC_WHAT_HSCXA:
 160                         bus_space_write_1(t, h, ADDR, HSCXA+reg);
 161                         bus_space_write_1(t, h, HSCX, data);
 162                         break;
 163                 case ISIC_WHAT_HSCXB:
 164                         bus_space_write_1(t, h, ADDR, HSCXB+reg);
 165                         bus_space_write_1(t, h, HSCX, data);
 166                         break;
 167         }
 168 }
 169
 170 static u_int8_t
 171 dynalink_read_reg(struct l1_softc *sc, int what, bus_size_t reg)
 172 {
 173         bus_space_tag_t    t = rman_get_bustag(sc->sc_resources.io_base[0]);
 174         bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
 175
 176         switch (what) {
 177                 case ISIC_WHAT_ISAC:
 178                         bus_space_write_1(t, h, ADDR, reg);
 179                         return bus_space_read_1(t, h, ISAC);
 180                 case ISIC_WHAT_HSCXA:
 181                         bus_space_write_1(t, h, ADDR, HSCXA+reg);
 182                         return bus_space_read_1(t, h, HSCX);
 183                 case ISIC_WHAT_HSCXB:
 184                         bus_space_write_1(t, h, ADDR, HSCXB+reg);
 185                         return bus_space_read_1(t, h, HSCX);
 186         }
 187         return 0;
 188 }
 189
 190 /* attach callback routine */
 191 int
 192 isic_attach_Dyn(device_t dev)
 193 {
 194         int unit = device_get_unit(dev);        /* get unit */
 195         struct l1_softc *sc = &l1_sc[unit];             /* pointer to softc */
 196
 197         struct i4b_info *  info = &(sc->sc_resources);
 198         bus_space_tag_t    t = rman_get_bustag(info->io_base[0]);
 199         bus_space_handle_t h = rman_get_bushandle(info->io_base[0]);
 200
 201         /* fill in l1_softc structure */
 202         sc->readreg     = dynalink_read_reg;
 203         sc->writereg    = dynalink_write_reg;
 204         sc->readfifo    = dynalink_read_fifo;
 205         sc->writefifo   = dynalink_write_fifo;
 206         sc->clearirq    = NULL;
 207         sc->sc_cardtyp = CARD_TYPEP_DYNALINK;
 208         sc->sc_bustyp = BUS_TYPE_IOM2;
 209         sc->sc_ipac = 0;
 210         sc->sc_bfifolen = HSCX_FIFO_LEN;
 211
 212         /* Read HSCX A/B VSTR.  Expected value is 0x05 (V2.1). */
 213         if( ((HSCX_READ(0, H_VSTR) & 0xf) != 0x5) ||
 214             ((HSCX_READ(1, H_VSTR) & 0xf) != 0x5) )
 215         {
 216                 printf("isic%d: HSCX VSTR test failed for Dynalink\n",
 217                         sc->sc_unit);
 218                 printf("isic%d: HSC0: VSTR: %#x\n",
 219                         sc->sc_unit, HSCX_READ(0, H_VSTR));
 220                 printf("isic%d: HSC1: VSTR: %#x\n",
 221                         sc->sc_unit, HSCX_READ(1, H_VSTR));
 222                 return ENXIO;
 223         }
 224
 225         /* reset card */
 226         bus_space_write_1(t,h,ADDR,RESET);
 227         DELAY(SEC_DELAY / 10);
 228         bus_space_write_1(t,h,ADDR,0);
 229         DELAY(SEC_DELAY / 10);
 230
 231         return 0;
 232 }
 233
 234 #endif /* (NISIC > 0) && defined(DYNALINK) */