2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 * Modifications for FreeBSD-stable by Edwin Groothuis
5 * <edwin at mavetju.org
6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v
32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.19 2005/08/10 13:31:03 joerg Exp $
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/queue.h>
43 #include <sys/thread2.h>
46 #include <net/ifq_var.h>
47 #include <net/if_arp.h>
48 #include <net/ethernet.h>
49 #include <net/if_dl.h>
50 #include <net/if_media.h>
54 #include <net/if_types.h>
55 #include <net/vlan/if_vlan_var.h>
57 #include <netinet/in_systm.h>
58 #include <netinet/in.h>
59 #include <netinet/ip.h>
61 #include <machine/bus_memio.h>
62 #include <machine/bus.h>
63 #include <machine/resource.h>
67 #include <bus/pci/pcireg.h>
68 #include <bus/pci/pcivar.h>
69 #include <bus/pci/pcidevs.h>
71 #include <dev/netif/mii_layer/mii.h>
72 #include <dev/netif/mii_layer/miivar.h>
74 #include "if_bfereg.h"
76 MODULE_DEPEND(bfe, pci, 1, 1, 1);
77 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
79 /* "controller miibus0" required. See GENERIC if you get errors here. */
80 #include "miibus_if.h"
82 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
84 static struct bfe_type bfe_devs[] = {
85 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401,
86 "Broadcom BCM4401 Fast Ethernet" },
87 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0,
88 "Broadcom BCM4401-B0 Fast Ethernet" },
92 static int bfe_probe(device_t);
93 static int bfe_attach(device_t);
94 static int bfe_detach(device_t);
95 static void bfe_intr(void *);
96 static void bfe_start(struct ifnet *);
97 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
98 static void bfe_init(void *);
99 static void bfe_stop(struct bfe_softc *);
100 static void bfe_watchdog(struct ifnet *);
101 static void bfe_shutdown(device_t);
102 static void bfe_tick(void *);
103 static void bfe_txeof(struct bfe_softc *);
104 static void bfe_rxeof(struct bfe_softc *);
105 static void bfe_set_rx_mode(struct bfe_softc *);
106 static int bfe_list_rx_init(struct bfe_softc *);
107 static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*);
108 static void bfe_rx_ring_free(struct bfe_softc *);
110 static void bfe_pci_setup(struct bfe_softc *, uint32_t);
111 static int bfe_ifmedia_upd(struct ifnet *);
112 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
113 static int bfe_miibus_readreg(device_t, int, int);
114 static int bfe_miibus_writereg(device_t, int, int, int);
115 static void bfe_miibus_statchg(device_t);
116 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t,
118 static void bfe_get_config(struct bfe_softc *sc);
119 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *);
120 static void bfe_stats_update(struct bfe_softc *);
121 static void bfe_clear_stats (struct bfe_softc *);
122 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*);
123 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t);
124 static int bfe_resetphy(struct bfe_softc *);
125 static int bfe_setupphy(struct bfe_softc *);
126 static void bfe_chip_reset(struct bfe_softc *);
127 static void bfe_chip_halt(struct bfe_softc *);
128 static void bfe_core_reset(struct bfe_softc *);
129 static void bfe_core_disable(struct bfe_softc *);
130 static int bfe_dma_alloc(device_t);
131 static void bfe_dma_free(struct bfe_softc *);
132 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int);
133 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int);
134 static void bfe_cam_write(struct bfe_softc *, u_char *, int);
136 static device_method_t bfe_methods[] = {
137 /* Device interface */
138 DEVMETHOD(device_probe, bfe_probe),
139 DEVMETHOD(device_attach, bfe_attach),
140 DEVMETHOD(device_detach, bfe_detach),
141 DEVMETHOD(device_shutdown, bfe_shutdown),
144 DEVMETHOD(bus_print_child, bus_generic_print_child),
145 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
148 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
149 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
150 DEVMETHOD(miibus_statchg, bfe_miibus_statchg),
155 static driver_t bfe_driver = {
158 sizeof(struct bfe_softc)
161 static devclass_t bfe_devclass;
163 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
164 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
167 * Probe for a Broadcom 4401 chip.
170 bfe_probe(device_t dev)
173 uint16_t vendor, product;
175 vendor = pci_get_vendor(dev);
176 product = pci_get_device(dev);
178 for (t = bfe_devs; t->bfe_name != NULL; t++) {
179 if (vendor == t->bfe_vid && product == t->bfe_did) {
180 device_set_desc(dev, t->bfe_name);
189 bfe_dma_alloc(device_t dev)
191 struct bfe_softc *sc;
192 int error, i, tx_pos, rx_pos;
194 sc = device_get_softc(dev);
197 error = bus_dma_tag_create(NULL, /* parent */
198 PAGE_SIZE, 0, /* alignment, boundary */
199 BUS_SPACE_MAXADDR, /* lowaddr */
200 BUS_SPACE_MAXADDR_32BIT, /* highaddr */
201 NULL, NULL, /* filter, filterarg */
202 MAXBSIZE, /* maxsize */
203 BUS_SPACE_UNRESTRICTED, /* num of segments */
204 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */
205 BUS_DMA_ALLOCNOW, /* flags */
206 &sc->bfe_parent_tag);
209 device_printf(dev, "could not allocate parent dma tag\n");
213 /* tag for TX ring */
214 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_TX_LIST_SIZE,
215 BFE_TX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
216 NULL, NULL, BFE_TX_LIST_SIZE, 1,
217 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_tx_tag);
220 device_printf(dev, "could not allocate dma tag for TX list\n");
224 /* tag for RX ring */
225 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_RX_LIST_SIZE,
226 BFE_RX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
227 NULL, NULL, BFE_RX_LIST_SIZE, 1,
228 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_rx_tag);
231 device_printf(dev, "could not allocate dma tag for RX list\n");
236 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0,
237 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
238 1, BUS_SPACE_MAXSIZE_32BIT, 0,
242 device_printf(dev, "could not allocate dma tag for mbufs\n");
248 /* pre allocate dmamaps for RX list */
249 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
250 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_rx_ring[i].bfe_map);
253 device_printf(dev, "cannot create DMA map for RX\n");
257 rx_pos = BFE_RX_LIST_CNT;
259 /* pre allocate dmamaps for TX list */
260 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
261 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_tx_ring[i].bfe_map);
264 device_printf(dev, "cannot create DMA map for TX\n");
269 /* Alloc dma for rx ring */
270 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
271 BUS_DMA_WAITOK, &sc->bfe_rx_map);
274 device_printf(dev, "cannot allocate DMA mem for RX\n");
278 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
279 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
280 sc->bfe_rx_list, sizeof(struct bfe_desc),
281 bfe_dma_map, &sc->bfe_rx_dma, 0);
284 device_printf(dev, "cannot load DMA map for RX\n");
288 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
290 /* Alloc dma for tx ring */
291 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
292 BUS_DMA_WAITOK, &sc->bfe_tx_map);
294 device_printf(dev, "cannot allocate DMA mem for TX\n");
298 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
299 sc->bfe_tx_list, sizeof(struct bfe_desc),
300 bfe_dma_map, &sc->bfe_tx_dma, 0);
302 device_printf(dev, "cannot load DMA map for TX\n");
306 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
307 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
312 for (i = 0; i < rx_pos; ++i)
313 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_rx_ring[i].bfe_map);
314 for (i = 0; i < tx_pos; ++i)
315 bus_dmamap_destroy(sc->bfe_tag, sc->bfe_tx_ring[i].bfe_map);
317 bus_dma_tag_destroy(sc->bfe_tag);
323 bfe_attach(device_t dev)
326 struct bfe_softc *sc;
329 sc = device_get_softc(dev);
332 callout_init(&sc->bfe_stat_timer);
335 * Handle power management nonsense.
337 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
338 uint32_t membase, irq;
340 /* Save important PCI config data. */
341 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4);
342 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4);
344 /* Reset the power state. */
345 device_printf(dev, "chip is in D%d power mode"
346 " -- setting to D0\n", pci_get_powerstate(dev));
348 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
350 /* Restore PCI config data. */
351 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4);
352 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4);
356 * Map control/status registers.
358 pci_enable_busmaster(dev);
361 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
363 if (sc->bfe_res == NULL) {
364 device_printf(dev, "couldn't map memory\n");
368 sc->bfe_btag = rman_get_bustag(sc->bfe_res);
369 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res);
371 /* Allocate interrupt */
374 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
375 RF_SHAREABLE | RF_ACTIVE);
376 if (sc->bfe_irq == NULL) {
377 device_printf(dev, "couldn't map interrupt\n");
382 error = bfe_dma_alloc(dev);
384 device_printf(dev, "failed to allocate DMA resources\n");
388 /* Set up ifnet structure */
389 ifp = &sc->arpcom.ac_if;
391 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
392 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
393 ifp->if_ioctl = bfe_ioctl;
394 ifp->if_start = bfe_start;
395 ifp->if_watchdog = bfe_watchdog;
396 ifp->if_init = bfe_init;
397 ifp->if_mtu = ETHERMTU;
398 ifp->if_baudrate = 10000000;
399 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN);
400 ifq_set_ready(&ifp->if_snd);
404 /* Reset the chip and turn on the PHY */
407 if (mii_phy_probe(dev, &sc->bfe_miibus,
408 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
409 device_printf(dev, "MII without any PHY!\n");
414 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
417 * Hook interrupt last to avoid having to lock softc
419 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET,
420 bfe_intr, sc, &sc->bfe_intrhand, NULL);
424 device_printf(dev, "couldn't set up irq\n");
434 bfe_detach(device_t dev)
436 struct bfe_softc *sc = device_get_softc(dev);
437 struct ifnet *ifp = &sc->arpcom.ac_if;
441 if (device_is_attached(dev)) {
446 if (sc->bfe_miibus != NULL)
447 device_delete_child(dev, sc->bfe_miibus);
448 bus_generic_detach(dev);
450 if (sc->bfe_intrhand != NULL)
451 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand);
455 if (sc->bfe_irq != NULL)
456 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq);
458 if (sc->bfe_res != NULL) {
459 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO,
468 * Stop all chip I/O so that the kernel's probe routines don't
469 * get confused by errant DMAs when rebooting.
472 bfe_shutdown(device_t dev)
474 struct bfe_softc *sc = device_get_softc(dev);
484 bfe_miibus_readreg(device_t dev, int phy, int reg)
486 struct bfe_softc *sc;
489 sc = device_get_softc(dev);
490 if (phy != sc->bfe_phyaddr)
492 bfe_readphy(sc, reg, &ret);
498 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
500 struct bfe_softc *sc;
502 sc = device_get_softc(dev);
503 if (phy != sc->bfe_phyaddr)
505 bfe_writephy(sc, reg, val);
511 bfe_miibus_statchg(device_t dev)
517 bfe_tx_ring_free(struct bfe_softc *sc)
521 for (i = 0; i < BFE_TX_LIST_CNT; i++)
522 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
523 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
524 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
525 bus_dmamap_unload(sc->bfe_tag,
526 sc->bfe_tx_ring[i].bfe_map);
528 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
529 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
533 bfe_rx_ring_free(struct bfe_softc *sc)
537 for (i = 0; i < BFE_RX_LIST_CNT; i++)
538 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
539 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
540 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
541 bus_dmamap_unload(sc->bfe_tag,
542 sc->bfe_rx_ring[i].bfe_map);
544 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
545 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
550 bfe_list_rx_init(struct bfe_softc *sc)
554 for (i = 0; i < BFE_RX_LIST_CNT; i++)
555 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS)
558 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
559 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
567 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m)
569 struct bfe_rxheader *rx_header;
574 if ((c < 0) || (c >= BFE_RX_LIST_CNT))
578 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
581 m->m_len = m->m_pkthdr.len = MCLBYTES;
584 m->m_data = m->m_ext.ext_buf;
586 rx_header = mtod(m, struct bfe_rxheader *);
588 rx_header->flags = 0;
590 /* Map the mbuf into DMA */
592 d = &sc->bfe_rx_list[c];
593 r = &sc->bfe_rx_ring[c];
594 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *),
595 MCLBYTES, bfe_dma_map_desc, d, 0);
596 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREREAD);
598 ctrl = ETHER_MAX_LEN + 32;
600 if(c == BFE_RX_LIST_CNT - 1)
601 ctrl |= BFE_DESC_EOT;
605 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
610 bfe_get_config(struct bfe_softc *sc)
614 bfe_read_eeprom(sc, eeprom);
616 sc->arpcom.ac_enaddr[0] = eeprom[79];
617 sc->arpcom.ac_enaddr[1] = eeprom[78];
618 sc->arpcom.ac_enaddr[2] = eeprom[81];
619 sc->arpcom.ac_enaddr[3] = eeprom[80];
620 sc->arpcom.ac_enaddr[4] = eeprom[83];
621 sc->arpcom.ac_enaddr[5] = eeprom[82];
623 sc->bfe_phyaddr = eeprom[90] & 0x1f;
624 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
626 sc->bfe_core_unit = 0;
627 sc->bfe_dma_offset = BFE_PCI_DMA;
631 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores)
633 uint32_t bar_orig, pci_rev, val;
635 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
636 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
637 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
639 val = CSR_READ_4(sc, BFE_SBINTVEC);
641 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
643 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
644 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
645 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
647 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
651 bfe_clear_stats(struct bfe_softc *sc)
657 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
658 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
660 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
667 bfe_resetphy(struct bfe_softc *sc)
673 bfe_writephy(sc, 0, BMCR_RESET);
675 bfe_readphy(sc, 0, &val);
676 if (val & BMCR_RESET) {
678 if_printf(&sc->arpcom.ac_if,
679 "PHY Reset would not complete.\n");
688 bfe_chip_halt(struct bfe_softc *sc)
692 /* disable interrupts - not that it actually does..*/
693 CSR_WRITE_4(sc, BFE_IMASK, 0);
694 CSR_READ_4(sc, BFE_IMASK);
696 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
697 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
699 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
700 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
707 bfe_chip_reset(struct bfe_softc *sc)
713 /* Set the interrupt vector for the enet core */
714 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
717 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK);
718 if (val == BFE_CLOCK) {
719 /* It is, so shut it down */
720 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
721 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
722 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
723 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
724 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
725 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
726 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0);
727 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
728 sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
735 * We want the phy registers to be accessible even when
736 * the driver is "downed" so initialize MDC preamble, frequency,
737 * and whether internal or external phy here.
740 /* 4402 has 62.5Mhz SB clock and internal phy */
741 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
743 /* Internal or external PHY? */
744 val = CSR_READ_4(sc, BFE_DEVCTRL);
745 if (!(val & BFE_IPP))
746 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
747 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
748 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
752 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB);
753 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
757 * We don't want lazy interrupts, so just send them at the end of a
760 BFE_OR(sc, BFE_RCV_LAZY, 0);
762 /* Set max lengths, accounting for VLAN tags */
763 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
764 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
766 /* Set watermark XXX - magic */
767 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
770 * Initialise DMA channels - not forgetting dma addresses need to be
771 * added to BFE_PCI_DMA
773 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
774 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
776 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
778 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
787 bfe_core_disable(struct bfe_softc *sc)
789 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
793 * Set reject, wait for it set, then wait for the core to stop being busy
794 * Then set reset and reject and enable the clocks
796 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
797 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
798 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
799 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
801 CSR_READ_4(sc, BFE_SBTMSLOW);
803 /* Leave reset and reject set */
804 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
809 bfe_core_reset(struct bfe_softc *sc)
813 /* Disable the core */
814 bfe_core_disable(sc);
816 /* and bring it back up */
817 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
818 CSR_READ_4(sc, BFE_SBTMSLOW);
821 /* Chip bug, clear SERR, IB and TO if they are set. */
822 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
823 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
824 val = CSR_READ_4(sc, BFE_SBIMSTATE);
825 if (val & (BFE_IBE | BFE_TO))
826 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
828 /* Clear reset and allow it to move through the core */
829 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
830 CSR_READ_4(sc, BFE_SBTMSLOW);
833 /* Leave the clock set */
834 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
835 CSR_READ_4(sc, BFE_SBTMSLOW);
840 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
844 val = ((uint32_t) data[2]) << 24;
845 val |= ((uint32_t) data[3]) << 16;
846 val |= ((uint32_t) data[4]) << 8;
847 val |= ((uint32_t) data[5]);
848 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
849 val = (BFE_CAM_HI_VALID |
850 (((uint32_t) data[0]) << 8) |
851 (((uint32_t) data[1])));
852 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
853 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
854 (index << BFE_CAM_INDEX_SHIFT)));
855 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
859 bfe_set_rx_mode(struct bfe_softc *sc)
861 struct ifnet *ifp = &sc->arpcom.ac_if;
865 val = CSR_READ_4(sc, BFE_RXCONF);
867 if (ifp->if_flags & IFF_PROMISC)
868 val |= BFE_RXCONF_PROMISC;
870 val &= ~BFE_RXCONF_PROMISC;
872 if (ifp->if_flags & IFF_BROADCAST)
873 val &= ~BFE_RXCONF_DBCAST;
875 val |= BFE_RXCONF_DBCAST;
878 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
879 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++);
881 CSR_WRITE_4(sc, BFE_RXCONF, val);
882 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
886 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
891 *ptr = segs->ds_addr;
895 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
900 /* The chip needs all addresses to be added to BFE_PCI_DMA */
901 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA;
905 bfe_dma_free(struct bfe_softc *sc)
907 if (sc->bfe_tx_tag != NULL) {
908 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
909 if (sc->bfe_tx_list != NULL) {
910 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
912 sc->bfe_tx_list = NULL;
914 bus_dma_tag_destroy(sc->bfe_tx_tag);
915 sc->bfe_tx_tag = NULL;
918 if (sc->bfe_rx_tag != NULL) {
919 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
920 if (sc->bfe_rx_list != NULL) {
921 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
923 sc->bfe_rx_list = NULL;
925 bus_dma_tag_destroy(sc->bfe_rx_tag);
926 sc->bfe_rx_tag = NULL;
929 if (sc->bfe_tag != NULL) {
932 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
933 bus_dmamap_destroy(sc->bfe_tag,
934 sc->bfe_tx_ring[i].bfe_map);
936 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
937 bus_dmamap_destroy(sc->bfe_tag,
938 sc->bfe_rx_ring[i].bfe_map);
941 bus_dma_tag_destroy(sc->bfe_tag);
945 if (sc->bfe_parent_tag != NULL) {
946 bus_dma_tag_destroy(sc->bfe_parent_tag);
947 sc->bfe_parent_tag = NULL;
952 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data)
955 uint16_t *ptr = (uint16_t *)data;
957 for (i = 0; i < 128; i += 2)
958 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
962 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit,
963 u_long timeout, const int clear)
967 for (i = 0; i < timeout; i++) {
968 uint32_t val = CSR_READ_4(sc, reg);
970 if (clear && !(val & bit))
972 if (!clear && (val & bit))
977 if_printf(&sc->arpcom.ac_if,
978 "BUG! Timeout waiting for bit %08x of register "
979 "%x to %s.\n", bit, reg,
980 (clear ? "clear" : "set"));
987 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val)
994 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
995 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
996 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
997 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
998 (reg << BFE_MDIO_RA_SHIFT) |
999 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
1000 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1001 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
1008 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val)
1014 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1015 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1016 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1017 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1018 (reg << BFE_MDIO_RA_SHIFT) |
1019 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1020 (val & BFE_MDIO_DATA_DATA)));
1021 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1029 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1033 bfe_setupphy(struct bfe_softc *sc)
1039 /* Enable activity LED */
1040 bfe_readphy(sc, 26, &val);
1041 bfe_writephy(sc, 26, val & 0x7fff);
1042 bfe_readphy(sc, 26, &val);
1044 /* Enable traffic meter LED mode */
1045 bfe_readphy(sc, 27, &val);
1046 bfe_writephy(sc, 27, val | (1 << 6));
1053 bfe_stats_update(struct bfe_softc *sc)
1058 val = &sc->bfe_hwstats.tx_good_octets;
1059 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1060 *val++ += CSR_READ_4(sc, reg);
1061 val = &sc->bfe_hwstats.rx_good_octets;
1062 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1063 *val++ += CSR_READ_4(sc, reg);
1067 bfe_txeof(struct bfe_softc *sc)
1069 struct ifnet *ifp = &sc->arpcom.ac_if;
1070 uint32_t i, chipidx;
1074 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1075 chipidx /= sizeof(struct bfe_desc);
1077 i = sc->bfe_tx_cons;
1078 /* Go through the mbufs and free those that have been transmitted */
1079 while (i != chipidx) {
1080 struct bfe_data *r = &sc->bfe_tx_ring[i];
1081 if (r->bfe_mbuf != NULL) {
1083 m_freem(r->bfe_mbuf);
1085 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1088 BFE_INC(i, BFE_TX_LIST_CNT);
1091 if (i != sc->bfe_tx_cons) {
1092 /* we freed up some mbufs */
1093 sc->bfe_tx_cons = i;
1094 ifp->if_flags &= ~IFF_OACTIVE;
1096 if (sc->bfe_tx_cnt == 0)
1104 /* Pass a received packet up the stack */
1106 bfe_rxeof(struct bfe_softc *sc)
1108 struct ifnet *ifp = &sc->arpcom.ac_if;
1110 struct bfe_rxheader *rxheader;
1112 uint32_t cons, status, current, len, flags;
1116 cons = sc->bfe_rx_cons;
1117 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1118 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1120 while (current != cons) {
1121 r = &sc->bfe_rx_ring[cons];
1123 rxheader = mtod(m, struct bfe_rxheader*);
1124 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE);
1125 len = rxheader->len;
1128 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1129 flags = rxheader->flags;
1131 len -= ETHER_CRC_LEN;
1133 /* flag an error and try again */
1134 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1136 if (flags & BFE_RX_FLAG_SERR)
1137 ifp->if_collisions++;
1138 bfe_list_newbuf(sc, cons, m);
1139 BFE_INC(cons, BFE_RX_LIST_CNT);
1143 /* Go past the rx header */
1144 if (bfe_list_newbuf(sc, cons, NULL) != 0) {
1145 bfe_list_newbuf(sc, cons, m);
1146 BFE_INC(cons, BFE_RX_LIST_CNT);
1151 m_adj(m, BFE_RX_OFFSET);
1152 m->m_len = m->m_pkthdr.len = len;
1155 m->m_pkthdr.rcvif = ifp;
1157 (*ifp->if_input)(ifp, m);
1158 BFE_INC(cons, BFE_RX_LIST_CNT);
1160 sc->bfe_rx_cons = cons;
1168 struct bfe_softc *sc = xsc;
1169 struct ifnet *ifp = &sc->arpcom.ac_if;
1170 uint32_t istat, imask, flag;
1174 istat = CSR_READ_4(sc, BFE_ISTAT);
1175 imask = CSR_READ_4(sc, BFE_IMASK);
1178 * Defer unsolicited interrupts - This is necessary because setting the
1179 * chips interrupt mask register to 0 doesn't actually stop the
1183 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1184 CSR_READ_4(sc, BFE_ISTAT);
1186 /* not expecting this interrupt, disregard it */
1192 if (istat & BFE_ISTAT_ERRORS) {
1193 flag = CSR_READ_4(sc, BFE_DMATX_STAT);
1194 if (flag & BFE_STAT_EMASK)
1197 flag = CSR_READ_4(sc, BFE_DMARX_STAT);
1198 if (flag & BFE_RX_FLAG_ERRORS)
1201 ifp->if_flags &= ~IFF_RUNNING;
1205 /* A packet was received */
1206 if (istat & BFE_ISTAT_RX)
1209 /* A packet was sent */
1210 if (istat & BFE_ISTAT_TX)
1213 /* We have packets pending, fire them out */
1214 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
1221 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1223 struct bfe_desc *d = NULL;
1224 struct bfe_data *r = NULL;
1226 uint32_t frag, cur, cnt = 0;
1228 if (BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2)
1232 * Start packing the mbufs in this chain into
1233 * the fragment pointers. Stop when we run out
1234 * of fragments or hit the end of the mbuf chain.
1237 cur = frag = *txidx;
1240 for (m = m_head; m != NULL; m = m->m_next) {
1241 if (m->m_len != 0) {
1242 if ((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2)
1245 d = &sc->bfe_tx_list[cur];
1246 r = &sc->bfe_tx_ring[cur];
1247 d->bfe_ctrl = BFE_DESC_LEN & m->m_len;
1248 /* always intterupt on completion */
1249 d->bfe_ctrl |= BFE_DESC_IOC;
1251 /* Set start of frame */
1252 d->bfe_ctrl |= BFE_DESC_SOF;
1253 if (cur == BFE_TX_LIST_CNT - 1)
1255 * Tell the chip to wrap to the start of the
1258 d->bfe_ctrl |= BFE_DESC_EOT;
1260 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void*),
1261 m->m_len, bfe_dma_map_desc, d, 0);
1262 bus_dmamap_sync(sc->bfe_tag, r->bfe_map,
1263 BUS_DMASYNC_PREREAD);
1266 BFE_INC(cur, BFE_TX_LIST_CNT);
1274 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF;
1275 sc->bfe_tx_ring[frag].bfe_mbuf = m_head;
1276 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
1279 sc->bfe_tx_cnt += cnt;
1284 * Set up to transmit a packet
1287 bfe_start(struct ifnet *ifp)
1289 struct bfe_softc *sc = ifp->if_softc;
1290 struct mbuf *m_head = NULL;
1296 * not much point trying to send if the link is down or we have nothing to
1299 if (!sc->bfe_link) {
1304 if (ifp->if_flags & IFF_OACTIVE) {
1309 idx = sc->bfe_tx_prod;
1311 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) {
1312 m_head = ifq_poll(&ifp->if_snd);
1317 * Pack the data into the tx ring. If we dont have enough room, let
1318 * the chip drain the ring
1320 if (bfe_encap(sc, m_head, &idx)) {
1321 ifp->if_flags |= IFF_OACTIVE;
1324 m_head = ifq_dequeue(&ifp->if_snd);
1327 * If there's a BPF listener, bounce a copy of this frame
1330 BPF_MTAP(ifp, m_head);
1333 sc->bfe_tx_prod = idx;
1334 /* Transmit - twice due to apparent hardware bug */
1335 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1336 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1339 * Set a timeout in case the chip goes out to lunch.
1349 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1350 struct ifnet *ifp = &sc->arpcom.ac_if;
1354 if (ifp->if_flags & IFF_RUNNING) {
1362 if (bfe_list_rx_init(sc) == ENOBUFS) {
1363 if_printf(ifp, "bfe_init failed. "
1364 " Not enough memory for list buffers\n");
1370 bfe_set_rx_mode(sc);
1372 /* Enable the chip and core */
1373 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1374 /* Enable interrupts */
1375 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1377 bfe_ifmedia_upd(ifp);
1378 ifp->if_flags |= IFF_RUNNING;
1379 ifp->if_flags &= ~IFF_OACTIVE;
1381 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1386 * Set media options.
1389 bfe_ifmedia_upd(struct ifnet *ifp)
1391 struct bfe_softc *sc = ifp->if_softc;
1392 struct mii_data *mii;
1396 mii = device_get_softc(sc->bfe_miibus);
1398 if (mii->mii_instance) {
1399 struct mii_softc *miisc;
1400 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1401 miisc = LIST_NEXT(miisc, mii_list))
1402 mii_phy_reset(miisc);
1411 * Report current media status.
1414 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1416 struct bfe_softc *sc = ifp->if_softc;
1417 struct mii_data *mii;
1421 mii = device_get_softc(sc->bfe_miibus);
1423 ifmr->ifm_active = mii->mii_media_active;
1424 ifmr->ifm_status = mii->mii_media_status;
1430 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1432 struct bfe_softc *sc = ifp->if_softc;
1433 struct ifreq *ifr = (struct ifreq *) data;
1434 struct mii_data *mii;
1441 if (ifp->if_flags & IFF_UP)
1442 if (ifp->if_flags & IFF_RUNNING)
1443 bfe_set_rx_mode(sc);
1446 else if (ifp->if_flags & IFF_RUNNING)
1451 if (ifp->if_flags & IFF_RUNNING)
1452 bfe_set_rx_mode(sc);
1456 mii = device_get_softc(sc->bfe_miibus);
1457 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1461 error = ether_ioctl(ifp, command, data);
1471 bfe_watchdog(struct ifnet *ifp)
1473 struct bfe_softc *sc = ifp->if_softc;
1475 if_printf(ifp, "watchdog timeout -- resetting\n");
1479 ifp->if_flags &= ~IFF_RUNNING;
1490 struct bfe_softc *sc = xsc;
1491 struct mii_data *mii;
1495 mii = device_get_softc(sc->bfe_miibus);
1497 bfe_stats_update(sc);
1498 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1506 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
1507 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1517 * Stop the adapter and free any mbufs allocated to the
1521 bfe_stop(struct bfe_softc *sc)
1523 struct ifnet *ifp = &sc->arpcom.ac_if;
1527 callout_stop(&sc->bfe_stat_timer);
1530 bfe_tx_ring_free(sc);
1531 bfe_rx_ring_free(sc);
1533 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);