sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.111 2008/10/22 14:24:24 sephe Exp $
  35  *
  36  */
  37
  38 /*
  39  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  40  *
  41  * Written by Bill Paul <wpaul@windriver.com>
  42  * Senior Engineer, Wind River Systems
  43  */
  44
  45 /*
  46  * The Broadcom BCM5700 is based on technology originally developed by
  47  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  48  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  49  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  50  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  51  * frames, highly configurable RX filtering, and 16 RX and TX queues
  52  * (which, along with RX filter rules, can be used for QOS applications).
  53  * Other features, such as TCP segmentation, may be available as part
  54  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  55  * firmware images can be stored in hardware and need not be compiled
  56  * into the driver.
  57  *
  58  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  59  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  60  *
  61  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  62  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  63  * does not support external SSRAM.
  64  *
  65  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  66  * brand name, which is functionally similar but lacks PCI-X support.
  67  *
  68  * Without external SSRAM, you can only have at most 4 TX rings,
  69  * and the use of the mini RX ring is disabled. This seems to imply
  70  * that these features are simply not available on the BCM5701. As a
  71  * result, this driver does not implement any support for the mini RX
  72  * ring.
  73  */
  74
  75 #include "opt_polling.h"
  76
  77 #include <sys/param.h>
  78 #include <sys/bus.h>
  79 #include <sys/endian.h>
  80 #include <sys/kernel.h>
  81 #include <sys/ktr.h>
  82 #include <sys/interrupt.h>
  83 #include <sys/mbuf.h>
  84 #include <sys/malloc.h>
  85 #include <sys/queue.h>
  86 #include <sys/rman.h>
  87 #include <sys/serialize.h>
  88 #include <sys/socket.h>
  89 #include <sys/sockio.h>
  90 #include <sys/sysctl.h>
  91
  92 #include <net/bpf.h>
  93 #include <net/ethernet.h>
  94 #include <net/if.h>
  95 #include <net/if_arp.h>
  96 #include <net/if_dl.h>
  97 #include <net/if_media.h>
  98 #include <net/if_types.h>
  99 #include <net/ifq_var.h>
 100 #include <net/vlan/if_vlan_var.h>
 101 #include <net/vlan/if_vlan_ether.h>
 102
 103 #include <dev/netif/mii_layer/mii.h>
 104 #include <dev/netif/mii_layer/miivar.h>
 105 #include <dev/netif/mii_layer/brgphyreg.h>
 106
 107 #include <bus/pci/pcidevs.h>
 108 #include <bus/pci/pcireg.h>
 109 #include <bus/pci/pcivar.h>
 110
 111 #include <dev/netif/bge/if_bgereg.h>
 112
 113 /* "device miibus" required.  See GENERIC if you get errors here. */
 114 #include "miibus_if.h"
 115
 116 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 117 #define BGE_MIN_FRAME           60
 118
 119 static const struct bge_type bge_devs[] = {
 120         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
 121                 "3COM 3C996 Gigabit Ethernet" },
 122
 123         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 124                 "Alteon BCM5700 Gigabit Ethernet" },
 125         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
 126                 "Alteon BCM5701 Gigabit Ethernet" },
 127
 128         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 129                 "Altima AC1000 Gigabit Ethernet" },
 130         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 131                 "Altima AC1002 Gigabit Ethernet" },
 132         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 133                 "Altima AC9100 Gigabit Ethernet" },
 134
 135         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
 136                 "Apple BCM5701 Gigabit Ethernet" },
 137
 138         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 139                 "Broadcom BCM5700 Gigabit Ethernet" },
 140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 141                 "Broadcom BCM5701 Gigabit Ethernet" },
 142         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
 143                 "Broadcom BCM5702 Gigabit Ethernet" },
 144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 145                 "Broadcom BCM5702X Gigabit Ethernet" },
 146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
 147                 "Broadcom BCM5702 Gigabit Ethernet" },
 148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
 149                 "Broadcom BCM5703 Gigabit Ethernet" },
 150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 151                 "Broadcom BCM5703X Gigabit Ethernet" },
 152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
 153                 "Broadcom BCM5703 Gigabit Ethernet" },
 154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 155                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 157                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
 159                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 161                 "Broadcom BCM5705 Gigabit Ethernet" },
 162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
 163                 "Broadcom BCM5705F Gigabit Ethernet" },
 164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
 165                 "Broadcom BCM5705K Gigabit Ethernet" },
 166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 167                 "Broadcom BCM5705M Gigabit Ethernet" },
 168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
 169                 "Broadcom BCM5705M Gigabit Ethernet" },
 170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
 171                 "Broadcom BCM5714C Gigabit Ethernet" },
 172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
 173                 "Broadcom BCM5714S Gigabit Ethernet" },
 174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
 175                 "Broadcom BCM5715 Gigabit Ethernet" },
 176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
 177                 "Broadcom BCM5715S Gigabit Ethernet" },
 178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
 179                 "Broadcom BCM5720 Gigabit Ethernet" },
 180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
 181                 "Broadcom BCM5721 Gigabit Ethernet" },
 182         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
 183                 "Broadcom BCM5722 Gigabit Ethernet" },
 184         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
 185                 "Broadcom BCM5750 Gigabit Ethernet" },
 186         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
 187                 "Broadcom BCM5750M Gigabit Ethernet" },
 188         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
 189                 "Broadcom BCM5751 Gigabit Ethernet" },
 190         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
 191                 "Broadcom BCM5751F Gigabit Ethernet" },
 192         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
 193                 "Broadcom BCM5751M Gigabit Ethernet" },
 194         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
 195                 "Broadcom BCM5752 Gigabit Ethernet" },
 196         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
 197                 "Broadcom BCM5752M Gigabit Ethernet" },
 198         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
 199                 "Broadcom BCM5753 Gigabit Ethernet" },
 200         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
 201                 "Broadcom BCM5753F Gigabit Ethernet" },
 202         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
 203                 "Broadcom BCM5753M Gigabit Ethernet" },
 204         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
 205                 "Broadcom BCM5754 Gigabit Ethernet" },
 206         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
 207                 "Broadcom BCM5754M Gigabit Ethernet" },
 208         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
 209                 "Broadcom BCM5755 Gigabit Ethernet" },
 210         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
 211                 "Broadcom BCM5755M Gigabit Ethernet" },
 212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
 213                 "Broadcom BCM5756 Gigabit Ethernet" },
 214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
 215                 "Broadcom BCM5780 Gigabit Ethernet" },
 216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
 217                 "Broadcom BCM5780S Gigabit Ethernet" },
 218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
 219                 "Broadcom BCM5781 Gigabit Ethernet" },
 220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 221                 "Broadcom BCM5782 Gigabit Ethernet" },
 222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
 223                 "Broadcom BCM5786 Gigabit Ethernet" },
 224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
 225                 "Broadcom BCM5787 Gigabit Ethernet" },
 226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
 227                 "Broadcom BCM5787F Gigabit Ethernet" },
 228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
 229                 "Broadcom BCM5787M Gigabit Ethernet" },
 230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
 231                 "Broadcom BCM5788 Gigabit Ethernet" },
 232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
 233                 "Broadcom BCM5789 Gigabit Ethernet" },
 234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 235                 "Broadcom BCM5901 Fast Ethernet" },
 236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 237                 "Broadcom BCM5901A2 Fast Ethernet" },
 238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
 239                 "Broadcom BCM5903M Fast Ethernet" },
 240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
 241                 "Broadcom BCM5906 Fast Ethernet"},
 242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
 243                 "Broadcom BCM5906M Fast Ethernet"},
 244
 245         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 246                 "SysKonnect Gigabit Ethernet" },
 247
 248         { 0, 0, NULL }
 249 };
 250
 251 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 252 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 253 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 254 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 255 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 256
 257 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 258
 259 static int      bge_probe(device_t);
 260 static int      bge_attach(device_t);
 261 static int      bge_detach(device_t);
 262 static void     bge_txeof(struct bge_softc *);
 263 static void     bge_rxeof(struct bge_softc *);
 264
 265 static void     bge_tick(void *);
 266 static void     bge_stats_update(struct bge_softc *);
 267 static void     bge_stats_update_regs(struct bge_softc *);
 268 static int      bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 269
 270 #ifdef DEVICE_POLLING
 271 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 272 #endif
 273 static void     bge_intr(void *);
 274 static void     bge_enable_intr(struct bge_softc *);
 275 static void     bge_disable_intr(struct bge_softc *);
 276 static void     bge_start(struct ifnet *);
 277 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 278 static void     bge_init(void *);
 279 static void     bge_stop(struct bge_softc *);
 280 static void     bge_watchdog(struct ifnet *);
 281 static void     bge_shutdown(device_t);
 282 static int      bge_suspend(device_t);
 283 static int      bge_resume(device_t);
 284 static int      bge_ifmedia_upd(struct ifnet *);
 285 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 286
 287 static uint8_t  bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 288 static int      bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 289
 290 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 291 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 292
 293 static void     bge_setmulti(struct bge_softc *);
 294 static void     bge_setpromisc(struct bge_softc *);
 295
 296 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 297 static void     bge_free_jumbo_mem(struct bge_softc *);
 298 static struct bge_jslot
 299                 *bge_jalloc(struct bge_softc *);
 300 static void     bge_jfree(void *);
 301 static void     bge_jref(void *);
 302 static int      bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
 303 static int      bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
 304 static int      bge_init_rx_ring_std(struct bge_softc *);
 305 static void     bge_free_rx_ring_std(struct bge_softc *);
 306 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 307 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 308 static void     bge_free_tx_ring(struct bge_softc *);
 309 static int      bge_init_tx_ring(struct bge_softc *);
 310
 311 static int      bge_chipinit(struct bge_softc *);
 312 static int      bge_blockinit(struct bge_softc *);
 313
 314 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 315 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 316 #ifdef notdef
 317 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 318 #endif
 319 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 320 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
 321 static void     bge_writembx(struct bge_softc *, int, int);
 322
 323 static int      bge_miibus_readreg(device_t, int, int);
 324 static int      bge_miibus_writereg(device_t, int, int, int);
 325 static void     bge_miibus_statchg(device_t);
 326 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
 327 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
 328 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
 329
 330 static void     bge_reset(struct bge_softc *);
 331
 332 static void     bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 333 static void     bge_dma_map_mbuf(void *, bus_dma_segment_t *, int,
 334                                  bus_size_t, int);
 335 static int      bge_dma_alloc(struct bge_softc *);
 336 static void     bge_dma_free(struct bge_softc *);
 337 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
 338                                     bus_dma_tag_t *, bus_dmamap_t *,
 339                                     void **, bus_addr_t *);
 340 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 341
 342 static int      bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 343 static int      bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 344 static int      bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 345 static int      bge_get_eaddr(struct bge_softc *, uint8_t[]);
 346
 347 static void     bge_coal_change(struct bge_softc *);
 348 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 349 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 350 static int      bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 351 static int      bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 352 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
 353
 354 /*
 355  * Set following tunable to 1 for some IBM blade servers with the DNLK
 356  * switch module. Auto negotiation is broken for those configurations.
 357  */
 358 static int      bge_fake_autoneg = 0;
 359 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
 360
 361 /* Interrupt moderation control variables. */
 362 static int      bge_rx_coal_ticks = 100;        /* usec */
 363 static int      bge_tx_coal_ticks = 1023;       /* usec */
 364 static int      bge_rx_max_coal_bds = 80;
 365 static int      bge_tx_max_coal_bds = 128;
 366
 367 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
 368 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
 369 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
 370 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
 371
 372 #if !defined(KTR_IF_BGE)
 373 #define KTR_IF_BGE      KTR_ALL
 374 #endif
 375 KTR_INFO_MASTER(if_bge);
 376 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr", 0);
 377 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt", 0);
 378 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt", 0);
 379 #define logif(name)     KTR_LOG(if_bge_ ## name)
 380
 381 static device_method_t bge_methods[] = {
 382         /* Device interface */
 383         DEVMETHOD(device_probe,         bge_probe),
 384         DEVMETHOD(device_attach,        bge_attach),
 385         DEVMETHOD(device_detach,        bge_detach),
 386         DEVMETHOD(device_shutdown,      bge_shutdown),
 387         DEVMETHOD(device_suspend,       bge_suspend),
 388         DEVMETHOD(device_resume,        bge_resume),
 389
 390         /* bus interface */
 391         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 392         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 393
 394         /* MII interface */
 395         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 396         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 397         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 398
 399         { 0, 0 }
 400 };
 401
 402 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 403 static devclass_t bge_devclass;
 404
 405 DECLARE_DUMMY_MODULE(if_bge);
 406 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
 407 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 408
 409 static uint32_t
 410 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 411 {
 412         device_t dev = sc->bge_dev;
 413         uint32_t val;
 414
 415         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 416         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 417         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 418         return (val);
 419 }
 420
 421 static void
 422 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 423 {
 424         device_t dev = sc->bge_dev;
 425
 426         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 427         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 428         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 429 }
 430
 431 #ifdef notdef
 432 static uint32_t
 433 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 434 {
 435         device_t dev = sc->bge_dev;
 436
 437         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 438         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 439 }
 440 #endif
 441
 442 static void
 443 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 444 {
 445         device_t dev = sc->bge_dev;
 446
 447         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 448         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 449 }
 450
 451 static void
 452 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
 453 {
 454         CSR_WRITE_4(sc, off, val);
 455 }
 456
 457 static void
 458 bge_writembx(struct bge_softc *sc, int off, int val)
 459 {
 460         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 461                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 462
 463         CSR_WRITE_4(sc, off, val);
 464 }
 465
 466 static uint8_t
 467 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 468 {
 469         uint32_t access, byte = 0;
 470         int i;
 471
 472         /* Lock. */
 473         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 474         for (i = 0; i < 8000; i++) {
 475                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 476                         break;
 477                 DELAY(20);
 478         }
 479         if (i == 8000)
 480                 return (1);
 481
 482         /* Enable access. */
 483         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 484         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 485
 486         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 487         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 488         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 489                 DELAY(10);
 490                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 491                         DELAY(10);
 492                         break;
 493                 }
 494         }
 495
 496         if (i == BGE_TIMEOUT * 10) {
 497                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
 498                 return (1);
 499         }
 500
 501         /* Get result. */
 502         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 503
 504         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 505
 506         /* Disable access. */
 507         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 508
 509         /* Unlock. */
 510         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 511         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 512
 513         return (0);
 514 }
 515
 516 /*
 517  * Read a sequence of bytes from NVRAM.
 518  */
 519 static int
 520 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 521 {
 522         int err = 0, i;
 523         uint8_t byte = 0;
 524
 525         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 526                 return (1);
 527
 528         for (i = 0; i < cnt; i++) {
 529                 err = bge_nvram_getbyte(sc, off + i, &byte);
 530                 if (err)
 531                         break;
 532                 *(dest + i) = byte;
 533         }
 534
 535         return (err ? 1 : 0);
 536 }
 537
 538 /*
 539  * Read a byte of data stored in the EEPROM at address 'addr.' The
 540  * BCM570x supports both the traditional bitbang interface and an
 541  * auto access interface for reading the EEPROM. We use the auto
 542  * access method.
 543  */
 544 static uint8_t
 545 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 546 {
 547         int i;
 548         uint32_t byte = 0;
 549
 550         /*
 551          * Enable use of auto EEPROM access so we can avoid
 552          * having to use the bitbang method.
 553          */
 554         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 555
 556         /* Reset the EEPROM, load the clock period. */
 557         CSR_WRITE_4(sc, BGE_EE_ADDR,
 558             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 559         DELAY(20);
 560
 561         /* Issue the read EEPROM command. */
 562         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 563
 564         /* Wait for completion */
 565         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 566                 DELAY(10);
 567                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 568                         break;
 569         }
 570
 571         if (i == BGE_TIMEOUT) {
 572                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 573                 return(1);
 574         }
 575
 576         /* Get result. */
 577         byte = CSR_READ_4(sc, BGE_EE_DATA);
 578
 579         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 580
 581         return(0);
 582 }
 583
 584 /*
 585  * Read a sequence of bytes from the EEPROM.
 586  */
 587 static int
 588 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 589 {
 590         size_t i;
 591         int err;
 592         uint8_t byte;
 593
 594         for (byte = 0, err = 0, i = 0; i < len; i++) {
 595                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 596                 if (err)
 597                         break;
 598                 *(dest + i) = byte;
 599         }
 600
 601         return(err ? 1 : 0);
 602 }
 603
 604 static int
 605 bge_miibus_readreg(device_t dev, int phy, int reg)
 606 {
 607         struct bge_softc *sc = device_get_softc(dev);
 608         struct ifnet *ifp = &sc->arpcom.ac_if;
 609         uint32_t val, autopoll;
 610         int i;
 611
 612         /*
 613          * Broadcom's own driver always assumes the internal
 614          * PHY is at GMII address 1. On some chips, the PHY responds
 615          * to accesses at all addresses, which could cause us to
 616          * bogusly attach the PHY 32 times at probe type. Always
 617          * restricting the lookup to address 1 is simpler than
 618          * trying to figure out which chips revisions should be
 619          * special-cased.
 620          */
 621         if (phy != 1)
 622                 return(0);
 623
 624         /* Reading with autopolling on may trigger PCI errors */
 625         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 626         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 627                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 628                 DELAY(40);
 629         }
 630
 631         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
 632             BGE_MIPHY(phy)|BGE_MIREG(reg));
 633
 634         for (i = 0; i < BGE_TIMEOUT; i++) {
 635                 DELAY(10);
 636                 val = CSR_READ_4(sc, BGE_MI_COMM);
 637                 if (!(val & BGE_MICOMM_BUSY))
 638                         break;
 639         }
 640
 641         if (i == BGE_TIMEOUT) {
 642                 if_printf(ifp, "PHY read timed out "
 643                           "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 644                 val = 0;
 645                 goto done;
 646         }
 647
 648         DELAY(5);
 649         val = CSR_READ_4(sc, BGE_MI_COMM);
 650
 651 done:
 652         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 653                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 654                 DELAY(40);
 655         }
 656
 657         if (val & BGE_MICOMM_READFAIL)
 658                 return(0);
 659
 660         return(val & 0xFFFF);
 661 }
 662
 663 static int
 664 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 665 {
 666         struct bge_softc *sc = device_get_softc(dev);
 667         uint32_t autopoll;
 668         int i;
 669
 670         /*
 671          * See the related comment in bge_miibus_readreg()
 672          */
 673         if (phy != 1)
 674                 return(0);
 675
 676         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 677             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 678                return(0);
 679
 680         /* Reading with autopolling on may trigger PCI errors */
 681         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 682         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 683                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 684                 DELAY(40);
 685         }
 686
 687         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
 688             BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
 689
 690         for (i = 0; i < BGE_TIMEOUT; i++) {
 691                 DELAY(10);
 692                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 693                         DELAY(5);
 694                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 695                         break;
 696                 }
 697         }
 698
 699         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 700                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 701                 DELAY(40);
 702         }
 703
 704         if (i == BGE_TIMEOUT) {
 705                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 706                           "(phy %d, reg %d, val %d)\n", phy, reg, val);
 707                 return(0);
 708         }
 709
 710         return(0);
 711 }
 712
 713 static void
 714 bge_miibus_statchg(device_t dev)
 715 {
 716         struct bge_softc *sc;
 717         struct mii_data *mii;
 718
 719         sc = device_get_softc(dev);
 720         mii = device_get_softc(sc->bge_miibus);
 721
 722         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 723         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
 724                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 725         } else {
 726                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 727         }
 728
 729         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 730                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 731         } else {
 732                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 733         }
 734 }
 735
 736 /*
 737  * Memory management for jumbo frames.
 738  */
 739 static int
 740 bge_alloc_jumbo_mem(struct bge_softc *sc)
 741 {
 742         struct ifnet *ifp = &sc->arpcom.ac_if;
 743         struct bge_jslot *entry;
 744         uint8_t *ptr;
 745         bus_addr_t paddr;
 746         int i, error;
 747
 748         /*
 749          * Create tag for jumbo mbufs.
 750          * This is really a bit of a kludge. We allocate a special
 751          * jumbo buffer pool which (thanks to the way our DMA
 752          * memory allocation works) will consist of contiguous
 753          * pages. This means that even though a jumbo buffer might
 754          * be larger than a page size, we don't really need to
 755          * map it into more than one DMA segment. However, the
 756          * default mbuf tag will result in multi-segment mappings,
 757          * so we have to create a special jumbo mbuf tag that
 758          * lets us get away with mapping the jumbo buffers as
 759          * a single segment. I think eventually the driver should
 760          * be changed so that it uses ordinary mbufs and cluster
 761          * buffers, i.e. jumbo frames can span multiple DMA
 762          * descriptors. But that's a project for another day.
 763          */
 764
 765         /*
 766          * Create DMA stuffs for jumbo RX ring.
 767          */
 768         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 769                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
 770                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
 771                                     (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
 772                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
 773         if (error) {
 774                 if_printf(ifp, "could not create jumbo RX ring\n");
 775                 return error;
 776         }
 777
 778         /*
 779          * Create DMA stuffs for jumbo buffer block.
 780          */
 781         error = bge_dma_block_alloc(sc, BGE_JMEM,
 782                                     &sc->bge_cdata.bge_jumbo_tag,
 783                                     &sc->bge_cdata.bge_jumbo_map,
 784                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
 785                                     &paddr);
 786         if (error) {
 787                 if_printf(ifp, "could not create jumbo buffer\n");
 788                 return error;
 789         }
 790
 791         SLIST_INIT(&sc->bge_jfree_listhead);
 792
 793         /*
 794          * Now divide it up into 9K pieces and save the addresses
 795          * in an array. Note that we play an evil trick here by using
 796          * the first few bytes in the buffer to hold the the address
 797          * of the softc structure for this interface. This is because
 798          * bge_jfree() needs it, but it is called by the mbuf management
 799          * code which will not pass it to us explicitly.
 800          */
 801         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
 802                 entry = &sc->bge_cdata.bge_jslots[i];
 803                 entry->bge_sc = sc;
 804                 entry->bge_buf = ptr;
 805                 entry->bge_paddr = paddr;
 806                 entry->bge_inuse = 0;
 807                 entry->bge_slot = i;
 808                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 809
 810                 ptr += BGE_JLEN;
 811                 paddr += BGE_JLEN;
 812         }
 813         return 0;
 814 }
 815
 816 static void
 817 bge_free_jumbo_mem(struct bge_softc *sc)
 818 {
 819         /* Destroy jumbo RX ring. */
 820         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 821                            sc->bge_cdata.bge_rx_jumbo_ring_map,
 822                            sc->bge_ldata.bge_rx_jumbo_ring);
 823
 824         /* Destroy jumbo buffer block. */
 825         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
 826                            sc->bge_cdata.bge_jumbo_map,
 827                            sc->bge_ldata.bge_jumbo_buf);
 828 }
 829
 830 /*
 831  * Allocate a jumbo buffer.
 832  */
 833 static struct bge_jslot *
 834 bge_jalloc(struct bge_softc *sc)
 835 {
 836         struct bge_jslot *entry;
 837
 838         lwkt_serialize_enter(&sc->bge_jslot_serializer);
 839         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 840         if (entry) {
 841                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 842                 entry->bge_inuse = 1;
 843         } else {
 844                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 845         }
 846         lwkt_serialize_exit(&sc->bge_jslot_serializer);
 847         return(entry);
 848 }
 849
 850 /*
 851  * Adjust usage count on a jumbo buffer.
 852  */
 853 static void
 854 bge_jref(void *arg)
 855 {
 856         struct bge_jslot *entry = (struct bge_jslot *)arg;
 857         struct bge_softc *sc = entry->bge_sc;
 858
 859         if (sc == NULL)
 860                 panic("bge_jref: can't find softc pointer!");
 861
 862         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 863                 panic("bge_jref: asked to reference buffer "
 864                     "that we don't manage!");
 865         } else if (entry->bge_inuse == 0) {
 866                 panic("bge_jref: buffer already free!");
 867         } else {
 868                 atomic_add_int(&entry->bge_inuse, 1);
 869         }
 870 }
 871
 872 /*
 873  * Release a jumbo buffer.
 874  */
 875 static void
 876 bge_jfree(void *arg)
 877 {
 878         struct bge_jslot *entry = (struct bge_jslot *)arg;
 879         struct bge_softc *sc = entry->bge_sc;
 880
 881         if (sc == NULL)
 882                 panic("bge_jfree: can't find softc pointer!");
 883
 884         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 885                 panic("bge_jfree: asked to free buffer that we don't manage!");
 886         } else if (entry->bge_inuse == 0) {
 887                 panic("bge_jfree: buffer already free!");
 888         } else {
 889                 /*
 890                  * Possible MP race to 0, use the serializer.  The atomic insn
 891                  * is still needed for races against bge_jref().
 892                  */
 893                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
 894                 atomic_subtract_int(&entry->bge_inuse, 1);
 895                 if (entry->bge_inuse == 0) {
 896                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
 897                                           entry, jslot_link);
 898                 }
 899                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
 900         }
 901 }
 902
 903
 904 /*
 905  * Intialize a standard receive ring descriptor.
 906  */
 907 static int
 908 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
 909 {
 910         struct mbuf *m_new = NULL;
 911         struct bge_dmamap_arg ctx;
 912         bus_dma_segment_t seg;
 913         struct bge_rx_bd *r;
 914         int error;
 915
 916         if (m == NULL) {
 917                 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
 918                 if (m_new == NULL)
 919                         return ENOBUFS;
 920         } else {
 921                 m_new = m;
 922                 m_new->m_data = m_new->m_ext.ext_buf;
 923         }
 924         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 925
 926         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 927                 m_adj(m_new, ETHER_ALIGN);
 928
 929         ctx.bge_maxsegs = 1;
 930         ctx.bge_segs = &seg;
 931         error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag,
 932                                      sc->bge_cdata.bge_rx_std_dmamap[i],
 933                                      m_new, bge_dma_map_mbuf, &ctx,
 934                                      BUS_DMA_NOWAIT);
 935         if (error || ctx.bge_maxsegs == 0) {
 936                 if (!error) {
 937                         if_printf(&sc->arpcom.ac_if, "too many segments?!\n");
 938                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
 939                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
 940                 }
 941                 if (m == NULL)
 942                         m_freem(m_new);
 943                 return ENOMEM;
 944         }
 945
 946         sc->bge_cdata.bge_rx_std_chain[i] = m_new;
 947
 948         r = &sc->bge_ldata.bge_rx_std_ring[i];
 949         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[0].ds_addr);
 950         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[0].ds_addr);
 951         r->bge_flags = BGE_RXBDFLAG_END;
 952         r->bge_len = m_new->m_len;
 953         r->bge_idx = i;
 954
 955         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
 956                         sc->bge_cdata.bge_rx_std_dmamap[i],
 957                         BUS_DMASYNC_PREREAD);
 958         return 0;
 959 }
 960
 961 /*
 962  * Initialize a jumbo receive ring descriptor. This allocates
 963  * a jumbo buffer from the pool managed internally by the driver.
 964  */
 965 static int
 966 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
 967 {
 968         struct mbuf *m_new = NULL;
 969         struct bge_jslot *buf;
 970         struct bge_rx_bd *r;
 971         bus_addr_t paddr;
 972
 973         if (m == NULL) {
 974                 /* Allocate the mbuf. */
 975                 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
 976                 if (m_new == NULL)
 977                         return(ENOBUFS);
 978
 979                 /* Allocate the jumbo buffer */
 980                 buf = bge_jalloc(sc);
 981                 if (buf == NULL) {
 982                         m_freem(m_new);
 983                         if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
 984                             "-- packet dropped!\n");
 985                         return ENOBUFS;
 986                 }
 987
 988                 /* Attach the buffer to the mbuf. */
 989                 m_new->m_ext.ext_arg = buf;
 990                 m_new->m_ext.ext_buf = buf->bge_buf;
 991                 m_new->m_ext.ext_free = bge_jfree;
 992                 m_new->m_ext.ext_ref = bge_jref;
 993                 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 994
 995                 m_new->m_flags |= M_EXT;
 996         } else {
 997                 KKASSERT(m->m_flags & M_EXT);
 998                 m_new = m;
 999                 buf = m_new->m_ext.ext_arg;
1000         }
1001         m_new->m_data = m_new->m_ext.ext_buf;
1002         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1003
1004         paddr = buf->bge_paddr;
1005         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1006                 m_adj(m_new, ETHER_ALIGN);
1007                 paddr += ETHER_ALIGN;
1008         }
1009
1010         /* Set up the descriptor. */
1011         sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
1012
1013         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1014         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(paddr);
1015         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(paddr);
1016         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1017         r->bge_len = m_new->m_len;
1018         r->bge_idx = i;
1019
1020         return 0;
1021 }
1022
1023 /*
1024  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1025  * that's 1MB or memory, which is a lot. For now, we fill only the first
1026  * 256 ring entries and hope that our CPU is fast enough to keep up with
1027  * the NIC.
1028  */
1029 static int
1030 bge_init_rx_ring_std(struct bge_softc *sc)
1031 {
1032         int i;
1033
1034         for (i = 0; i < BGE_SSLOTS; i++) {
1035                 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
1036                         return(ENOBUFS);
1037         };
1038
1039         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1040                         sc->bge_cdata.bge_rx_std_ring_map,
1041                         BUS_DMASYNC_PREWRITE);
1042
1043         sc->bge_std = i - 1;
1044         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1045
1046         return(0);
1047 }
1048
1049 static void
1050 bge_free_rx_ring_std(struct bge_softc *sc)
1051 {
1052         int i;
1053
1054         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1055                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1056                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1057                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
1058                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1059                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1060                 }
1061                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1062                     sizeof(struct bge_rx_bd));
1063         }
1064 }
1065
1066 static int
1067 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1068 {
1069         int i;
1070         struct bge_rcb *rcb;
1071
1072         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1073                 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1074                         return(ENOBUFS);
1075         };
1076
1077         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1078                         sc->bge_cdata.bge_rx_jumbo_ring_map,
1079                         BUS_DMASYNC_PREWRITE);
1080
1081         sc->bge_jumbo = i - 1;
1082
1083         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1084         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1085         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1086
1087         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1088
1089         return(0);
1090 }
1091
1092 static void
1093 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1094 {
1095         int i;
1096
1097         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1098                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1099                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1100                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1101                 }
1102                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1103                     sizeof(struct bge_rx_bd));
1104         }
1105 }
1106
1107 static void
1108 bge_free_tx_ring(struct bge_softc *sc)
1109 {
1110         int i;
1111
1112         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1113                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1114                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1115                                           sc->bge_cdata.bge_tx_dmamap[i]);
1116                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1117                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1118                 }
1119                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1120                     sizeof(struct bge_tx_bd));
1121         }
1122 }
1123
1124 static int
1125 bge_init_tx_ring(struct bge_softc *sc)
1126 {
1127         sc->bge_txcnt = 0;
1128         sc->bge_tx_saved_considx = 0;
1129         sc->bge_tx_prodidx = 0;
1130
1131         /* Initialize transmit producer index for host-memory send ring. */
1132         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1133
1134         /* 5700 b2 errata */
1135         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1136                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1137
1138         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1139         /* 5700 b2 errata */
1140         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1141                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1142
1143         return(0);
1144 }
1145
1146 static void
1147 bge_setmulti(struct bge_softc *sc)
1148 {
1149         struct ifnet *ifp;
1150         struct ifmultiaddr *ifma;
1151         uint32_t hashes[4] = { 0, 0, 0, 0 };
1152         int h, i;
1153
1154         ifp = &sc->arpcom.ac_if;
1155
1156         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1157                 for (i = 0; i < 4; i++)
1158                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1159                 return;
1160         }
1161
1162         /* First, zot all the existing filters. */
1163         for (i = 0; i < 4; i++)
1164                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1165
1166         /* Now program new ones. */
1167         LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1168                 if (ifma->ifma_addr->sa_family != AF_LINK)
1169                         continue;
1170                 h = ether_crc32_le(
1171                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1172                     ETHER_ADDR_LEN) & 0x7f;
1173                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1174         }
1175
1176         for (i = 0; i < 4; i++)
1177                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1178 }
1179
1180 /*
1181  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1182  * self-test results.
1183  */
1184 static int
1185 bge_chipinit(struct bge_softc *sc)
1186 {
1187         int i;
1188         uint32_t dma_rw_ctl;
1189
1190         /* Set endian type before we access any non-PCI registers. */
1191         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1192
1193         /*
1194          * Check the 'ROM failed' bit on the RX CPU to see if
1195          * self-tests passed.
1196          */
1197         if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1198                 if_printf(&sc->arpcom.ac_if,
1199                           "RX CPU self-diagnostics failed!\n");
1200                 return(ENODEV);
1201         }
1202
1203         /* Clear the MAC control register */
1204         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1205
1206         /*
1207          * Clear the MAC statistics block in the NIC's
1208          * internal memory.
1209          */
1210         for (i = BGE_STATS_BLOCK;
1211             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1212                 BGE_MEMWIN_WRITE(sc, i, 0);
1213
1214         for (i = BGE_STATUS_BLOCK;
1215             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1216                 BGE_MEMWIN_WRITE(sc, i, 0);
1217
1218         /* Set up the PCI DMA control register. */
1219         if (sc->bge_flags & BGE_FLAG_PCIE) {
1220                 /* PCI Express */
1221                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1222                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1223                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1224         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1225                 /* PCI-X bus */
1226                 if (BGE_IS_5714_FAMILY(sc)) {
1227                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1228                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1229                         /* XXX magic values, Broadcom-supplied Linux driver */
1230                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1231                                 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1232                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1233                         } else {
1234                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1235                         }
1236                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1237                         /*
1238                          * The 5704 uses a different encoding of read/write
1239                          * watermarks.
1240                          */
1241                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1242                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1243                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1244                 } else {
1245                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1246                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1247                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1248                             (0x0F);
1249                 }
1250
1251                 /*
1252                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1253                  * for hardware bugs.
1254                  */
1255                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1256                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1257                         uint32_t tmp;
1258
1259                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1260                         if (tmp == 0x6 || tmp == 0x7)
1261                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1262                 }
1263         } else {
1264                 /* Conventional PCI bus */
1265                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1266                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1267                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1268                     (0x0F);
1269         }
1270
1271         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1272             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1273             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1274                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1275         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1276
1277         /*
1278          * Set up general mode register.
1279          */
1280         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1281             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1282             BGE_MODECTL_TX_NO_PHDR_CSUM);
1283
1284         /*
1285          * Disable memory write invalidate.  Apparently it is not supported
1286          * properly by these devices.
1287          */
1288         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1289
1290         /* Set the timer prescaler (always 66Mhz) */
1291         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1292
1293         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1294                 DELAY(40);      /* XXX */
1295
1296                 /* Put PHY into ready state */
1297                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1298                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1299                 DELAY(40);
1300         }
1301
1302         return(0);
1303 }
1304
1305 static int
1306 bge_blockinit(struct bge_softc *sc)
1307 {
1308         struct bge_rcb *rcb;
1309         bus_size_t vrcb;
1310         bge_hostaddr taddr;
1311         uint32_t val;
1312         int i;
1313
1314         /*
1315          * Initialize the memory window pointer register so that
1316          * we can access the first 32K of internal NIC RAM. This will
1317          * allow us to set up the TX send ring RCBs and the RX return
1318          * ring RCBs, plus other things which live in NIC memory.
1319          */
1320         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1321
1322         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1323
1324         if (!BGE_IS_5705_PLUS(sc)) {
1325                 /* Configure mbuf memory pool */
1326                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1327                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1328                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1329                 else
1330                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1331
1332                 /* Configure DMA resource pool */
1333                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1334                     BGE_DMA_DESCRIPTORS);
1335                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1336         }
1337
1338         /* Configure mbuf pool watermarks */
1339         if (!BGE_IS_5705_PLUS(sc)) {
1340                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1341                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1342                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1343         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1344                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1345                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1346                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1347         } else {
1348                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1349                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1350                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1351         }
1352
1353         /* Configure DMA resource watermarks */
1354         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1355         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1356
1357         /* Enable buffer manager */
1358         if (!BGE_IS_5705_PLUS(sc)) {
1359                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1360                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1361
1362                 /* Poll for buffer manager start indication */
1363                 for (i = 0; i < BGE_TIMEOUT; i++) {
1364                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1365                                 break;
1366                         DELAY(10);
1367                 }
1368
1369                 if (i == BGE_TIMEOUT) {
1370                         if_printf(&sc->arpcom.ac_if,
1371                                   "buffer manager failed to start\n");
1372                         return(ENXIO);
1373                 }
1374         }
1375
1376         /* Enable flow-through queues */
1377         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1378         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1379
1380         /* Wait until queue initialization is complete */
1381         for (i = 0; i < BGE_TIMEOUT; i++) {
1382                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1383                         break;
1384                 DELAY(10);
1385         }
1386
1387         if (i == BGE_TIMEOUT) {
1388                 if_printf(&sc->arpcom.ac_if,
1389                           "flow-through queue init failed\n");
1390                 return(ENXIO);
1391         }
1392
1393         /* Initialize the standard RX ring control block */
1394         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1395         rcb->bge_hostaddr.bge_addr_lo =
1396             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1397         rcb->bge_hostaddr.bge_addr_hi =
1398             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1399         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1400             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1401         if (BGE_IS_5705_PLUS(sc))
1402                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1403         else
1404                 rcb->bge_maxlen_flags =
1405                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1406         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1407         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1408         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1409         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1410         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1411
1412         /*
1413          * Initialize the jumbo RX ring control block
1414          * We set the 'ring disabled' bit in the flags
1415          * field until we're actually ready to start
1416          * using this ring (i.e. once we set the MTU
1417          * high enough to require it).
1418          */
1419         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1420                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1421
1422                 rcb->bge_hostaddr.bge_addr_lo =
1423                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1424                 rcb->bge_hostaddr.bge_addr_hi =
1425                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1426                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1427                     sc->bge_cdata.bge_rx_jumbo_ring_map,
1428                     BUS_DMASYNC_PREREAD);
1429                 rcb->bge_maxlen_flags =
1430                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1431                     BGE_RCB_FLAG_RING_DISABLED);
1432                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1433                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1434                     rcb->bge_hostaddr.bge_addr_hi);
1435                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1436                     rcb->bge_hostaddr.bge_addr_lo);
1437                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1438                     rcb->bge_maxlen_flags);
1439                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1440
1441                 /* Set up dummy disabled mini ring RCB */
1442                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1443                 rcb->bge_maxlen_flags =
1444                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1445                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1446                     rcb->bge_maxlen_flags);
1447         }
1448
1449         /*
1450          * Set the BD ring replentish thresholds. The recommended
1451          * values are 1/8th the number of descriptors allocated to
1452          * each ring.
1453          */
1454         if (BGE_IS_5705_PLUS(sc))
1455                 val = 8;
1456         else
1457                 val = BGE_STD_RX_RING_CNT / 8;
1458         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1459         CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1460
1461         /*
1462          * Disable all unused send rings by setting the 'ring disabled'
1463          * bit in the flags field of all the TX send ring control blocks.
1464          * These are located in NIC memory.
1465          */
1466         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1467         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1468                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1469                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1470                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1471                 vrcb += sizeof(struct bge_rcb);
1472         }
1473
1474         /* Configure TX RCB 0 (we use only the first ring) */
1475         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1476         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1477         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1478         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1479         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1480             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1481         if (!BGE_IS_5705_PLUS(sc)) {
1482                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1483                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1484         }
1485
1486         /* Disable all unused RX return rings */
1487         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1488         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1489                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1490                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1491                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1492                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1493                     BGE_RCB_FLAG_RING_DISABLED));
1494                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1495                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1496                     (i * (sizeof(uint64_t))), 0);
1497                 vrcb += sizeof(struct bge_rcb);
1498         }
1499
1500         /* Initialize RX ring indexes */
1501         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1502         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1503         bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1504
1505         /*
1506          * Set up RX return ring 0
1507          * Note that the NIC address for RX return rings is 0x00000000.
1508          * The return rings live entirely within the host, so the
1509          * nicaddr field in the RCB isn't used.
1510          */
1511         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1512         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1513         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1514         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1515         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1516         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1517             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1518
1519         /* Set random backoff seed for TX */
1520         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1521             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1522             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1523             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1524             BGE_TX_BACKOFF_SEED_MASK);
1525
1526         /* Set inter-packet gap */
1527         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1528
1529         /*
1530          * Specify which ring to use for packets that don't match
1531          * any RX rules.
1532          */
1533         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1534
1535         /*
1536          * Configure number of RX lists. One interrupt distribution
1537          * list, sixteen active lists, one bad frames class.
1538          */
1539         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1540
1541         /* Inialize RX list placement stats mask. */
1542         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1543         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1544
1545         /* Disable host coalescing until we get it set up */
1546         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1547
1548         /* Poll to make sure it's shut down. */
1549         for (i = 0; i < BGE_TIMEOUT; i++) {
1550                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1551                         break;
1552                 DELAY(10);
1553         }
1554
1555         if (i == BGE_TIMEOUT) {
1556                 if_printf(&sc->arpcom.ac_if,
1557                           "host coalescing engine failed to idle\n");
1558                 return(ENXIO);
1559         }
1560
1561         /* Set up host coalescing defaults */
1562         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1563         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1564         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1565         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1566         if (!BGE_IS_5705_PLUS(sc)) {
1567                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1568                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1569         }
1570         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1571         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1572
1573         /* Set up address of statistics block */
1574         if (!BGE_IS_5705_PLUS(sc)) {
1575                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1576                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1577                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1578                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1579
1580                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1581                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1582                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1583         }
1584
1585         /* Set up address of status block */
1586         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1587             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1588         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1589             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1590         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1591         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1592
1593         /* Turn on host coalescing state machine */
1594         CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1595
1596         /* Turn on RX BD completion state machine and enable attentions */
1597         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1598             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1599
1600         /* Turn on RX list placement state machine */
1601         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1602
1603         /* Turn on RX list selector state machine. */
1604         if (!BGE_IS_5705_PLUS(sc))
1605                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1606
1607         /* Turn on DMA, clear stats */
1608         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1609             BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1610             BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1611             BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1612             ((sc->bge_flags & BGE_FLAG_TBI) ?
1613              BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1614
1615         /* Set misc. local control, enable interrupts on attentions */
1616         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1617
1618 #ifdef notdef
1619         /* Assert GPIO pins for PHY reset */
1620         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1621             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1622         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1623             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1624 #endif
1625
1626         /* Turn on DMA completion state machine */
1627         if (!BGE_IS_5705_PLUS(sc))
1628                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1629
1630         /* Turn on write DMA state machine */
1631         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1632         if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1633             sc->bge_asicrev == BGE_ASICREV_BCM5787)
1634                 val |= (1 << 29);       /* Enable host coalescing bug fix. */
1635         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1636         DELAY(40);
1637
1638         /* Turn on read DMA state machine */
1639         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1640         if (sc->bge_flags & BGE_FLAG_PCIE)
1641                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1642         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1643         DELAY(40);
1644
1645         /* Turn on RX data completion state machine */
1646         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1647
1648         /* Turn on RX BD initiator state machine */
1649         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1650
1651         /* Turn on RX data and RX BD initiator state machine */
1652         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1653
1654         /* Turn on Mbuf cluster free state machine */
1655         if (!BGE_IS_5705_PLUS(sc))
1656                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1657
1658         /* Turn on send BD completion state machine */
1659         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1660
1661         /* Turn on send data completion state machine */
1662         CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1663
1664         /* Turn on send data initiator state machine */
1665         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1666
1667         /* Turn on send BD initiator state machine */
1668         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1669
1670         /* Turn on send BD selector state machine */
1671         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1672
1673         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1674         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1675             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1676
1677         /* ack/clear link change events */
1678         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1679             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1680             BGE_MACSTAT_LINK_CHANGED);
1681         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1682
1683         /* Enable PHY auto polling (for MII/GMII only) */
1684         if (sc->bge_flags & BGE_FLAG_TBI) {
1685                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1686         } else {
1687                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1688                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1689                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1690                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1691                             BGE_EVTENB_MI_INTERRUPT);
1692                 }
1693         }
1694
1695         /*
1696          * Clear any pending link state attention.
1697          * Otherwise some link state change events may be lost until attention
1698          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1699          * It's not necessary on newer BCM chips - perhaps enabling link
1700          * state change attentions implies clearing pending attention.
1701          */
1702         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1703             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1704             BGE_MACSTAT_LINK_CHANGED);
1705
1706         /* Enable link state change attentions. */
1707         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1708
1709         return(0);
1710 }
1711
1712 /*
1713  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1714  * against our list and return its name if we find a match. Note
1715  * that since the Broadcom controller contains VPD support, we
1716  * can get the device name string from the controller itself instead
1717  * of the compiled-in string. This is a little slow, but it guarantees
1718  * we'll always announce the right product name.
1719  */
1720 static int
1721 bge_probe(device_t dev)
1722 {
1723         const struct bge_type *t;
1724         uint16_t product, vendor;
1725
1726         product = pci_get_device(dev);
1727         vendor = pci_get_vendor(dev);
1728
1729         for (t = bge_devs; t->bge_name != NULL; t++) {
1730                 if (vendor == t->bge_vid && product == t->bge_did)
1731                         break;
1732         }
1733         if (t->bge_name == NULL)
1734                 return(ENXIO);
1735
1736         device_set_desc(dev, t->bge_name);
1737         if (pci_get_subvendor(dev) == PCI_VENDOR_DELL) {
1738                 struct bge_softc *sc = device_get_softc(dev);
1739                 sc->bge_flags |= BGE_FLAG_NO_3LED;
1740         }
1741         return(0);
1742 }
1743
1744 static int
1745 bge_attach(device_t dev)
1746 {
1747         struct ifnet *ifp;
1748         struct bge_softc *sc;
1749         uint32_t hwcfg = 0;
1750         int error = 0, rid;
1751         uint8_t ether_addr[ETHER_ADDR_LEN];
1752
1753         sc = device_get_softc(dev);
1754         sc->bge_dev = dev;
1755         callout_init(&sc->bge_stat_timer);
1756         lwkt_serialize_init(&sc->bge_jslot_serializer);
1757
1758 #ifndef BURN_BRIDGES
1759         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1760                 uint32_t irq, mem;
1761
1762                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1763                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1764
1765                 device_printf(dev, "chip is in D%d power mode "
1766                     "-- setting to D0\n", pci_get_powerstate(dev));
1767
1768                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1769
1770                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1771                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1772         }
1773 #endif  /* !BURN_BRIDGE */
1774
1775         /*
1776          * Map control/status registers.
1777          */
1778         pci_enable_busmaster(dev);
1779
1780         rid = BGE_PCI_BAR0;
1781         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1782             RF_ACTIVE);
1783
1784         if (sc->bge_res == NULL) {
1785                 device_printf(dev, "couldn't map memory\n");
1786                 return ENXIO;
1787         }
1788
1789         sc->bge_btag = rman_get_bustag(sc->bge_res);
1790         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1791
1792         /* Save various chip information */
1793         sc->bge_chipid =
1794             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1795             BGE_PCIMISCCTL_ASICREV;
1796         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1797         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1798
1799         /* Save chipset family. */
1800         switch (sc->bge_asicrev) {
1801         case BGE_ASICREV_BCM5700:
1802         case BGE_ASICREV_BCM5701:
1803         case BGE_ASICREV_BCM5703:
1804         case BGE_ASICREV_BCM5704:
1805                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1806                 break;
1807
1808         case BGE_ASICREV_BCM5714_A0:
1809         case BGE_ASICREV_BCM5780:
1810         case BGE_ASICREV_BCM5714:
1811                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1812                 /* Fall through */
1813
1814         case BGE_ASICREV_BCM5750:
1815         case BGE_ASICREV_BCM5752:
1816         case BGE_ASICREV_BCM5755:
1817         case BGE_ASICREV_BCM5787:
1818         case BGE_ASICREV_BCM5906:
1819                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1820                 /* Fall through */
1821
1822         case BGE_ASICREV_BCM5705:
1823                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1824                 break;
1825         }
1826
1827         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
1828                 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
1829
1830         /*
1831          * Set various quirk flags.
1832          */
1833
1834         sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1835         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1836             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1837              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1838               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1839             sc->bge_asicrev == BGE_ASICREV_BCM5906)
1840                 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1841
1842         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1843             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1844                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1845
1846         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1847             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1848                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1849
1850         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1851                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1852
1853         if (BGE_IS_5705_PLUS(sc)) {
1854                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1855                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1856                         uint32_t product = pci_get_device(dev);
1857
1858                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
1859                             product != PCI_PRODUCT_BROADCOM_BCM5756)
1860                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1861                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1862                                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1863                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1864                         sc->bge_flags |= BGE_FLAG_BER_BUG;
1865                 }
1866         }
1867
1868         /* Allocate interrupt */
1869         rid = 0;
1870
1871         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1872             RF_SHAREABLE | RF_ACTIVE);
1873
1874         if (sc->bge_irq == NULL) {
1875                 device_printf(dev, "couldn't map interrupt\n");
1876                 error = ENXIO;
1877                 goto fail;
1878         }
1879
1880         /*
1881          * Check if this is a PCI-X or PCI Express device.
1882          */
1883         if (BGE_IS_5705_PLUS(sc)) {
1884                 if (pci_get_pciecap_ptr(dev) != 0) {
1885                         sc->bge_flags |= BGE_FLAG_PCIE;
1886                         pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1887                 }
1888         } else {
1889                 /*
1890                  * Check if the device is in PCI-X Mode.
1891                  * (This bit is not valid on PCI Express controllers.)
1892                  */
1893                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1894                     BGE_PCISTATE_PCI_BUSMODE) == 0)
1895                         sc->bge_flags |= BGE_FLAG_PCIX;
1896         }
1897
1898         device_printf(dev, "CHIP ID 0x%08x; "
1899                       "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
1900                       sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
1901                       (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
1902                       : ((sc->bge_flags & BGE_FLAG_PCIE) ?
1903                         "PCI-E" : "PCI"));
1904
1905         ifp = &sc->arpcom.ac_if;
1906         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1907
1908         /* Try to reset the chip. */
1909         bge_reset(sc);
1910
1911         if (bge_chipinit(sc)) {
1912                 device_printf(dev, "chip initialization failed\n");
1913                 error = ENXIO;
1914                 goto fail;
1915         }
1916
1917         /*
1918          * Get station address
1919          */
1920         error = bge_get_eaddr(sc, ether_addr);
1921         if (error) {
1922                 device_printf(dev, "failed to read station address\n");
1923                 goto fail;
1924         }
1925
1926         /* 5705/5750 limits RX return ring to 512 entries. */
1927         if (BGE_IS_5705_PLUS(sc))
1928                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1929         else
1930                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1931
1932         error = bge_dma_alloc(sc);
1933         if (error)
1934                 goto fail;
1935
1936         /* Set default tuneable values. */
1937         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1938         sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
1939         sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
1940         sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
1941         sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
1942
1943         /* Set up ifnet structure */
1944         ifp->if_softc = sc;
1945         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1946         ifp->if_ioctl = bge_ioctl;
1947         ifp->if_start = bge_start;
1948 #ifdef DEVICE_POLLING
1949         ifp->if_poll = bge_poll;
1950 #endif
1951         ifp->if_watchdog = bge_watchdog;
1952         ifp->if_init = bge_init;
1953         ifp->if_mtu = ETHERMTU;
1954         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1955         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1956         ifq_set_ready(&ifp->if_snd);
1957
1958         /*
1959          * 5700 B0 chips do not support checksumming correctly due
1960          * to hardware bugs.
1961          */
1962         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
1963                 ifp->if_capabilities |= IFCAP_HWCSUM;
1964                 ifp->if_hwassist = BGE_CSUM_FEATURES;
1965         }
1966         ifp->if_capenable = ifp->if_capabilities;
1967
1968         /*
1969          * Figure out what sort of media we have by checking the
1970          * hardware config word in the first 32k of NIC internal memory,
1971          * or fall back to examining the EEPROM if necessary.
1972          * Note: on some BCM5700 cards, this value appears to be unset.
1973          * If that's the case, we have to rely on identifying the NIC
1974          * by its PCI subsystem ID, as we do below for the SysKonnect
1975          * SK-9D41.
1976          */
1977         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1978                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1979         else {
1980                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1981                                     sizeof(hwcfg))) {
1982                         device_printf(dev, "failed to read EEPROM\n");
1983                         error = ENXIO;
1984                         goto fail;
1985                 }
1986                 hwcfg = ntohl(hwcfg);
1987         }
1988
1989         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1990                 sc->bge_flags |= BGE_FLAG_TBI;
1991
1992         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1993         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1994                 sc->bge_flags |= BGE_FLAG_TBI;
1995
1996         if (sc->bge_flags & BGE_FLAG_TBI) {
1997                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1998                     bge_ifmedia_upd, bge_ifmedia_sts);
1999                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2000                 ifmedia_add(&sc->bge_ifmedia,
2001                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2002                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2003                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2004                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2005         } else {
2006                 /*
2007                  * Do transceiver setup.
2008                  */
2009                 if (mii_phy_probe(dev, &sc->bge_miibus,
2010                     bge_ifmedia_upd, bge_ifmedia_sts)) {
2011                         device_printf(dev, "MII without any PHY!\n");
2012                         error = ENXIO;
2013                         goto fail;
2014                 }
2015         }
2016
2017         /*
2018          * When using the BCM5701 in PCI-X mode, data corruption has
2019          * been observed in the first few bytes of some received packets.
2020          * Aligning the packet buffer in memory eliminates the corruption.
2021          * Unfortunately, this misaligns the packet payloads.  On platforms
2022          * which do not support unaligned accesses, we will realign the
2023          * payloads by copying the received packets.
2024          */
2025         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2026             (sc->bge_flags & BGE_FLAG_PCIX))
2027                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2028
2029         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2030             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2031                 sc->bge_link_upd = bge_bcm5700_link_upd;
2032                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2033         } else if (sc->bge_flags & BGE_FLAG_TBI) {
2034                 sc->bge_link_upd = bge_tbi_link_upd;
2035                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2036         } else {
2037                 sc->bge_link_upd = bge_copper_link_upd;
2038                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2039         }
2040
2041         /*
2042          * Create sysctl nodes.
2043          */
2044         sysctl_ctx_init(&sc->bge_sysctl_ctx);
2045         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2046                                               SYSCTL_STATIC_CHILDREN(_hw),
2047                                               OID_AUTO,
2048                                               device_get_nameunit(dev),
2049                                               CTLFLAG_RD, 0, "");
2050         if (sc->bge_sysctl_tree == NULL) {
2051                 device_printf(dev, "can't add sysctl node\n");
2052                 error = ENXIO;
2053                 goto fail;
2054         }
2055
2056         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2057                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2058                         OID_AUTO, "rx_coal_ticks",
2059                         CTLTYPE_INT | CTLFLAG_RW,
2060                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
2061                         "Receive coalescing ticks (usec).");
2062         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2063                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2064                         OID_AUTO, "tx_coal_ticks",
2065                         CTLTYPE_INT | CTLFLAG_RW,
2066                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
2067                         "Transmit coalescing ticks (usec).");
2068         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2069                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2070                         OID_AUTO, "rx_max_coal_bds",
2071                         CTLTYPE_INT | CTLFLAG_RW,
2072                         sc, 0, bge_sysctl_rx_max_coal_bds, "I",
2073                         "Receive max coalesced BD count.");
2074         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2075                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2076                         OID_AUTO, "tx_max_coal_bds",
2077                         CTLTYPE_INT | CTLFLAG_RW,
2078                         sc, 0, bge_sysctl_tx_max_coal_bds, "I",
2079                         "Transmit max coalesced BD count.");
2080
2081         /*
2082          * Call MI attach routine.
2083          */
2084         ether_ifattach(ifp, ether_addr, NULL);
2085
2086         error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE,
2087                                bge_intr, sc, &sc->bge_intrhand,
2088                                ifp->if_serializer);
2089         if (error) {
2090                 ether_ifdetach(ifp);
2091                 device_printf(dev, "couldn't set up irq\n");
2092                 goto fail;
2093         }
2094
2095         ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bge_irq));
2096         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2097
2098         return(0);
2099 fail:
2100         bge_detach(dev);
2101         return(error);
2102 }
2103
2104 static int
2105 bge_detach(device_t dev)
2106 {
2107         struct bge_softc *sc = device_get_softc(dev);
2108
2109         if (device_is_attached(dev)) {
2110                 struct ifnet *ifp = &sc->arpcom.ac_if;
2111
2112                 lwkt_serialize_enter(ifp->if_serializer);
2113                 bge_stop(sc);
2114                 bge_reset(sc);
2115                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2116                 lwkt_serialize_exit(ifp->if_serializer);
2117
2118                 ether_ifdetach(ifp);
2119         }
2120
2121         if (sc->bge_flags & BGE_FLAG_TBI)
2122                 ifmedia_removeall(&sc->bge_ifmedia);
2123         if (sc->bge_miibus)
2124                 device_delete_child(dev, sc->bge_miibus);
2125         bus_generic_detach(dev);
2126
2127         if (sc->bge_irq != NULL)
2128                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2129
2130         if (sc->bge_res != NULL)
2131                 bus_release_resource(dev, SYS_RES_MEMORY,
2132                     BGE_PCI_BAR0, sc->bge_res);
2133
2134         if (sc->bge_sysctl_tree != NULL)
2135                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2136
2137         bge_dma_free(sc);
2138
2139         return 0;
2140 }
2141
2142 static void
2143 bge_reset(struct bge_softc *sc)
2144 {
2145         device_t dev;
2146         uint32_t cachesize, command, pcistate, reset;
2147         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2148         int i, val = 0;
2149
2150         dev = sc->bge_dev;
2151
2152         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2153             sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2154                 if (sc->bge_flags & BGE_FLAG_PCIE)
2155                         write_op = bge_writemem_direct;
2156                 else
2157                         write_op = bge_writemem_ind;
2158         } else {
2159                 write_op = bge_writereg_ind;
2160         }
2161
2162         /* Save some important PCI state. */
2163         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2164         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2165         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2166
2167         pci_write_config(dev, BGE_PCI_MISC_CTL,
2168             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2169             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2170
2171         /* Disable fastboot on controllers that support it. */
2172         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2173             sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2174             sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2175                 if (bootverbose)
2176                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2177                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2178         }
2179
2180         /*
2181          * Write the magic number to SRAM at offset 0xB50.
2182          * When firmware finishes its initialization it will
2183          * write ~BGE_MAGIC_NUMBER to the same location.
2184          */
2185         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2186
2187         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2188
2189         /* XXX: Broadcom Linux driver. */
2190         if (sc->bge_flags & BGE_FLAG_PCIE) {
2191                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
2192                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
2193                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2194                         /* Prevent PCIE link training during global reset */
2195                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2196                         reset |= (1<<29);
2197                 }
2198         }
2199
2200         /*
2201          * Set GPHY Power Down Override to leave GPHY
2202          * powered up in D0 uninitialized.
2203          */
2204         if (BGE_IS_5705_PLUS(sc))
2205                 reset |= 0x04000000;
2206
2207         /* Issue global reset */
2208         write_op(sc, BGE_MISC_CFG, reset);
2209
2210         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2211                 uint32_t status, ctrl;
2212
2213                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2214                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2215                     status | BGE_VCPU_STATUS_DRV_RESET);
2216                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2217                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2218                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2219         }
2220
2221         DELAY(1000);
2222
2223         /* XXX: Broadcom Linux driver. */
2224         if (sc->bge_flags & BGE_FLAG_PCIE) {
2225                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2226                         uint32_t v;
2227
2228                         DELAY(500000); /* wait for link training to complete */
2229                         v = pci_read_config(dev, 0xc4, 4);
2230                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2231                 }
2232                 /*
2233                  * Set PCIE max payload size to 128 bytes and
2234                  * clear error status.
2235                  */
2236                 pci_write_config(dev, 0xd8, 0xf5000, 4);
2237         }
2238
2239         /* Reset some of the PCI state that got zapped by reset */
2240         pci_write_config(dev, BGE_PCI_MISC_CTL,
2241             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2242             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2243         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2244         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2245         write_op(sc, BGE_MISC_CFG, (65 << 1));
2246
2247         /* Enable memory arbiter. */
2248         if (BGE_IS_5714_FAMILY(sc)) {
2249                 uint32_t val;
2250
2251                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2252                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2253         } else {
2254                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2255         }
2256
2257         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2258                 for (i = 0; i < BGE_TIMEOUT; i++) {
2259                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2260                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2261                                 break;
2262                         DELAY(100);
2263                 }
2264                 if (i == BGE_TIMEOUT) {
2265                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2266                         return;
2267                 }
2268         } else {
2269                 /*
2270                  * Poll until we see the 1's complement of the magic number.
2271                  * This indicates that the firmware initialization
2272                  * is complete.
2273                  */
2274                 for (i = 0; i < BGE_TIMEOUT; i++) {
2275                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2276                         if (val == ~BGE_MAGIC_NUMBER)
2277                                 break;
2278                         DELAY(10);
2279                 }
2280                 if (i == BGE_TIMEOUT) {
2281                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2282                                   "timed out, found 0x%08x\n", val);
2283                         return;
2284                 }
2285         }
2286
2287         /*
2288          * XXX Wait for the value of the PCISTATE register to
2289          * return to its original pre-reset state. This is a
2290          * fairly good indicator of reset completion. If we don't
2291          * wait for the reset to fully complete, trying to read
2292          * from the device's non-PCI registers may yield garbage
2293          * results.
2294          */
2295         for (i = 0; i < BGE_TIMEOUT; i++) {
2296                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2297                         break;
2298                 DELAY(10);
2299         }
2300
2301         if (sc->bge_flags & BGE_FLAG_PCIE) {
2302                 reset = bge_readmem_ind(sc, 0x7c00);
2303                 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2304         }
2305
2306         /* Fix up byte swapping */
2307         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2308             BGE_MODECTL_BYTESWAP_DATA);
2309
2310         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2311
2312         /*
2313          * The 5704 in TBI mode apparently needs some special
2314          * adjustment to insure the SERDES drive level is set
2315          * to 1.2V.
2316          */
2317         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2318             (sc->bge_flags & BGE_FLAG_TBI)) {
2319                 uint32_t serdescfg;
2320
2321                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2322                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2323                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2324         }
2325
2326         /* XXX: Broadcom Linux driver. */
2327         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2328             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2329                 uint32_t v;
2330
2331                 v = CSR_READ_4(sc, 0x7c00);
2332                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2333         }
2334
2335         DELAY(10000);
2336 }
2337
2338 /*
2339  * Frame reception handling. This is called if there's a frame
2340  * on the receive return list.
2341  *
2342  * Note: we have to be able to handle two possibilities here:
2343  * 1) the frame is from the jumbo recieve ring
2344  * 2) the frame is from the standard receive ring
2345  */
2346
2347 static void
2348 bge_rxeof(struct bge_softc *sc)
2349 {
2350         struct ifnet *ifp;
2351         int stdcnt = 0, jumbocnt = 0;
2352         struct mbuf_chain chain[MAXCPU];
2353
2354         if (sc->bge_rx_saved_considx ==
2355             sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2356                 return;
2357
2358         ether_input_chain_init(chain);
2359
2360         ifp = &sc->arpcom.ac_if;
2361
2362         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2363                         sc->bge_cdata.bge_rx_return_ring_map,
2364                         BUS_DMASYNC_POSTREAD);
2365         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2366                         sc->bge_cdata.bge_rx_std_ring_map,
2367                         BUS_DMASYNC_POSTREAD);
2368         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2369                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2370                                 sc->bge_cdata.bge_rx_jumbo_ring_map,
2371                                 BUS_DMASYNC_POSTREAD);
2372         }
2373
2374         while (sc->bge_rx_saved_considx !=
2375                sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2376                 struct bge_rx_bd        *cur_rx;
2377                 uint32_t                rxidx;
2378                 struct mbuf             *m = NULL;
2379                 uint16_t                vlan_tag = 0;
2380                 int                     have_tag = 0;
2381
2382                 cur_rx =
2383             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2384
2385                 rxidx = cur_rx->bge_idx;
2386                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2387                 logif(rx_pkt);
2388
2389                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2390                         have_tag = 1;
2391                         vlan_tag = cur_rx->bge_vlan_tag;
2392                 }
2393
2394                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2395                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2396                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2397                         sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2398                         jumbocnt++;
2399                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2400                                 ifp->if_ierrors++;
2401                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2402                                 continue;
2403                         }
2404                         if (bge_newbuf_jumbo(sc,
2405                             sc->bge_jumbo, NULL) == ENOBUFS) {
2406                                 ifp->if_ierrors++;
2407                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2408                                 continue;
2409                         }
2410                 } else {
2411                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2412                         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2413                                         sc->bge_cdata.bge_rx_std_dmamap[rxidx],
2414                                         BUS_DMASYNC_POSTREAD);
2415                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2416                                 sc->bge_cdata.bge_rx_std_dmamap[rxidx]);
2417                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2418                         sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2419                         stdcnt++;
2420                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2421                                 ifp->if_ierrors++;
2422                                 bge_newbuf_std(sc, sc->bge_std, m);
2423                                 continue;
2424                         }
2425                         if (bge_newbuf_std(sc, sc->bge_std,
2426                             NULL) == ENOBUFS) {
2427                                 ifp->if_ierrors++;
2428                                 bge_newbuf_std(sc, sc->bge_std, m);
2429                                 continue;
2430                         }
2431                 }
2432
2433                 ifp->if_ipackets++;
2434 #ifndef __i386__
2435                 /*
2436                  * The i386 allows unaligned accesses, but for other
2437                  * platforms we must make sure the payload is aligned.
2438                  */
2439                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2440                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2441                             cur_rx->bge_len);
2442                         m->m_data += ETHER_ALIGN;
2443                 }
2444 #endif
2445                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2446                 m->m_pkthdr.rcvif = ifp;
2447
2448                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2449                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2450                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2451                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2452                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2453                         }
2454                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2455                             m->m_pkthdr.len >= BGE_MIN_FRAME) {
2456                                 m->m_pkthdr.csum_data =
2457                                         cur_rx->bge_tcp_udp_csum;
2458                                 m->m_pkthdr.csum_flags |=
2459                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2460                         }
2461                 }
2462
2463                 /*
2464                  * If we received a packet with a vlan tag, pass it
2465                  * to vlan_input() instead of ether_input().
2466                  */
2467                 if (have_tag) {
2468                         m->m_flags |= M_VLANTAG;
2469                         m->m_pkthdr.ether_vlantag = vlan_tag;
2470                         have_tag = vlan_tag = 0;
2471                 }
2472                 ether_input_chain(ifp, m, chain);
2473         }
2474
2475         ether_input_dispatch(chain);
2476
2477         if (stdcnt > 0) {
2478                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2479                                 sc->bge_cdata.bge_rx_std_ring_map,
2480                                 BUS_DMASYNC_PREWRITE);
2481         }
2482
2483         if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) {
2484                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2485                                 sc->bge_cdata.bge_rx_jumbo_ring_map,
2486                                 BUS_DMASYNC_PREWRITE);
2487         }
2488
2489         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2490         if (stdcnt)
2491                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2492         if (jumbocnt)
2493                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2494 }
2495
2496 static void
2497 bge_txeof(struct bge_softc *sc)
2498 {
2499         struct bge_tx_bd *cur_tx = NULL;
2500         struct ifnet *ifp;
2501
2502         if (sc->bge_tx_saved_considx ==
2503             sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2504                 return;
2505
2506         ifp = &sc->arpcom.ac_if;
2507
2508         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
2509                         sc->bge_cdata.bge_tx_ring_map,
2510                         BUS_DMASYNC_POSTREAD);
2511
2512         /*
2513          * Go through our tx ring and free mbufs for those
2514          * frames that have been sent.
2515          */
2516         while (sc->bge_tx_saved_considx !=
2517                sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2518                 uint32_t idx = 0;
2519
2520                 idx = sc->bge_tx_saved_considx;
2521                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2522                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2523                         ifp->if_opackets++;
2524                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2525                         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2526                                         sc->bge_cdata.bge_tx_dmamap[idx],
2527                                         BUS_DMASYNC_POSTWRITE);
2528                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2529                             sc->bge_cdata.bge_tx_dmamap[idx]);
2530                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2531                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2532                 }
2533                 sc->bge_txcnt--;
2534                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2535                 logif(tx_pkt);
2536         }
2537
2538         if (cur_tx != NULL &&
2539             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2540             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2541                 ifp->if_flags &= ~IFF_OACTIVE;
2542
2543         if (sc->bge_txcnt == 0)
2544                 ifp->if_timer = 0;
2545
2546         if (!ifq_is_empty(&ifp->if_snd))
2547                 if_devstart(ifp);
2548 }
2549
2550 #ifdef DEVICE_POLLING
2551
2552 static void
2553 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2554 {
2555         struct bge_softc *sc = ifp->if_softc;
2556         uint32_t status;
2557
2558         switch(cmd) {
2559         case POLL_REGISTER:
2560                 bge_disable_intr(sc);
2561                 break;
2562         case POLL_DEREGISTER:
2563                 bge_enable_intr(sc);
2564                 break;
2565         case POLL_AND_CHECK_STATUS:
2566                 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2567                                 sc->bge_cdata.bge_status_map,
2568                                 BUS_DMASYNC_POSTREAD);
2569
2570                 /*
2571                  * Process link state changes.
2572                  */
2573                 status = CSR_READ_4(sc, BGE_MAC_STS);
2574                 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2575                         sc->bge_link_evt = 0;
2576                         sc->bge_link_upd(sc, status);
2577                 }
2578                 /* fall through */
2579         case POLL_ONLY:
2580                 if (ifp->if_flags & IFF_RUNNING) {
2581                         bge_rxeof(sc);
2582                         bge_txeof(sc);
2583                 }
2584                 break;
2585         }
2586 }
2587
2588 #endif
2589
2590 static void
2591 bge_intr(void *xsc)
2592 {
2593         struct bge_softc *sc = xsc;
2594         struct ifnet *ifp = &sc->arpcom.ac_if;
2595         uint32_t status;
2596
2597         logif(intr);
2598
2599         /*
2600          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2601          * disable interrupts by writing nonzero like we used to, since with
2602          * our current organization this just gives complications and
2603          * pessimizations for re-enabling interrupts.  We used to have races
2604          * instead of the necessary complications.  Disabling interrupts
2605          * would just reduce the chance of a status update while we are
2606          * running (by switching to the interrupt-mode coalescence
2607          * parameters), but this chance is already very low so it is more
2608          * efficient to get another interrupt than prevent it.
2609          *
2610          * We do the ack first to ensure another interrupt if there is a
2611          * status update after the ack.  We don't check for the status
2612          * changing later because it is more efficient to get another
2613          * interrupt than prevent it, not quite as above (not checking is
2614          * a smaller optimization than not toggling the interrupt enable,
2615          * since checking doesn't involve PCI accesses and toggling require
2616          * the status check).  So toggling would probably be a pessimization
2617          * even with MSI.  It would only be needed for using a task queue.
2618          */
2619         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
2620
2621         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2622                         sc->bge_cdata.bge_status_map,
2623                         BUS_DMASYNC_POSTREAD);
2624
2625         /*
2626          * Process link state changes.
2627          */
2628         status = CSR_READ_4(sc, BGE_MAC_STS);
2629         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2630                 sc->bge_link_evt = 0;
2631                 sc->bge_link_upd(sc, status);
2632         }
2633
2634         if (ifp->if_flags & IFF_RUNNING) {
2635                 /* Check RX return ring producer/consumer */
2636                 bge_rxeof(sc);
2637
2638                 /* Check TX ring producer/consumer */
2639                 bge_txeof(sc);
2640         }
2641
2642         if (sc->bge_coal_chg)
2643                 bge_coal_change(sc);
2644 }
2645
2646 static void
2647 bge_tick(void *xsc)
2648 {
2649         struct bge_softc *sc = xsc;
2650         struct ifnet *ifp = &sc->arpcom.ac_if;
2651
2652         lwkt_serialize_enter(ifp->if_serializer);
2653
2654         if (BGE_IS_5705_PLUS(sc))
2655                 bge_stats_update_regs(sc);
2656         else
2657                 bge_stats_update(sc);
2658
2659         if (sc->bge_flags & BGE_FLAG_TBI) {
2660                 /*
2661                  * Since in TBI mode auto-polling can't be used we should poll
2662                  * link status manually. Here we register pending link event
2663                  * and trigger interrupt.
2664                  */
2665                 sc->bge_link_evt++;
2666                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2667         } else if (!sc->bge_link) {
2668                 mii_tick(device_get_softc(sc->bge_miibus));
2669         }
2670
2671         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2672
2673         lwkt_serialize_exit(ifp->if_serializer);
2674 }
2675
2676 static void
2677 bge_stats_update_regs(struct bge_softc *sc)
2678 {
2679         struct ifnet *ifp = &sc->arpcom.ac_if;
2680         struct bge_mac_stats_regs stats;
2681         uint32_t *s;
2682         int i;
2683
2684         s = (uint32_t *)&stats;
2685         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2686                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2687                 s++;
2688         }
2689
2690         ifp->if_collisions +=
2691            (stats.dot3StatsSingleCollisionFrames +
2692            stats.dot3StatsMultipleCollisionFrames +
2693            stats.dot3StatsExcessiveCollisions +
2694            stats.dot3StatsLateCollisions) -
2695            ifp->if_collisions;
2696 }
2697
2698 static void
2699 bge_stats_update(struct bge_softc *sc)
2700 {
2701         struct ifnet *ifp = &sc->arpcom.ac_if;
2702         bus_size_t stats;
2703
2704         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2705
2706 #define READ_STAT(sc, stats, stat)      \
2707         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2708
2709         ifp->if_collisions +=
2710            (READ_STAT(sc, stats,
2711                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2712             READ_STAT(sc, stats,
2713                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2714             READ_STAT(sc, stats,
2715                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2716             READ_STAT(sc, stats,
2717                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
2718            ifp->if_collisions;
2719
2720 #undef READ_STAT
2721
2722 #ifdef notdef
2723         ifp->if_collisions +=
2724            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2725            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2726            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2727            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2728            ifp->if_collisions;
2729 #endif
2730 }
2731
2732 /*
2733  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2734  * pointers to descriptors.
2735  */
2736 static int
2737 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
2738 {
2739         struct bge_tx_bd *d = NULL;
2740         uint16_t csum_flags = 0;
2741         struct bge_dmamap_arg ctx;
2742         bus_dma_segment_t segs[BGE_NSEG_NEW];
2743         bus_dmamap_t map;
2744         int error, maxsegs, idx, i;
2745         struct mbuf *m_head = *m_head0;
2746
2747         if (m_head->m_pkthdr.csum_flags) {
2748                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2749                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2750                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2751                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2752                 if (m_head->m_flags & M_LASTFRAG)
2753                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2754                 else if (m_head->m_flags & M_FRAG)
2755                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2756         }
2757
2758         idx = *txidx;
2759         map = sc->bge_cdata.bge_tx_dmamap[idx];
2760
2761         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2762         KASSERT(maxsegs >= BGE_NSEG_SPARE,
2763                 ("not enough segments %d\n", maxsegs));
2764
2765         if (maxsegs > BGE_NSEG_NEW)
2766                 maxsegs = BGE_NSEG_NEW;
2767
2768         /*
2769          * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2770          * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2771          * but when such padded frames employ the bge IP/TCP checksum
2772          * offload, the hardware checksum assist gives incorrect results
2773          * (possibly from incorporating its own padding into the UDP/TCP
2774          * checksum; who knows).  If we pad such runts with zeros, the
2775          * onboard checksum comes out correct.
2776          */
2777         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2778             m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2779                 error = m_devpad(m_head, BGE_MIN_FRAME);
2780                 if (error)
2781                         goto back;
2782         }
2783
2784         ctx.bge_segs = segs;
2785         ctx.bge_maxsegs = maxsegs;
2786         error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map, m_head,
2787                                      bge_dma_map_mbuf, &ctx, BUS_DMA_NOWAIT);
2788         if (error == EFBIG || ctx.bge_maxsegs == 0) {
2789                 struct mbuf *m_new;
2790
2791                 if (!error)
2792                         bus_dmamap_unload(sc->bge_cdata.bge_mtag, map);
2793
2794                 m_new = m_defrag(m_head, MB_DONTWAIT);
2795                 if (m_new == NULL) {
2796                         if_printf(&sc->arpcom.ac_if,
2797                                   "could not defrag TX mbuf\n");
2798                         error = ENOBUFS;
2799                         goto back;
2800                 } else {
2801                         m_head = m_new;
2802                         *m_head0 = m_head;
2803                 }
2804
2805                 ctx.bge_segs = segs;
2806                 ctx.bge_maxsegs = maxsegs;
2807                 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2808                                              m_head, bge_dma_map_mbuf, &ctx,
2809                                              BUS_DMA_NOWAIT);
2810                 if (error || ctx.bge_maxsegs == 0) {
2811                         if_printf(&sc->arpcom.ac_if,
2812                                   "could not defrag TX mbuf\n");
2813                         if (!error) {
2814                                 bus_dmamap_unload(sc->bge_cdata.bge_mtag, map);
2815                                 error = EFBIG;
2816                         }
2817                         goto back;
2818                 }
2819         } else if (error) {
2820                 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
2821                 goto back;
2822         }
2823
2824         bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE);
2825
2826         for (i = 0; ; i++) {
2827                 d = &sc->bge_ldata.bge_tx_ring[idx];
2828
2829                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[i].ds_addr);
2830                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[i].ds_addr);
2831                 d->bge_len = segs[i].ds_len;
2832                 d->bge_flags = csum_flags;
2833
2834                 if (i == ctx.bge_maxsegs - 1)
2835                         break;
2836                 BGE_INC(idx, BGE_TX_RING_CNT);
2837         }
2838         /* Mark the last segment as end of packet... */
2839         d->bge_flags |= BGE_TXBDFLAG_END;
2840
2841         /* Set vlan tag to the first segment of the packet. */
2842         d = &sc->bge_ldata.bge_tx_ring[*txidx];
2843         if (m_head->m_flags & M_VLANTAG) {
2844                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2845                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
2846         } else {
2847                 d->bge_vlan_tag = 0;
2848         }
2849
2850         /*
2851          * Insure that the map for this transmission is placed at
2852          * the array index of the last descriptor in this chain.
2853          */
2854         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2855         sc->bge_cdata.bge_tx_dmamap[idx] = map;
2856         sc->bge_cdata.bge_tx_chain[idx] = m_head;
2857         sc->bge_txcnt += ctx.bge_maxsegs;
2858
2859         BGE_INC(idx, BGE_TX_RING_CNT);
2860         *txidx = idx;
2861 back:
2862         if (error) {
2863                 m_freem(m_head);
2864                 *m_head0 = NULL;
2865         }
2866         return error;
2867 }
2868
2869 /*
2870  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2871  * to the mbuf data regions directly in the transmit descriptors.
2872  */
2873 static void
2874 bge_start(struct ifnet *ifp)
2875 {
2876         struct bge_softc *sc = ifp->if_softc;
2877         struct mbuf *m_head = NULL;
2878         uint32_t prodidx;
2879         int need_trans;
2880
2881         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2882                 return;
2883
2884         prodidx = sc->bge_tx_prodidx;
2885
2886         need_trans = 0;
2887         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2888                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2889                 if (m_head == NULL)
2890                         break;
2891
2892                 /*
2893                  * XXX
2894                  * The code inside the if() block is never reached since we
2895                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2896                  * requests to checksum TCP/UDP in a fragmented packet.
2897                  *
2898                  * XXX
2899                  * safety overkill.  If this is a fragmented packet chain
2900                  * with delayed TCP/UDP checksums, then only encapsulate
2901                  * it if we have enough descriptors to handle the entire
2902                  * chain at once.
2903                  * (paranoia -- may not actually be needed)
2904                  */
2905                 if ((m_head->m_flags & M_FIRSTFRAG) &&
2906                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
2907                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2908                             m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
2909                                 ifp->if_flags |= IFF_OACTIVE;
2910                                 ifq_prepend(&ifp->if_snd, m_head);
2911                                 break;
2912                         }
2913                 }
2914
2915                 /*
2916                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2917                  * descriptors of the end of the ring.  Also make
2918                  * sure there are BGE_NSEG_SPARE descriptors for
2919                  * jumbo buffers' defragmentation.
2920                  */
2921                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2922                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
2923                         ifp->if_flags |= IFF_OACTIVE;
2924                         ifq_prepend(&ifp->if_snd, m_head);
2925                         break;
2926                 }
2927
2928                 /*
2929                  * Pack the data into the transmit ring. If we
2930                  * don't have room, set the OACTIVE flag and wait
2931                  * for the NIC to drain the ring.
2932                  */
2933                 if (bge_encap(sc, &m_head, &prodidx)) {
2934                         ifp->if_flags |= IFF_OACTIVE;
2935                         ifp->if_oerrors++;
2936                         break;
2937                 }
2938                 need_trans = 1;
2939
2940                 ETHER_BPF_MTAP(ifp, m_head);
2941         }
2942
2943         if (!need_trans)
2944                 return;
2945
2946         /* Transmit */
2947         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2948         /* 5700 b2 errata */
2949         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2950                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2951
2952         sc->bge_tx_prodidx = prodidx;
2953
2954         /*
2955          * Set a timeout in case the chip goes out to lunch.
2956          */
2957         ifp->if_timer = 5;
2958 }
2959
2960 static void
2961 bge_init(void *xsc)
2962 {
2963         struct bge_softc *sc = xsc;
2964         struct ifnet *ifp = &sc->arpcom.ac_if;
2965         uint16_t *m;
2966
2967         ASSERT_SERIALIZED(ifp->if_serializer);
2968
2969         if (ifp->if_flags & IFF_RUNNING)
2970                 return;
2971
2972         /* Cancel pending I/O and flush buffers. */
2973         bge_stop(sc);
2974         bge_reset(sc);
2975         bge_chipinit(sc);
2976
2977         /*
2978          * Init the various state machines, ring
2979          * control blocks and firmware.
2980          */
2981         if (bge_blockinit(sc)) {
2982                 if_printf(ifp, "initialization failure\n");
2983                 return;
2984         }
2985
2986         /* Specify MTU. */
2987         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2988             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2989
2990         /* Load our MAC address. */
2991         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2992         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2993         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2994
2995         /* Enable or disable promiscuous mode as needed. */
2996         bge_setpromisc(sc);
2997
2998         /* Program multicast filter. */
2999         bge_setmulti(sc);
3000
3001         /* Init RX ring. */
3002         bge_init_rx_ring_std(sc);
3003
3004         /*
3005          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3006          * memory to insure that the chip has in fact read the first
3007          * entry of the ring.
3008          */
3009         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3010                 uint32_t                v, i;
3011                 for (i = 0; i < 10; i++) {
3012                         DELAY(20);
3013                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3014                         if (v == (MCLBYTES - ETHER_ALIGN))
3015                                 break;
3016                 }
3017                 if (i == 10)
3018                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3019         }
3020
3021         /* Init jumbo RX ring. */
3022         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
3023                 bge_init_rx_ring_jumbo(sc);
3024
3025         /* Init our RX return ring index */
3026         sc->bge_rx_saved_considx = 0;
3027
3028         /* Init TX ring. */
3029         bge_init_tx_ring(sc);
3030
3031         /* Turn on transmitter */
3032         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
3033
3034         /* Turn on receiver */
3035         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3036
3037         /* Tell firmware we're alive. */
3038         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3039
3040         /* Enable host interrupts if polling(4) is not enabled. */
3041         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3042 #ifdef DEVICE_POLLING
3043         if (ifp->if_flags & IFF_POLLING)
3044                 bge_disable_intr(sc);
3045         else
3046 #endif
3047         bge_enable_intr(sc);
3048
3049         bge_ifmedia_upd(ifp);
3050
3051         ifp->if_flags |= IFF_RUNNING;
3052         ifp->if_flags &= ~IFF_OACTIVE;
3053
3054         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3055 }
3056
3057 /*
3058  * Set media options.
3059  */
3060 static int
3061 bge_ifmedia_upd(struct ifnet *ifp)
3062 {
3063         struct bge_softc *sc = ifp->if_softc;
3064
3065         /* If this is a 1000baseX NIC, enable the TBI port. */
3066         if (sc->bge_flags & BGE_FLAG_TBI) {
3067                 struct ifmedia *ifm = &sc->bge_ifmedia;
3068
3069                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3070                         return(EINVAL);
3071
3072                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3073                 case IFM_AUTO:
3074                         /*
3075                          * The BCM5704 ASIC appears to have a special
3076                          * mechanism for programming the autoneg
3077                          * advertisement registers in TBI mode.
3078                          */
3079                         if (!bge_fake_autoneg &&
3080                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3081                                 uint32_t sgdig;
3082
3083                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3084                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3085                                 sgdig |= BGE_SGDIGCFG_AUTO |
3086                                          BGE_SGDIGCFG_PAUSE_CAP |
3087                                          BGE_SGDIGCFG_ASYM_PAUSE;
3088                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3089                                             sgdig | BGE_SGDIGCFG_SEND);
3090                                 DELAY(5);
3091                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3092                         }
3093                         break;
3094                 case IFM_1000_SX:
3095                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3096                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3097                                     BGE_MACMODE_HALF_DUPLEX);
3098                         } else {
3099                                 BGE_SETBIT(sc, BGE_MAC_MODE,
3100                                     BGE_MACMODE_HALF_DUPLEX);
3101                         }
3102                         break;
3103                 default:
3104                         return(EINVAL);
3105                 }
3106         } else {
3107                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3108
3109                 sc->bge_link_evt++;
3110                 sc->bge_link = 0;
3111                 if (mii->mii_instance) {
3112                         struct mii_softc *miisc;
3113
3114                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3115                                 mii_phy_reset(miisc);
3116                 }
3117                 mii_mediachg(mii);
3118         }
3119         return(0);
3120 }
3121
3122 /*
3123  * Report current media status.
3124  */
3125 static void
3126 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3127 {
3128         struct bge_softc *sc = ifp->if_softc;
3129
3130         if (sc->bge_flags & BGE_FLAG_TBI) {
3131                 ifmr->ifm_status = IFM_AVALID;
3132                 ifmr->ifm_active = IFM_ETHER;
3133                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3134                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3135                         ifmr->ifm_status |= IFM_ACTIVE;
3136                 } else {
3137                         ifmr->ifm_active |= IFM_NONE;
3138                         return;
3139                 }
3140
3141                 ifmr->ifm_active |= IFM_1000_SX;
3142                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3143                         ifmr->ifm_active |= IFM_HDX;
3144                 else
3145                         ifmr->ifm_active |= IFM_FDX;
3146         } else {
3147                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3148
3149                 mii_pollstat(mii);
3150                 ifmr->ifm_active = mii->mii_media_active;
3151                 ifmr->ifm_status = mii->mii_media_status;
3152         }
3153 }
3154
3155 static int
3156 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3157 {
3158         struct bge_softc *sc = ifp->if_softc;
3159         struct ifreq *ifr = (struct ifreq *)data;
3160         int mask, error = 0;
3161
3162         ASSERT_SERIALIZED(ifp->if_serializer);
3163
3164         switch (command) {
3165         case SIOCSIFMTU:
3166                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3167                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3168                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3169                         error = EINVAL;
3170                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3171                         ifp->if_mtu = ifr->ifr_mtu;
3172                         ifp->if_flags &= ~IFF_RUNNING;
3173                         bge_init(sc);
3174                 }
3175                 break;
3176         case SIOCSIFFLAGS:
3177                 if (ifp->if_flags & IFF_UP) {
3178                         if (ifp->if_flags & IFF_RUNNING) {
3179                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3180
3181                                 /*
3182                                  * If only the state of the PROMISC flag
3183                                  * changed, then just use the 'set promisc
3184                                  * mode' command instead of reinitializing
3185                                  * the entire NIC. Doing a full re-init
3186                                  * means reloading the firmware and waiting
3187                                  * for it to start up, which may take a
3188                                  * second or two.  Similarly for ALLMULTI.
3189                                  */
3190                                 if (mask & IFF_PROMISC)
3191                                         bge_setpromisc(sc);
3192                                 if (mask & IFF_ALLMULTI)
3193                                         bge_setmulti(sc);
3194                         } else {
3195                                 bge_init(sc);
3196                         }
3197                 } else {
3198                         if (ifp->if_flags & IFF_RUNNING)
3199                                 bge_stop(sc);
3200                 }
3201                 sc->bge_if_flags = ifp->if_flags;
3202                 break;
3203         case SIOCADDMULTI:
3204         case SIOCDELMULTI:
3205                 if (ifp->if_flags & IFF_RUNNING)
3206                         bge_setmulti(sc);
3207                 break;
3208         case SIOCSIFMEDIA:
3209         case SIOCGIFMEDIA:
3210                 if (sc->bge_flags & BGE_FLAG_TBI) {
3211                         error = ifmedia_ioctl(ifp, ifr,
3212                             &sc->bge_ifmedia, command);
3213                 } else {
3214                         struct mii_data *mii;
3215
3216                         mii = device_get_softc(sc->bge_miibus);
3217                         error = ifmedia_ioctl(ifp, ifr,
3218                                               &mii->mii_media, command);
3219                 }
3220                 break;
3221         case SIOCSIFCAP:
3222                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3223                 if (mask & IFCAP_HWCSUM) {
3224                         ifp->if_capenable ^= IFCAP_HWCSUM;
3225                         if (IFCAP_HWCSUM & ifp->if_capenable)
3226                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3227                         else
3228                                 ifp->if_hwassist = 0;
3229                 }
3230                 break;
3231         default:
3232                 error = ether_ioctl(ifp, command, data);
3233                 break;
3234         }
3235         return error;
3236 }
3237
3238 static void
3239 bge_watchdog(struct ifnet *ifp)
3240 {
3241         struct bge_softc *sc = ifp->if_softc;
3242
3243         if_printf(ifp, "watchdog timeout -- resetting\n");
3244
3245         ifp->if_flags &= ~IFF_RUNNING;
3246         bge_init(sc);
3247
3248         ifp->if_oerrors++;
3249
3250         if (!ifq_is_empty(&ifp->if_snd))
3251                 if_devstart(ifp);
3252 }
3253
3254 /*
3255  * Stop the adapter and free any mbufs allocated to the
3256  * RX and TX lists.
3257  */
3258 static void
3259 bge_stop(struct bge_softc *sc)
3260 {
3261         struct ifnet *ifp = &sc->arpcom.ac_if;
3262         struct ifmedia_entry *ifm;
3263         struct mii_data *mii = NULL;
3264         int mtmp, itmp;
3265
3266         ASSERT_SERIALIZED(ifp->if_serializer);
3267
3268         if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
3269                 mii = device_get_softc(sc->bge_miibus);
3270
3271         callout_stop(&sc->bge_stat_timer);
3272
3273         /*
3274          * Disable all of the receiver blocks
3275          */
3276         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3277         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3278         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3279         if (!BGE_IS_5705_PLUS(sc))
3280                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3281         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3282         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3283         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3284
3285         /*
3286          * Disable all of the transmit blocks
3287          */
3288         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3289         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3290         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3291         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3292         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3293         if (!BGE_IS_5705_PLUS(sc))
3294                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3295         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3296
3297         /*
3298          * Shut down all of the memory managers and related
3299          * state machines.
3300          */
3301         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3302         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3303         if (!BGE_IS_5705_PLUS(sc))
3304                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3305         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3306         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3307         if (!BGE_IS_5705_PLUS(sc)) {
3308                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3309                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3310         }
3311
3312         /* Disable host interrupts. */
3313         bge_disable_intr(sc);
3314
3315         /*
3316          * Tell firmware we're shutting down.
3317          */
3318         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3319
3320         /* Free the RX lists. */
3321         bge_free_rx_ring_std(sc);
3322
3323         /* Free jumbo RX list. */
3324         if (BGE_IS_JUMBO_CAPABLE(sc))
3325                 bge_free_rx_ring_jumbo(sc);
3326
3327         /* Free TX buffers. */
3328         bge_free_tx_ring(sc);
3329
3330         /*
3331          * Isolate/power down the PHY, but leave the media selection
3332          * unchanged so that things will be put back to normal when
3333          * we bring the interface back up.
3334          *
3335          * 'mii' may be NULL in the following cases:
3336          * - The device uses TBI.
3337          * - bge_stop() is called by bge_detach().
3338          */
3339         if (mii != NULL) {
3340                 itmp = ifp->if_flags;
3341                 ifp->if_flags |= IFF_UP;
3342                 ifm = mii->mii_media.ifm_cur;
3343                 mtmp = ifm->ifm_media;
3344                 ifm->ifm_media = IFM_ETHER|IFM_NONE;
3345                 mii_mediachg(mii);
3346                 ifm->ifm_media = mtmp;
3347                 ifp->if_flags = itmp;
3348         }
3349
3350         sc->bge_link = 0;
3351         sc->bge_coal_chg = 0;
3352
3353         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3354
3355         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3356         ifp->if_timer = 0;
3357 }
3358
3359 /*
3360  * Stop all chip I/O so that the kernel's probe routines don't
3361  * get confused by errant DMAs when rebooting.
3362  */
3363 static void
3364 bge_shutdown(device_t dev)
3365 {
3366         struct bge_softc *sc = device_get_softc(dev);
3367         struct ifnet *ifp = &sc->arpcom.ac_if;
3368
3369         lwkt_serialize_enter(ifp->if_serializer);
3370         bge_stop(sc);
3371         bge_reset(sc);
3372         lwkt_serialize_exit(ifp->if_serializer);
3373 }
3374
3375 static int
3376 bge_suspend(device_t dev)
3377 {
3378         struct bge_softc *sc = device_get_softc(dev);
3379         struct ifnet *ifp = &sc->arpcom.ac_if;
3380
3381         lwkt_serialize_enter(ifp->if_serializer);
3382         bge_stop(sc);
3383         lwkt_serialize_exit(ifp->if_serializer);
3384
3385         return 0;
3386 }
3387
3388 static int
3389 bge_resume(device_t dev)
3390 {
3391         struct bge_softc *sc = device_get_softc(dev);
3392         struct ifnet *ifp = &sc->arpcom.ac_if;
3393
3394         lwkt_serialize_enter(ifp->if_serializer);
3395
3396         if (ifp->if_flags & IFF_UP) {
3397                 bge_init(sc);
3398
3399                 if (!ifq_is_empty(&ifp->if_snd))
3400                         if_devstart(ifp);
3401         }
3402
3403         lwkt_serialize_exit(ifp->if_serializer);
3404
3405         return 0;
3406 }
3407
3408 static void
3409 bge_setpromisc(struct bge_softc *sc)
3410 {
3411         struct ifnet *ifp = &sc->arpcom.ac_if;
3412
3413         if (ifp->if_flags & IFF_PROMISC)
3414                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3415         else
3416                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3417 }
3418
3419 static void
3420 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3421 {
3422         struct bge_dmamap_arg *ctx = arg;
3423
3424         if (error)
3425                 return;
3426
3427         KASSERT(nsegs == 1 && ctx->bge_maxsegs == 1,
3428                 ("only one segment is allowed\n"));
3429
3430         ctx->bge_segs[0] = *segs;
3431 }
3432
3433 static void
3434 bge_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nsegs,
3435                  bus_size_t mapsz __unused, int error)
3436 {
3437         struct bge_dmamap_arg *ctx = arg;
3438         int i;
3439
3440         if (error)
3441                 return;
3442
3443         if (nsegs > ctx->bge_maxsegs) {
3444                 ctx->bge_maxsegs = 0;
3445                 return;
3446         }
3447
3448         ctx->bge_maxsegs = nsegs;
3449         for (i = 0; i < nsegs; ++i)
3450                 ctx->bge_segs[i] = segs[i];
3451 }
3452
3453 static void
3454 bge_dma_free(struct bge_softc *sc)
3455 {
3456         int i;
3457
3458         /* Destroy RX/TX mbuf DMA stuffs. */
3459         if (sc->bge_cdata.bge_mtag != NULL) {
3460                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3461                         if (sc->bge_cdata.bge_rx_std_dmamap[i]) {
3462                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3463                                     sc->bge_cdata.bge_rx_std_dmamap[i]);
3464                         }
3465                 }
3466
3467                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3468                         if (sc->bge_cdata.bge_tx_dmamap[i]) {
3469                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3470                                     sc->bge_cdata.bge_tx_dmamap[i]);
3471                         }
3472                 }
3473                 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3474         }
3475
3476         /* Destroy standard RX ring */
3477         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3478                            sc->bge_cdata.bge_rx_std_ring_map,
3479                            sc->bge_ldata.bge_rx_std_ring);
3480
3481         if (BGE_IS_JUMBO_CAPABLE(sc))
3482                 bge_free_jumbo_mem(sc);
3483
3484         /* Destroy RX return ring */
3485         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3486                            sc->bge_cdata.bge_rx_return_ring_map,
3487                            sc->bge_ldata.bge_rx_return_ring);
3488
3489         /* Destroy TX ring */
3490         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3491                            sc->bge_cdata.bge_tx_ring_map,
3492                            sc->bge_ldata.bge_tx_ring);
3493
3494         /* Destroy status block */
3495         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3496                            sc->bge_cdata.bge_status_map,
3497                            sc->bge_ldata.bge_status_block);
3498
3499         /* Destroy statistics block */
3500         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3501                            sc->bge_cdata.bge_stats_map,
3502                            sc->bge_ldata.bge_stats);
3503
3504         /* Destroy the parent tag */
3505         if (sc->bge_cdata.bge_parent_tag != NULL)
3506                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3507 }
3508
3509 static int
3510 bge_dma_alloc(struct bge_softc *sc)
3511 {
3512         struct ifnet *ifp = &sc->arpcom.ac_if;
3513         int nseg, i, error;
3514
3515         /*
3516          * Allocate the parent bus DMA tag appropriate for PCI.
3517          */
3518         error = bus_dma_tag_create(NULL, 1, 0,
3519                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3520                                    NULL, NULL,
3521                                    MAXBSIZE, BGE_NSEG_NEW,
3522                                    BUS_SPACE_MAXSIZE_32BIT,
3523                                    0, &sc->bge_cdata.bge_parent_tag);
3524         if (error) {
3525                 if_printf(ifp, "could not allocate parent dma tag\n");
3526                 return error;
3527         }
3528
3529         /*
3530          * Create DMA tag for mbufs.
3531          */
3532         nseg = BGE_NSEG_NEW;
3533         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3534                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3535                                    NULL, NULL,
3536                                    MCLBYTES * nseg, nseg, MCLBYTES,
3537                                    BUS_DMA_ALLOCNOW, &sc->bge_cdata.bge_mtag);
3538         if (error) {
3539                 if_printf(ifp, "could not allocate mbuf dma tag\n");
3540                 return error;
3541         }
3542
3543         /*
3544          * Create DMA maps for TX/RX mbufs.
3545          */
3546         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3547                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3548                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
3549                 if (error) {
3550                         int j;
3551
3552                         for (j = 0; j < i; ++j) {
3553                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3554                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3555                         }
3556                         bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3557                         sc->bge_cdata.bge_mtag = NULL;
3558
3559                         if_printf(ifp, "could not create DMA map for RX\n");
3560                         return error;
3561                 }
3562         }
3563
3564         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3565                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3566                                           &sc->bge_cdata.bge_tx_dmamap[i]);
3567                 if (error) {
3568                         int j;
3569
3570                         for (j = 0; j < BGE_STD_RX_RING_CNT; ++j) {
3571                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3572                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3573                         }
3574                         for (j = 0; j < i; ++j) {
3575                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3576                                         sc->bge_cdata.bge_tx_dmamap[j]);
3577                         }
3578                         bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3579                         sc->bge_cdata.bge_mtag = NULL;
3580
3581                         if_printf(ifp, "could not create DMA map for TX\n");
3582                         return error;
3583                 }
3584         }
3585
3586         /*
3587          * Create DMA stuffs for standard RX ring.
3588          */
3589         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3590                                     &sc->bge_cdata.bge_rx_std_ring_tag,
3591                                     &sc->bge_cdata.bge_rx_std_ring_map,
3592                                     (void **)&sc->bge_ldata.bge_rx_std_ring,
3593                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
3594         if (error) {
3595                 if_printf(ifp, "could not create std RX ring\n");
3596                 return error;
3597         }
3598
3599         /*
3600          * Create jumbo buffer pool.
3601          */
3602         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3603                 error = bge_alloc_jumbo_mem(sc);
3604                 if (error) {
3605                         if_printf(ifp, "could not create jumbo buffer pool\n");
3606                         return error;
3607                 }
3608         }
3609
3610         /*
3611          * Create DMA stuffs for RX return ring.
3612          */
3613         error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3614                                     &sc->bge_cdata.bge_rx_return_ring_tag,
3615                                     &sc->bge_cdata.bge_rx_return_ring_map,
3616                                     (void **)&sc->bge_ldata.bge_rx_return_ring,
3617                                     &sc->bge_ldata.bge_rx_return_ring_paddr);
3618         if (error) {
3619                 if_printf(ifp, "could not create RX ret ring\n");
3620                 return error;
3621         }
3622
3623         /*
3624          * Create DMA stuffs for TX ring.
3625          */
3626         error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3627                                     &sc->bge_cdata.bge_tx_ring_tag,
3628                                     &sc->bge_cdata.bge_tx_ring_map,
3629                                     (void **)&sc->bge_ldata.bge_tx_ring,
3630                                     &sc->bge_ldata.bge_tx_ring_paddr);
3631         if (error) {
3632                 if_printf(ifp, "could not create TX ring\n");
3633                 return error;
3634         }
3635
3636         /*
3637          * Create DMA stuffs for status block.
3638          */
3639         error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3640                                     &sc->bge_cdata.bge_status_tag,
3641                                     &sc->bge_cdata.bge_status_map,
3642                                     (void **)&sc->bge_ldata.bge_status_block,
3643                                     &sc->bge_ldata.bge_status_block_paddr);
3644         if (error) {
3645                 if_printf(ifp, "could not create status block\n");
3646                 return error;
3647         }
3648
3649         /*
3650          * Create DMA stuffs for statistics block.
3651          */
3652         error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3653                                     &sc->bge_cdata.bge_stats_tag,
3654                                     &sc->bge_cdata.bge_stats_map,
3655                                     (void **)&sc->bge_ldata.bge_stats,
3656                                     &sc->bge_ldata.bge_stats_paddr);
3657         if (error) {
3658                 if_printf(ifp, "could not create stats block\n");
3659                 return error;
3660         }
3661         return 0;
3662 }
3663
3664 static int
3665 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3666                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3667 {
3668         struct ifnet *ifp = &sc->arpcom.ac_if;
3669         struct bge_dmamap_arg ctx;
3670         bus_dma_segment_t seg;
3671         int error;
3672
3673         /*
3674          * Create DMA tag
3675          */
3676         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3677                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3678                                    NULL, NULL, size, 1, size, 0, tag);
3679         if (error) {
3680                 if_printf(ifp, "could not allocate dma tag\n");
3681                 return error;
3682         }
3683
3684         /*
3685          * Allocate DMA'able memory
3686          */
3687         error = bus_dmamem_alloc(*tag, addr, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3688                                  map);
3689         if (error) {
3690                 if_printf(ifp, "could not allocate dma memory\n");
3691                 bus_dma_tag_destroy(*tag);
3692                 *tag = NULL;
3693                 return error;
3694         }
3695
3696         /*
3697          * Load the DMA'able memory
3698          */
3699         ctx.bge_maxsegs = 1;
3700         ctx.bge_segs = &seg;
3701         error = bus_dmamap_load(*tag, *map, *addr, size, bge_dma_map_addr, &ctx,
3702                                 BUS_DMA_WAITOK);
3703         if (error) {
3704                 if_printf(ifp, "could not load dma memory\n");
3705                 bus_dmamem_free(*tag, *addr, *map);
3706                 bus_dma_tag_destroy(*tag);
3707                 *tag = NULL;
3708                 return error;
3709         }
3710         *paddr = ctx.bge_segs[0].ds_addr;
3711
3712         return 0;
3713 }
3714
3715 static void
3716 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3717 {
3718         if (tag != NULL) {
3719                 bus_dmamap_unload(tag, map);
3720                 bus_dmamem_free(tag, addr, map);
3721                 bus_dma_tag_destroy(tag);
3722         }
3723 }
3724
3725 /*
3726  * Grrr. The link status word in the status block does
3727  * not work correctly on the BCM5700 rev AX and BX chips,
3728  * according to all available information. Hence, we have
3729  * to enable MII interrupts in order to properly obtain
3730  * async link changes. Unfortunately, this also means that
3731  * we have to read the MAC status register to detect link
3732  * changes, thereby adding an additional register access to
3733  * the interrupt handler.
3734  *
3735  * XXX: perhaps link state detection procedure used for
3736  * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3737  */
3738 static void
3739 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3740 {
3741         struct ifnet *ifp = &sc->arpcom.ac_if;
3742         struct mii_data *mii = device_get_softc(sc->bge_miibus);
3743
3744         mii_pollstat(mii);
3745
3746         if (!sc->bge_link &&
3747             (mii->mii_media_status & IFM_ACTIVE) &&
3748             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3749                 sc->bge_link++;
3750                 if (bootverbose)
3751                         if_printf(ifp, "link UP\n");
3752         } else if (sc->bge_link &&
3753             (!(mii->mii_media_status & IFM_ACTIVE) ||
3754             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3755                 sc->bge_link = 0;
3756                 if (bootverbose)
3757                         if_printf(ifp, "link DOWN\n");
3758         }
3759
3760         /* Clear the interrupt. */
3761         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
3762         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
3763         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
3764 }
3765
3766 static void
3767 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
3768 {
3769         struct ifnet *ifp = &sc->arpcom.ac_if;
3770
3771 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3772
3773         /*
3774          * Sometimes PCS encoding errors are detected in
3775          * TBI mode (on fiber NICs), and for some reason
3776          * the chip will signal them as link changes.
3777          * If we get a link change event, but the 'PCS
3778          * encoding error' bit in the MAC status register
3779          * is set, don't bother doing a link check.
3780          * This avoids spurious "gigabit link up" messages
3781          * that sometimes appear on fiber NICs during
3782          * periods of heavy traffic.
3783          */
3784         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3785                 if (!sc->bge_link) {
3786                         sc->bge_link++;
3787                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3788                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3789                                     BGE_MACMODE_TBI_SEND_CFGS);
3790                         }
3791                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3792
3793                         if (bootverbose)
3794                                 if_printf(ifp, "link UP\n");
3795
3796                         ifp->if_link_state = LINK_STATE_UP;
3797                         if_link_state_change(ifp);
3798                 }
3799         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3800                 if (sc->bge_link) {
3801                         sc->bge_link = 0;
3802
3803                         if (bootverbose)
3804                                 if_printf(ifp, "link DOWN\n");
3805
3806                         ifp->if_link_state = LINK_STATE_DOWN;
3807                         if_link_state_change(ifp);
3808                 }
3809         }
3810
3811 #undef PCS_ENCODE_ERR
3812
3813         /* Clear the attention. */
3814         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3815             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3816             BGE_MACSTAT_LINK_CHANGED);
3817 }
3818
3819 static void
3820 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
3821 {
3822         /*
3823          * Check that the AUTOPOLL bit is set before
3824          * processing the event as a real link change.
3825          * Turning AUTOPOLL on and off in the MII read/write
3826          * functions will often trigger a link status
3827          * interrupt for no reason.
3828          */
3829         if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
3830                 struct ifnet *ifp = &sc->arpcom.ac_if;
3831                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3832
3833                 mii_pollstat(mii);
3834
3835                 if (!sc->bge_link &&
3836                     (mii->mii_media_status & IFM_ACTIVE) &&
3837                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3838                         sc->bge_link++;
3839                         if (bootverbose)
3840                                 if_printf(ifp, "link UP\n");
3841                 } else if (sc->bge_link &&
3842                     (!(mii->mii_media_status & IFM_ACTIVE) ||
3843                     IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3844                         sc->bge_link = 0;
3845                         if (bootverbose)
3846                                 if_printf(ifp, "link DOWN\n");
3847                 }
3848         }
3849
3850         /* Clear the attention. */
3851         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3852             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3853             BGE_MACSTAT_LINK_CHANGED);
3854 }
3855
3856 static int
3857 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3858 {
3859         struct bge_softc *sc = arg1;
3860
3861         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3862                                    &sc->bge_rx_coal_ticks,
3863                                    BGE_RX_COAL_TICKS_CHG);
3864 }
3865
3866 static int
3867 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3868 {
3869         struct bge_softc *sc = arg1;
3870
3871         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3872                                    &sc->bge_tx_coal_ticks,
3873                                    BGE_TX_COAL_TICKS_CHG);
3874 }
3875
3876 static int
3877 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3878 {
3879         struct bge_softc *sc = arg1;
3880
3881         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3882                                    &sc->bge_rx_max_coal_bds,
3883                                    BGE_RX_MAX_COAL_BDS_CHG);
3884 }
3885
3886 static int
3887 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3888 {
3889         struct bge_softc *sc = arg1;
3890
3891         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3892                                    &sc->bge_tx_max_coal_bds,
3893                                    BGE_TX_MAX_COAL_BDS_CHG);
3894 }
3895
3896 static int
3897 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3898                     uint32_t coal_chg_mask)
3899 {
3900         struct bge_softc *sc = arg1;
3901         struct ifnet *ifp = &sc->arpcom.ac_if;
3902         int error = 0, v;
3903
3904         lwkt_serialize_enter(ifp->if_serializer);
3905
3906         v = *coal;
3907         error = sysctl_handle_int(oidp, &v, 0, req);
3908         if (!error && req->newptr != NULL) {
3909                 if (v < 0) {
3910                         error = EINVAL;
3911                 } else {
3912                         *coal = v;
3913                         sc->bge_coal_chg |= coal_chg_mask;
3914                 }
3915         }
3916
3917         lwkt_serialize_exit(ifp->if_serializer);
3918         return error;
3919 }
3920
3921 static void
3922 bge_coal_change(struct bge_softc *sc)
3923 {
3924         struct ifnet *ifp = &sc->arpcom.ac_if;
3925         uint32_t val;
3926
3927         ASSERT_SERIALIZED(ifp->if_serializer);
3928
3929         if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
3930                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3931                             sc->bge_rx_coal_ticks);
3932                 DELAY(10);
3933                 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3934
3935                 if (bootverbose) {
3936                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3937                                   sc->bge_rx_coal_ticks);
3938                 }
3939         }
3940
3941         if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
3942                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3943                             sc->bge_tx_coal_ticks);
3944                 DELAY(10);
3945                 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3946
3947                 if (bootverbose) {
3948                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3949                                   sc->bge_tx_coal_ticks);
3950                 }
3951         }
3952
3953         if (sc->bge_coal_chg & BGE_RX_MAX_COAL_BDS_CHG) {
3954                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3955                             sc->bge_rx_max_coal_bds);
3956                 DELAY(10);
3957                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3958
3959                 if (bootverbose) {
3960                         if_printf(ifp, "rx_max_coal_bds -> %u\n",
3961                                   sc->bge_rx_max_coal_bds);
3962                 }
3963         }
3964
3965         if (sc->bge_coal_chg & BGE_TX_MAX_COAL_BDS_CHG) {
3966                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3967                             sc->bge_tx_max_coal_bds);
3968                 DELAY(10);
3969                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3970
3971                 if (bootverbose) {
3972                         if_printf(ifp, "tx_max_coal_bds -> %u\n",
3973                                   sc->bge_tx_max_coal_bds);
3974                 }
3975         }
3976
3977         sc->bge_coal_chg = 0;
3978 }
3979
3980 static void
3981 bge_enable_intr(struct bge_softc *sc)
3982 {
3983         struct ifnet *ifp = &sc->arpcom.ac_if;
3984
3985         lwkt_serialize_handler_enable(ifp->if_serializer);
3986
3987         /*
3988          * Enable interrupt.
3989          */
3990         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3991
3992         /*
3993          * Unmask the interrupt when we stop polling.
3994          */
3995         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3996
3997         /*
3998          * Trigger another interrupt, since above writing
3999          * to interrupt mailbox0 may acknowledge pending
4000          * interrupt.
4001          */
4002         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4003 }
4004
4005 static void
4006 bge_disable_intr(struct bge_softc *sc)
4007 {
4008         struct ifnet *ifp = &sc->arpcom.ac_if;
4009
4010         /*
4011          * Mask the interrupt when we start polling.
4012          */
4013         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4014
4015         /*
4016          * Acknowledge possible asserted interrupt.
4017          */
4018         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4019
4020         lwkt_serialize_handler_disable(ifp->if_serializer);
4021 }
4022
4023 static int
4024 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
4025 {
4026         uint32_t mac_addr;
4027         int ret = 1;
4028
4029         mac_addr = bge_readmem_ind(sc, 0x0c14);
4030         if ((mac_addr >> 16) == 0x484b) {
4031                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4032                 ether_addr[1] = (uint8_t)mac_addr;
4033                 mac_addr = bge_readmem_ind(sc, 0x0c18);
4034                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4035                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4036                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4037                 ether_addr[5] = (uint8_t)mac_addr;
4038                 ret = 0;
4039         }
4040         return ret;
4041 }
4042
4043 static int
4044 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
4045 {
4046         int mac_offset = BGE_EE_MAC_OFFSET;
4047
4048         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4049                 mac_offset = BGE_EE_MAC_OFFSET_5906;
4050
4051         return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4052 }
4053
4054 static int
4055 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
4056 {
4057         if (sc->bge_flags & BGE_FLAG_NO_EEPROM)
4058                 return 1;
4059
4060         return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4061                                ETHER_ADDR_LEN);
4062 }
4063
4064 static int
4065 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
4066 {
4067         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
4068                 /* NOTE: Order is critical */
4069                 bge_get_eaddr_mem,
4070                 bge_get_eaddr_nvram,
4071                 bge_get_eaddr_eeprom,
4072                 NULL
4073         };
4074         const bge_eaddr_fcn_t *func;
4075
4076         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
4077                 if ((*func)(sc, eaddr) == 0)
4078                         break;
4079         }
4080         return (*func == NULL ? ENXIO : 0);
4081 }