2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
28 * $DragonFly: src/sys/dev/netif/jme/if_jme.c,v 1.6 2008/09/13 03:12:23 sephe Exp $
31 #include "opt_ethernet.h"
33 #include <sys/param.h>
34 #include <sys/endian.h>
35 #include <sys/kernel.h>
37 #include <sys/interrupt.h>
38 #include <sys/malloc.h>
41 #include <sys/serialize.h>
42 #include <sys/socket.h>
43 #include <sys/sockio.h>
44 #include <sys/sysctl.h>
46 #include <net/ethernet.h>
49 #include <net/if_arp.h>
50 #include <net/if_dl.h>
51 #include <net/if_media.h>
52 #include <net/ifq_var.h>
53 #include <net/vlan/if_vlan_var.h>
54 #include <net/vlan/if_vlan_ether.h>
56 #include <dev/netif/mii_layer/miivar.h>
58 #include <bus/pci/pcireg.h>
59 #include <bus/pci/pcivar.h>
60 #include <bus/pci/pcidevs.h>
62 #include <dev/netif/jme/if_jmereg.h>
63 #include <dev/netif/jme/if_jmevar.h>
65 #include "miibus_if.h"
67 /* Define the following to disable printing Rx errors. */
68 #undef JME_SHOW_ERRORS
70 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
72 static int jme_probe(device_t);
73 static int jme_attach(device_t);
74 static int jme_detach(device_t);
75 static int jme_shutdown(device_t);
76 static int jme_suspend(device_t);
77 static int jme_resume(device_t);
79 static int jme_miibus_readreg(device_t, int, int);
80 static int jme_miibus_writereg(device_t, int, int, int);
81 static void jme_miibus_statchg(device_t);
83 static void jme_init(void *);
84 static int jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
85 static void jme_start(struct ifnet *);
86 static void jme_watchdog(struct ifnet *);
87 static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
88 static int jme_mediachange(struct ifnet *);
90 static void jme_intr(void *);
91 static void jme_txeof(struct jme_softc *);
92 static void jme_rxeof(struct jme_softc *);
94 static int jme_dma_alloc(struct jme_softc *);
95 static void jme_dma_free(struct jme_softc *);
96 static void jme_dmamap_ring_cb(void *, bus_dma_segment_t *, int, int);
97 static void jme_dmamap_buf_cb(void *, bus_dma_segment_t *, int,
99 static int jme_init_rx_ring(struct jme_softc *);
100 static void jme_init_tx_ring(struct jme_softc *);
101 static void jme_init_ssb(struct jme_softc *);
102 static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *, int);
103 static int jme_encap(struct jme_softc *, struct mbuf **);
104 static void jme_rxpkt(struct jme_softc *);
106 static void jme_tick(void *);
107 static void jme_stop(struct jme_softc *);
108 static void jme_reset(struct jme_softc *);
109 static void jme_set_vlan(struct jme_softc *);
110 static void jme_set_filter(struct jme_softc *);
111 static void jme_stop_tx(struct jme_softc *);
112 static void jme_stop_rx(struct jme_softc *);
113 static void jme_mac_config(struct jme_softc *);
114 static void jme_reg_macaddr(struct jme_softc *, uint8_t[]);
115 static int jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
116 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
118 static void jme_setwol(struct jme_softc *);
119 static void jme_setlinkspeed(struct jme_softc *);
122 static void jme_sysctl_node(struct jme_softc *);
123 static int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS);
124 static int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
125 static int sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS);
126 static int sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
129 * Devices supported by this driver.
131 static const struct jme_dev {
132 uint16_t jme_vendorid;
133 uint16_t jme_deviceid;
135 const char *jme_name;
137 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
139 "JMicron Inc, JMC250 Gigabit Ethernet" },
140 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
142 "JMicron Inc, JMC260 Fast Ethernet" },
146 static device_method_t jme_methods[] = {
147 /* Device interface. */
148 DEVMETHOD(device_probe, jme_probe),
149 DEVMETHOD(device_attach, jme_attach),
150 DEVMETHOD(device_detach, jme_detach),
151 DEVMETHOD(device_shutdown, jme_shutdown),
152 DEVMETHOD(device_suspend, jme_suspend),
153 DEVMETHOD(device_resume, jme_resume),
156 DEVMETHOD(bus_print_child, bus_generic_print_child),
157 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
160 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
161 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
162 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
167 static driver_t jme_driver = {
170 sizeof(struct jme_softc)
173 static devclass_t jme_devclass;
175 DECLARE_DUMMY_MODULE(if_jme);
176 MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
177 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, 0, 0);
178 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, 0, 0);
181 * Read a PHY register on the MII of the JMC250.
184 jme_miibus_readreg(device_t dev, int phy, int reg)
186 struct jme_softc *sc = device_get_softc(dev);
190 /* For FPGA version, PHY address 0 should be ignored. */
191 if (sc->jme_caps & JME_CAP_FPGA) {
195 if (sc->jme_phyaddr != phy)
199 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
200 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
202 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
204 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
208 device_printf(sc->jme_dev, "phy read timeout: "
209 "phy %d, reg %d\n", phy, reg);
213 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
217 * Write a PHY register on the MII of the JMC250.
220 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
222 struct jme_softc *sc = device_get_softc(dev);
225 /* For FPGA version, PHY address 0 should be ignored. */
226 if (sc->jme_caps & JME_CAP_FPGA) {
230 if (sc->jme_phyaddr != phy)
234 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
235 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
236 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
238 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
240 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
244 device_printf(sc->jme_dev, "phy write timeout: "
245 "phy %d, reg %d\n", phy, reg);
252 * Callback from MII layer when media changes.
255 jme_miibus_statchg(device_t dev)
257 struct jme_softc *sc = device_get_softc(dev);
258 struct ifnet *ifp = &sc->arpcom.ac_if;
259 struct mii_data *mii;
260 struct jme_txdesc *txd;
264 ASSERT_SERIALIZED(ifp->if_serializer);
266 if ((ifp->if_flags & IFF_RUNNING) == 0)
269 mii = device_get_softc(sc->jme_miibus);
271 sc->jme_flags &= ~JME_FLAG_LINK;
272 if ((mii->mii_media_status & IFM_AVALID) != 0) {
273 switch (IFM_SUBTYPE(mii->mii_media_active)) {
276 sc->jme_flags |= JME_FLAG_LINK;
279 if (sc->jme_caps & JME_CAP_FASTETH)
281 sc->jme_flags |= JME_FLAG_LINK;
289 * Disabling Rx/Tx MACs have a side-effect of resetting
290 * JME_TXNDA/JME_RXNDA register to the first address of
291 * Tx/Rx descriptor address. So driver should reset its
292 * internal procucer/consumer pointer and reclaim any
293 * allocated resources. Note, just saving the value of
294 * JME_TXNDA and JME_RXNDA registers before stopping MAC
295 * and restoring JME_TXNDA/JME_RXNDA register is not
296 * sufficient to make sure correct MAC state because
297 * stopping MAC operation can take a while and hardware
298 * might have updated JME_TXNDA/JME_RXNDA registers
299 * during the stop operation.
302 /* Disable interrupts */
303 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
306 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
308 callout_stop(&sc->jme_tick_ch);
310 /* Stop receiver/transmitter. */
315 if (sc->jme_cdata.jme_rxhead != NULL)
316 m_freem(sc->jme_cdata.jme_rxhead);
317 JME_RXCHAIN_RESET(sc);
320 if (sc->jme_cdata.jme_tx_cnt != 0) {
321 /* Remove queued packets for transmit. */
322 for (i = 0; i < JME_TX_RING_CNT; i++) {
323 txd = &sc->jme_cdata.jme_txdesc[i];
324 if (txd->tx_m != NULL) {
326 sc->jme_cdata.jme_tx_tag,
337 * Reuse configured Rx descriptors and reset
338 * procuder/consumer index.
340 sc->jme_cdata.jme_rx_cons = 0;
342 jme_init_tx_ring(sc);
344 /* Initialize shadow status block. */
347 /* Program MAC with resolved speed/duplex/flow-control. */
348 if (sc->jme_flags & JME_FLAG_LINK) {
351 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr);
352 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
354 /* Set Tx ring address to the hardware. */
355 paddr = JME_TX_RING_ADDR(sc, 0);
356 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
357 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
359 /* Set Rx ring address to the hardware. */
360 paddr = JME_RX_RING_ADDR(sc, 0);
361 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
362 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
364 /* Restart receiver/transmitter. */
365 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
367 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
370 ifp->if_flags |= IFF_RUNNING;
371 ifp->if_flags &= ~IFF_OACTIVE;
372 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
374 /* Reenable interrupts. */
375 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
379 * Get the current interface media status.
382 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
384 struct jme_softc *sc = ifp->if_softc;
385 struct mii_data *mii = device_get_softc(sc->jme_miibus);
387 ASSERT_SERIALIZED(ifp->if_serializer);
390 ifmr->ifm_status = mii->mii_media_status;
391 ifmr->ifm_active = mii->mii_media_active;
395 * Set hardware to newly-selected media.
398 jme_mediachange(struct ifnet *ifp)
400 struct jme_softc *sc = ifp->if_softc;
401 struct mii_data *mii = device_get_softc(sc->jme_miibus);
404 ASSERT_SERIALIZED(ifp->if_serializer);
406 if (mii->mii_instance != 0) {
407 struct mii_softc *miisc;
409 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
410 mii_phy_reset(miisc);
412 error = mii_mediachg(mii);
418 jme_probe(device_t dev)
420 const struct jme_dev *sp;
423 vid = pci_get_vendor(dev);
424 did = pci_get_device(dev);
425 for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
426 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
427 struct jme_softc *sc = device_get_softc(dev);
429 sc->jme_caps = sp->jme_caps;
430 device_set_desc(dev, sp->jme_name);
438 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
444 for (i = JME_TIMEOUT; i > 0; i--) {
445 reg = CSR_READ_4(sc, JME_SMBCSR);
446 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
452 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
456 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
457 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
458 for (i = JME_TIMEOUT; i > 0; i--) {
460 reg = CSR_READ_4(sc, JME_SMBINTF);
461 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
466 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
470 reg = CSR_READ_4(sc, JME_SMBINTF);
471 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
477 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
479 uint8_t fup, reg, val;
484 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
485 fup != JME_EEPROM_SIG0)
487 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
488 fup != JME_EEPROM_SIG1)
492 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
494 /* Check for the end of EEPROM descriptor. */
495 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
497 if ((uint8_t)JME_EEPROM_MKDESC(JME_EEPROM_FUNC0,
498 JME_EEPROM_PAGE_BAR1) == fup) {
499 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0)
501 if (reg >= JME_PAR0 &&
502 reg < JME_PAR0 + ETHER_ADDR_LEN) {
503 if (jme_eeprom_read_byte(sc, offset + 2,
506 eaddr[reg - JME_PAR0] = val;
510 /* Try next eeprom descriptor. */
511 offset += JME_EEPROM_DESC_BYTES;
512 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
514 if (match == ETHER_ADDR_LEN)
521 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
525 /* Read station address. */
526 par0 = CSR_READ_4(sc, JME_PAR0);
527 par1 = CSR_READ_4(sc, JME_PAR1);
529 if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
530 device_printf(sc->jme_dev,
531 "generating fake ethernet address.\n");
532 par0 = karc4random();
533 /* Set OUI to JMicron. */
537 eaddr[3] = (par0 >> 16) & 0xff;
538 eaddr[4] = (par0 >> 8) & 0xff;
539 eaddr[5] = par0 & 0xff;
541 eaddr[0] = (par0 >> 0) & 0xFF;
542 eaddr[1] = (par0 >> 8) & 0xFF;
543 eaddr[2] = (par0 >> 16) & 0xFF;
544 eaddr[3] = (par0 >> 24) & 0xFF;
545 eaddr[4] = (par1 >> 0) & 0xFF;
546 eaddr[5] = (par1 >> 8) & 0xFF;
551 jme_attach(device_t dev)
553 struct jme_softc *sc = device_get_softc(dev);
554 struct ifnet *ifp = &sc->arpcom.ac_if;
558 uint8_t eaddr[ETHER_ADDR_LEN];
561 ifp = &sc->arpcom.ac_if;
562 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
564 callout_init(&sc->jme_tick_ch);
567 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
570 irq = pci_read_config(dev, PCIR_INTLINE, 4);
571 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
573 device_printf(dev, "chip is in D%d power mode "
574 "-- setting to D0\n", pci_get_powerstate(dev));
576 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
578 pci_write_config(dev, PCIR_INTLINE, irq, 4);
579 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
581 #endif /* !BURN_BRIDGE */
583 /* Enable bus mastering */
584 pci_enable_busmaster(dev);
589 * JMC250 supports both memory mapped and I/O register space
590 * access. Because I/O register access should use different
591 * BARs to access registers it's waste of time to use I/O
592 * register spce access. JMC250 uses 16K to map entire memory
595 sc->jme_mem_rid = JME_PCIR_BAR;
596 sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
597 &sc->jme_mem_rid, RF_ACTIVE);
598 if (sc->jme_mem_res == NULL) {
599 device_printf(dev, "can't allocate IO memory\n");
602 sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
603 sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
609 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
611 RF_SHAREABLE | RF_ACTIVE);
612 if (sc->jme_irq_res == NULL) {
613 device_printf(dev, "can't allocate irq\n");
619 * Extract FPGA revision
621 reg = CSR_READ_4(sc, JME_CHIPMODE);
622 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
624 sc->jme_caps |= JME_CAP_FPGA;
626 device_printf(dev, "FPGA revision : 0x%04x\n",
627 (reg & CHIPMODE_FPGA_REV_MASK) >>
628 CHIPMODE_FPGA_REV_SHIFT);
632 /* Reset the ethernet controller. */
635 /* Get station address. */
636 reg = CSR_READ_4(sc, JME_SMBCSR);
637 if (reg & SMBCSR_EEPROM_PRESENT)
638 error = jme_eeprom_macaddr(sc, eaddr);
639 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
640 if (error != 0 && (bootverbose)) {
641 device_printf(dev, "ethernet hardware address "
642 "not found in EEPROM.\n");
644 jme_reg_macaddr(sc, eaddr);
649 * Integrated JR0211 has fixed PHY address whereas FPGA version
650 * requires PHY probing to get correct PHY address.
652 if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
653 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
654 GPREG0_PHY_ADDR_MASK;
656 device_printf(dev, "PHY is at address %d.\n",
663 /* Set max allowable DMA size. */
664 pcie_ptr = pci_get_pciecap_ptr(dev);
668 sc->jme_caps |= JME_CAP_PCIE;
669 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
671 device_printf(dev, "Read request size : %d bytes.\n",
672 128 << ((ctrl >> 12) & 0x07));
673 device_printf(dev, "TLP payload size : %d bytes.\n",
674 128 << ((ctrl >> 5) & 0x07));
676 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
677 case PCIEM_DEVCTL_MAX_READRQ_128:
678 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
680 case PCIEM_DEVCTL_MAX_READRQ_256:
681 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
684 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
687 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
689 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
690 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
694 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
695 sc->jme_caps |= JME_CAP_PMCAP;
703 /* Allocate DMA stuffs */
704 error = jme_dma_alloc(sc);
709 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
710 ifp->if_init = jme_init;
711 ifp->if_ioctl = jme_ioctl;
712 ifp->if_start = jme_start;
713 ifp->if_watchdog = jme_watchdog;
714 ifq_set_maxlen(&ifp->if_snd, JME_TX_RING_CNT - 1);
715 ifq_set_ready(&ifp->if_snd);
717 /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
718 ifp->if_capabilities = IFCAP_HWCSUM |
720 IFCAP_VLAN_HWTAGGING;
721 ifp->if_hwassist = JME_CSUM_FEATURES;
722 ifp->if_capenable = ifp->if_capabilities;
724 /* Set up MII bus. */
725 error = mii_phy_probe(dev, &sc->jme_miibus,
726 jme_mediachange, jme_mediastatus);
728 device_printf(dev, "no PHY found!\n");
733 * Save PHYADDR for FPGA mode PHY.
735 if (sc->jme_caps & JME_CAP_FPGA) {
736 struct mii_data *mii = device_get_softc(sc->jme_miibus);
738 if (mii->mii_instance != 0) {
739 struct mii_softc *miisc;
741 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
742 if (miisc->mii_phy != 0) {
743 sc->jme_phyaddr = miisc->mii_phy;
747 if (sc->jme_phyaddr != 0) {
748 device_printf(sc->jme_dev,
749 "FPGA PHY is at %d\n", sc->jme_phyaddr);
751 jme_miibus_writereg(dev, sc->jme_phyaddr, 27,
757 ether_ifattach(ifp, eaddr, NULL);
759 /* Tell the upper layer(s) we support long frames. */
760 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
762 error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE, jme_intr, sc,
763 &sc->jme_irq_handle, ifp->if_serializer);
765 device_printf(dev, "could not set up interrupt handler.\n");
770 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->jme_irq_res));
771 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
779 jme_detach(device_t dev)
781 struct jme_softc *sc = device_get_softc(dev);
783 if (device_is_attached(dev)) {
784 struct ifnet *ifp = &sc->arpcom.ac_if;
786 lwkt_serialize_enter(ifp->if_serializer);
788 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle);
789 lwkt_serialize_exit(ifp->if_serializer);
794 if (sc->jme_sysctl_tree != NULL)
795 sysctl_ctx_free(&sc->jme_sysctl_ctx);
797 if (sc->jme_miibus != NULL)
798 device_delete_child(dev, sc->jme_miibus);
799 bus_generic_detach(dev);
801 if (sc->jme_irq_res != NULL) {
802 bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
806 if (sc->jme_mem_res != NULL) {
807 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
817 jme_sysctl_node(struct jme_softc *sc)
821 sysctl_ctx_init(&sc->jme_sysctl_ctx);
822 sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
823 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
824 device_get_nameunit(sc->jme_dev),
826 if (sc->jme_sysctl_tree == NULL) {
827 device_printf(sc->jme_dev, "can't add sysctl node\n");
831 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
832 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
833 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_to,
834 0, sysctl_hw_jme_tx_coal_to, "I", "jme tx coalescing timeout");
836 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
837 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
838 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_pkt,
839 0, sysctl_hw_jme_tx_coal_pkt, "I", "jme tx coalescing packet");
841 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
842 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
843 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_to,
844 0, sysctl_hw_jme_rx_coal_to, "I", "jme rx coalescing timeout");
846 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
847 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
848 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_pkt,
849 0, sysctl_hw_jme_rx_coal_pkt, "I", "jme rx coalescing packet");
851 /* Pull in device tunables. */
852 sc->jme_process_limit = JME_PROC_DEFAULT;
854 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
855 error = resource_int_value(device_get_name(sc->jme_dev),
856 device_get_unit(sc->jme_dev), "tx_coal_to", &sc->jme_tx_coal_to);
858 if (sc->jme_tx_coal_to < PCCTX_COAL_TO_MIN ||
859 sc->jme_tx_coal_to > PCCTX_COAL_TO_MAX) {
860 device_printf(sc->jme_dev,
861 "tx_coal_to value out of range; "
862 "using default: %d\n", PCCTX_COAL_TO_DEFAULT);
863 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
867 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
868 error = resource_int_value(device_get_name(sc->jme_dev),
869 device_get_unit(sc->jme_dev), "tx_coal_pkt", &sc->jme_tx_coal_to);
871 if (sc->jme_tx_coal_pkt < PCCTX_COAL_PKT_MIN ||
872 sc->jme_tx_coal_pkt > PCCTX_COAL_PKT_MAX) {
873 device_printf(sc->jme_dev,
874 "tx_coal_pkt value out of range; "
875 "using default: %d\n", PCCTX_COAL_PKT_DEFAULT);
876 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
880 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
881 error = resource_int_value(device_get_name(sc->jme_dev),
882 device_get_unit(sc->jme_dev), "rx_coal_to", &sc->jme_rx_coal_to);
884 if (sc->jme_rx_coal_to < PCCRX_COAL_TO_MIN ||
885 sc->jme_rx_coal_to > PCCRX_COAL_TO_MAX) {
886 device_printf(sc->jme_dev,
887 "rx_coal_to value out of range; "
888 "using default: %d\n", PCCRX_COAL_TO_DEFAULT);
889 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
893 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
894 error = resource_int_value(device_get_name(sc->jme_dev),
895 device_get_unit(sc->jme_dev), "rx_coal_pkt", &sc->jme_rx_coal_to);
897 if (sc->jme_rx_coal_pkt < PCCRX_COAL_PKT_MIN ||
898 sc->jme_rx_coal_pkt > PCCRX_COAL_PKT_MAX) {
899 device_printf(sc->jme_dev,
900 "tx_coal_pkt value out of range; "
901 "using default: %d\n", PCCRX_COAL_PKT_DEFAULT);
902 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
908 jme_dmamap_ring_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
913 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
914 *((bus_addr_t *)arg) = segs->ds_addr;
918 jme_dmamap_buf_cb(void *xctx, bus_dma_segment_t *segs, int nsegs,
919 bus_size_t mapsz __unused, int error)
921 struct jme_dmamap_ctx *ctx = xctx;
927 if (nsegs > ctx->nsegs) {
933 for (i = 0; i < nsegs; ++i)
934 ctx->segs[i] = segs[i];
938 jme_dma_alloc(struct jme_softc *sc)
940 struct jme_txdesc *txd;
941 struct jme_rxdesc *rxd;
942 bus_addr_t busaddr, lowaddr, rx_ring_end, tx_ring_end;
945 lowaddr = BUS_SPACE_MAXADDR;
948 /* Create parent ring tag. */
949 error = bus_dma_tag_create(NULL,/* parent */
950 1, 0, /* algnmnt, boundary */
951 lowaddr, /* lowaddr */
952 BUS_SPACE_MAXADDR, /* highaddr */
953 NULL, NULL, /* filter, filterarg */
954 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
956 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
958 &sc->jme_cdata.jme_ring_tag);
960 device_printf(sc->jme_dev,
961 "could not create parent ring DMA tag.\n");
966 * Create DMA stuffs for TX ring
969 /* Create tag for Tx ring. */
970 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */
971 JME_TX_RING_ALIGN, 0, /* algnmnt, boundary */
972 BUS_SPACE_MAXADDR, /* lowaddr */
973 BUS_SPACE_MAXADDR, /* highaddr */
974 NULL, NULL, /* filter, filterarg */
975 JME_TX_RING_SIZE, /* maxsize */
977 JME_TX_RING_SIZE, /* maxsegsize */
979 &sc->jme_cdata.jme_tx_ring_tag);
981 device_printf(sc->jme_dev,
982 "could not allocate Tx ring DMA tag.\n");
986 /* Allocate DMA'able memory for TX ring */
987 error = bus_dmamem_alloc(sc->jme_cdata.jme_tx_ring_tag,
988 (void **)&sc->jme_rdata.jme_tx_ring,
989 BUS_DMA_WAITOK | BUS_DMA_ZERO,
990 &sc->jme_cdata.jme_tx_ring_map);
992 device_printf(sc->jme_dev,
993 "could not allocate DMA'able memory for Tx ring.\n");
994 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
995 sc->jme_cdata.jme_tx_ring_tag = NULL;
999 /* Load the DMA map for Tx ring. */
1000 error = bus_dmamap_load(sc->jme_cdata.jme_tx_ring_tag,
1001 sc->jme_cdata.jme_tx_ring_map, sc->jme_rdata.jme_tx_ring,
1002 JME_TX_RING_SIZE, jme_dmamap_ring_cb, &busaddr, BUS_DMA_NOWAIT);
1004 device_printf(sc->jme_dev,
1005 "could not load DMA'able memory for Tx ring.\n");
1006 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1007 sc->jme_rdata.jme_tx_ring,
1008 sc->jme_cdata.jme_tx_ring_map);
1009 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1010 sc->jme_cdata.jme_tx_ring_tag = NULL;
1013 sc->jme_rdata.jme_tx_ring_paddr = busaddr;
1016 * Create DMA stuffs for RX ring
1019 /* Create tag for Rx ring. */
1020 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */
1021 JME_RX_RING_ALIGN, 0, /* algnmnt, boundary */
1022 lowaddr, /* lowaddr */
1023 BUS_SPACE_MAXADDR, /* highaddr */
1024 NULL, NULL, /* filter, filterarg */
1025 JME_RX_RING_SIZE, /* maxsize */
1027 JME_RX_RING_SIZE, /* maxsegsize */
1029 &sc->jme_cdata.jme_rx_ring_tag);
1031 device_printf(sc->jme_dev,
1032 "could not allocate Rx ring DMA tag.\n");
1036 /* Allocate DMA'able memory for RX ring */
1037 error = bus_dmamem_alloc(sc->jme_cdata.jme_rx_ring_tag,
1038 (void **)&sc->jme_rdata.jme_rx_ring,
1039 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1040 &sc->jme_cdata.jme_rx_ring_map);
1042 device_printf(sc->jme_dev,
1043 "could not allocate DMA'able memory for Rx ring.\n");
1044 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag);
1045 sc->jme_cdata.jme_rx_ring_tag = NULL;
1049 /* Load the DMA map for Rx ring. */
1050 error = bus_dmamap_load(sc->jme_cdata.jme_rx_ring_tag,
1051 sc->jme_cdata.jme_rx_ring_map, sc->jme_rdata.jme_rx_ring,
1052 JME_RX_RING_SIZE, jme_dmamap_ring_cb, &busaddr, BUS_DMA_NOWAIT);
1054 device_printf(sc->jme_dev,
1055 "could not load DMA'able memory for Rx ring.\n");
1056 bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag,
1057 sc->jme_rdata.jme_rx_ring,
1058 sc->jme_cdata.jme_rx_ring_map);
1059 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag);
1060 sc->jme_cdata.jme_rx_ring_tag = NULL;
1063 sc->jme_rdata.jme_rx_ring_paddr = busaddr;
1065 /* Tx/Rx descriptor queue should reside within 4GB boundary. */
1066 tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr + JME_TX_RING_SIZE;
1067 rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr + JME_RX_RING_SIZE;
1068 if ((JME_ADDR_HI(tx_ring_end) !=
1069 JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) ||
1070 (JME_ADDR_HI(rx_ring_end) !=
1071 JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) {
1072 device_printf(sc->jme_dev, "4GB boundary crossed, "
1073 "switching to 32bit DMA address mode.\n");
1075 /* Limit DMA address space to 32bit and try again. */
1076 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1080 /* Create parent buffer tag. */
1081 error = bus_dma_tag_create(NULL,/* parent */
1082 1, 0, /* algnmnt, boundary */
1083 BUS_SPACE_MAXADDR, /* lowaddr */
1084 BUS_SPACE_MAXADDR, /* highaddr */
1085 NULL, NULL, /* filter, filterarg */
1086 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1088 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1090 &sc->jme_cdata.jme_buffer_tag);
1092 device_printf(sc->jme_dev,
1093 "could not create parent buffer DMA tag.\n");
1098 * Create DMA stuffs for shadow status block
1101 /* Create shadow status block tag. */
1102 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1103 JME_SSB_ALIGN, 0, /* algnmnt, boundary */
1104 BUS_SPACE_MAXADDR, /* lowaddr */
1105 BUS_SPACE_MAXADDR, /* highaddr */
1106 NULL, NULL, /* filter, filterarg */
1107 JME_SSB_SIZE, /* maxsize */
1109 JME_SSB_SIZE, /* maxsegsize */
1111 &sc->jme_cdata.jme_ssb_tag);
1113 device_printf(sc->jme_dev,
1114 "could not create shared status block DMA tag.\n");
1118 /* Allocate DMA'able memory for shared status block. */
1119 error = bus_dmamem_alloc(sc->jme_cdata.jme_ssb_tag,
1120 (void **)&sc->jme_rdata.jme_ssb_block,
1121 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1122 &sc->jme_cdata.jme_ssb_map);
1124 device_printf(sc->jme_dev, "could not allocate DMA'able "
1125 "memory for shared status block.\n");
1126 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1127 sc->jme_cdata.jme_ssb_tag = NULL;
1131 /* Load the DMA map for shared status block */
1132 error = bus_dmamap_load(sc->jme_cdata.jme_ssb_tag,
1133 sc->jme_cdata.jme_ssb_map, sc->jme_rdata.jme_ssb_block,
1134 JME_SSB_SIZE, jme_dmamap_ring_cb, &busaddr, BUS_DMA_NOWAIT);
1136 device_printf(sc->jme_dev, "could not load DMA'able memory "
1137 "for shared status block.\n");
1138 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1139 sc->jme_rdata.jme_ssb_block,
1140 sc->jme_cdata.jme_ssb_map);
1141 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1142 sc->jme_cdata.jme_ssb_tag = NULL;
1145 sc->jme_rdata.jme_ssb_block_paddr = busaddr;
1148 * Create DMA stuffs for TX buffers
1151 /* Create tag for Tx buffers. */
1152 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1153 1, 0, /* algnmnt, boundary */
1154 BUS_SPACE_MAXADDR, /* lowaddr */
1155 BUS_SPACE_MAXADDR, /* highaddr */
1156 NULL, NULL, /* filter, filterarg */
1157 JME_TSO_MAXSIZE, /* maxsize */
1158 JME_MAXTXSEGS, /* nsegments */
1159 JME_TSO_MAXSEGSIZE, /* maxsegsize */
1161 &sc->jme_cdata.jme_tx_tag);
1163 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1167 /* Create DMA maps for Tx buffers. */
1168 for (i = 0; i < JME_TX_RING_CNT; i++) {
1169 txd = &sc->jme_cdata.jme_txdesc[i];
1170 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag, 0,
1175 device_printf(sc->jme_dev,
1176 "could not create %dth Tx dmamap.\n", i);
1178 for (j = 0; j < i; ++j) {
1179 txd = &sc->jme_cdata.jme_txdesc[j];
1180 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1183 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1184 sc->jme_cdata.jme_tx_tag = NULL;
1190 * Create DMA stuffs for RX buffers
1193 /* Create tag for Rx buffers. */
1194 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1195 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
1196 BUS_SPACE_MAXADDR, /* lowaddr */
1197 BUS_SPACE_MAXADDR, /* highaddr */
1198 NULL, NULL, /* filter, filterarg */
1199 MCLBYTES, /* maxsize */
1201 MCLBYTES, /* maxsegsize */
1203 &sc->jme_cdata.jme_rx_tag);
1205 device_printf(sc->jme_dev, "could not create Rx DMA tag.\n");
1209 /* Create DMA maps for Rx buffers. */
1210 error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0,
1211 &sc->jme_cdata.jme_rx_sparemap);
1213 device_printf(sc->jme_dev,
1214 "could not create spare Rx dmamap.\n");
1215 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag);
1216 sc->jme_cdata.jme_rx_tag = NULL;
1219 for (i = 0; i < JME_RX_RING_CNT; i++) {
1220 rxd = &sc->jme_cdata.jme_rxdesc[i];
1221 error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0,
1226 device_printf(sc->jme_dev,
1227 "could not create %dth Rx dmamap.\n", i);
1229 for (j = 0; j < i; ++j) {
1230 rxd = &sc->jme_cdata.jme_rxdesc[j];
1231 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1234 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1235 sc->jme_cdata.jme_rx_sparemap);
1236 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag);
1237 sc->jme_cdata.jme_rx_tag = NULL;
1245 jme_dma_free(struct jme_softc *sc)
1247 struct jme_txdesc *txd;
1248 struct jme_rxdesc *rxd;
1252 if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1253 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1254 sc->jme_cdata.jme_tx_ring_map);
1255 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1256 sc->jme_rdata.jme_tx_ring,
1257 sc->jme_cdata.jme_tx_ring_map);
1258 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1259 sc->jme_cdata.jme_tx_ring_tag = NULL;
1263 if (sc->jme_cdata.jme_rx_ring_tag != NULL) {
1264 bus_dmamap_unload(sc->jme_cdata.jme_rx_ring_tag,
1265 sc->jme_cdata.jme_rx_ring_map);
1266 bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag,
1267 sc->jme_rdata.jme_rx_ring,
1268 sc->jme_cdata.jme_rx_ring_map);
1269 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag);
1270 sc->jme_cdata.jme_rx_ring_tag = NULL;
1274 if (sc->jme_cdata.jme_tx_tag != NULL) {
1275 for (i = 0; i < JME_TX_RING_CNT; i++) {
1276 txd = &sc->jme_cdata.jme_txdesc[i];
1277 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1280 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1281 sc->jme_cdata.jme_tx_tag = NULL;
1285 if (sc->jme_cdata.jme_rx_tag != NULL) {
1286 for (i = 0; i < JME_RX_RING_CNT; i++) {
1287 rxd = &sc->jme_cdata.jme_rxdesc[i];
1288 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1291 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1292 sc->jme_cdata.jme_rx_sparemap);
1293 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag);
1294 sc->jme_cdata.jme_rx_tag = NULL;
1297 /* Shadow status block. */
1298 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1299 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1300 sc->jme_cdata.jme_ssb_map);
1301 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1302 sc->jme_rdata.jme_ssb_block,
1303 sc->jme_cdata.jme_ssb_map);
1304 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1305 sc->jme_cdata.jme_ssb_tag = NULL;
1308 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1309 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1310 sc->jme_cdata.jme_buffer_tag = NULL;
1312 if (sc->jme_cdata.jme_ring_tag != NULL) {
1313 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1314 sc->jme_cdata.jme_ring_tag = NULL;
1319 * Make sure the interface is stopped at reboot time.
1322 jme_shutdown(device_t dev)
1324 return jme_suspend(dev);
1329 * Unlike other ethernet controllers, JMC250 requires
1330 * explicit resetting link speed to 10/100Mbps as gigabit
1331 * link will cunsume more power than 375mA.
1332 * Note, we reset the link speed to 10/100Mbps with
1333 * auto-negotiation but we don't know whether that operation
1334 * would succeed or not as we have no control after powering
1335 * off. If the renegotiation fail WOL may not work. Running
1336 * at 1Gbps draws more power than 375mA at 3.3V which is
1337 * specified in PCI specification and that would result in
1338 * complete shutdowning power to ethernet controller.
1341 * Save current negotiated media speed/duplex/flow-control
1342 * to softc and restore the same link again after resuming.
1343 * PHY handling such as power down/resetting to 100Mbps
1344 * may be better handled in suspend method in phy driver.
1347 jme_setlinkspeed(struct jme_softc *sc)
1349 struct mii_data *mii;
1352 JME_LOCK_ASSERT(sc);
1354 mii = device_get_softc(sc->jme_miibus);
1357 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1358 switch IFM_SUBTYPE(mii->mii_media_active) {
1368 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1369 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1370 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1371 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1372 BMCR_AUTOEN | BMCR_STARTNEG);
1375 /* Poll link state until jme(4) get a 10/100 link. */
1376 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1378 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1379 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1389 pause("jmelnk", hz);
1392 if (i == MII_ANEGTICKS_GIGE)
1393 device_printf(sc->jme_dev, "establishing link failed, "
1394 "WOL may not work!");
1397 * No link, force MAC to have 100Mbps, full-duplex link.
1398 * This is the last resort and may/may not work.
1400 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1401 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1406 jme_setwol(struct jme_softc *sc)
1408 struct ifnet *ifp = &sc->arpcom.ac_if;
1413 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1414 /* No PME capability, PHY power down. */
1415 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1416 MII_BMCR, BMCR_PDOWN);
1420 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1421 pmcs = CSR_READ_4(sc, JME_PMCS);
1422 pmcs &= ~PMCS_WOL_ENB_MASK;
1423 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1424 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1425 /* Enable PME message. */
1426 gpr |= GPREG0_PME_ENB;
1427 /* For gigabit controllers, reset link speed to 10/100. */
1428 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
1429 jme_setlinkspeed(sc);
1432 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1433 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1436 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1437 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1438 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1439 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1440 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1441 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1442 /* No WOL, PHY power down. */
1443 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1444 MII_BMCR, BMCR_PDOWN);
1450 jme_suspend(device_t dev)
1452 struct jme_softc *sc = device_get_softc(dev);
1453 struct ifnet *ifp = &sc->arpcom.ac_if;
1455 lwkt_serialize_enter(ifp->if_serializer);
1460 lwkt_serialize_exit(ifp->if_serializer);
1466 jme_resume(device_t dev)
1468 struct jme_softc *sc = device_get_softc(dev);
1469 struct ifnet *ifp = &sc->arpcom.ac_if;
1474 lwkt_serialize_enter(ifp->if_serializer);
1477 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1480 pmstat = pci_read_config(sc->jme_dev,
1481 pmc + PCIR_POWER_STATUS, 2);
1482 /* Disable PME clear PME status. */
1483 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1484 pci_write_config(sc->jme_dev,
1485 pmc + PCIR_POWER_STATUS, pmstat, 2);
1489 if (ifp->if_flags & IFF_UP)
1492 lwkt_serialize_exit(ifp->if_serializer);
1498 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1500 struct jme_txdesc *txd;
1501 struct jme_desc *desc;
1503 struct jme_dmamap_ctx ctx;
1504 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1509 M_ASSERTPKTHDR((*m_head));
1511 prod = sc->jme_cdata.jme_tx_prod;
1512 txd = &sc->jme_cdata.jme_txdesc[prod];
1514 maxsegs = (JME_TX_RING_CNT - sc->jme_cdata.jme_tx_cnt) -
1516 if (maxsegs > JME_MAXTXSEGS)
1517 maxsegs = JME_MAXTXSEGS;
1518 KASSERT(maxsegs >= (sc->jme_txd_spare - 1),
1519 ("not enough segments %d\n", maxsegs));
1521 ctx.nsegs = maxsegs;
1523 error = bus_dmamap_load_mbuf(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1524 *m_head, jme_dmamap_buf_cb, &ctx,
1526 if (!error && ctx.nsegs == 0) {
1527 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
1530 if (error == EFBIG) {
1531 m = m_defrag(*m_head, MB_DONTWAIT);
1533 if_printf(&sc->arpcom.ac_if,
1534 "could not defrag TX mbuf\n");
1541 ctx.nsegs = maxsegs;
1543 error = bus_dmamap_load_mbuf(sc->jme_cdata.jme_tx_tag,
1544 txd->tx_dmamap, *m_head,
1545 jme_dmamap_buf_cb, &ctx,
1547 if (error || ctx.nsegs == 0) {
1548 if_printf(&sc->arpcom.ac_if,
1549 "could not load defragged TX mbuf\n");
1551 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
1560 if_printf(&sc->arpcom.ac_if, "could not load TX mbuf\n");
1567 /* Configure checksum offload. */
1568 if (m->m_pkthdr.csum_flags & CSUM_IP)
1569 cflags |= JME_TD_IPCSUM;
1570 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1571 cflags |= JME_TD_TCPCSUM;
1572 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1573 cflags |= JME_TD_UDPCSUM;
1575 /* Configure VLAN. */
1576 if (m->m_flags & M_VLANTAG) {
1577 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1578 cflags |= JME_TD_VLAN_TAG;
1581 desc = &sc->jme_rdata.jme_tx_ring[prod];
1582 desc->flags = htole32(cflags);
1584 desc->addr_hi = htole32(m->m_pkthdr.len);
1586 sc->jme_cdata.jme_tx_cnt++;
1587 KKASSERT(sc->jme_cdata.jme_tx_cnt < JME_TX_RING_CNT - JME_TXD_RSVD);
1588 JME_DESC_INC(prod, JME_TX_RING_CNT);
1589 for (i = 0; i < ctx.nsegs; i++) {
1590 desc = &sc->jme_rdata.jme_tx_ring[prod];
1591 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT);
1592 desc->buflen = htole32(txsegs[i].ds_len);
1593 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1594 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1596 sc->jme_cdata.jme_tx_cnt++;
1597 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
1598 JME_TX_RING_CNT - JME_TXD_RSVD);
1599 JME_DESC_INC(prod, JME_TX_RING_CNT);
1602 /* Update producer index. */
1603 sc->jme_cdata.jme_tx_prod = prod;
1605 * Finally request interrupt and give the first descriptor
1606 * owenership to hardware.
1608 desc = txd->tx_desc;
1609 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1612 txd->tx_ndesc = ctx.nsegs + 1;
1614 /* Sync descriptors. */
1615 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1616 BUS_DMASYNC_PREWRITE);
1617 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
1618 sc->jme_cdata.jme_tx_ring_map, BUS_DMASYNC_PREWRITE);
1623 jme_start(struct ifnet *ifp)
1625 struct jme_softc *sc = ifp->if_softc;
1626 struct mbuf *m_head;
1629 ASSERT_SERIALIZED(ifp->if_serializer);
1631 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1632 ifq_purge(&ifp->if_snd);
1636 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1639 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT)
1642 while (!ifq_is_empty(&ifp->if_snd)) {
1644 * Check number of available TX descs, always
1645 * leave JME_TXD_RSVD free TX descs.
1647 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare >
1648 JME_TX_RING_CNT - JME_TXD_RSVD) {
1649 ifp->if_flags |= IFF_OACTIVE;
1653 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1658 * Pack the data into the transmit ring. If we
1659 * don't have room, set the OACTIVE flag and wait
1660 * for the NIC to drain the ring.
1662 if (jme_encap(sc, &m_head)) {
1663 if (m_head == NULL) {
1667 ifq_prepend(&ifp->if_snd, m_head);
1668 ifp->if_flags |= IFF_OACTIVE;
1674 * If there's a BPF listener, bounce a copy of this frame
1677 ETHER_BPF_MTAP(ifp, m_head);
1682 * Reading TXCSR takes very long time under heavy load
1683 * so cache TXCSR value and writes the ORed value with
1684 * the kick command to the TXCSR. This saves one register
1687 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1688 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1689 /* Set a timeout in case the chip goes out to lunch. */
1690 ifp->if_timer = JME_TX_TIMEOUT;
1695 jme_watchdog(struct ifnet *ifp)
1697 struct jme_softc *sc = ifp->if_softc;
1699 ASSERT_SERIALIZED(ifp->if_serializer);
1701 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1702 if_printf(ifp, "watchdog timeout (missed link)\n");
1709 if (sc->jme_cdata.jme_tx_cnt == 0) {
1710 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1712 if (!ifq_is_empty(&ifp->if_snd))
1717 if_printf(ifp, "watchdog timeout\n");
1720 if (!ifq_is_empty(&ifp->if_snd))
1725 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1727 struct jme_softc *sc = ifp->if_softc;
1728 struct mii_data *mii = device_get_softc(sc->jme_miibus);
1729 struct ifreq *ifr = (struct ifreq *)data;
1730 int error = 0, mask;
1732 ASSERT_SERIALIZED(ifp->if_serializer);
1736 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1737 (!(sc->jme_caps & JME_CAP_JUMBO) &&
1738 ifr->ifr_mtu > JME_MAX_MTU)) {
1743 if (ifp->if_mtu != ifr->ifr_mtu) {
1745 * No special configuration is required when interface
1746 * MTU is changed but availability of Tx checksum
1747 * offload should be chcked against new MTU size as
1748 * FIFO size is just 2K.
1750 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1751 ifp->if_capenable &= ~IFCAP_TXCSUM;
1752 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1754 ifp->if_mtu = ifr->ifr_mtu;
1755 if (ifp->if_flags & IFF_RUNNING)
1761 if (ifp->if_flags & IFF_UP) {
1762 if (ifp->if_flags & IFF_RUNNING) {
1763 if ((ifp->if_flags ^ sc->jme_if_flags) &
1764 (IFF_PROMISC | IFF_ALLMULTI))
1770 if (ifp->if_flags & IFF_RUNNING)
1773 sc->jme_if_flags = ifp->if_flags;
1778 if (ifp->if_flags & IFF_RUNNING)
1784 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1788 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1790 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1791 if (IFCAP_TXCSUM & ifp->if_capabilities) {
1792 ifp->if_capenable ^= IFCAP_TXCSUM;
1793 if (IFCAP_TXCSUM & ifp->if_capenable)
1794 ifp->if_hwassist |= JME_CSUM_FEATURES;
1796 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1799 if ((mask & IFCAP_RXCSUM) &&
1800 (IFCAP_RXCSUM & ifp->if_capabilities)) {
1803 ifp->if_capenable ^= IFCAP_RXCSUM;
1804 reg = CSR_READ_4(sc, JME_RXMAC);
1805 reg &= ~RXMAC_CSUM_ENB;
1806 if (ifp->if_capenable & IFCAP_RXCSUM)
1807 reg |= RXMAC_CSUM_ENB;
1808 CSR_WRITE_4(sc, JME_RXMAC, reg);
1811 if ((mask & IFCAP_VLAN_HWTAGGING) &&
1812 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities)) {
1813 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1819 error = ether_ioctl(ifp, cmd, data);
1826 jme_mac_config(struct jme_softc *sc)
1828 struct mii_data *mii;
1829 uint32_t ghc, rxmac, txmac, txpause;
1831 mii = device_get_softc(sc->jme_miibus);
1833 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1835 CSR_WRITE_4(sc, JME_GHC, 0);
1837 rxmac = CSR_READ_4(sc, JME_RXMAC);
1838 rxmac &= ~RXMAC_FC_ENB;
1839 txmac = CSR_READ_4(sc, JME_TXMAC);
1840 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1841 txpause = CSR_READ_4(sc, JME_TXPFC);
1842 txpause &= ~TXPFC_PAUSE_ENB;
1843 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1844 ghc |= GHC_FULL_DUPLEX;
1845 rxmac &= ~RXMAC_COLL_DET_ENB;
1846 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1847 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1850 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1851 txpause |= TXPFC_PAUSE_ENB;
1852 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1853 rxmac |= RXMAC_FC_ENB;
1855 /* Disable retry transmit timer/retry limit. */
1856 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1857 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1859 rxmac |= RXMAC_COLL_DET_ENB;
1860 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1861 /* Enable retry transmit timer/retry limit. */
1862 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1863 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1866 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */
1867 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1869 ghc |= GHC_SPEED_10;
1872 ghc |= GHC_SPEED_100;
1875 if (sc->jme_caps & JME_CAP_FASTETH)
1877 ghc |= GHC_SPEED_1000;
1878 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1879 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1884 CSR_WRITE_4(sc, JME_GHC, ghc);
1885 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1886 CSR_WRITE_4(sc, JME_TXMAC, txmac);
1887 CSR_WRITE_4(sc, JME_TXPFC, txpause);
1893 struct jme_softc *sc = xsc;
1894 struct ifnet *ifp = &sc->arpcom.ac_if;
1897 ASSERT_SERIALIZED(ifp->if_serializer);
1899 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
1900 if (status == 0 || status == 0xFFFFFFFF)
1903 /* Disable interrupts. */
1904 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
1906 status = CSR_READ_4(sc, JME_INTR_STATUS);
1907 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
1910 /* Reset PCC counter/timer and Ack interrupts. */
1911 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
1912 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
1913 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
1914 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
1915 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP;
1916 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
1918 if (ifp->if_flags & IFF_RUNNING) {
1919 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
1922 if (status & INTR_RXQ_DESC_EMPTY) {
1924 * Notify hardware availability of new Rx buffers.
1925 * Reading RXCSR takes very long time under heavy
1926 * load so cache RXCSR value and writes the ORed
1927 * value with the kick command to the RXCSR. This
1928 * saves one register access cycle.
1930 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
1931 RXCSR_RX_ENB | RXCSR_RXQ_START);
1934 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
1936 if (!ifq_is_empty(&ifp->if_snd))
1941 /* Reenable interrupts. */
1942 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
1946 jme_txeof(struct jme_softc *sc)
1948 struct ifnet *ifp = &sc->arpcom.ac_if;
1949 struct jme_txdesc *txd;
1953 cons = sc->jme_cdata.jme_tx_cons;
1954 if (cons == sc->jme_cdata.jme_tx_prod)
1957 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
1958 sc->jme_cdata.jme_tx_ring_map,
1959 BUS_DMASYNC_POSTREAD);
1962 * Go through our Tx list and free mbufs for those
1963 * frames which have been transmitted.
1965 while (cons != sc->jme_cdata.jme_tx_prod) {
1966 txd = &sc->jme_cdata.jme_txdesc[cons];
1967 KASSERT(txd->tx_m != NULL,
1968 ("%s: freeing NULL mbuf!\n", __func__));
1970 status = le32toh(txd->tx_desc->flags);
1971 if ((status & JME_TD_OWN) == JME_TD_OWN)
1974 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
1978 if (status & JME_TD_COLLISION) {
1979 ifp->if_collisions +=
1980 le32toh(txd->tx_desc->buflen) &
1981 JME_TD_BUF_LEN_MASK;
1986 * Only the first descriptor of multi-descriptor
1987 * transmission is updated so driver have to skip entire
1988 * chained buffers for the transmiited frame. In other
1989 * words, JME_TD_OWN bit is valid only at the first
1990 * descriptor of a multi-descriptor transmission.
1992 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
1993 sc->jme_rdata.jme_tx_ring[cons].flags = 0;
1994 JME_DESC_INC(cons, JME_TX_RING_CNT);
1997 /* Reclaim transferred mbufs. */
1998 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2001 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2002 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2003 ("%s: Active Tx desc counter was garbled\n", __func__));
2006 sc->jme_cdata.jme_tx_cons = cons;
2008 if (sc->jme_cdata.jme_tx_cnt == 0)
2011 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare <=
2012 JME_TX_RING_CNT - JME_TXD_RSVD)
2013 ifp->if_flags &= ~IFF_OACTIVE;
2015 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2016 sc->jme_cdata.jme_tx_ring_map,
2017 BUS_DMASYNC_PREWRITE);
2020 static __inline void
2021 jme_discard_rxbufs(struct jme_softc *sc, int cons, int count)
2025 for (i = 0; i < count; ++i) {
2026 struct jme_desc *desc = &sc->jme_rdata.jme_rx_ring[cons];
2028 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2029 desc->buflen = htole32(MCLBYTES);
2030 JME_DESC_INC(cons, JME_RX_RING_CNT);
2034 /* Receive a frame. */
2036 jme_rxpkt(struct jme_softc *sc)
2038 struct ifnet *ifp = &sc->arpcom.ac_if;
2039 struct jme_desc *desc;
2040 struct jme_rxdesc *rxd;
2041 struct mbuf *mp, *m;
2042 uint32_t flags, status;
2043 int cons, count, nsegs;
2045 cons = sc->jme_cdata.jme_rx_cons;
2046 desc = &sc->jme_rdata.jme_rx_ring[cons];
2047 flags = le32toh(desc->flags);
2048 status = le32toh(desc->buflen);
2049 nsegs = JME_RX_NSEGS(status);
2051 if (status & JME_RX_ERR_STAT) {
2053 jme_discard_rxbufs(sc, cons, nsegs);
2054 #ifdef JME_SHOW_ERRORS
2055 device_printf(sc->jme_dev, "%s : receive error = 0x%b\n",
2056 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2058 sc->jme_cdata.jme_rx_cons += nsegs;
2059 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT;
2063 sc->jme_cdata.jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2064 for (count = 0; count < nsegs; count++,
2065 JME_DESC_INC(cons, JME_RX_RING_CNT)) {
2066 rxd = &sc->jme_cdata.jme_rxdesc[cons];
2069 /* Add a new receive buffer to the ring. */
2070 if (jme_newbuf(sc, rxd, 0) != 0) {
2073 jme_discard_rxbufs(sc, cons, nsegs - count);
2074 if (sc->jme_cdata.jme_rxhead != NULL) {
2075 m_freem(sc->jme_cdata.jme_rxhead);
2076 JME_RXCHAIN_RESET(sc);
2082 * Assume we've received a full sized frame.
2083 * Actual size is fixed when we encounter the end of
2084 * multi-segmented frame.
2086 mp->m_len = MCLBYTES;
2088 /* Chain received mbufs. */
2089 if (sc->jme_cdata.jme_rxhead == NULL) {
2090 sc->jme_cdata.jme_rxhead = mp;
2091 sc->jme_cdata.jme_rxtail = mp;
2094 * Receive processor can receive a maximum frame
2095 * size of 65535 bytes.
2097 mp->m_flags &= ~M_PKTHDR;
2098 sc->jme_cdata.jme_rxtail->m_next = mp;
2099 sc->jme_cdata.jme_rxtail = mp;
2102 if (count == nsegs - 1) {
2103 /* Last desc. for this frame. */
2104 m = sc->jme_cdata.jme_rxhead;
2105 /* XXX assert PKTHDR? */
2106 m->m_flags |= M_PKTHDR;
2107 m->m_pkthdr.len = sc->jme_cdata.jme_rxlen;
2109 /* Set first mbuf size. */
2110 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2111 /* Set last mbuf size. */
2112 mp->m_len = sc->jme_cdata.jme_rxlen -
2113 ((MCLBYTES - JME_RX_PAD_BYTES) +
2114 (MCLBYTES * (nsegs - 2)));
2116 m->m_len = sc->jme_cdata.jme_rxlen;
2118 m->m_pkthdr.rcvif = ifp;
2121 * Account for 10bytes auto padding which is used
2122 * to align IP header on 32bit boundary. Also note,
2123 * CRC bytes is automatically removed by the
2126 m->m_data += JME_RX_PAD_BYTES;
2128 /* Set checksum information. */
2129 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2130 (flags & JME_RD_IPV4)) {
2131 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2132 if (flags & JME_RD_IPCSUM)
2133 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2134 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2135 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2136 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2137 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2138 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2139 m->m_pkthdr.csum_flags |=
2140 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2141 m->m_pkthdr.csum_data = 0xffff;
2145 /* Check for VLAN tagged packets. */
2146 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2147 (flags & JME_RD_VLAN_TAG)) {
2148 m->m_pkthdr.ether_vlantag =
2149 flags & JME_RD_VLAN_MASK;
2150 m->m_flags |= M_VLANTAG;
2155 ifp->if_input(ifp, m);
2157 /* Reset mbuf chains. */
2158 JME_RXCHAIN_RESET(sc);
2162 sc->jme_cdata.jme_rx_cons += nsegs;
2163 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT;
2167 jme_rxeof(struct jme_softc *sc)
2169 struct jme_desc *desc;
2170 int nsegs, prog, pktlen;
2172 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2173 sc->jme_cdata.jme_rx_ring_map,
2174 BUS_DMASYNC_POSTREAD);
2178 desc = &sc->jme_rdata.jme_rx_ring[sc->jme_cdata.jme_rx_cons];
2179 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2181 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2185 * Check number of segments against received bytes.
2186 * Non-matching value would indicate that hardware
2187 * is still trying to update Rx descriptors. I'm not
2188 * sure whether this check is needed.
2190 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2191 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2192 if (nsegs != howmany(pktlen, MCLBYTES)) {
2193 if_printf(&sc->arpcom.ac_if, "RX fragment count(%d) "
2194 "and packet size(%d) mismach\n",
2199 /* Received a frame. */
2205 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2206 sc->jme_cdata.jme_rx_ring_map,
2207 BUS_DMASYNC_PREWRITE);
2214 struct jme_softc *sc = xsc;
2215 struct ifnet *ifp = &sc->arpcom.ac_if;
2216 struct mii_data *mii = device_get_softc(sc->jme_miibus);
2218 lwkt_serialize_enter(ifp->if_serializer);
2221 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2223 lwkt_serialize_exit(ifp->if_serializer);
2227 jme_reset(struct jme_softc *sc)
2230 /* Stop receiver, transmitter. */
2234 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2236 CSR_WRITE_4(sc, JME_GHC, 0);
2242 struct jme_softc *sc = xsc;
2243 struct ifnet *ifp = &sc->arpcom.ac_if;
2244 struct mii_data *mii;
2245 uint8_t eaddr[ETHER_ADDR_LEN];
2250 ASSERT_SERIALIZED(ifp->if_serializer);
2253 * Cancel any pending I/O.
2258 * Reset the chip to a known state.
2263 * Since we always use 64bit address mode for transmitting,
2264 * each Tx request requires one more dummy descriptor.
2267 howmany(ifp->if_mtu + sizeof(struct ether_vlan_header), MCLBYTES) + 1;
2268 KKASSERT(sc->jme_txd_spare >= 2);
2270 /* Init descriptors. */
2271 error = jme_init_rx_ring(sc);
2273 device_printf(sc->jme_dev,
2274 "%s: initialization failed: no memory for Rx buffers.\n",
2279 jme_init_tx_ring(sc);
2281 /* Initialize shadow status block. */
2284 /* Reprogram the station address. */
2285 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2286 CSR_WRITE_4(sc, JME_PAR0,
2287 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2288 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2291 * Configure Tx queue.
2292 * Tx priority queue weight value : 0
2293 * Tx FIFO threshold for processing next packet : 16QW
2294 * Maximum Tx DMA length : 512
2295 * Allow Tx DMA burst.
2297 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2298 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2299 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2300 sc->jme_txcsr |= sc->jme_tx_dma_size;
2301 sc->jme_txcsr |= TXCSR_DMA_BURST;
2302 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2304 /* Set Tx descriptor counter. */
2305 CSR_WRITE_4(sc, JME_TXQDC, JME_TX_RING_CNT);
2307 /* Set Tx ring address to the hardware. */
2308 paddr = JME_TX_RING_ADDR(sc, 0);
2309 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2310 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2312 /* Configure TxMAC parameters. */
2313 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2314 reg |= TXMAC_THRESH_1_PKT;
2315 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2316 CSR_WRITE_4(sc, JME_TXMAC, reg);
2319 * Configure Rx queue.
2320 * FIFO full threshold for transmitting Tx pause packet : 128T
2321 * FIFO threshold for processing next packet : 128QW
2323 * Max Rx DMA length : 128
2324 * Rx descriptor retry : 32
2325 * Rx descriptor retry time gap : 256ns
2326 * Don't receive runt/bad frame.
2328 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2330 * Since Rx FIFO size is 4K bytes, receiving frames larger
2331 * than 4K bytes will suffer from Rx FIFO overruns. So
2332 * decrease FIFO threshold to reduce the FIFO overruns for
2333 * frames larger than 4000 bytes.
2334 * For best performance of standard MTU sized frames use
2335 * maximum allowable FIFO threshold, 128QW.
2337 if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2339 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2341 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2342 sc->jme_rxcsr |= sc->jme_rx_dma_size | RXCSR_RXQ_N_SEL(RXCSR_RXQ0);
2343 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2344 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2345 /* XXX TODO DROP_BAD */
2346 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr);
2348 /* Set Rx descriptor counter. */
2349 CSR_WRITE_4(sc, JME_RXQDC, JME_RX_RING_CNT);
2351 /* Set Rx ring address to the hardware. */
2352 paddr = JME_RX_RING_ADDR(sc, 0);
2353 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2354 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2356 /* Clear receive filter. */
2357 CSR_WRITE_4(sc, JME_RXMAC, 0);
2359 /* Set up the receive filter. */
2364 * Disable all WOL bits as WOL can interfere normal Rx
2365 * operation. Also clear WOL detection status bits.
2367 reg = CSR_READ_4(sc, JME_PMCS);
2368 reg &= ~PMCS_WOL_ENB_MASK;
2369 CSR_WRITE_4(sc, JME_PMCS, reg);
2372 * Pad 10bytes right before received frame. This will greatly
2373 * help Rx performance on strict-alignment architectures as
2374 * it does not need to copy the frame to align the payload.
2376 reg = CSR_READ_4(sc, JME_RXMAC);
2377 reg |= RXMAC_PAD_10BYTES;
2379 if (ifp->if_capenable & IFCAP_RXCSUM)
2380 reg |= RXMAC_CSUM_ENB;
2381 CSR_WRITE_4(sc, JME_RXMAC, reg);
2383 /* Configure general purpose reg0 */
2384 reg = CSR_READ_4(sc, JME_GPREG0);
2385 reg &= ~GPREG0_PCC_UNIT_MASK;
2386 /* Set PCC timer resolution to micro-seconds unit. */
2387 reg |= GPREG0_PCC_UNIT_US;
2389 * Disable all shadow register posting as we have to read
2390 * JME_INTR_STATUS register in jme_intr. Also it seems
2391 * that it's hard to synchronize interrupt status between
2392 * hardware and software with shadow posting due to
2393 * requirements of bus_dmamap_sync(9).
2395 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2396 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2397 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2398 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2399 /* Disable posting of DW0. */
2400 reg &= ~GPREG0_POST_DW0_ENB;
2401 /* Clear PME message. */
2402 reg &= ~GPREG0_PME_ENB;
2403 /* Set PHY address. */
2404 reg &= ~GPREG0_PHY_ADDR_MASK;
2405 reg |= sc->jme_phyaddr;
2406 CSR_WRITE_4(sc, JME_GPREG0, reg);
2408 /* Configure Tx queue 0 packet completion coalescing. */
2409 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
2411 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
2412 PCCTX_COAL_PKT_MASK;
2413 reg |= PCCTX_COAL_TXQ0;
2414 CSR_WRITE_4(sc, JME_PCCTX, reg);
2416 /* Configure Rx queue 0 packet completion coalescing. */
2417 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
2419 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
2420 PCCRX_COAL_PKT_MASK;
2421 CSR_WRITE_4(sc, JME_PCCRX0, reg);
2423 /* Configure shadow status block but don't enable posting. */
2424 paddr = sc->jme_rdata.jme_ssb_block_paddr;
2425 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2426 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2428 /* Disable Timer 1 and Timer 2. */
2429 CSR_WRITE_4(sc, JME_TIMER1, 0);
2430 CSR_WRITE_4(sc, JME_TIMER2, 0);
2432 /* Configure retry transmit period, retry limit value. */
2433 CSR_WRITE_4(sc, JME_TXTRHD,
2434 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2435 TXTRHD_RT_PERIOD_MASK) |
2436 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2437 TXTRHD_RT_LIMIT_SHIFT));
2440 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
2442 /* Initialize the interrupt mask. */
2443 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2444 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2447 * Enabling Tx/Rx DMA engines and Rx queue processing is
2448 * done after detection of valid link in jme_miibus_statchg.
2450 sc->jme_flags &= ~JME_FLAG_LINK;
2452 /* Set the current media. */
2453 mii = device_get_softc(sc->jme_miibus);
2456 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2458 ifp->if_flags |= IFF_RUNNING;
2459 ifp->if_flags &= ~IFF_OACTIVE;
2463 jme_stop(struct jme_softc *sc)
2465 struct ifnet *ifp = &sc->arpcom.ac_if;
2466 struct jme_txdesc *txd;
2467 struct jme_rxdesc *rxd;
2470 ASSERT_SERIALIZED(ifp->if_serializer);
2473 * Mark the interface down and cancel the watchdog timer.
2475 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2478 callout_stop(&sc->jme_tick_ch);
2479 sc->jme_flags &= ~JME_FLAG_LINK;
2482 * Disable interrupts.
2484 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2485 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2487 /* Disable updating shadow status block. */
2488 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2489 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2491 /* Stop receiver, transmitter. */
2496 /* Reclaim Rx/Tx buffers that have been completed. */
2498 if (sc->jme_cdata.jme_rxhead != NULL)
2499 m_freem(sc->jme_cdata.jme_rxhead);
2500 JME_RXCHAIN_RESET(sc);
2505 * Free partial finished RX segments
2507 if (sc->jme_cdata.jme_rxhead != NULL)
2508 m_freem(sc->jme_cdata.jme_rxhead);
2509 JME_RXCHAIN_RESET(sc);
2512 * Free RX and TX mbufs still in the queues.
2514 for (i = 0; i < JME_RX_RING_CNT; i++) {
2515 rxd = &sc->jme_cdata.jme_rxdesc[i];
2516 if (rxd->rx_m != NULL) {
2517 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag,
2523 for (i = 0; i < JME_TX_RING_CNT; i++) {
2524 txd = &sc->jme_cdata.jme_txdesc[i];
2525 if (txd->tx_m != NULL) {
2526 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2536 jme_stop_tx(struct jme_softc *sc)
2541 reg = CSR_READ_4(sc, JME_TXCSR);
2542 if ((reg & TXCSR_TX_ENB) == 0)
2544 reg &= ~TXCSR_TX_ENB;
2545 CSR_WRITE_4(sc, JME_TXCSR, reg);
2546 for (i = JME_TIMEOUT; i > 0; i--) {
2548 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2552 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2556 jme_stop_rx(struct jme_softc *sc)
2561 reg = CSR_READ_4(sc, JME_RXCSR);
2562 if ((reg & RXCSR_RX_ENB) == 0)
2564 reg &= ~RXCSR_RX_ENB;
2565 CSR_WRITE_4(sc, JME_RXCSR, reg);
2566 for (i = JME_TIMEOUT; i > 0; i--) {
2568 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2572 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2576 jme_init_tx_ring(struct jme_softc *sc)
2578 struct jme_ring_data *rd;
2579 struct jme_txdesc *txd;
2582 sc->jme_cdata.jme_tx_prod = 0;
2583 sc->jme_cdata.jme_tx_cons = 0;
2584 sc->jme_cdata.jme_tx_cnt = 0;
2586 rd = &sc->jme_rdata;
2587 bzero(rd->jme_tx_ring, JME_TX_RING_SIZE);
2588 for (i = 0; i < JME_TX_RING_CNT; i++) {
2589 txd = &sc->jme_cdata.jme_txdesc[i];
2591 txd->tx_desc = &rd->jme_tx_ring[i];
2595 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2596 sc->jme_cdata.jme_tx_ring_map,
2597 BUS_DMASYNC_PREWRITE);
2601 jme_init_ssb(struct jme_softc *sc)
2603 struct jme_ring_data *rd;
2605 rd = &sc->jme_rdata;
2606 bzero(rd->jme_ssb_block, JME_SSB_SIZE);
2607 bus_dmamap_sync(sc->jme_cdata.jme_ssb_tag, sc->jme_cdata.jme_ssb_map,
2608 BUS_DMASYNC_PREWRITE);
2612 jme_init_rx_ring(struct jme_softc *sc)
2614 struct jme_ring_data *rd;
2615 struct jme_rxdesc *rxd;
2618 KKASSERT(sc->jme_cdata.jme_rxhead == NULL &&
2619 sc->jme_cdata.jme_rxtail == NULL &&
2620 sc->jme_cdata.jme_rxlen == 0);
2621 sc->jme_cdata.jme_rx_cons = 0;
2623 rd = &sc->jme_rdata;
2624 bzero(rd->jme_rx_ring, JME_RX_RING_SIZE);
2625 for (i = 0; i < JME_RX_RING_CNT; i++) {
2628 rxd = &sc->jme_cdata.jme_rxdesc[i];
2630 rxd->rx_desc = &rd->jme_rx_ring[i];
2631 error = jme_newbuf(sc, rxd, 1);
2636 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2637 sc->jme_cdata.jme_rx_ring_map,
2638 BUS_DMASYNC_PREWRITE);
2643 jme_newbuf(struct jme_softc *sc, struct jme_rxdesc *rxd, int init)
2645 struct jme_desc *desc;
2647 struct jme_dmamap_ctx ctx;
2648 bus_dma_segment_t segs;
2652 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2656 * JMC250 has 64bit boundary alignment limitation so jme(4)
2657 * takes advantage of 10 bytes padding feature of hardware
2658 * in order not to copy entire frame to align IP header on
2661 m->m_len = m->m_pkthdr.len = MCLBYTES;
2665 error = bus_dmamap_load_mbuf(sc->jme_cdata.jme_rx_tag,
2666 sc->jme_cdata.jme_rx_sparemap,
2667 m, jme_dmamap_buf_cb, &ctx,
2669 if (error || ctx.nsegs == 0) {
2671 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag,
2672 sc->jme_cdata.jme_rx_sparemap);
2674 if_printf(&sc->arpcom.ac_if, "too many segments?!\n");
2679 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
2683 if (rxd->rx_m != NULL) {
2684 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap,
2685 BUS_DMASYNC_POSTREAD);
2686 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap);
2688 map = rxd->rx_dmamap;
2689 rxd->rx_dmamap = sc->jme_cdata.jme_rx_sparemap;
2690 sc->jme_cdata.jme_rx_sparemap = map;
2693 desc = rxd->rx_desc;
2694 desc->buflen = htole32(segs.ds_len);
2695 desc->addr_lo = htole32(JME_ADDR_LO(segs.ds_addr));
2696 desc->addr_hi = htole32(JME_ADDR_HI(segs.ds_addr));
2697 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2703 jme_set_vlan(struct jme_softc *sc)
2705 struct ifnet *ifp = &sc->arpcom.ac_if;
2708 ASSERT_SERIALIZED(ifp->if_serializer);
2710 reg = CSR_READ_4(sc, JME_RXMAC);
2711 reg &= ~RXMAC_VLAN_ENB;
2712 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2713 reg |= RXMAC_VLAN_ENB;
2714 CSR_WRITE_4(sc, JME_RXMAC, reg);
2718 jme_set_filter(struct jme_softc *sc)
2720 struct ifnet *ifp = &sc->arpcom.ac_if;
2721 struct ifmultiaddr *ifma;
2726 ASSERT_SERIALIZED(ifp->if_serializer);
2728 rxcfg = CSR_READ_4(sc, JME_RXMAC);
2729 rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
2733 * Always accept frames destined to our station address.
2734 * Always accept broadcast frames.
2736 rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
2738 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2739 if (ifp->if_flags & IFF_PROMISC)
2740 rxcfg |= RXMAC_PROMISC;
2741 if (ifp->if_flags & IFF_ALLMULTI)
2742 rxcfg |= RXMAC_ALLMULTI;
2743 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
2744 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
2745 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2750 * Set up the multicast address filter by passing all multicast
2751 * addresses through a CRC generator, and then using the low-order
2752 * 6 bits as an index into the 64 bit multicast hash table. The
2753 * high order bits select the register, while the rest of the bits
2754 * select the bit within the register.
2756 rxcfg |= RXMAC_MULTICAST;
2757 bzero(mchash, sizeof(mchash));
2759 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2760 if (ifma->ifma_addr->sa_family != AF_LINK)
2762 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2763 ifma->ifma_addr), ETHER_ADDR_LEN);
2765 /* Just want the 6 least significant bits. */
2768 /* Set the corresponding bit in the hash table. */
2769 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2772 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
2773 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
2774 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2778 sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS)
2780 return (sysctl_int_range(oidp, arg1, arg2, req,
2781 PCCTX_COAL_TO_MIN, PCCTX_COAL_TO_MAX));
2785 sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
2787 return (sysctl_int_range(oidp, arg1, arg2, req,
2788 PCCTX_COAL_PKT_MIN, PCCTX_COAL_PKT_MAX));
2792 sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS)
2794 return (sysctl_int_range(oidp, arg1, arg2, req,
2795 PCCRX_COAL_TO_MIN, PCCRX_COAL_TO_MAX));
2799 sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
2801 return (sysctl_int_range(oidp, arg1, arg2, req,
2802 PCCRX_COAL_PKT_MIN, PCCRX_COAL_PKT_MAX));