sys/dev/drm/radeon_cp.c

   1 /*-
   2  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   3  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   4  * Copyright 2007 Advanced Micro Devices, Inc.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  * __FBSDID("$FreeBSD: src/sys/dev/drm/radeon_cp.c,v 1.36 2009/10/30 18:07:22 rnoland Exp $");
  30  */
  31
  32 #include "dev/drm/drmP.h"
  33 #include "dev/drm/drm.h"
  34 #include "dev/drm/drm_sarea.h"
  35 #include "dev/drm/radeon_drm.h"
  36 #include "dev/drm/radeon_drv.h"
  37 #include "dev/drm/r300_reg.h"
  38
  39 #include "dev/drm/radeon_microcode.h"
  40
  41 #define RADEON_FIFO_DEBUG       0
  42
  43 static int radeon_do_cleanup_cp(struct drm_device * dev);
  44 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
  45
  46 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
  47 {
  48         u32 val;
  49
  50         if (dev_priv->flags & RADEON_IS_AGP) {
  51                 val = DRM_READ32(dev_priv->ring_rptr, off);
  52         } else {
  53                 val = *(((volatile u32 *)
  54                          dev_priv->ring_rptr->handle) +
  55                         (off / sizeof(u32)));
  56                 val = le32_to_cpu(val);
  57         }
  58         return val;
  59 }
  60
  61 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
  62 {
  63         if (dev_priv->writeback_works)
  64                 return radeon_read_ring_rptr(dev_priv, 0);
  65         else {
  66                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  67                         return RADEON_READ(R600_CP_RB_RPTR);
  68                 else
  69                         return RADEON_READ(RADEON_CP_RB_RPTR);
  70         }
  71 }
  72
  73 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
  74 {
  75         if (dev_priv->flags & RADEON_IS_AGP)
  76                 DRM_WRITE32(dev_priv->ring_rptr, off, val);
  77         else
  78                 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
  79                   (off / sizeof(u32))) = cpu_to_le32(val);
  80 }
  81
  82 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
  83 {
  84         radeon_write_ring_rptr(dev_priv, 0, val);
  85 }
  86
  87 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
  88 {
  89         if (dev_priv->writeback_works) {
  90                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  91                         return radeon_read_ring_rptr(dev_priv,
  92                                                      R600_SCRATCHOFF(index));
  93                 else
  94                         return radeon_read_ring_rptr(dev_priv,
  95                                                      RADEON_SCRATCHOFF(index));
  96         } else {
  97                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  98                         return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
  99                 else
 100                         return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
 101         }
 102 }
 103
 104 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
 105 {
 106         u32 ret;
 107
 108         if (addr < 0x10000)
 109                 ret = DRM_READ32(dev_priv->mmio, addr);
 110         else {
 111                 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
 112                 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
 113         }
 114
 115         return ret;
 116 }
 117
 118 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 119 {
 120         u32 ret;
 121         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
 122         ret = RADEON_READ(R520_MC_IND_DATA);
 123         RADEON_WRITE(R520_MC_IND_INDEX, 0);
 124         return ret;
 125 }
 126
 127 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 128 {
 129         u32 ret;
 130         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
 131         ret = RADEON_READ(RS480_NB_MC_DATA);
 132         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
 133         return ret;
 134 }
 135
 136 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 137 {
 138         u32 ret;
 139         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
 140         ret = RADEON_READ(RS690_MC_DATA);
 141         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
 142         return ret;
 143 }
 144
 145 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 146 {
 147         u32 ret;
 148         RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
 149                                       RS600_MC_IND_CITF_ARB0));
 150         ret = RADEON_READ(RS600_MC_DATA);
 151         return ret;
 152 }
 153
 154 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 155 {
 156         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 157             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 158                 return RS690_READ_MCIND(dev_priv, addr);
 159         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 160                 return RS600_READ_MCIND(dev_priv, addr);
 161         else
 162                 return RS480_READ_MCIND(dev_priv, addr);
 163 }
 164
 165 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 166 {
 167
 168         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 169                 return RADEON_READ(R700_MC_VM_FB_LOCATION);
 170         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 171                 return RADEON_READ(R600_MC_VM_FB_LOCATION);
 172         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 173                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
 174         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 175                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 176                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
 177         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 178                 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
 179         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 180                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
 181         else
 182                 return RADEON_READ(RADEON_MC_FB_LOCATION);
 183 }
 184
 185 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 186 {
 187         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 188                 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
 189         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 190                 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
 191         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 192                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
 193         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 194                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 195                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
 196         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 197                 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
 198         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 199                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 200         else
 201                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 202 }
 203
 204 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 205 {
 206         /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
 207         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
 208                 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 209                 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 210         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
 211                 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 212                 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 213         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 214                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 215         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 216                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 217                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 218         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 219                 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
 220         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 221                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 222         else
 223                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 224 }
 225
 226 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 227 {
 228         u32 agp_base_hi = upper_32_bits(agp_base);
 229         u32 agp_base_lo = agp_base & 0xffffffff;
 230         u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
 231
 232         /* R6xx/R7xx must be aligned to a 4MB boundry */
 233         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 234                 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
 235         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 236                 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
 237         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
 238                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
 239                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
 240         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 241                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 242                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
 243                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
 244         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
 245                 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
 246                 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
 247         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
 248                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
 249                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
 250         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 251                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 252                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 253                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
 254         } else {
 255                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 256                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
 257                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
 258         }
 259 }
 260
 261 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
 262 {
 263         u32 tmp;
 264         /* Turn on bus mastering */
 265         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 266             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 267                 /* rs600/rs690/rs740 */
 268                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 269                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 270         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
 271                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 272                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 273                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 274                 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 275                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 276                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 277         } /* PCIE cards appears to not need this */
 278 }
 279
 280 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 281 {
 282         drm_radeon_private_t *dev_priv = dev->dev_private;
 283
 284         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 285         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 286 }
 287
 288 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 289 {
 290         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 291         return RADEON_READ(RADEON_PCIE_DATA);
 292 }
 293
 294 #if RADEON_FIFO_DEBUG
 295 static void radeon_status(drm_radeon_private_t * dev_priv)
 296 {
 297         printk("%s:\n", __func__);
 298         printk("RBBM_STATUS = 0x%08x\n",
 299                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 300         printk("CP_RB_RTPR = 0x%08x\n",
 301                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 302         printk("CP_RB_WTPR = 0x%08x\n",
 303                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 304         printk("AIC_CNTL = 0x%08x\n",
 305                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 306         printk("AIC_STAT = 0x%08x\n",
 307                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 308         printk("AIC_PT_BASE = 0x%08x\n",
 309                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 310         printk("TLB_ADDR = 0x%08x\n",
 311                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 312         printk("TLB_DATA = 0x%08x\n",
 313                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 314 }
 315 #endif
 316
 317 /* ================================================================
 318  * Engine, FIFO control
 319  */
 320
 321 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 322 {
 323         u32 tmp;
 324         int i;
 325
 326         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 327
 328         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
 329                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 330                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 331                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 332
 333                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 334                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 335                               & RADEON_RB3D_DC_BUSY)) {
 336                                 return 0;
 337                         }
 338                         DRM_UDELAY(1);
 339                 }
 340         } else {
 341                 /* don't flush or purge cache here or lockup */
 342                 return 0;
 343         }
 344
 345 #if RADEON_FIFO_DEBUG
 346         DRM_ERROR("failed!\n");
 347         radeon_status(dev_priv);
 348 #endif
 349         return -EBUSY;
 350 }
 351
 352 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 353 {
 354         int i;
 355
 356         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 357
 358         for (i = 0; i < dev_priv->usec_timeout; i++) {
 359                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 360                              & RADEON_RBBM_FIFOCNT_MASK);
 361                 if (slots >= entries)
 362                         return 0;
 363                 DRM_UDELAY(1);
 364         }
 365         DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
 366                  RADEON_READ(RADEON_RBBM_STATUS),
 367                  RADEON_READ(R300_VAP_CNTL_STATUS));
 368
 369 #if RADEON_FIFO_DEBUG
 370         DRM_ERROR("failed!\n");
 371         radeon_status(dev_priv);
 372 #endif
 373         return -EBUSY;
 374 }
 375
 376 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 377 {
 378         int i, ret;
 379
 380         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 381
 382         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 383         if (ret)
 384                 return ret;
 385
 386         for (i = 0; i < dev_priv->usec_timeout; i++) {
 387                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 388                       & RADEON_RBBM_ACTIVE)) {
 389                         radeon_do_pixcache_flush(dev_priv);
 390                         return 0;
 391                 }
 392                 DRM_UDELAY(1);
 393         }
 394         DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
 395                  RADEON_READ(RADEON_RBBM_STATUS),
 396                  RADEON_READ(R300_VAP_CNTL_STATUS));
 397
 398 #if RADEON_FIFO_DEBUG
 399         DRM_ERROR("failed!\n");
 400         radeon_status(dev_priv);
 401 #endif
 402         return -EBUSY;
 403 }
 404
 405 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
 406 {
 407         uint32_t gb_tile_config, gb_pipe_sel = 0;
 408
 409         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
 410                 uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);
 411                 if ((z_pipe_sel & 3) == 3)
 412                         dev_priv->num_z_pipes = 2;
 413                 else
 414                         dev_priv->num_z_pipes = 1;
 415         } else
 416                 dev_priv->num_z_pipes = 1;
 417
 418         /* RS4xx/RS6xx/R4xx/R5xx */
 419         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
 420                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
 421                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
 422         } else {
 423                 /* R3xx */
 424                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 425                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
 426                         dev_priv->num_gb_pipes = 2;
 427                 } else {
 428                         /* R3Vxx */
 429                         dev_priv->num_gb_pipes = 1;
 430                 }
 431         }
 432         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
 433
 434         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
 435
 436         switch (dev_priv->num_gb_pipes) {
 437         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 438         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 439         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 440         default:
 441         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 442         }
 443
 444         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 445                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
 446                 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
 447         }
 448         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
 449         radeon_do_wait_for_idle(dev_priv);
 450         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
 451         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
 452                                                R300_DC_AUTOFLUSH_ENABLE |
 453                                                R300_DC_DC_DISABLE_IGNORE_PE));
 454
 455
 456 }
 457
 458 /* ================================================================
 459  * CP control, initialization
 460  */
 461
 462 /* Load the microcode for the CP */
 463 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 464 {
 465         const u32 (*cp)[2];
 466         int i;
 467
 468         DRM_DEBUG("\n");
 469
 470         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 471         case CHIP_R100:
 472         case CHIP_RV100:
 473         case CHIP_RV200:
 474         case CHIP_RS100:
 475         case CHIP_RS200:
 476                 DRM_INFO("Loading R100 Microcode\n");
 477                 cp = R100_cp_microcode;
 478                 break;
 479         case CHIP_R200:
 480         case CHIP_RV250:
 481         case CHIP_RV280:
 482         case CHIP_RS300:
 483                 DRM_INFO("Loading R200 Microcode\n");
 484                 cp = R200_cp_microcode;
 485                 break;
 486         case CHIP_R300:
 487         case CHIP_R350:
 488         case CHIP_RV350:
 489         case CHIP_RV380:
 490         case CHIP_RS400:
 491         case CHIP_RS480:
 492                 DRM_INFO("Loading R300 Microcode\n");
 493                 cp = R300_cp_microcode;
 494                 break;
 495         case CHIP_R420:
 496         case CHIP_R423:
 497         case CHIP_RV410:
 498                 DRM_INFO("Loading R400 Microcode\n");
 499                 cp = R420_cp_microcode;
 500                 break;
 501         case CHIP_RS690:
 502         case CHIP_RS740:
 503                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 504                 cp = RS690_cp_microcode;
 505                 break;
 506         case CHIP_RS600:
 507                 DRM_INFO("Loading RS600 Microcode\n");
 508                 cp = RS600_cp_microcode;
 509                 break;
 510         case CHIP_RV515:
 511         case CHIP_R520:
 512         case CHIP_RV530:
 513         case CHIP_R580:
 514         case CHIP_RV560:
 515         case CHIP_RV570:
 516                 DRM_INFO("Loading R500 Microcode\n");
 517                 cp = R520_cp_microcode;
 518                 break;
 519         default:
 520                 return;
 521         }
 522
 523         radeon_do_wait_for_idle(dev_priv);
 524
 525         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 526
 527         for (i = 0; i != 256; i++) {
 528                 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, cp[i][1]);
 529                 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, cp[i][0]);
 530         }
 531 }
 532
 533 /* Flush any pending commands to the CP.  This should only be used just
 534  * prior to a wait for idle, as it informs the engine that the command
 535  * stream is ending.
 536  */
 537 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 538 {
 539         DRM_DEBUG("\n");
 540 #if 0
 541         u32 tmp;
 542
 543         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 544         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 545 #endif
 546 }
 547
 548 /* Wait for the CP to go idle.
 549  */
 550 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 551 {
 552         RING_LOCALS;
 553         DRM_DEBUG("\n");
 554
 555         BEGIN_RING(6);
 556
 557         RADEON_PURGE_CACHE();
 558         RADEON_PURGE_ZCACHE();
 559         RADEON_WAIT_UNTIL_IDLE();
 560
 561         ADVANCE_RING();
 562         COMMIT_RING();
 563
 564         return radeon_do_wait_for_idle(dev_priv);
 565 }
 566
 567 /* Start the Command Processor.
 568  */
 569 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 570 {
 571         RING_LOCALS;
 572         DRM_DEBUG("\n");
 573
 574         radeon_do_wait_for_idle(dev_priv);
 575
 576         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 577
 578         dev_priv->cp_running = 1;
 579
 580         BEGIN_RING(8);
 581         /* isync can only be written through cp on r5xx write it here */
 582         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
 583         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
 584                  RADEON_ISYNC_ANY3D_IDLE2D |
 585                  RADEON_ISYNC_WAIT_IDLEGUI |
 586                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 587         RADEON_PURGE_CACHE();
 588         RADEON_PURGE_ZCACHE();
 589         RADEON_WAIT_UNTIL_IDLE();
 590         ADVANCE_RING();
 591         COMMIT_RING();
 592
 593         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
 594 }
 595
 596 /* Reset the Command Processor.  This will not flush any pending
 597  * commands, so you must wait for the CP command stream to complete
 598  * before calling this routine.
 599  */
 600 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 601 {
 602         u32 cur_read_ptr;
 603         DRM_DEBUG("\n");
 604
 605         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 606         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 607         SET_RING_HEAD(dev_priv, cur_read_ptr);
 608         dev_priv->ring.tail = cur_read_ptr;
 609 }
 610
 611 /* Stop the Command Processor.  This will not flush any pending
 612  * commands, so you must flush the command stream and wait for the CP
 613  * to go idle before calling this routine.
 614  */
 615 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 616 {
 617         DRM_DEBUG("\n");
 618
 619         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 620
 621         dev_priv->cp_running = 0;
 622 }
 623
 624 /* Reset the engine.  This will stop the CP if it is running.
 625  */
 626 static int radeon_do_engine_reset(struct drm_device * dev)
 627 {
 628         drm_radeon_private_t *dev_priv = dev->dev_private;
 629         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
 630         DRM_DEBUG("\n");
 631
 632         radeon_do_pixcache_flush(dev_priv);
 633
 634         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 635                 /* may need something similar for newer chips */
 636                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 637                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 638
 639                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 640                                                     RADEON_FORCEON_MCLKA |
 641                                                     RADEON_FORCEON_MCLKB |
 642                                                     RADEON_FORCEON_YCLKA |
 643                                                     RADEON_FORCEON_YCLKB |
 644                                                     RADEON_FORCEON_MC |
 645                                                     RADEON_FORCEON_AIC));
 646         }
 647
 648         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 649
 650         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 651                                               RADEON_SOFT_RESET_CP |
 652                                               RADEON_SOFT_RESET_HI |
 653                                               RADEON_SOFT_RESET_SE |
 654                                               RADEON_SOFT_RESET_RE |
 655                                               RADEON_SOFT_RESET_PP |
 656                                               RADEON_SOFT_RESET_E2 |
 657                                               RADEON_SOFT_RESET_RB));
 658         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 659         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 660                                               ~(RADEON_SOFT_RESET_CP |
 661                                                 RADEON_SOFT_RESET_HI |
 662                                                 RADEON_SOFT_RESET_SE |
 663                                                 RADEON_SOFT_RESET_RE |
 664                                                 RADEON_SOFT_RESET_PP |
 665                                                 RADEON_SOFT_RESET_E2 |
 666                                                 RADEON_SOFT_RESET_RB)));
 667         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 668
 669         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 670                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 671                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 672                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 673         }
 674
 675         /* setup the raster pipes */
 676         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
 677             radeon_init_pipes(dev_priv);
 678
 679         /* Reset the CP ring */
 680         radeon_do_cp_reset(dev_priv);
 681
 682         /* The CP is no longer running after an engine reset */
 683         dev_priv->cp_running = 0;
 684
 685         /* Reset any pending vertex, indirect buffers */
 686         radeon_freelist_reset(dev);
 687
 688         return 0;
 689 }
 690
 691 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 692                                        drm_radeon_private_t *dev_priv,
 693                                        struct drm_file *file_priv)
 694 {
 695         u32 ring_start, cur_read_ptr;
 696
 697         /* Initialize the memory controller. With new memory map, the fb location
 698          * is not changed, it should have been properly initialized already. Part
 699          * of the problem is that the code below is bogus, assuming the GART is
 700          * always appended to the fb which is not necessarily the case
 701          */
 702         if (!dev_priv->new_memmap)
 703                 radeon_write_fb_location(dev_priv,
 704                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 705                              | (dev_priv->fb_location >> 16));
 706
 707 #if __OS_HAS_AGP
 708         if (dev_priv->flags & RADEON_IS_AGP) {
 709                 radeon_write_agp_base(dev_priv, dev->agp->base);
 710
 711                 radeon_write_agp_location(dev_priv,
 712                              (((dev_priv->gart_vm_start - 1 +
 713                                 dev_priv->gart_size) & 0xffff0000) |
 714                               (dev_priv->gart_vm_start >> 16)));
 715
 716                 ring_start = (dev_priv->cp_ring->offset
 717                               - dev->agp->base
 718                               + dev_priv->gart_vm_start);
 719         } else
 720 #endif
 721                 ring_start = (dev_priv->cp_ring->offset
 722                               - (unsigned long)dev->sg->virtual
 723                               + dev_priv->gart_vm_start);
 724
 725         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 726
 727         /* Set the write pointer delay */
 728         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 729
 730         /* Initialize the ring buffer's read and write pointers */
 731         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 732         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 733         SET_RING_HEAD(dev_priv, cur_read_ptr);
 734         dev_priv->ring.tail = cur_read_ptr;
 735
 736 #if __OS_HAS_AGP
 737         if (dev_priv->flags & RADEON_IS_AGP) {
 738                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 739                              dev_priv->ring_rptr->offset
 740                              - dev->agp->base + dev_priv->gart_vm_start);
 741         } else
 742 #endif
 743         {
 744                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 745                              dev_priv->ring_rptr->offset
 746                              - ((unsigned long) dev->sg->virtual)
 747                              + dev_priv->gart_vm_start);
 748         }
 749
 750         /* Set ring buffer size */
 751 #ifdef __BIG_ENDIAN
 752         RADEON_WRITE(RADEON_CP_RB_CNTL,
 753                      RADEON_BUF_SWAP_32BIT |
 754                      (dev_priv->ring.fetch_size_l2ow << 18) |
 755                      (dev_priv->ring.rptr_update_l2qw << 8) |
 756                      dev_priv->ring.size_l2qw);
 757 #else
 758         RADEON_WRITE(RADEON_CP_RB_CNTL,
 759                      (dev_priv->ring.fetch_size_l2ow << 18) |
 760                      (dev_priv->ring.rptr_update_l2qw << 8) |
 761                      dev_priv->ring.size_l2qw);
 762 #endif
 763
 764
 765         /* Initialize the scratch register pointer.  This will cause
 766          * the scratch register values to be written out to memory
 767          * whenever they are updated.
 768          *
 769          * We simply put this behind the ring read pointer, this works
 770          * with PCI GART as well as (whatever kind of) AGP GART
 771          */
 772         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 773                      + RADEON_SCRATCH_REG_OFFSET);
 774
 775         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 776
 777         radeon_enable_bm(dev_priv);
 778
 779         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
 780         RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
 781
 782         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 783         RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
 784
 785         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
 786         RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
 787
 788         /* reset sarea copies of these */
 789         if (dev_priv->sarea_priv) {
 790                 dev_priv->sarea_priv->last_frame = 0;
 791                 dev_priv->sarea_priv->last_dispatch = 0;
 792                 dev_priv->sarea_priv->last_clear = 0;
 793         }
 794
 795         radeon_do_wait_for_idle(dev_priv);
 796
 797         /* Sync everything up */
 798         RADEON_WRITE(RADEON_ISYNC_CNTL,
 799                      (RADEON_ISYNC_ANY2D_IDLE3D |
 800                       RADEON_ISYNC_ANY3D_IDLE2D |
 801                       RADEON_ISYNC_WAIT_IDLEGUI |
 802                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 803
 804 }
 805
 806 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 807 {
 808         u32 tmp;
 809
 810         /* Start with assuming that writeback doesn't work */
 811         dev_priv->writeback_works = 0;
 812
 813         /* Writeback doesn't seem to work everywhere, test it here and possibly
 814          * enable it if it appears to work
 815          */
 816         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 817
 818         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 819
 820         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 821                 u32 val;
 822
 823                 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
 824                 if (val == 0xdeadbeef)
 825                         break;
 826                 DRM_UDELAY(1);
 827         }
 828
 829         if (tmp < dev_priv->usec_timeout) {
 830                 dev_priv->writeback_works = 1;
 831                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 832         } else {
 833                 dev_priv->writeback_works = 0;
 834                 DRM_INFO("writeback test failed\n");
 835         }
 836         if (radeon_no_wb == 1) {
 837                 dev_priv->writeback_works = 0;
 838                 DRM_INFO("writeback forced off\n");
 839         }
 840
 841         if (!dev_priv->writeback_works) {
 842                 /* Disable writeback to avoid unnecessary bus master transfer */
 843                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
 844                              RADEON_RB_NO_UPDATE);
 845                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 846         }
 847 }
 848
 849 /* Enable or disable IGP GART on the chip */
 850 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 851 {
 852         u32 temp;
 853
 854         if (on) {
 855                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 856                           dev_priv->gart_vm_start,
 857                           (long)dev_priv->gart_info.bus_addr,
 858                           dev_priv->gart_size);
 859
 860                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 861                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 862                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 863                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 864                                                              RS690_BLOCK_GFX_D3_EN));
 865                 else
 866                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 867
 868                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 869                                                                RS480_VA_SIZE_32MB));
 870
 871                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 872                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 873                                                         RS480_TLB_ENABLE |
 874                                                         RS480_GTW_LAC_EN |
 875                                                         RS480_1LEVEL_GART));
 876
 877                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 878                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 879                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 880
 881                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 882                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 883                                                       RS480_REQ_TYPE_SNOOP_DIS));
 884
 885                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 886
 887                 dev_priv->gart_size = 32*1024*1024;
 888                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 889                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
 890
 891                 radeon_write_agp_location(dev_priv, temp);
 892
 893                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 894                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 895                                                                RS480_VA_SIZE_32MB));
 896
 897                 do {
 898                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 899                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 900                                 break;
 901                         DRM_UDELAY(1);
 902                 } while (1);
 903
 904                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 905                                 RS480_GART_CACHE_INVALIDATE);
 906
 907                 do {
 908                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 909                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 910                                 break;
 911                         DRM_UDELAY(1);
 912                 } while (1);
 913
 914                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 915         } else {
 916                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 917         }
 918 }
 919
 920 /* Enable or disable IGP GART on the chip */
 921 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
 922 {
 923         u32 temp;
 924         int i;
 925
 926         if (on) {
 927                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 928                          dev_priv->gart_vm_start,
 929                          (long)dev_priv->gart_info.bus_addr,
 930                          dev_priv->gart_size);
 931
 932                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
 933                                                     RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
 934
 935                 for (i = 0; i < 19; i++)
 936                         IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
 937                                         (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
 938                                          RS600_SYSTEM_ACCESS_MODE_IN_SYS |
 939                                          RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
 940                                          RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
 941                                          RS600_ENABLE_FRAGMENT_PROCESSING |
 942                                          RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
 943
 944                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
 945                                                              RS600_PAGE_TABLE_TYPE_FLAT));
 946
 947                 /* disable all other contexts */
 948                 for (i = 1; i < 8; i++)
 949                         IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
 950
 951                 /* setup the page table aperture */
 952                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
 953                                 dev_priv->gart_info.bus_addr);
 954                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
 955                                 dev_priv->gart_vm_start);
 956                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
 957                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
 958                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
 959
 960                 /* setup the system aperture */
 961                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
 962                                 dev_priv->gart_vm_start);
 963                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
 964                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
 965
 966                 /* enable page tables */
 967                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 968                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
 969
 970                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
 971                 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
 972
 973                 /* invalidate the cache */
 974                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 975
 976                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
 977                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
 978                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 979
 980                 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
 981                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
 982                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 983
 984                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
 985                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
 986                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 987
 988         } else {
 989                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
 990                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
 991                 temp &= ~RS600_ENABLE_PAGE_TABLES;
 992                 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
 993         }
 994 }
 995
 996 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 997 {
 998         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
 999         if (on) {
1000
1001                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1002                           dev_priv->gart_vm_start,
1003                           (long)dev_priv->gart_info.bus_addr,
1004                           dev_priv->gart_size);
1005                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1006                                   dev_priv->gart_vm_start);
1007                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1008                                   dev_priv->gart_info.bus_addr);
1009                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1010                                   dev_priv->gart_vm_start);
1011                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1012                                   dev_priv->gart_vm_start +
1013                                   dev_priv->gart_size - 1);
1014
1015                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1016
1017                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1018                                   RADEON_PCIE_TX_GART_EN);
1019         } else {
1020                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1021                                   tmp & ~RADEON_PCIE_TX_GART_EN);
1022         }
1023 }
1024
1025 /* Enable or disable PCI GART on the chip */
1026 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1027 {
1028         u32 tmp;
1029
1030         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1031             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1032             (dev_priv->flags & RADEON_IS_IGPGART)) {
1033                 radeon_set_igpgart(dev_priv, on);
1034                 return;
1035         }
1036
1037         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1038                 rs600_set_igpgart(dev_priv, on);
1039                 return;
1040         }
1041
1042         if (dev_priv->flags & RADEON_IS_PCIE) {
1043                 radeon_set_pciegart(dev_priv, on);
1044                 return;
1045         }
1046
1047         tmp = RADEON_READ(RADEON_AIC_CNTL);
1048
1049         if (on) {
1050                 RADEON_WRITE(RADEON_AIC_CNTL,
1051                              tmp | RADEON_PCIGART_TRANSLATE_EN);
1052
1053                 /* set PCI GART page-table base address
1054                  */
1055                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1056
1057                 /* set address range for PCI address translate
1058                  */
1059                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1060                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1061                              + dev_priv->gart_size - 1);
1062
1063                 /* Turn off AGP aperture -- is this required for PCI GART?
1064                  */
1065                 radeon_write_agp_location(dev_priv, 0xffffffc0);
1066                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
1067         } else {
1068                 RADEON_WRITE(RADEON_AIC_CNTL,
1069                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1070         }
1071 }
1072
1073 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1074 {
1075         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1076         struct radeon_virt_surface *vp;
1077         int i;
1078
1079         for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1080                 if (!dev_priv->virt_surfaces[i].file_priv ||
1081                     dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1082                         break;
1083         }
1084         if (i >= 2 * RADEON_MAX_SURFACES)
1085                 return -ENOMEM;
1086         vp = &dev_priv->virt_surfaces[i];
1087
1088         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1089                 struct radeon_surface *sp = &dev_priv->surfaces[i];
1090                 if (sp->refcount)
1091                         continue;
1092
1093                 vp->surface_index = i;
1094                 vp->lower = gart_info->bus_addr;
1095                 vp->upper = vp->lower + gart_info->table_size;
1096                 vp->flags = 0;
1097                 vp->file_priv = PCIGART_FILE_PRIV;
1098
1099                 sp->refcount = 1;
1100                 sp->lower = vp->lower;
1101                 sp->upper = vp->upper;
1102                 sp->flags = 0;
1103
1104                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1105                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1106                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1107                 return 0;
1108         }
1109
1110         return -ENOMEM;
1111 }
1112
1113 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1114                              struct drm_file *file_priv)
1115 {
1116         drm_radeon_private_t *dev_priv = dev->dev_private;
1117
1118         DRM_DEBUG("\n");
1119
1120         /* if we require new memory map but we don't have it fail */
1121         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1122                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1123                 radeon_do_cleanup_cp(dev);
1124                 return -EINVAL;
1125         }
1126
1127         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1128                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1129                 dev_priv->flags &= ~RADEON_IS_AGP;
1130         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1131                    && !init->is_pci) {
1132                 DRM_DEBUG("Restoring AGP flag\n");
1133                 dev_priv->flags |= RADEON_IS_AGP;
1134         }
1135
1136         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1137                 DRM_ERROR("PCI GART memory not allocated!\n");
1138                 radeon_do_cleanup_cp(dev);
1139                 return -EINVAL;
1140         }
1141
1142         dev_priv->usec_timeout = init->usec_timeout;
1143         if (dev_priv->usec_timeout < 1 ||
1144             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1145                 DRM_DEBUG("TIMEOUT problem!\n");
1146                 radeon_do_cleanup_cp(dev);
1147                 return -EINVAL;
1148         }
1149
1150         /* Enable vblank on CRTC1 for older X servers
1151          */
1152         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1153
1154         switch(init->func) {
1155         case RADEON_INIT_R200_CP:
1156                 dev_priv->microcode_version = UCODE_R200;
1157                 break;
1158         case RADEON_INIT_R300_CP:
1159                 dev_priv->microcode_version = UCODE_R300;
1160                 break;
1161         default:
1162                 dev_priv->microcode_version = UCODE_R100;
1163         }
1164
1165         dev_priv->do_boxes = 0;
1166         dev_priv->cp_mode = init->cp_mode;
1167
1168         /* We don't support anything other than bus-mastering ring mode,
1169          * but the ring can be in either AGP or PCI space for the ring
1170          * read pointer.
1171          */
1172         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1173             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1174                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1175                 radeon_do_cleanup_cp(dev);
1176                 return -EINVAL;
1177         }
1178
1179         switch (init->fb_bpp) {
1180         case 16:
1181                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1182                 break;
1183         case 32:
1184         default:
1185                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1186                 break;
1187         }
1188         dev_priv->front_offset = init->front_offset;
1189         dev_priv->front_pitch = init->front_pitch;
1190         dev_priv->back_offset = init->back_offset;
1191         dev_priv->back_pitch = init->back_pitch;
1192
1193         switch (init->depth_bpp) {
1194         case 16:
1195                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1196                 break;
1197         case 32:
1198         default:
1199                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1200                 break;
1201         }
1202         dev_priv->depth_offset = init->depth_offset;
1203         dev_priv->depth_pitch = init->depth_pitch;
1204
1205         /* Hardware state for depth clears.  Remove this if/when we no
1206          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1207          * all values to prevent unwanted 3D state from slipping through
1208          * and screwing with the clear operation.
1209          */
1210         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1211                                            (dev_priv->color_fmt << 10) |
1212                                            (dev_priv->microcode_version ==
1213                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1214
1215         dev_priv->depth_clear.rb3d_zstencilcntl =
1216             (dev_priv->depth_fmt |
1217              RADEON_Z_TEST_ALWAYS |
1218              RADEON_STENCIL_TEST_ALWAYS |
1219              RADEON_STENCIL_S_FAIL_REPLACE |
1220              RADEON_STENCIL_ZPASS_REPLACE |
1221              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1222
1223         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1224                                          RADEON_BFACE_SOLID |
1225                                          RADEON_FFACE_SOLID |
1226                                          RADEON_FLAT_SHADE_VTX_LAST |
1227                                          RADEON_DIFFUSE_SHADE_FLAT |
1228                                          RADEON_ALPHA_SHADE_FLAT |
1229                                          RADEON_SPECULAR_SHADE_FLAT |
1230                                          RADEON_FOG_SHADE_FLAT |
1231                                          RADEON_VTX_PIX_CENTER_OGL |
1232                                          RADEON_ROUND_MODE_TRUNC |
1233                                          RADEON_ROUND_PREC_8TH_PIX);
1234
1235
1236         dev_priv->ring_offset = init->ring_offset;
1237         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1238         dev_priv->buffers_offset = init->buffers_offset;
1239         dev_priv->gart_textures_offset = init->gart_textures_offset;
1240
1241         dev_priv->sarea = drm_getsarea(dev);
1242         if (!dev_priv->sarea) {
1243                 DRM_ERROR("could not find sarea!\n");
1244                 radeon_do_cleanup_cp(dev);
1245                 return -EINVAL;
1246         }
1247
1248         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1249         if (!dev_priv->cp_ring) {
1250                 DRM_ERROR("could not find cp ring region!\n");
1251                 radeon_do_cleanup_cp(dev);
1252                 return -EINVAL;
1253         }
1254         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1255         if (!dev_priv->ring_rptr) {
1256                 DRM_ERROR("could not find ring read pointer!\n");
1257                 radeon_do_cleanup_cp(dev);
1258                 return -EINVAL;
1259         }
1260         dev->agp_buffer_token = init->buffers_offset;
1261         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1262         if (!dev->agp_buffer_map) {
1263                 DRM_ERROR("could not find dma buffer region!\n");
1264                 radeon_do_cleanup_cp(dev);
1265                 return -EINVAL;
1266         }
1267
1268         if (init->gart_textures_offset) {
1269                 dev_priv->gart_textures =
1270                     drm_core_findmap(dev, init->gart_textures_offset);
1271                 if (!dev_priv->gart_textures) {
1272                         DRM_ERROR("could not find GART texture region!\n");
1273                         radeon_do_cleanup_cp(dev);
1274                         return -EINVAL;
1275                 }
1276         }
1277
1278         dev_priv->sarea_priv =
1279             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1280                                     init->sarea_priv_offset);
1281
1282 #if __OS_HAS_AGP
1283         if (dev_priv->flags & RADEON_IS_AGP) {
1284                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1285                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1286                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1287                 if (!dev_priv->cp_ring->handle ||
1288                     !dev_priv->ring_rptr->handle ||
1289                     !dev->agp_buffer_map->handle) {
1290                         DRM_ERROR("could not find ioremap agp regions!\n");
1291                         radeon_do_cleanup_cp(dev);
1292                         return -EINVAL;
1293                 }
1294         } else
1295 #endif
1296         {
1297                 dev_priv->cp_ring->handle =
1298                         (void *)(unsigned long)dev_priv->cp_ring->offset;
1299                 dev_priv->ring_rptr->handle =
1300                         (void *)(unsigned long)dev_priv->ring_rptr->offset;
1301                 dev->agp_buffer_map->handle =
1302                         (void *)(unsigned long)dev->agp_buffer_map->offset;
1303
1304                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1305                           dev_priv->cp_ring->handle);
1306                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1307                           dev_priv->ring_rptr->handle);
1308                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1309                           dev->agp_buffer_map->handle);
1310         }
1311
1312         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1313         dev_priv->fb_size =
1314                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1315                 - dev_priv->fb_location;
1316
1317         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1318                                         ((dev_priv->front_offset
1319                                           + dev_priv->fb_location) >> 10));
1320
1321         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1322                                        ((dev_priv->back_offset
1323                                          + dev_priv->fb_location) >> 10));
1324
1325         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1326                                         ((dev_priv->depth_offset
1327                                           + dev_priv->fb_location) >> 10));
1328
1329         dev_priv->gart_size = init->gart_size;
1330
1331         /* New let's set the memory map ... */
1332         if (dev_priv->new_memmap) {
1333                 u32 base = 0;
1334
1335                 DRM_INFO("Setting GART location based on new memory map\n");
1336
1337                 /* If using AGP, try to locate the AGP aperture at the same
1338                  * location in the card and on the bus, though we have to
1339                  * align it down.
1340                  */
1341 #if __OS_HAS_AGP
1342                 if (dev_priv->flags & RADEON_IS_AGP) {
1343                         base = dev->agp->base;
1344                         /* Check if valid */
1345                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1346                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1347                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1348                                          dev->agp->base);
1349                                 base = 0;
1350                         }
1351                 }
1352 #endif
1353                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1354                 if (base == 0) {
1355                         base = dev_priv->fb_location + dev_priv->fb_size;
1356                         if (base < dev_priv->fb_location ||
1357                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1358                                 base = dev_priv->fb_location
1359                                         - dev_priv->gart_size;
1360                 }
1361                 dev_priv->gart_vm_start = base & 0xffc00000u;
1362                 if (dev_priv->gart_vm_start != base)
1363                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1364                                  base, dev_priv->gart_vm_start);
1365         } else {
1366                 DRM_INFO("Setting GART location based on old memory map\n");
1367                 dev_priv->gart_vm_start = dev_priv->fb_location +
1368                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1369         }
1370
1371 #if __OS_HAS_AGP
1372         if (dev_priv->flags & RADEON_IS_AGP)
1373                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1374                                                  - dev->agp->base
1375                                                  + dev_priv->gart_vm_start);
1376         else
1377 #endif
1378                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1379                                         - (unsigned long)dev->sg->virtual
1380                                         + dev_priv->gart_vm_start);
1381
1382         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1383         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1384         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1385                   dev_priv->gart_buffers_offset);
1386
1387         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1388         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1389                               + init->ring_size / sizeof(u32));
1390         dev_priv->ring.size = init->ring_size;
1391         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1392
1393         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1394         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1395
1396         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1397         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1398         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1399
1400         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1401
1402 #if __OS_HAS_AGP
1403         if (dev_priv->flags & RADEON_IS_AGP) {
1404                 /* Turn off PCI GART */
1405                 radeon_set_pcigart(dev_priv, 0);
1406         } else
1407 #endif
1408         {
1409                 u32 sctrl;
1410                 int ret;
1411
1412                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1413                 /* if we have an offset set from userspace */
1414                 if (dev_priv->pcigart_offset_set) {
1415                         dev_priv->gart_info.bus_addr =
1416                             dev_priv->pcigart_offset + dev_priv->fb_location;
1417                         dev_priv->gart_info.mapping.offset =
1418                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1419                         dev_priv->gart_info.mapping.size =
1420                             dev_priv->gart_info.table_size;
1421
1422                         drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1423                         dev_priv->gart_info.addr =
1424                             dev_priv->gart_info.mapping.handle;
1425
1426                         if (dev_priv->flags & RADEON_IS_PCIE)
1427                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1428                         else
1429                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1430                         dev_priv->gart_info.gart_table_location =
1431                             DRM_ATI_GART_FB;
1432
1433                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1434                                   dev_priv->gart_info.addr,
1435                                   dev_priv->pcigart_offset);
1436                 } else {
1437                         if (dev_priv->flags & RADEON_IS_IGPGART)
1438                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1439                         else
1440                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1441                         dev_priv->gart_info.gart_table_location =
1442                             DRM_ATI_GART_MAIN;
1443                         dev_priv->gart_info.addr = NULL;
1444                         dev_priv->gart_info.bus_addr = 0;
1445                         if (dev_priv->flags & RADEON_IS_PCIE) {
1446                                 DRM_ERROR
1447                                     ("Cannot use PCI Express without GART in FB memory\n");
1448                                 radeon_do_cleanup_cp(dev);
1449                                 return -EINVAL;
1450                         }
1451                 }
1452
1453                 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1454                 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1455                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1456                         ret = r600_page_table_init(dev);
1457                 else
1458                         ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1459                 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1460
1461                 if (!ret) {
1462                         DRM_ERROR("failed to init PCI GART!\n");
1463                         radeon_do_cleanup_cp(dev);
1464                         return -ENOMEM;
1465                 }
1466
1467                 ret = radeon_setup_pcigart_surface(dev_priv);
1468                 if (ret) {
1469                         DRM_ERROR("failed to setup GART surface!\n");
1470                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1471                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1472                         else
1473                                 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1474                         radeon_do_cleanup_cp(dev);
1475                         return ret;
1476                 }
1477
1478                 /* Turn on PCI GART */
1479                 radeon_set_pcigart(dev_priv, 1);
1480         }
1481
1482         radeon_cp_load_microcode(dev_priv);
1483         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1484
1485         dev_priv->last_buf = 0;
1486
1487         radeon_do_engine_reset(dev);
1488         radeon_test_writeback(dev_priv);
1489
1490         return 0;
1491 }
1492
1493 static int radeon_do_cleanup_cp(struct drm_device * dev)
1494 {
1495         drm_radeon_private_t *dev_priv = dev->dev_private;
1496         DRM_DEBUG("\n");
1497
1498         /* Make sure interrupts are disabled here because the uninstall ioctl
1499          * may not have been called from userspace and after dev_private
1500          * is freed, it's too late.
1501          */
1502         if (dev->irq_enabled)
1503                 drm_irq_uninstall(dev);
1504
1505 #if __OS_HAS_AGP
1506         if (dev_priv->flags & RADEON_IS_AGP) {
1507                 if (dev_priv->cp_ring != NULL) {
1508                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1509                         dev_priv->cp_ring = NULL;
1510                 }
1511                 if (dev_priv->ring_rptr != NULL) {
1512                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1513                         dev_priv->ring_rptr = NULL;
1514                 }
1515                 if (dev->agp_buffer_map != NULL) {
1516                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1517                         dev->agp_buffer_map = NULL;
1518                 }
1519         } else
1520 #endif
1521         {
1522
1523                 if (dev_priv->gart_info.bus_addr) {
1524                         /* Turn off PCI GART */
1525                         radeon_set_pcigart(dev_priv, 0);
1526                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1527                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1528                         else {
1529                                 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1530                                         DRM_ERROR("failed to cleanup PCI GART!\n");
1531                         }
1532                 }
1533
1534                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1535                 {
1536                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1537                         dev_priv->gart_info.addr = 0;
1538                 }
1539         }
1540         /* only clear to the start of flags */
1541         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1542
1543         return 0;
1544 }
1545
1546 /* This code will reinit the Radeon CP hardware after a resume from disc.
1547  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1548  * here we make sure that all Radeon hardware initialisation is re-done without
1549  * affecting running applications.
1550  *
1551  * Charl P. Botha <http://cpbotha.net>
1552  */
1553 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1554 {
1555         drm_radeon_private_t *dev_priv = dev->dev_private;
1556
1557         if (!dev_priv) {
1558                 DRM_ERROR("Called with no initialization\n");
1559                 return -EINVAL;
1560         }
1561
1562         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1563
1564 #if __OS_HAS_AGP
1565         if (dev_priv->flags & RADEON_IS_AGP) {
1566                 /* Turn off PCI GART */
1567                 radeon_set_pcigart(dev_priv, 0);
1568         } else
1569 #endif
1570         {
1571                 /* Turn on PCI GART */
1572                 radeon_set_pcigart(dev_priv, 1);
1573         }
1574
1575         radeon_cp_load_microcode(dev_priv);
1576         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1577
1578         radeon_do_engine_reset(dev);
1579         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1580
1581         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1582
1583         return 0;
1584 }
1585
1586 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1587 {
1588         drm_radeon_private_t *dev_priv = dev->dev_private;
1589         drm_radeon_init_t *init = data;
1590
1591         LOCK_TEST_WITH_RETURN(dev, file_priv);
1592
1593         if (init->func == RADEON_INIT_R300_CP)
1594                 r300_init_reg_flags(dev);
1595
1596         switch (init->func) {
1597         case RADEON_INIT_CP:
1598         case RADEON_INIT_R200_CP:
1599         case RADEON_INIT_R300_CP:
1600                 return radeon_do_init_cp(dev, init, file_priv);
1601         case RADEON_INIT_R600_CP:
1602                 return r600_do_init_cp(dev, init, file_priv);
1603         case RADEON_CLEANUP_CP:
1604                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1605                         return r600_do_cleanup_cp(dev);
1606                 else
1607                         return radeon_do_cleanup_cp(dev);
1608         }
1609
1610         return -EINVAL;
1611 }
1612
1613 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1614 {
1615         drm_radeon_private_t *dev_priv = dev->dev_private;
1616         DRM_DEBUG("\n");
1617
1618         LOCK_TEST_WITH_RETURN(dev, file_priv);
1619
1620         if (dev_priv->cp_running) {
1621                 DRM_DEBUG("while CP running\n");
1622                 return 0;
1623         }
1624         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1625                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1626                           dev_priv->cp_mode);
1627                 return 0;
1628         }
1629
1630         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1631                 r600_do_cp_start(dev_priv);
1632         else
1633                 radeon_do_cp_start(dev_priv);
1634
1635         return 0;
1636 }
1637
1638 /* Stop the CP.  The engine must have been idled before calling this
1639  * routine.
1640  */
1641 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1642 {
1643         drm_radeon_private_t *dev_priv = dev->dev_private;
1644         drm_radeon_cp_stop_t *stop = data;
1645         int ret;
1646         DRM_DEBUG("\n");
1647
1648         LOCK_TEST_WITH_RETURN(dev, file_priv);
1649
1650         if (!dev_priv->cp_running)
1651                 return 0;
1652
1653         /* Flush any pending CP commands.  This ensures any outstanding
1654          * commands are exectuted by the engine before we turn it off.
1655          */
1656         if (stop->flush) {
1657                 radeon_do_cp_flush(dev_priv);
1658         }
1659
1660         /* If we fail to make the engine go idle, we return an error
1661          * code so that the DRM ioctl wrapper can try again.
1662          */
1663         if (stop->idle) {
1664                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1665                         ret = r600_do_cp_idle(dev_priv);
1666                 else
1667                         ret = radeon_do_cp_idle(dev_priv);
1668                 if (ret)
1669                         return ret;
1670         }
1671
1672         /* Finally, we can turn off the CP.  If the engine isn't idle,
1673          * we will get some dropped triangles as they won't be fully
1674          * rendered before the CP is shut down.
1675          */
1676         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1677                 r600_do_cp_stop(dev_priv);
1678         else
1679                 radeon_do_cp_stop(dev_priv);
1680
1681         /* Reset the engine */
1682         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1683                 r600_do_engine_reset(dev);
1684         else
1685                 radeon_do_engine_reset(dev);
1686
1687         return 0;
1688 }
1689
1690 void radeon_do_release(struct drm_device * dev)
1691 {
1692         drm_radeon_private_t *dev_priv = dev->dev_private;
1693         int i, ret;
1694
1695         if (dev_priv) {
1696                 if (dev_priv->cp_running) {
1697                         /* Stop the cp */
1698                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1699                                 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1700                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1701                                         tsleep_interlock(&dev->lock.lock_queue,
1702                                                          PCATCH);
1703                                         DRM_UNLOCK();
1704                                         ret = tsleep(&dev->lock.lock_queue,
1705                                                     PCATCH | PINTERLOCKED,
1706                                                     "rdnrel", 0);
1707                                         DRM_LOCK();
1708 /* DragonFly equivalent of
1709  *                                      mtx_sleep(&ret, &dev->dev_lock, 0,
1710  *                                          "rdnrel", 1);
1711  */
1712                                 }
1713                         } else {
1714                                 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1715                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1716                                         tsleep_interlock(&dev->lock.lock_queue,
1717                                                          PCATCH);
1718                                         DRM_UNLOCK();
1719                                         ret = tsleep(&dev->lock.lock_queue,
1720                                                     PCATCH | PINTERLOCKED,
1721                                                     "rdnrel", 0);
1722                                         DRM_LOCK();
1723                                 }
1724                         }
1725                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1726                                 r600_do_cp_stop(dev_priv);
1727                                 r600_do_engine_reset(dev);
1728                         } else {
1729                                 radeon_do_cp_stop(dev_priv);
1730                                 radeon_do_engine_reset(dev);
1731                         }
1732                 }
1733
1734                 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1735                         /* Disable *all* interrupts */
1736                         if (dev_priv->mmio)     /* remove this after permanent addmaps */
1737                                 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1738
1739                         if (dev_priv->mmio) {   /* remove all surfaces */
1740                                 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1741                                         RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1742                                         RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1743                                                      16 * i, 0);
1744                                         RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1745                                                      16 * i, 0);
1746                                 }
1747                         }
1748                 }
1749
1750                 /* Free memory heap structures */
1751                 radeon_mem_takedown(&(dev_priv->gart_heap));
1752                 radeon_mem_takedown(&(dev_priv->fb_heap));
1753
1754                 /* deallocate kernel resources */
1755                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1756                         r600_do_cleanup_cp(dev);
1757                 else
1758                         radeon_do_cleanup_cp(dev);
1759         }
1760 }
1761
1762 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1763  */
1764 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1765 {
1766         drm_radeon_private_t *dev_priv = dev->dev_private;
1767         DRM_DEBUG("\n");
1768
1769         LOCK_TEST_WITH_RETURN(dev, file_priv);
1770
1771         if (!dev_priv) {
1772                 DRM_DEBUG("called before init done\n");
1773                 return -EINVAL;
1774         }
1775
1776         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1777                 r600_do_cp_reset(dev_priv);
1778         else
1779                 radeon_do_cp_reset(dev_priv);
1780
1781         /* The CP is no longer running after an engine reset */
1782         dev_priv->cp_running = 0;
1783
1784         return 0;
1785 }
1786
1787 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1788 {
1789         drm_radeon_private_t *dev_priv = dev->dev_private;
1790         DRM_DEBUG("\n");
1791
1792         LOCK_TEST_WITH_RETURN(dev, file_priv);
1793
1794         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1795                 return r600_do_cp_idle(dev_priv);
1796         else
1797                 return radeon_do_cp_idle(dev_priv);
1798 }
1799
1800 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1801  */
1802 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1803 {
1804         drm_radeon_private_t *dev_priv = dev->dev_private;
1805         DRM_DEBUG("\n");
1806
1807         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1808                 return r600_do_resume_cp(dev, file_priv);
1809         else
1810                 return radeon_do_resume_cp(dev, file_priv);
1811 }
1812
1813 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1814 {
1815         drm_radeon_private_t *dev_priv = dev->dev_private;
1816         DRM_DEBUG("\n");
1817
1818         LOCK_TEST_WITH_RETURN(dev, file_priv);
1819
1820         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1821                 return r600_do_engine_reset(dev);
1822         else
1823                 return radeon_do_engine_reset(dev);
1824 }
1825
1826 /* ================================================================
1827  * Fullscreen mode
1828  */
1829
1830 /* KW: Deprecated to say the least:
1831  */
1832 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1833 {
1834         return 0;
1835 }
1836
1837 /* ================================================================
1838  * Freelist management
1839  */
1840
1841 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1842  *   bufs until freelist code is used.  Note this hides a problem with
1843  *   the scratch register * (used to keep track of last buffer
1844  *   completed) being written to before * the last buffer has actually
1845  *   completed rendering.
1846  *
1847  * KW:  It's also a good way to find free buffers quickly.
1848  *
1849  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1850  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1851  * we essentially have to do this, else old clients will break.
1852  *
1853  * However, it does leave open a potential deadlock where all the
1854  * buffers are held by other clients, which can't release them because
1855  * they can't get the lock.
1856  */
1857
1858 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1859 {
1860         struct drm_device_dma *dma = dev->dma;
1861         drm_radeon_private_t *dev_priv = dev->dev_private;
1862         drm_radeon_buf_priv_t *buf_priv;
1863         struct drm_buf *buf;
1864         int i, t;
1865         int start;
1866
1867         if (++dev_priv->last_buf >= dma->buf_count)
1868                 dev_priv->last_buf = 0;
1869
1870         start = dev_priv->last_buf;
1871
1872         for (t = 0; t < dev_priv->usec_timeout; t++) {
1873                 u32 done_age = GET_SCRATCH(dev_priv, 1);
1874                 DRM_DEBUG("done_age = %d\n", done_age);
1875                 for (i = 0; i < dma->buf_count; i++) {
1876                         buf = dma->buflist[start];
1877                         buf_priv = buf->dev_private;
1878                         if (buf->file_priv == NULL || (buf->pending &&
1879                                                        buf_priv->age <=
1880                                                        done_age)) {
1881                                 dev_priv->stats.requested_bufs++;
1882                                 buf->pending = 0;
1883                                 return buf;
1884                         }
1885                         if (++start >= dma->buf_count)
1886                                 start = 0;
1887                 }
1888
1889                 if (t) {
1890                         DRM_UDELAY(1);
1891                         dev_priv->stats.freelist_loops++;
1892                 }
1893         }
1894
1895         DRM_DEBUG("returning NULL!\n");
1896         return NULL;
1897 }
1898
1899 void radeon_freelist_reset(struct drm_device * dev)
1900 {
1901         struct drm_device_dma *dma = dev->dma;
1902         drm_radeon_private_t *dev_priv = dev->dev_private;
1903         int i;
1904
1905         dev_priv->last_buf = 0;
1906         for (i = 0; i < dma->buf_count; i++) {
1907                 struct drm_buf *buf = dma->buflist[i];
1908                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1909                 buf_priv->age = 0;
1910         }
1911 }
1912
1913 /* ================================================================
1914  * CP command submission
1915  */
1916
1917 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1918 {
1919         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1920         int i;
1921         u32 last_head = GET_RING_HEAD(dev_priv);
1922
1923         for (i = 0; i < dev_priv->usec_timeout; i++) {
1924                 u32 head = GET_RING_HEAD(dev_priv);
1925
1926                 ring->space = (head - ring->tail) * sizeof(u32);
1927                 if (ring->space <= 0)
1928                         ring->space += ring->size;
1929                 if (ring->space > n)
1930                         return 0;
1931
1932                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1933
1934                 if (head != last_head)
1935                         i = 0;
1936                 last_head = head;
1937
1938                 DRM_UDELAY(1);
1939         }
1940
1941         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1942 #if RADEON_FIFO_DEBUG
1943         radeon_status(dev_priv);
1944         DRM_ERROR("failed!\n");
1945 #endif
1946         return -EBUSY;
1947 }
1948
1949 static int radeon_cp_get_buffers(struct drm_device *dev,
1950                                  struct drm_file *file_priv,
1951                                  struct drm_dma * d)
1952 {
1953         int i;
1954         struct drm_buf *buf;
1955
1956         for (i = d->granted_count; i < d->request_count; i++) {
1957                 buf = radeon_freelist_get(dev);
1958                 if (!buf)
1959                         return -EBUSY;  /* NOTE: broken client */
1960
1961                 buf->file_priv = file_priv;
1962
1963                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1964                                      sizeof(buf->idx)))
1965                         return -EFAULT;
1966                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1967                                      sizeof(buf->total)))
1968                         return -EFAULT;
1969
1970                 d->granted_count++;
1971         }
1972         return 0;
1973 }
1974
1975 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1976 {
1977         struct drm_device_dma *dma = dev->dma;
1978         int ret = 0;
1979         struct drm_dma *d = data;
1980
1981         LOCK_TEST_WITH_RETURN(dev, file_priv);
1982
1983         /* Please don't send us buffers.
1984          */
1985         if (d->send_count != 0) {
1986                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1987                           DRM_CURRENTPID, d->send_count);
1988                 return -EINVAL;
1989         }
1990
1991         /* We'll send you buffers.
1992          */
1993         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1994                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1995                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1996                 return -EINVAL;
1997         }
1998
1999         d->granted_count = 0;
2000
2001         if (d->request_count) {
2002                 ret = radeon_cp_get_buffers(dev, file_priv, d);
2003         }
2004
2005         return ret;
2006 }
2007
2008 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2009 {
2010         drm_radeon_private_t *dev_priv;
2011         int ret = 0;
2012
2013         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2014         if (dev_priv == NULL)
2015                 return -ENOMEM;
2016
2017         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2018         dev->dev_private = (void *)dev_priv;
2019         dev_priv->flags = flags;
2020
2021         switch (flags & RADEON_FAMILY_MASK) {
2022         case CHIP_R100:
2023         case CHIP_RV200:
2024         case CHIP_R200:
2025         case CHIP_R300:
2026         case CHIP_R350:
2027         case CHIP_R420:
2028         case CHIP_R423:
2029         case CHIP_RV410:
2030         case CHIP_RV515:
2031         case CHIP_R520:
2032         case CHIP_RV570:
2033         case CHIP_R580:
2034                 dev_priv->flags |= RADEON_HAS_HIERZ;
2035                 break;
2036         default:
2037                 /* all other chips have no hierarchical z buffer */
2038                 break;
2039         }
2040
2041         if (drm_device_is_agp(dev))
2042                 dev_priv->flags |= RADEON_IS_AGP;
2043         else if (drm_device_is_pcie(dev))
2044                 dev_priv->flags |= RADEON_IS_PCIE;
2045         else
2046                 dev_priv->flags |= RADEON_IS_PCI;
2047
2048         DRM_SPININIT(&dev_priv->cs.cs_mutex, "cs_mtx");
2049
2050         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2051                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2052                          _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2053         if (ret != 0)
2054                 goto error;
2055
2056         ret = drm_vblank_init(dev, 2);
2057         if (ret != 0)
2058                 goto error;
2059
2060         dev->max_vblank_count = 0x001fffff;
2061
2062         DRM_DEBUG("%s card detected\n",
2063                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" :
2064                     (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2065
2066         return ret;
2067
2068 error:
2069         radeon_driver_unload(dev);
2070         return ret;
2071 }
2072
2073 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2074  * have to find them.
2075  */
2076 int radeon_driver_firstopen(struct drm_device *dev)
2077 {
2078         int ret;
2079         drm_local_map_t *map;
2080         drm_radeon_private_t *dev_priv = dev->dev_private;
2081
2082         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2083
2084         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2085         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2086                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2087                          _DRM_WRITE_COMBINING, &map);
2088         if (ret != 0)
2089                 return ret;
2090
2091         return 0;
2092 }
2093
2094 int radeon_driver_unload(struct drm_device *dev)
2095 {
2096         drm_radeon_private_t *dev_priv = dev->dev_private;
2097
2098         DRM_DEBUG("\n");
2099
2100         drm_rmmap(dev, dev_priv->mmio);
2101
2102         DRM_SPINUNINIT(&dev_priv->cs.cs_mutex);
2103
2104         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2105
2106         dev->dev_private = NULL;
2107         return 0;
2108 }
2109
2110 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2111 {
2112         int i;
2113         u32 *ring;
2114         int tail_aligned;
2115
2116         /* check if the ring is padded out to 16-dword alignment */
2117
2118         tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN - 1);
2119         if (tail_aligned) {
2120                 int num_p2 = RADEON_RING_ALIGN - tail_aligned;
2121
2122                 ring = dev_priv->ring.start;
2123                 /* pad with some CP_PACKET2 */
2124                 for (i = 0; i < num_p2; i++)
2125                         ring[dev_priv->ring.tail + i] = CP_PACKET2();
2126
2127                 dev_priv->ring.tail += i;
2128
2129                 dev_priv->ring.space -= num_p2 * sizeof(u32);
2130         }
2131
2132         dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2133
2134         DRM_MEMORYBARRIER();
2135         GET_RING_HEAD( dev_priv );
2136
2137         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2138                 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2139                 /* read from PCI bus to ensure correct posting */
2140                 RADEON_READ(R600_CP_RB_RPTR);
2141         } else {
2142                 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2143                 /* read from PCI bus to ensure correct posting */
2144                 RADEON_READ(RADEON_CP_RB_RPTR);
2145         }
2146 }