2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $
29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.60 2008/09/17 07:51:59 sephe Exp $
33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
36 #include "opt_polling.h"
37 #include "opt_ethernet.h"
39 #include <sys/param.h>
40 #include <sys/systm.h>
42 #include <sys/malloc.h>
43 #include <sys/kernel.h>
44 #include <sys/interrupt.h>
45 #include <sys/socket.h>
46 #include <sys/sysctl.h>
47 #include <sys/thread2.h>
50 #include <net/ifq_var.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
56 #include <netns/ns_if.h>
60 #include <sys/sockio.h>
64 #include <net/ethernet.h>
65 #include <net/if_arp.h>
67 #include <vm/vm.h> /* for vtophys */
68 #include <vm/pmap.h> /* for vtophys */
70 #include <net/if_types.h>
71 #include <net/vlan/if_vlan_var.h>
73 #include <bus/pci/pcivar.h>
74 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */
76 #include "../mii_layer/mii.h"
77 #include "../mii_layer/miivar.h"
79 #include "if_fxpreg.h"
80 #include "if_fxpvar.h"
83 #include "miibus_if.h"
86 * NOTE! On the Alpha, we have an alignment constraint. The
87 * card DMAs the packet immediately following the RFA. However,
88 * the first thing in the packet is a 14-byte Ethernet header.
89 * This means that the packet is misaligned. To compensate,
90 * we actually offset the RFA 2 bytes into the cluster. This
91 * alignes the packet after the Ethernet header at a 32-bit
92 * boundary. HOWEVER! This means that the RFA is misaligned!
94 #define RFA_ALIGNMENT_FUDGE 2
97 * Set initial transmit threshold at 64 (512 bytes). This is
98 * increased by 64 (512 bytes) at a time, to maximum of 192
99 * (1536 bytes), if an underrun occurs.
101 static int tx_threshold = 64;
104 * The configuration byte map has several undefined fields which
105 * must be one or must be zero. Set up a template for these bits
106 * only, (assuming a 82557 chip) leaving the actual configuration
109 * See struct fxp_cb_config for the bit definitions.
111 static u_char fxp_cb_config_template[] = {
112 0x0, 0x0, /* cb_status */
113 0x0, 0x0, /* cb_command */
114 0x0, 0x0, 0x0, 0x0, /* link_addr */
141 int16_t revid; /* -1 matches anything */
146 * Claim various Intel PCI device identifiers for this driver. The
147 * sub-vendor and sub-device field are extensively used to identify
148 * particular variants, but we don't currently differentiate between
151 static struct fxp_ident fxp_ident_table[] = {
152 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" },
153 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" },
154 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
155 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
156 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
157 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
158 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
159 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
160 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
161 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
162 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
163 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
164 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
165 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
166 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
167 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
168 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
169 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
170 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" },
171 { 0x1064, -1, "Intel 82562ET/EZ/GT/GZ (ICH6/ICH6R) Pro/100 VE Ethernet" },
172 { 0x1065, -1, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
173 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
174 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
175 { 0x1091, -1, "Intel 82562GX Pro/100 Ethernet" },
176 { 0x1092, -1, "Intel Pro/100 VE Network Connection" },
177 { 0x1093, -1, "Intel Pro/100 VM Network Connection" },
178 { 0x1094, -1, "Intel Pro/100 946GZ (ICH7) Network Connection" },
179 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" },
180 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" },
181 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" },
182 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" },
183 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" },
184 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" },
185 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" },
186 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" },
187 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" },
188 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" },
189 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" },
190 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" },
191 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" },
192 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" },
193 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" },
194 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" },
195 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
196 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" },
200 static int fxp_probe(device_t dev);
201 static int fxp_attach(device_t dev);
202 static int fxp_detach(device_t dev);
203 static int fxp_shutdown(device_t dev);
204 static int fxp_suspend(device_t dev);
205 static int fxp_resume(device_t dev);
207 static void fxp_intr(void *xsc);
208 static void fxp_intr_body(struct fxp_softc *sc,
209 u_int8_t statack, int count);
211 static void fxp_init(void *xsc);
212 static void fxp_tick(void *xsc);
213 static void fxp_powerstate_d0(device_t dev);
214 static void fxp_start(struct ifnet *ifp);
215 static void fxp_stop(struct fxp_softc *sc);
216 static void fxp_release(device_t dev);
217 static int fxp_ioctl(struct ifnet *ifp, u_long command,
218 caddr_t data, struct ucred *);
219 static void fxp_watchdog(struct ifnet *ifp);
220 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm);
221 static int fxp_mc_addrs(struct fxp_softc *sc);
222 static void fxp_mc_setup(struct fxp_softc *sc);
223 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
225 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
227 static void fxp_autosize_eeprom(struct fxp_softc *sc);
228 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
229 int offset, int words);
230 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
231 int offset, int words);
232 static int fxp_ifmedia_upd(struct ifnet *ifp);
233 static void fxp_ifmedia_sts(struct ifnet *ifp,
234 struct ifmediareq *ifmr);
235 static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
236 static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
237 struct ifmediareq *ifmr);
238 static int fxp_miibus_readreg(device_t dev, int phy, int reg);
239 static void fxp_miibus_writereg(device_t dev, int phy, int reg,
241 static void fxp_load_ucode(struct fxp_softc *sc);
242 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
243 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
244 #ifdef DEVICE_POLLING
245 static poll_handler_t fxp_poll;
248 static void fxp_lwcopy(volatile u_int32_t *src,
249 volatile u_int32_t *dst);
250 static void fxp_scb_wait(struct fxp_softc *sc);
251 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
252 static void fxp_dma_wait(volatile u_int16_t *status,
253 struct fxp_softc *sc);
255 static device_method_t fxp_methods[] = {
256 /* Device interface */
257 DEVMETHOD(device_probe, fxp_probe),
258 DEVMETHOD(device_attach, fxp_attach),
259 DEVMETHOD(device_detach, fxp_detach),
260 DEVMETHOD(device_shutdown, fxp_shutdown),
261 DEVMETHOD(device_suspend, fxp_suspend),
262 DEVMETHOD(device_resume, fxp_resume),
265 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
266 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
271 static driver_t fxp_driver = {
274 sizeof(struct fxp_softc),
277 static devclass_t fxp_devclass;
279 DECLARE_DUMMY_MODULE(if_fxp);
280 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1);
281 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0);
282 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0);
283 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
286 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events");
289 * Copy a 16-bit aligned 32-bit quantity.
292 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst)
297 volatile u_int16_t *a = (volatile u_int16_t *)src;
298 volatile u_int16_t *b = (volatile u_int16_t *)dst;
306 * Wait for the previous command to be accepted (but not necessarily
310 fxp_scb_wait(struct fxp_softc *sc)
314 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
317 if_printf(&sc->arpcom.ac_if,
318 "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
319 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
320 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
321 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
322 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
327 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
330 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
331 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
334 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
338 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc)
342 while (!(*status & FXP_CB_STATUS_C) && --i)
345 if_printf(&sc->arpcom.ac_if, "DMA timeout\n");
349 * Return identification string if this is device is ours.
352 fxp_probe(device_t dev)
356 struct fxp_ident *ident;
358 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
359 devid = pci_get_device(dev);
360 revid = pci_get_revid(dev);
361 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
362 if (ident->devid == devid &&
363 (ident->revid == revid || ident->revid == -1)) {
364 device_set_desc(dev, ident->name);
373 fxp_powerstate_d0(device_t dev)
375 u_int32_t iobase, membase, irq;
377 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
378 /* Save important PCI config data. */
379 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4);
380 membase = pci_read_config(dev, FXP_PCI_MMBA, 4);
381 irq = pci_read_config(dev, PCIR_INTLINE, 4);
383 /* Reset the power state. */
384 device_printf(dev, "chip is in D%d power mode "
385 "-- setting to D0\n", pci_get_powerstate(dev));
387 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
389 /* Restore PCI config data. */
390 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4);
391 pci_write_config(dev, FXP_PCI_MMBA, membase, 4);
392 pci_write_config(dev, PCIR_INTLINE, irq, 4);
397 fxp_attach(device_t dev)
400 struct fxp_softc *sc = device_get_softc(dev);
404 int i, rid, m1, m2, prefer_iomap;
406 callout_init(&sc->fxp_stat_timer);
407 sysctl_ctx_init(&sc->sysctl_ctx);
410 * Enable bus mastering. Enable memory space too, in case
411 * BIOS/Prom forgot about it.
413 pci_enable_busmaster(dev);
414 pci_enable_io(dev, SYS_RES_MEMORY);
415 val = pci_read_config(dev, PCIR_COMMAND, 2);
417 fxp_powerstate_d0(dev);
420 * Figure out which we should try first - memory mapping or i/o mapping?
421 * We default to memory mapping. Then we accept an override from the
422 * command line. Then we check to see which one is enabled.
425 m2 = PCIM_CMD_PORTEN;
427 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
428 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
429 m1 = PCIM_CMD_PORTEN;
435 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
436 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
437 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd,
440 if (sc->mem == NULL && (val & m2)) {
442 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
443 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
444 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd,
449 device_printf(dev, "could not map device registers\n");
454 device_printf(dev, "using %s space register mapping\n",
455 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
458 sc->sc_st = rman_get_bustag(sc->mem);
459 sc->sc_sh = rman_get_bushandle(sc->mem);
462 * Allocate our interrupt.
465 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
466 RF_SHAREABLE | RF_ACTIVE);
467 if (sc->irq == NULL) {
468 device_printf(dev, "could not map interrupt\n");
474 * Reset to a stable state.
476 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
479 sc->cbl_base = kmalloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
480 M_DEVBUF, M_WAITOK | M_ZERO);
482 sc->fxp_stats = kmalloc(sizeof(struct fxp_stats), M_DEVBUF,
485 sc->mcsp = kmalloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK);
488 * Pre-allocate our receive buffers.
490 for (i = 0; i < FXP_NRFABUFS; i++) {
491 if (fxp_add_rfabuf(sc, NULL) != 0) {
497 * Find out how large of an SEEPROM we have.
499 fxp_autosize_eeprom(sc);
502 * Determine whether we must use the 503 serial interface.
504 fxp_read_eeprom(sc, &data, 6, 1);
505 if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
506 (data & FXP_PHY_SERIAL_ONLY))
507 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
510 * Create the sysctl tree
512 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
513 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
514 device_get_nameunit(dev), CTLFLAG_RD, 0, "");
515 if (sc->sysctl_tree == NULL)
517 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
518 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
519 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I",
520 "FXP driver receive interrupt microcode bundling delay");
521 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
522 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
523 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I",
524 "FXP driver receive interrupt microcode bundle size limit");
527 * Pull in device tunables.
529 sc->tunable_int_delay = TUNABLE_INT_DELAY;
530 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
531 resource_int_value(device_get_name(dev), device_get_unit(dev),
532 "int_delay", &sc->tunable_int_delay);
533 resource_int_value(device_get_name(dev), device_get_unit(dev),
534 "bundle_max", &sc->tunable_bundle_max);
537 * Find out the chip revision; lump all 82557 revs together.
539 fxp_read_eeprom(sc, &data, 5, 1);
540 if ((data >> 8) == 1)
541 sc->revision = FXP_REV_82557;
543 sc->revision = pci_get_revid(dev);
546 * Enable workarounds for certain chip revision deficiencies.
548 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
549 * some systems based a normal 82559 design, have a defect where
550 * the chip can cause a PCI protocol violation if it receives
551 * a CU_RESUME command when it is entering the IDLE state. The
552 * workaround is to disable Dynamic Standby Mode, so the chip never
553 * deasserts CLKRUN#, and always remains in an active state.
555 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
557 i = pci_get_device(dev);
558 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) ||
559 sc->revision >= FXP_REV_82559_A0) {
560 fxp_read_eeprom(sc, &data, 10, 1);
561 if (data & 0x02) { /* STB enable */
566 "Disabling dynamic standby mode in EEPROM\n");
568 fxp_write_eeprom(sc, &data, 10, 1);
569 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
571 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
572 fxp_read_eeprom(sc, &data, i, 1);
575 i = (1 << sc->eeprom_size) - 1;
576 cksum = 0xBABA - cksum;
577 fxp_read_eeprom(sc, &data, i, 1);
578 fxp_write_eeprom(sc, &cksum, i, 1);
580 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
584 * If the user elects to continue, try the software
585 * workaround, as it is better than nothing.
587 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
593 * If we are not a 82557 chip, we can enable extended features.
595 if (sc->revision != FXP_REV_82557) {
597 * If MWI is enabled in the PCI configuration, and there
598 * is a valid cacheline size (8 or 16 dwords), then tell
599 * the board to turn on MWI.
601 if (val & PCIM_CMD_MWRICEN &&
602 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
603 sc->flags |= FXP_FLAG_MWI_ENABLE;
605 /* turn on the extended TxCB feature */
606 sc->flags |= FXP_FLAG_EXT_TXCB;
608 /* enable reception of long frames for VLAN */
609 sc->flags |= FXP_FLAG_LONG_PKT_EN;
615 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3);
616 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
617 device_printf(dev, "10Mbps\n");
619 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
620 pci_get_vendor(dev), pci_get_device(dev),
621 pci_get_subvendor(dev), pci_get_subdevice(dev),
623 fxp_read_eeprom(sc, &data, 10, 1);
624 device_printf(dev, "Dynamic Standby mode is %s\n",
625 data & 0x02 ? "enabled" : "disabled");
629 * If this is only a 10Mbps device, then there is no MII, and
630 * the PHY will use a serial interface instead.
632 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
633 * doesn't have a programming interface of any sort. The
634 * media is sensed automatically based on how the link partner
635 * is configured. This is, in essence, manual configuration.
637 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
638 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
639 fxp_serial_ifmedia_sts);
640 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
641 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
643 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
645 device_printf(dev, "MII without any PHY!\n");
651 ifp = &sc->arpcom.ac_if;
652 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
653 ifp->if_baudrate = 100000000;
654 ifp->if_init = fxp_init;
656 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
657 ifp->if_ioctl = fxp_ioctl;
658 ifp->if_start = fxp_start;
659 #ifdef DEVICE_POLLING
660 ifp->if_poll = fxp_poll;
662 ifp->if_watchdog = fxp_watchdog;
665 * Attach the interface.
667 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
670 * Tell the upper layer(s) we support long frames.
672 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
675 * Let the system queue as many packets as we have available
678 ifq_set_maxlen(&ifp->if_snd, FXP_USABLE_TXCB);
679 ifq_set_ready(&ifp->if_snd);
681 error = bus_setup_intr(dev, sc->irq, INTR_MPSAFE,
682 fxp_intr, sc, &sc->ih,
686 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
687 ifmedia_removeall(&sc->sc_media);
688 device_printf(dev, "could not setup irq\n");
692 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->irq));
693 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
698 device_printf(dev, "Failed to malloc memory\n");
706 * release all resources
709 fxp_release(device_t dev)
711 struct fxp_softc *sc = device_get_softc(dev);
714 device_delete_child(dev, sc->miibus);
715 bus_generic_detach(dev);
718 kfree(sc->cbl_base, M_DEVBUF);
720 kfree(sc->fxp_stats, M_DEVBUF);
722 kfree(sc->mcsp, M_DEVBUF);
724 m_freem(sc->rfa_headm);
727 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
729 bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem);
731 sysctl_ctx_free(&sc->sysctl_ctx);
738 fxp_detach(device_t dev)
740 struct fxp_softc *sc = device_get_softc(dev);
742 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
745 * Stop DMA and drop transmit queue.
750 * Disable interrupts.
752 * NOTE: This should be done after fxp_stop(), because software
753 * resetting in fxp_stop() may leave interrupts turned on.
755 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
758 * Free all media structures.
760 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
761 ifmedia_removeall(&sc->sc_media);
764 bus_teardown_intr(dev, sc->irq, sc->ih);
766 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
769 * Close down routes etc.
771 ether_ifdetach(&sc->arpcom.ac_if);
773 /* Release our allocated resources. */
780 * Device shutdown routine. Called at system shutdown after sync. The
781 * main purpose of this routine is to shut off receiver DMA so that
782 * kernel memory doesn't get clobbered during warmboot.
785 fxp_shutdown(device_t dev)
787 struct fxp_softc *sc = device_get_softc(dev);
788 struct ifnet *ifp = &sc->arpcom.ac_if;
790 lwkt_serialize_enter(ifp->if_serializer);
792 * Make sure that DMA is disabled prior to reboot. Not doing
793 * do could allow DMA to corrupt kernel memory during the
794 * reboot before the driver initializes.
797 lwkt_serialize_exit(ifp->if_serializer);
802 * Device suspend routine. Stop the interface and save some PCI
803 * settings in case the BIOS doesn't restore them properly on
807 fxp_suspend(device_t dev)
809 struct fxp_softc *sc = device_get_softc(dev);
812 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
816 for (i = 0; i < 5; i++)
817 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
818 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
819 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
820 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
821 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
825 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
830 * Device resume routine. Restore some PCI settings in case the BIOS
831 * doesn't, re-enable busmastering, and restart the interface if
835 fxp_resume(device_t dev)
837 struct fxp_softc *sc = device_get_softc(dev);
838 struct ifnet *ifp = &sc->arpcom.ac_if;
841 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
843 fxp_powerstate_d0(dev);
845 /* better way to do this? */
846 for (i = 0; i < 5; i++)
847 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
848 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
849 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
850 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
851 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
853 /* reenable busmastering and memory space */
854 pci_enable_busmaster(dev);
855 pci_enable_io(dev, SYS_RES_MEMORY);
857 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
860 /* reinitialize interface if necessary */
861 if (ifp->if_flags & IFF_UP)
866 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
871 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
879 for (x = 1 << (length - 1); x; x >>= 1) {
881 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
883 reg = FXP_EEPROM_EECS;
884 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
886 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
888 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
894 * Read from the serial EEPROM. Basically, you manually shift in
895 * the read opcode (one bit at a time) and then shift in the address,
896 * and then you shift out the data (all of this one bit at a time).
897 * The word size is 16 bits, so you have to provide the address for
898 * every 16 bits of data.
901 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
906 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
908 * Shift in read opcode.
910 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
915 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
917 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
919 reg = FXP_EEPROM_EECS;
920 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
922 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
924 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
926 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
928 if (autosize && reg == 0) {
929 sc->eeprom_size = data;
937 reg = FXP_EEPROM_EECS;
938 for (x = 1 << 15; x; x >>= 1) {
939 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
941 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
943 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
946 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
953 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
958 * Erase/write enable.
960 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
961 fxp_eeprom_shiftin(sc, 0x4, 3);
962 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
963 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
966 * Shift in write opcode, address, data.
968 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
969 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
970 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
971 fxp_eeprom_shiftin(sc, data, 16);
972 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
975 * Wait for EEPROM to finish up.
977 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
979 for (i = 0; i < 1000; i++) {
980 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
984 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
987 * Erase/write disable.
989 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
990 fxp_eeprom_shiftin(sc, 0x4, 3);
991 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
992 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
999 * Figure out EEPROM size.
1001 * 559's can have either 64-word or 256-word EEPROMs, the 558
1002 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1003 * talks about the existance of 16 to 256 word EEPROMs.
1005 * The only known sizes are 64 and 256, where the 256 version is used
1006 * by CardBus cards to store CIS information.
1008 * The address is shifted in msb-to-lsb, and after the last
1009 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
1010 * after which follows the actual data. We try to detect this zero, by
1011 * probing the data-out bit in the EEPROM control register just after
1012 * having shifted in a bit. If the bit is zero, we assume we've
1013 * shifted enough address bits. The data-out should be tri-state,
1014 * before this, which should translate to a logical one.
1017 fxp_autosize_eeprom(struct fxp_softc *sc)
1020 /* guess maximum size of 256 words */
1021 sc->eeprom_size = 8;
1024 fxp_eeprom_getword(sc, 0, 1);
1028 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1032 for (i = 0; i < words; i++)
1033 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1037 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1041 for (i = 0; i < words; i++)
1042 fxp_eeprom_putword(sc, offset + i, data[i]);
1046 * Start packet transmission on the interface.
1049 fxp_start(struct ifnet *ifp)
1051 struct fxp_softc *sc = ifp->if_softc;
1052 struct fxp_cb_tx *txp;
1054 ASSERT_SERIALIZED(ifp->if_serializer);
1057 * See if we need to suspend xmit until the multicast filter
1058 * has been reprogrammed (which can only be done at the head
1059 * of the command chain).
1061 if (sc->need_mcsetup) {
1062 ifq_purge(&ifp->if_snd);
1066 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1072 * We're finished if there is nothing more to add to the list or if
1073 * we're all filled up with buffers to transmit.
1074 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1075 * a NOP command when needed.
1077 while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_USABLE_TXCB) {
1078 struct mbuf *m, *mb_head;
1079 int segment, ntries = 0;
1082 * Grab a packet to transmit.
1084 mb_head = ifq_dequeue(&ifp->if_snd, NULL);
1085 if (mb_head == NULL)
1089 * Make sure that the packet fits into one TX desc
1092 for (m = mb_head; m != NULL; m = m->m_next) {
1093 if (m->m_len != 0) {
1095 if (segment >= FXP_NTXSEG)
1099 if (segment >= FXP_NTXSEG) {
1104 * Packet is excessively fragmented,
1105 * and will never fit into one TX
1113 mn = m_dup(mb_head, MB_DONTWAIT);
1127 * Get pointer to next available tx desc.
1129 txp = sc->cbl_last->next;
1132 * Go through each of the mbufs in the chain and initialize
1133 * the transmit buffer descriptors with the physical address
1134 * and size of the mbuf.
1136 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
1137 if (m->m_len != 0) {
1138 KKASSERT(segment < FXP_NTXSEG);
1140 txp->tbd[segment].tb_addr =
1141 vtophys(mtod(m, vm_offset_t));
1142 txp->tbd[segment].tb_size = m->m_len;
1146 KKASSERT(m == NULL);
1148 txp->tbd_number = segment;
1149 txp->mb_head = mb_head;
1151 if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1153 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1157 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1158 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
1160 txp->tx_threshold = tx_threshold;
1163 * Advance the end of list forward.
1165 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
1169 * Advance the beginning of the list forward if there are
1170 * no other packets queued (when nothing is queued, cbl_first
1171 * sits on the last TxCB that was sent out).
1173 if (sc->tx_queued == 0)
1174 sc->cbl_first = txp;
1178 * Set a 5 second timer just in case we don't hear
1179 * from the card again.
1183 BPF_MTAP(ifp, mb_head);
1186 if (sc->tx_queued >= FXP_USABLE_TXCB)
1187 ifp->if_flags |= IFF_OACTIVE;
1190 * We're finished. If we added to the list, issue a RESUME to get DMA
1191 * going again if suspended.
1195 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1199 #ifdef DEVICE_POLLING
1202 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1204 struct fxp_softc *sc = ifp->if_softc;
1207 ASSERT_SERIALIZED(ifp->if_serializer);
1211 /* disable interrupts */
1212 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1214 case POLL_DEREGISTER:
1215 /* enable interrupts */
1216 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1219 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1221 if (cmd == POLL_AND_CHECK_STATUS) {
1224 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1225 if (tmp == 0xff || tmp == 0)
1226 return; /* nothing to do */
1228 /* ack what we can */
1230 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1233 fxp_intr_body(sc, statack, count);
1238 #endif /* DEVICE_POLLING */
1241 * Process interface interrupts.
1246 struct fxp_softc *sc = xsc;
1249 ASSERT_SERIALIZED(sc->arpcom.ac_if.if_serializer);
1251 if (sc->suspended) {
1255 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1257 * It should not be possible to have all bits set; the
1258 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1259 * all bits are set, this may indicate that the card has
1260 * been physically ejected, so ignore it.
1262 if (statack == 0xff)
1266 * First ACK all the interrupts in this pass.
1268 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1269 fxp_intr_body(sc, statack, -1);
1274 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count)
1276 struct ifnet *ifp = &sc->arpcom.ac_if;
1278 struct fxp_rfa *rfa;
1279 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1280 #ifdef ETHER_INPUT_CHAIN
1281 struct mbuf_chain chain[MAXCPU];
1286 #ifdef DEVICE_POLLING
1287 /* Pick up a deferred RNR condition if `count' ran out last time. */
1288 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1289 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1295 * Free any finished transmit mbuf chains.
1297 * Handle the CNA event likt a CXTNO event. It used to
1298 * be that this event (control unit not ready) was not
1299 * encountered, but it is now with the SMPng modifications.
1300 * The exact sequence of events that occur when the interface
1301 * is brought up are different now, and if this event
1302 * goes unhandled, the configuration/rxfilter setup sequence
1303 * can stall for several seconds. The result is that no
1304 * packets go out onto the wire for about 5 to 10 seconds
1305 * after the interface is ifconfig'ed for the first time.
1307 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1308 struct fxp_cb_tx *txp;
1310 for (txp = sc->cbl_first; sc->tx_queued &&
1311 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1313 if ((m = txp->mb_head) != NULL) {
1314 txp->mb_head = NULL;
1321 sc->cbl_first = txp;
1323 if (sc->tx_queued < FXP_USABLE_TXCB)
1324 ifp->if_flags &= ~IFF_OACTIVE;
1326 if (sc->tx_queued == 0) {
1328 if (sc->need_mcsetup)
1333 * Try to start more packets transmitting.
1335 if (!ifq_is_empty(&ifp->if_snd))
1340 * Just return if nothing happened on the receive side.
1342 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1345 #ifdef ETHER_INPUT_CHAIN
1346 ether_input_chain_init(chain);
1350 * Process receiver interrupts. If a no-resource (RNR)
1351 * condition exists, get whatever packets we can and
1352 * re-start the receiver.
1354 * When using polling, we do not process the list to completion,
1355 * so when we get an RNR interrupt we must defer the restart
1356 * until we hit the last buffer with the C bit set.
1357 * If we run out of cycles and rfa_headm has the C bit set,
1358 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1359 * that the info will be used in the subsequent polling cycle.
1363 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1364 RFA_ALIGNMENT_FUDGE);
1366 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1367 if (count >= 0 && count-- == 0) {
1369 /* Defer RNR processing until the next time. */
1370 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1375 #endif /* DEVICE_POLLING */
1377 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0)
1381 * Remove first packet from the chain.
1383 sc->rfa_headm = m->m_next;
1387 * Add a new buffer to the receive chain.
1388 * If this fails, the old buffer is recycled
1391 if (fxp_add_rfabuf(sc, m) == 0) {
1395 * Fetch packet length (the top 2 bits of
1396 * actual_size are flags set by the controller
1397 * upon completion), and drop the packet in case
1398 * of bogus length or CRC errors.
1400 total_len = rfa->actual_size & 0x3fff;
1401 if (total_len < sizeof(struct ether_header) ||
1402 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE -
1403 sizeof(struct fxp_rfa) ||
1404 rfa->rfa_status & FXP_RFA_STATUS_CRC) {
1408 m->m_pkthdr.len = m->m_len = total_len;
1409 #ifdef ETHER_INPUT_CHAIN
1410 ether_input_chain(ifp, m, chain);
1412 ifp->if_input(ifp, m);
1417 #ifdef ETHER_INPUT_CHAIN
1418 ether_input_dispatch(chain);
1423 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1424 vtophys(sc->rfa_headm->m_ext.ext_buf) +
1425 RFA_ALIGNMENT_FUDGE);
1426 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1431 * Update packet in/out/collision statistics. The i82557 doesn't
1432 * allow you to access these counters without doing a fairly
1433 * expensive DMA to get _all_ of the statistics it maintains, so
1434 * we do this operation here only once per second. The statistics
1435 * counters in the kernel are updated from the previous dump-stats
1436 * DMA and then a new dump-stats DMA is started. The on-chip
1437 * counters are zeroed when the DMA completes. If we can't start
1438 * the DMA immediately, we don't wait - we just prepare to read
1439 * them again next time.
1444 struct fxp_softc *sc = xsc;
1445 struct ifnet *ifp = &sc->arpcom.ac_if;
1446 struct fxp_stats *sp = sc->fxp_stats;
1447 struct fxp_cb_tx *txp;
1450 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1452 ifp->if_opackets += sp->tx_good;
1453 ifp->if_collisions += sp->tx_total_collisions;
1455 ifp->if_ipackets += sp->rx_good;
1456 sc->rx_idle_secs = 0;
1459 * Receiver's been idle for another second.
1465 sp->rx_alignment_errors +
1467 sp->rx_overrun_errors;
1469 * If any transmit underruns occured, bump up the transmit
1470 * threshold by another 512 bytes (64 * 8).
1472 if (sp->tx_underruns) {
1473 ifp->if_oerrors += sp->tx_underruns;
1474 if (tx_threshold < 192)
1479 * Release any xmit buffers that have completed DMA. This isn't
1480 * strictly necessary to do here, but it's advantagous for mbufs
1481 * with external storage to be released in a timely manner rather
1482 * than being defered for a potentially long time. This limits
1483 * the delay to a maximum of one second.
1485 for (txp = sc->cbl_first; sc->tx_queued &&
1486 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1488 if ((m = txp->mb_head) != NULL) {
1489 txp->mb_head = NULL;
1496 sc->cbl_first = txp;
1498 if (sc->tx_queued < FXP_USABLE_TXCB)
1499 ifp->if_flags &= ~IFF_OACTIVE;
1500 if (sc->tx_queued == 0)
1504 * Try to start more packets transmitting.
1506 if (!ifq_is_empty(&ifp->if_snd))
1510 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1511 * then assume the receiver has locked up and attempt to clear
1512 * the condition by reprogramming the multicast filter. This is
1513 * a work-around for a bug in the 82557 where the receiver locks
1514 * up if it gets certain types of garbage in the syncronization
1515 * bits prior to the packet header. This bug is supposed to only
1516 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1517 * mode as well (perhaps due to a 10/100 speed transition).
1519 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1520 sc->rx_idle_secs = 0;
1524 * If there is no pending command, start another stats
1525 * dump. Otherwise punt for now.
1527 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1529 * Start another stats dump.
1531 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1534 * A previous command is still waiting to be accepted.
1535 * Just zero our copy of the stats and wait for the
1536 * next timer event to update them.
1539 sp->tx_underruns = 0;
1540 sp->tx_total_collisions = 0;
1543 sp->rx_crc_errors = 0;
1544 sp->rx_alignment_errors = 0;
1545 sp->rx_rnr_errors = 0;
1546 sp->rx_overrun_errors = 0;
1548 if (sc->miibus != NULL)
1549 mii_tick(device_get_softc(sc->miibus));
1551 * Schedule another timeout one second from now.
1553 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc);
1555 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1559 * Stop the interface. Cancels the statistics updater and resets
1563 fxp_stop(struct fxp_softc *sc)
1565 struct ifnet *ifp = &sc->arpcom.ac_if;
1566 struct fxp_cb_tx *txp;
1569 ASSERT_SERIALIZED(ifp->if_serializer);
1571 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1575 * Cancel stats updater.
1577 callout_stop(&sc->fxp_stat_timer);
1580 * Issue software reset, which also unloads the microcode.
1582 sc->flags &= ~FXP_FLAG_UCODE;
1583 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
1587 * Release any xmit buffers.
1591 for (i = 0; i < FXP_NTXCB; i++) {
1592 if (txp[i].mb_head != NULL) {
1593 m_freem(txp[i].mb_head);
1594 txp[i].mb_head = NULL;
1601 * Free all the receive buffers then reallocate/reinitialize
1603 if (sc->rfa_headm != NULL)
1604 m_freem(sc->rfa_headm);
1605 sc->rfa_headm = NULL;
1606 sc->rfa_tailm = NULL;
1607 for (i = 0; i < FXP_NRFABUFS; i++) {
1608 if (fxp_add_rfabuf(sc, NULL) != 0) {
1610 * This "can't happen" - we're at splimp()
1611 * and we just freed all the buffers we need
1614 panic("fxp_stop: no buffers!");
1620 * Watchdog/transmission transmit timeout handler. Called when a
1621 * transmission is started on the interface, but no interrupt is
1622 * received before the timeout. This usually indicates that the
1623 * card has wedged for some reason.
1626 fxp_watchdog(struct ifnet *ifp)
1628 ASSERT_SERIALIZED(ifp->if_serializer);
1630 if_printf(ifp, "device timeout\n");
1632 fxp_init(ifp->if_softc);
1638 struct fxp_softc *sc = xsc;
1639 struct ifnet *ifp = &sc->arpcom.ac_if;
1640 struct fxp_cb_config *cbp;
1641 struct fxp_cb_ias *cb_ias;
1642 struct fxp_cb_tx *txp;
1643 struct fxp_cb_mcs *mcsp;
1646 ASSERT_SERIALIZED(ifp->if_serializer);
1649 * Cancel any pending I/O
1653 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1656 * Initialize base of CBL and RFA memory. Loading with zero
1657 * sets it up for regular linear addressing.
1659 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1660 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1663 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1666 * Initialize base of dump-stats buffer.
1669 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1670 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1673 * Attempt to load microcode if requested.
1675 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0)
1679 * Initialize the multicast address list.
1681 if (fxp_mc_addrs(sc)) {
1683 mcsp->cb_status = 0;
1684 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL;
1685 mcsp->link_addr = -1;
1687 * Start the multicast setup command.
1690 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
1691 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1692 /* ...and wait for it to complete. */
1693 fxp_dma_wait(&mcsp->cb_status, sc);
1697 * We temporarily use memory that contains the TxCB list to
1698 * construct the config CB. The TxCB list memory is rebuilt
1701 cbp = (struct fxp_cb_config *) sc->cbl_base;
1704 * This bcopy is kind of disgusting, but there are a bunch of must be
1705 * zero and must be one bits in this structure and this is the easiest
1706 * way to initialize them all to proper values.
1708 bcopy(fxp_cb_config_template,
1709 (void *)(uintptr_t)(volatile void *)&cbp->cb_status,
1710 sizeof(fxp_cb_config_template));
1713 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
1714 cbp->link_addr = -1; /* (no) next command */
1715 cbp->byte_count = 22; /* (22) bytes to config */
1716 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1717 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
1718 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
1719 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
1720 cbp->type_enable = 0; /* actually reserved */
1721 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
1722 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
1723 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
1724 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
1725 cbp->dma_mbce = 0; /* (disable) dma max counters */
1726 cbp->late_scb = 0; /* (don't) defer SCB update */
1727 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
1728 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
1729 cbp->ci_int = 1; /* interrupt on CU idle */
1730 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
1731 cbp->ext_stats_dis = 1; /* disable extended counters */
1732 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
1733 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm;
1734 cbp->disc_short_rx = !prm; /* discard short packets */
1735 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
1736 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
1737 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */
1738 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
1739 cbp->csma_dis = 0; /* (don't) disable link */
1740 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */
1741 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
1742 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
1743 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
1744 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
1745 cbp->nsai = 1; /* (don't) disable source addr insert */
1746 cbp->preamble_length = 2; /* (7 byte) preamble */
1747 cbp->loopback = 0; /* (don't) loopback */
1748 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
1749 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
1750 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
1751 cbp->promiscuous = prm; /* promiscuous mode */
1752 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
1753 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
1754 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
1755 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
1756 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
1758 cbp->stripping = !prm; /* truncate rx packet to byte count */
1759 cbp->padding = 1; /* (do) pad short tx packets */
1760 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
1761 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
1762 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
1763 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */
1764 /* must set wake_en in PMCSR also */
1765 cbp->force_fdx = 0; /* (don't) force full duplex */
1766 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
1767 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
1768 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
1770 if (sc->revision == FXP_REV_82557) {
1772 * The 82557 has no hardware flow control, the values
1773 * below are the defaults for the chip.
1775 cbp->fc_delay_lsb = 0;
1776 cbp->fc_delay_msb = 0x40;
1777 cbp->pri_fc_thresh = 3;
1779 cbp->rx_fc_restop = 0;
1780 cbp->rx_fc_restart = 0;
1782 cbp->pri_fc_loc = 1;
1784 cbp->fc_delay_lsb = 0x1f;
1785 cbp->fc_delay_msb = 0x01;
1786 cbp->pri_fc_thresh = 3;
1787 cbp->tx_fc_dis = 0; /* enable transmit FC */
1788 cbp->rx_fc_restop = 1; /* enable FC restop frames */
1789 cbp->rx_fc_restart = 1; /* enable FC restart frames */
1790 cbp->fc_filter = !prm; /* drop FC frames to host */
1791 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
1795 * Start the config command/DMA.
1798 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1799 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1800 /* ...and wait for it to complete. */
1801 fxp_dma_wait(&cbp->cb_status, sc);
1804 * Now initialize the station address. Temporarily use the TxCB
1805 * memory area like we did above for the config CB.
1807 cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1808 cb_ias->cb_status = 0;
1809 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
1810 cb_ias->link_addr = -1;
1811 bcopy(sc->arpcom.ac_enaddr,
1812 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr,
1813 sizeof(sc->arpcom.ac_enaddr));
1816 * Start the IAS (Individual Address Setup) command/DMA.
1819 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1820 /* ...and wait for it to complete. */
1821 fxp_dma_wait(&cb_ias->cb_status, sc);
1824 * Initialize transmit control block (TxCB) list.
1828 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1829 for (i = 0; i < FXP_NTXCB; i++) {
1830 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK;
1831 txp[i].cb_command = FXP_CB_COMMAND_NOP;
1833 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1834 if (sc->flags & FXP_FLAG_EXT_TXCB)
1835 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]);
1837 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1838 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1841 * Set the suspend flag on the first TxCB and start the control
1842 * unit. It will execute the NOP and then suspend.
1844 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S;
1845 sc->cbl_first = sc->cbl_last = txp;
1849 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1852 * Initialize receiver buffer area - RFA.
1855 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1856 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1857 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1860 * Set current media.
1862 if (sc->miibus != NULL)
1863 mii_mediachg(device_get_softc(sc->miibus));
1865 ifp->if_flags |= IFF_RUNNING;
1866 ifp->if_flags &= ~IFF_OACTIVE;
1869 * Enable interrupts.
1871 #ifdef DEVICE_POLLING
1873 * ... but only do that if we are not polling. And because (presumably)
1874 * the default is interrupts on, we need to disable them explicitly!
1876 if ( ifp->if_flags & IFF_POLLING )
1877 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1879 #endif /* DEVICE_POLLING */
1880 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1883 * Start stats updater.
1885 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc);
1889 fxp_serial_ifmedia_upd(struct ifnet *ifp)
1891 ASSERT_SERIALIZED(ifp->if_serializer);
1896 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1898 ASSERT_SERIALIZED(ifp->if_serializer);
1899 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
1903 * Change media according to request.
1906 fxp_ifmedia_upd(struct ifnet *ifp)
1908 struct fxp_softc *sc = ifp->if_softc;
1909 struct mii_data *mii;
1911 ASSERT_SERIALIZED(ifp->if_serializer);
1913 mii = device_get_softc(sc->miibus);
1919 * Notify the world which media we're using.
1922 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1924 struct fxp_softc *sc = ifp->if_softc;
1925 struct mii_data *mii;
1927 ASSERT_SERIALIZED(ifp->if_serializer);
1929 mii = device_get_softc(sc->miibus);
1931 ifmr->ifm_active = mii->mii_media_active;
1932 ifmr->ifm_status = mii->mii_media_status;
1934 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
1935 sc->cu_resume_bug = 1;
1937 sc->cu_resume_bug = 0;
1941 * Add a buffer to the end of the RFA buffer list.
1942 * Return 0 if successful, 1 for failure. A failure results in
1943 * adding the 'oldm' (if non-NULL) on to the end of the list -
1944 * tossing out its old contents and recycling it.
1945 * The RFA struct is stuck at the beginning of mbuf cluster and the
1946 * data pointer is fixed up to point just past it.
1949 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm)
1953 struct fxp_rfa *rfa, *p_rfa;
1955 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1956 if (m == NULL) { /* try to recycle the old mbuf instead */
1960 m->m_data = m->m_ext.ext_buf;
1964 * Move the data pointer up so that the incoming data packet
1965 * will be 32-bit aligned.
1967 m->m_data += RFA_ALIGNMENT_FUDGE;
1970 * Get a pointer to the base of the mbuf cluster and move
1971 * data start past it.
1973 rfa = mtod(m, struct fxp_rfa *);
1974 m->m_data += sizeof(struct fxp_rfa);
1975 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE);
1978 * Initialize the rest of the RFA. Note that since the RFA
1979 * is misaligned, we cannot store values directly. Instead,
1980 * we use an optimized, inline copy.
1983 rfa->rfa_status = 0;
1984 rfa->rfa_control = FXP_RFA_CONTROL_EL;
1985 rfa->actual_size = 0;
1988 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr);
1989 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr);
1992 * If there are other buffers already on the list, attach this
1993 * one to the end by fixing up the tail to point to this one.
1995 if (sc->rfa_headm != NULL) {
1996 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf +
1997 RFA_ALIGNMENT_FUDGE);
1998 sc->rfa_tailm->m_next = m;
2000 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr);
2001 p_rfa->rfa_control = 0;
2011 fxp_miibus_readreg(device_t dev, int phy, int reg)
2013 struct fxp_softc *sc = device_get_softc(dev);
2017 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2018 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
2020 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2025 device_printf(dev, "fxp_miibus_readreg: timed out\n");
2027 return (value & 0xffff);
2031 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2033 struct fxp_softc *sc = device_get_softc(dev);
2036 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2037 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
2040 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2045 device_printf(dev, "fxp_miibus_writereg: timed out\n");
2049 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2051 struct fxp_softc *sc = ifp->if_softc;
2052 struct ifreq *ifr = (struct ifreq *)data;
2053 struct mii_data *mii;
2056 ASSERT_SERIALIZED(ifp->if_serializer);
2061 if (ifp->if_flags & IFF_ALLMULTI)
2062 sc->flags |= FXP_FLAG_ALL_MCAST;
2064 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2067 * If interface is marked up and not running, then start it.
2068 * If it is marked down and running, stop it.
2069 * XXX If it's up then re-initialize it. This is so flags
2070 * such as IFF_PROMISC are handled.
2072 if (ifp->if_flags & IFF_UP) {
2075 if (ifp->if_flags & IFF_RUNNING)
2082 if (ifp->if_flags & IFF_ALLMULTI)
2083 sc->flags |= FXP_FLAG_ALL_MCAST;
2085 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2087 * Multicast list has changed; set the hardware filter
2090 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2093 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2094 * again rather than else {}.
2096 if (sc->flags & FXP_FLAG_ALL_MCAST)
2103 if (sc->miibus != NULL) {
2104 mii = device_get_softc(sc->miibus);
2105 error = ifmedia_ioctl(ifp, ifr,
2106 &mii->mii_media, command);
2108 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2113 error = ether_ioctl(ifp, command, data);
2120 * Fill in the multicast address list and return number of entries.
2123 fxp_mc_addrs(struct fxp_softc *sc)
2125 struct fxp_cb_mcs *mcsp = sc->mcsp;
2126 struct ifnet *ifp = &sc->arpcom.ac_if;
2127 struct ifmultiaddr *ifma;
2131 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2132 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2133 if (ifma->ifma_addr->sa_family != AF_LINK)
2135 if (nmcasts >= MAXMCADDR) {
2136 sc->flags |= FXP_FLAG_ALL_MCAST;
2140 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2141 (void *)(uintptr_t)(volatile void *)
2142 &sc->mcsp->mc_addr[nmcasts][0], 6);
2146 mcsp->mc_cnt = nmcasts * 6;
2151 * Program the multicast filter.
2153 * We have an artificial restriction that the multicast setup command
2154 * must be the first command in the chain, so we take steps to ensure
2155 * this. By requiring this, it allows us to keep up the performance of
2156 * the pre-initialized command ring (esp. link pointers) by not actually
2157 * inserting the mcsetup command in the ring - i.e. its link pointer
2158 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2159 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2160 * lead into the regular TxCB ring when it completes.
2162 * This function must be called at splimp.
2165 fxp_mc_setup(struct fxp_softc *sc)
2167 struct fxp_cb_mcs *mcsp = sc->mcsp;
2168 struct ifnet *ifp = &sc->arpcom.ac_if;
2172 * If there are queued commands, we must wait until they are all
2173 * completed. If we are already waiting, then add a NOP command
2174 * with interrupt option so that we're notified when all commands
2175 * have been completed - fxp_start() ensures that no additional
2176 * TX commands will be added when need_mcsetup is true.
2178 if (sc->tx_queued) {
2179 struct fxp_cb_tx *txp;
2182 * need_mcsetup will be true if we are already waiting for the
2183 * NOP command to be completed (see below). In this case, bail.
2185 if (sc->need_mcsetup)
2187 sc->need_mcsetup = 1;
2190 * Add a NOP command with interrupt so that we are notified
2191 * when all TX commands have been processed.
2193 txp = sc->cbl_last->next;
2194 txp->mb_head = NULL;
2196 txp->cb_command = FXP_CB_COMMAND_NOP |
2197 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2199 * Advance the end of list forward.
2201 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
2205 * Issue a resume in case the CU has just suspended.
2208 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2210 * Set a 5 second timer just in case we don't hear from the
2217 sc->need_mcsetup = 0;
2220 * Initialize multicast setup descriptor.
2222 mcsp->next = sc->cbl_base;
2223 mcsp->mb_head = NULL;
2224 mcsp->cb_status = 0;
2225 mcsp->cb_command = FXP_CB_COMMAND_MCAS |
2226 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2227 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
2229 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
2233 * Wait until command unit is not active. This should never
2234 * be the case when nothing is queued, but make sure anyway.
2237 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2238 FXP_SCB_CUS_ACTIVE && --count)
2241 if_printf(&sc->arpcom.ac_if, "command queue timeout\n");
2246 * Start the multicast setup command.
2249 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
2250 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2256 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2257 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2258 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2259 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2260 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2261 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2263 #define UCODE(x) x, sizeof(x)
2269 u_short int_delay_offset;
2270 u_short bundle_max_offset;
2272 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2273 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2274 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2275 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2276 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2277 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2278 { FXP_REV_82550, UCODE(fxp_ucode_d102),
2279 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2280 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2281 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2282 { 0, NULL, 0, 0, 0 }
2286 fxp_load_ucode(struct fxp_softc *sc)
2289 struct fxp_cb_ucode *cbp;
2291 for (uc = ucode_table; uc->ucode != NULL; uc++)
2292 if (sc->revision == uc->revision)
2294 if (uc->ucode == NULL)
2296 cbp = (struct fxp_cb_ucode *)sc->cbl_base;
2298 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL;
2299 cbp->link_addr = -1; /* (no) next command */
2300 memcpy(cbp->ucode, uc->ucode, uc->length);
2301 if (uc->int_delay_offset)
2302 *(u_short *)&cbp->ucode[uc->int_delay_offset] =
2303 sc->tunable_int_delay + sc->tunable_int_delay / 2;
2304 if (uc->bundle_max_offset)
2305 *(u_short *)&cbp->ucode[uc->bundle_max_offset] =
2306 sc->tunable_bundle_max;
2308 * Download the ucode to the chip.
2311 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
2312 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2313 /* ...and wait for it to complete. */
2314 fxp_dma_wait(&cbp->cb_status, sc);
2315 if_printf(&sc->arpcom.ac_if,
2316 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
2317 sc->tunable_int_delay,
2318 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
2319 sc->flags |= FXP_FLAG_UCODE;
2323 * Interrupt delay is expressed in microseconds, a multiplier is used
2324 * to convert this to the appropriate clock ticks before using.
2327 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
2329 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
2333 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
2335 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));