2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.24 2005/04/20 10:51:24 joerg Exp $
34 #include "opt_simos.h"
35 #include "opt_compat_oldpci.h"
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/malloc.h>
40 #include <sys/module.h>
41 #include <sys/fcntl.h>
43 #include <sys/kernel.h>
44 #include <sys/queue.h>
45 #include <sys/types.h>
50 #include <vm/vm_extern.h>
53 #include <machine/bus.h>
55 #include <machine/resource.h>
56 #include <machine/md_var.h> /* For the Alpha */
58 #include <bus/pci/i386/pci_cfgreg.h>
61 #include <sys/pciio.h>
64 #include "pci_private.h"
69 #include <machine/rpb.h>
73 #include <machine/smp.h>
76 devclass_t pci_devclass;
78 static void pci_read_extcap(device_t dev, pcicfgregs *cfg);
81 u_int32_t devid; /* Vendor/device of the card */
83 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
88 struct pci_quirk pci_quirks[] = {
90 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
92 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
93 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
94 /* As does the Serverworks OSB4 (the SMBus mapping register) */
95 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
100 /* map register information */
101 #define PCI_MAPMEM 0x01 /* memory map */
102 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
103 #define PCI_MAPPORT 0x04 /* port map */
105 static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
106 u_int32_t pci_numdevs = 0;
107 static u_int32_t pci_generation = 0;
110 pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func)
112 struct pci_devinfo *dinfo;
114 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
115 if ((dinfo->cfg.bus == bus) &&
116 (dinfo->cfg.slot == slot) &&
117 (dinfo->cfg.func == func)) {
118 return (dinfo->cfg.dev);
126 pci_find_device (u_int16_t vendor, u_int16_t device)
128 struct pci_devinfo *dinfo;
130 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
131 if ((dinfo->cfg.vendor == vendor) &&
132 (dinfo->cfg.device == device)) {
133 return (dinfo->cfg.dev);
140 /* return base address of memory or port map */
143 pci_mapbase(unsigned mapreg)
146 if ((mapreg & 0x01) == 0)
148 return (mapreg & ~mask);
151 /* return map type of memory or port map */
154 pci_maptype(unsigned mapreg)
156 static u_int8_t maptype[0x10] = {
157 PCI_MAPMEM, PCI_MAPPORT,
159 PCI_MAPMEM, PCI_MAPPORT,
161 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
162 PCI_MAPMEM|PCI_MAPMEMP, 0,
163 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
167 return maptype[mapreg & 0x0f];
170 /* return log2 of map size decoded for memory or port map */
173 pci_mapsize(unsigned testval)
177 testval = pci_mapbase(testval);
180 while ((testval & 1) == 0)
189 /* return log2 of address range supported by map register */
192 pci_maprange(unsigned mapreg)
195 switch (mapreg & 0x07) {
211 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
214 pci_fixancient(pcicfgregs *cfg)
216 if (cfg->hdrtype != 0)
219 /* PCI to PCI bridges use header type 1 */
220 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
224 /* read config data specific to header type 1 device (PCI to PCI bridge) */
227 pci_readppb(device_t pcib, int b, int s, int f)
231 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
235 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
236 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
238 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
240 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
242 PCIB_READ_CONFIG(pcib, b, s, f,
244 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
246 PCIB_READ_CONFIG(pcib, b, s, f,
247 PCIR_IOLIMITL_1, 1));
249 p->membase = PCI_PPBMEMBASE (0,
250 PCIB_READ_CONFIG(pcib, b, s, f,
252 p->memlimit = PCI_PPBMEMLIMIT (0,
253 PCIB_READ_CONFIG(pcib, b, s, f,
254 PCIR_MEMLIMIT_1, 2));
256 p->pmembase = PCI_PPBMEMBASE (
257 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
258 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
260 p->pmemlimit = PCI_PPBMEMLIMIT (
261 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
263 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
268 /* read config data specific to header type 2 device (PCI to CardBus bridge) */
271 pci_readpcb(device_t pcib, int b, int s, int f)
275 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
279 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
280 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
282 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
284 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
285 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
286 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
287 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
289 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
290 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
291 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
292 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
294 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
298 /* extract header type specific config data */
301 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
303 #define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
304 switch (cfg->hdrtype) {
306 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
307 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
308 cfg->nummaps = PCI_MAXMAPS_0;
311 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
312 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
313 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
314 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
315 cfg->nummaps = PCI_MAXMAPS_1;
316 cfg->hdrspec = pci_readppb(pcib, b, s, f);
319 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
320 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
321 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
322 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
323 cfg->nummaps = PCI_MAXMAPS_2;
324 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
330 /* read configuration header into pcicfgrect structure */
333 pci_read_device(device_t pcib, int b, int s, int f, size_t size)
335 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
337 pcicfgregs *cfg = NULL;
338 struct pci_devinfo *devlist_entry;
339 struct devlist *devlist_head;
341 devlist_head = &pci_devq;
343 devlist_entry = NULL;
345 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
347 devlist_entry = malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
348 if (devlist_entry == NULL)
351 cfg = &devlist_entry->cfg;
356 cfg->vendor = REG(PCIR_VENDOR, 2);
357 cfg->device = REG(PCIR_DEVICE, 2);
358 cfg->cmdreg = REG(PCIR_COMMAND, 2);
359 cfg->statreg = REG(PCIR_STATUS, 2);
360 cfg->baseclass = REG(PCIR_CLASS, 1);
361 cfg->subclass = REG(PCIR_SUBCLASS, 1);
362 cfg->progif = REG(PCIR_PROGIF, 1);
363 cfg->revid = REG(PCIR_REVID, 1);
364 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
365 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
366 cfg->lattimer = REG(PCIR_LATTIMER, 1);
367 cfg->intpin = REG(PCIR_INTPIN, 1);
368 cfg->intline = REG(PCIR_INTLINE, 1);
370 alpha_platform_assign_pciintr(cfg);
374 if (cfg->intpin != 0) {
377 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
379 /* PCI specific entry found in MP table */
380 if (airq != cfg->intline) {
381 undirect_pci_irq(cfg->intline);
386 * PCI interrupts might be redirected to the
387 * ISA bus according to some MP tables. Use the
388 * same methods as used by the ISA devices
389 * devices to find the proper IOAPIC int pin.
391 airq = isa_apic_irq(cfg->intline);
392 if ((airq >= 0) && (airq != cfg->intline)) {
393 /* XXX: undirect_pci_irq() ? */
394 undirect_isa_irq(cfg->intline);
401 cfg->mingnt = REG(PCIR_MINGNT, 1);
402 cfg->maxlat = REG(PCIR_MAXLAT, 1);
404 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
405 cfg->hdrtype &= ~PCIM_MFDEV;
408 pci_hdrtypedata(pcib, b, s, f, cfg);
410 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
411 pci_read_extcap(pcib, cfg);
413 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
415 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
416 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
417 devlist_entry->conf.pc_sel.pc_func = cfg->func;
418 devlist_entry->conf.pc_hdr = cfg->hdrtype;
420 devlist_entry->conf.pc_subvendor = cfg->subvendor;
421 devlist_entry->conf.pc_subdevice = cfg->subdevice;
422 devlist_entry->conf.pc_vendor = cfg->vendor;
423 devlist_entry->conf.pc_device = cfg->device;
425 devlist_entry->conf.pc_class = cfg->baseclass;
426 devlist_entry->conf.pc_subclass = cfg->subclass;
427 devlist_entry->conf.pc_progif = cfg->progif;
428 devlist_entry->conf.pc_revid = cfg->revid;
433 return (devlist_entry);
438 pci_read_extcap(device_t pcib, pcicfgregs *cfg)
440 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
441 int ptr, nextptr, ptrptr;
443 switch (cfg->hdrtype) {
451 return; /* no extended capabilities support */
453 nextptr = REG(ptrptr, 1); /* sanity check? */
456 * Read capability entries.
458 while (nextptr != 0) {
461 printf("illegal PCI extended capability offset %d\n",
465 /* Find the next entry */
467 nextptr = REG(ptr + 1, 1);
469 /* Process this entry */
470 switch (REG(ptr, 1)) {
471 case 0x01: /* PCI power management */
472 if (cfg->pp_cap == 0) {
473 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
474 cfg->pp_status = ptr + PCIR_POWER_STATUS;
475 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
476 if ((nextptr - ptr) > PCIR_POWER_DATA)
477 cfg->pp_data = ptr + PCIR_POWER_DATA;
487 /* free pcicfgregs structure and all depending data structures */
490 pci_freecfg(struct pci_devinfo *dinfo)
492 struct devlist *devlist_head;
494 devlist_head = &pci_devq;
496 if (dinfo->cfg.hdrspec != NULL)
497 free(dinfo->cfg.hdrspec, M_DEVBUF);
498 /* XXX this hasn't been tested */
499 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
500 free(dinfo, M_DEVBUF);
502 /* increment the generation count */
505 /* we're losing one device */
512 * PCI power manangement
515 pci_set_powerstate_method(device_t dev, device_t child, int state)
517 struct pci_devinfo *dinfo = device_get_ivars(child);
518 pcicfgregs *cfg = &dinfo->cfg;
522 if (cfg->pp_cap != 0) {
523 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK;
526 case PCI_POWERSTATE_D0:
527 status |= PCIM_PSTAT_D0;
529 case PCI_POWERSTATE_D1:
530 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) {
531 status |= PCIM_PSTAT_D1;
536 case PCI_POWERSTATE_D2:
537 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) {
538 status |= PCIM_PSTAT_D2;
543 case PCI_POWERSTATE_D3:
544 status |= PCIM_PSTAT_D3;
550 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2);
558 pci_get_powerstate_method(device_t dev, device_t child)
560 struct pci_devinfo *dinfo = device_get_ivars(child);
561 pcicfgregs *cfg = &dinfo->cfg;
565 if (cfg->pp_cap != 0) {
566 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2);
567 switch (status & PCIM_PSTAT_DMASK) {
569 result = PCI_POWERSTATE_D0;
572 result = PCI_POWERSTATE_D1;
575 result = PCI_POWERSTATE_D2;
578 result = PCI_POWERSTATE_D3;
581 result = PCI_POWERSTATE_UNKNOWN;
585 /* No support, device is always at D0 */
586 result = PCI_POWERSTATE_D0;
592 * Some convenience functions for PCI device drivers.
596 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
600 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
602 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
606 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
610 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
612 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
616 pci_enable_busmaster_method(device_t dev, device_t child)
618 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
623 pci_disable_busmaster_method(device_t dev, device_t child)
625 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
630 pci_enable_io_method(device_t dev, device_t child, int space)
641 bit = PCIM_CMD_PORTEN;
645 bit = PCIM_CMD_MEMEN;
651 pci_set_command_bit(dev, child, bit);
652 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
655 device_printf(child, "failed to enable %s mapping!\n", error);
660 pci_disable_io_method(device_t dev, device_t child, int space)
671 bit = PCIM_CMD_PORTEN;
675 bit = PCIM_CMD_MEMEN;
681 pci_clear_command_bit(dev, child, bit);
682 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
684 device_printf(child, "failed to disable %s mapping!\n", error);
691 * This is the user interface to PCI configuration space.
695 pci_open(dev_t dev, int oflags, int devtype, struct thread *td)
697 if ((oflags & FWRITE) && securelevel > 0) {
704 pci_close(dev_t dev, int flag, int devtype, struct thread *td)
710 * Match a single pci_conf structure against an array of pci_match_conf
711 * structures. The first argument, 'matches', is an array of num_matches
712 * pci_match_conf structures. match_buf is a pointer to the pci_conf
713 * structure that will be compared to every entry in the matches array.
714 * This function returns 1 on failure, 0 on success.
717 pci_conf_match(struct pci_match_conf *matches, int num_matches,
718 struct pci_conf *match_buf)
722 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
725 for (i = 0; i < num_matches; i++) {
727 * I'm not sure why someone would do this...but...
729 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
733 * Look at each of the match flags. If it's set, do the
734 * comparison. If the comparison fails, we don't have a
735 * match, go on to the next item if there is one.
737 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
738 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
741 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
742 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
745 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
746 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
749 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
750 && (match_buf->pc_vendor != matches[i].pc_vendor))
753 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
754 && (match_buf->pc_device != matches[i].pc_device))
757 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
758 && (match_buf->pc_class != matches[i].pc_class))
761 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
762 && (match_buf->pd_unit != matches[i].pd_unit))
765 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
766 && (strncmp(matches[i].pd_name, match_buf->pd_name,
767 sizeof(match_buf->pd_name)) != 0))
777 * Locate the parent of a PCI device by scanning the PCI devlist
778 * and return the entry for the parent.
779 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
780 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
784 pci_devlist_get_parent(pcicfgregs *cfg)
786 struct devlist *devlist_head;
787 struct pci_devinfo *dinfo;
788 pcicfgregs *bridge_cfg;
791 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
793 /* If the device is on PCI bus 0, look for the host */
795 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
796 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
797 bridge_cfg = &dinfo->cfg;
798 if (bridge_cfg->baseclass == PCIC_BRIDGE
799 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
800 && bridge_cfg->bus == cfg->bus) {
806 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
808 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
809 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
810 bridge_cfg = &dinfo->cfg;
811 if (bridge_cfg->baseclass == PCIC_BRIDGE
812 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
813 && bridge_cfg->secondarybus == cfg->bus) {
823 pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct thread *td)
830 if (!(flag & FWRITE))
837 struct pci_devinfo *dinfo;
838 struct pci_conf_io *cio;
839 struct devlist *devlist_head;
840 struct pci_match_conf *pattern_buf;
845 cio = (struct pci_conf_io *)data;
851 * Hopefully the user won't pass in a null pointer, but it
852 * can't hurt to check.
860 * If the user specified an offset into the device list,
861 * but the list has changed since they last called this
862 * ioctl, tell them that the list has changed. They will
863 * have to get the list from the beginning.
865 if ((cio->offset != 0)
866 && (cio->generation != pci_generation)){
867 cio->num_matches = 0;
868 cio->status = PCI_GETCONF_LIST_CHANGED;
874 * Check to see whether the user has asked for an offset
875 * past the end of our list.
877 if (cio->offset >= pci_numdevs) {
878 cio->num_matches = 0;
879 cio->status = PCI_GETCONF_LAST_DEVICE;
884 /* get the head of the device queue */
885 devlist_head = &pci_devq;
888 * Determine how much room we have for pci_conf structures.
889 * Round the user's buffer size down to the nearest
890 * multiple of sizeof(struct pci_conf) in case the user
891 * didn't specify a multiple of that size.
893 iolen = min(cio->match_buf_len -
894 (cio->match_buf_len % sizeof(struct pci_conf)),
895 pci_numdevs * sizeof(struct pci_conf));
898 * Since we know that iolen is a multiple of the size of
899 * the pciconf union, it's okay to do this.
901 ionum = iolen / sizeof(struct pci_conf);
904 * If this test is true, the user wants the pci_conf
905 * structures returned to match the supplied entries.
907 if ((cio->num_patterns > 0)
908 && (cio->pat_buf_len > 0)) {
910 * pat_buf_len needs to be:
911 * num_patterns * sizeof(struct pci_match_conf)
912 * While it is certainly possible the user just
913 * allocated a large buffer, but set the number of
914 * matches correctly, it is far more likely that
915 * their kernel doesn't match the userland utility
916 * they're using. It's also possible that the user
917 * forgot to initialize some variables. Yes, this
918 * may be overly picky, but I hazard to guess that
919 * it's far more likely to just catch folks that
920 * updated their kernel but not their userland.
922 if ((cio->num_patterns *
923 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
924 /* The user made a mistake, return an error*/
925 cio->status = PCI_GETCONF_ERROR;
926 printf("pci_ioctl: pat_buf_len %d != "
927 "num_patterns (%d) * sizeof(struct "
928 "pci_match_conf) (%d)\npci_ioctl: "
929 "pat_buf_len should be = %d\n",
930 cio->pat_buf_len, cio->num_patterns,
931 (int)sizeof(struct pci_match_conf),
932 (int)sizeof(struct pci_match_conf) *
934 printf("pci_ioctl: do your headers match your "
936 cio->num_matches = 0;
942 * Check the user's buffer to make sure it's readable.
944 if (!useracc((caddr_t)cio->patterns,
945 cio->pat_buf_len, VM_PROT_READ)) {
946 printf("pci_ioctl: pattern buffer %p, "
947 "length %u isn't user accessible for"
948 " READ\n", cio->patterns,
954 * Allocate a buffer to hold the patterns.
956 pattern_buf = malloc(cio->pat_buf_len, M_TEMP,
958 error = copyin(cio->patterns, pattern_buf,
962 num_patterns = cio->num_patterns;
964 } else if ((cio->num_patterns > 0)
965 || (cio->pat_buf_len > 0)) {
967 * The user made a mistake, spit out an error.
969 cio->status = PCI_GETCONF_ERROR;
970 cio->num_matches = 0;
971 printf("pci_ioctl: invalid GETCONF arguments\n");
978 * Make sure we can write to the match buffer.
980 if (!useracc((caddr_t)cio->matches,
981 cio->match_buf_len, VM_PROT_WRITE)) {
982 printf("pci_ioctl: match buffer %p, length %u "
983 "isn't user accessible for WRITE\n",
984 cio->matches, cio->match_buf_len);
990 * Go through the list of devices and copy out the devices
991 * that match the user's criteria.
993 for (cio->num_matches = 0, error = 0, i = 0,
994 dinfo = STAILQ_FIRST(devlist_head);
995 (dinfo != NULL) && (cio->num_matches < ionum)
996 && (error == 0) && (i < pci_numdevs);
997 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
1002 /* Populate pd_name and pd_unit */
1004 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
1005 name = device_get_name(dinfo->cfg.dev);
1007 strncpy(dinfo->conf.pd_name, name,
1008 sizeof(dinfo->conf.pd_name));
1009 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
1010 dinfo->conf.pd_unit =
1011 device_get_unit(dinfo->cfg.dev);
1014 if ((pattern_buf == NULL) ||
1015 (pci_conf_match(pattern_buf, num_patterns,
1016 &dinfo->conf) == 0)) {
1019 * If we've filled up the user's buffer,
1020 * break out at this point. Since we've
1021 * got a match here, we'll pick right back
1022 * up at the matching entry. We can also
1023 * tell the user that there are more matches
1026 if (cio->num_matches >= ionum)
1029 error = copyout(&dinfo->conf,
1030 &cio->matches[cio->num_matches],
1031 sizeof(struct pci_conf));
1037 * Set the pointer into the list, so if the user is getting
1038 * n records at a time, where n < pci_numdevs,
1043 * Set the generation, the user will need this if they make
1044 * another ioctl call with offset != 0.
1046 cio->generation = pci_generation;
1049 * If this is the last device, inform the user so he won't
1050 * bother asking for more devices. If dinfo isn't NULL, we
1051 * know that there are more matches in the list because of
1052 * the way the traversal is done.
1055 cio->status = PCI_GETCONF_LAST_DEVICE;
1057 cio->status = PCI_GETCONF_MORE_DEVS;
1059 if (pattern_buf != NULL)
1060 free(pattern_buf, M_TEMP);
1065 io = (struct pci_io *)data;
1066 switch(io->pi_width) {
1071 * Assume that the user-level bus number is
1072 * actually the pciN instance number. We map
1073 * from that to the real pcib+bus combination.
1075 pci = devclass_get_device(pci_devclass,
1078 int b = pcib_get_bus(pci);
1079 pcib = device_get_parent(pci);
1081 PCIB_READ_CONFIG(pcib,
1099 io = (struct pci_io *)data;
1100 switch(io->pi_width) {
1105 * Assume that the user-level bus number is
1106 * actually the pciN instance number. We map
1107 * from that to the real pcib+bus combination.
1109 pci = devclass_get_device(pci_devclass,
1112 int b = pcib_get_bus(pci);
1113 pcib = device_get_parent(pci);
1114 PCIB_WRITE_CONFIG(pcib,
1142 static struct cdevsw pcicdev = {
1149 /* open */ pci_open,
1150 /* close */ pci_close,
1152 /* write */ nowrite,
1153 /* ioctl */ pci_ioctl,
1156 /* strategy */ nostrategy,
1164 * New style pci driver. Parent device is either a pci-host-bridge or a
1165 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1168 pci_class_to_string(int baseclass)
1185 case PCIC_MULTIMEDIA:
1186 name = "MULTIMEDIA";
1194 case PCIC_SIMPLECOMM:
1195 name = "SIMPLECOMM";
1197 case PCIC_BASEPERIPH:
1198 name = "BASEPERIPH";
1206 case PCIC_PROCESSOR:
1209 case PCIC_SERIALBUS:
1218 case PCIC_SATELLITE:
1238 pci_print_verbose(struct pci_devinfo *dinfo)
1241 pcicfgregs *cfg = &dinfo->cfg;
1243 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
1244 cfg->vendor, cfg->device, cfg->revid);
1245 printf("\tbus=%d, slot=%d, func=%d\n",
1246 cfg->bus, cfg->slot, cfg->func);
1247 printf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
1248 pci_class_to_string(cfg->baseclass),
1249 cfg->baseclass, cfg->subclass, cfg->progif,
1250 cfg->hdrtype, cfg->mfdev);
1251 printf("\tsubordinatebus=%x \tsecondarybus=%x\n",
1252 cfg->subordinatebus, cfg->secondarybus);
1254 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
1255 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
1256 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
1257 cfg->lattimer, cfg->lattimer * 30,
1258 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1259 #endif /* PCI_DEBUG */
1260 if (cfg->intpin > 0)
1261 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
1266 pci_porten(device_t pcib, int b, int s, int f)
1268 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1269 & PCIM_CMD_PORTEN) != 0;
1273 pci_memen(device_t pcib, int b, int s, int f)
1275 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1276 & PCIM_CMD_MEMEN) != 0;
1280 * Add a resource based on a pci map register. Return 1 if the map
1281 * register is a 32bit map register or 2 if it is a 64bit register.
1284 pci_add_map(device_t pcib, int b, int s, int f, int reg,
1285 struct resource_list *rl)
1294 #ifdef PCI_ENABLE_IO_MODES
1299 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1301 if (map == 0 || map == 0xffffffff)
1302 return 1; /* skip invalid entry */
1304 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1305 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1306 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
1308 base = pci_mapbase(map);
1309 if (pci_maptype(map) & PCI_MAPMEM)
1310 type = SYS_RES_MEMORY;
1312 type = SYS_RES_IOPORT;
1313 ln2size = pci_mapsize(testval);
1314 ln2range = pci_maprange(testval);
1315 if (ln2range == 64) {
1316 /* Read the other half of a 64bit map register */
1317 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
1321 * This code theoretically does the right thing, but has
1322 * undesirable side effects in some cases where
1323 * peripherals respond oddly to having these bits
1324 * enabled. Leave them alone by default.
1326 #ifdef PCI_ENABLE_IO_MODES
1327 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1328 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1329 cmd |= PCIM_CMD_PORTEN;
1330 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1332 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1333 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1334 cmd |= PCIM_CMD_MEMEN;
1335 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1338 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
1340 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
1344 resource_list_add(rl, type, reg,
1345 base, base + (1 << ln2size) - 1,
1349 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
1350 reg, pci_maptype(base), ln2range,
1351 (unsigned int) base, ln2size);
1354 return (ln2range == 64) ? 2 : 1;
1358 pci_add_resources(device_t pcib, device_t bus, device_t dev)
1360 struct pci_devinfo *dinfo = device_get_ivars(dev);
1361 pcicfgregs *cfg = &dinfo->cfg;
1362 struct resource_list *rl = &dinfo->resources;
1363 struct pci_quirk *q;
1365 #if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */
1372 for (i = 0; i < cfg->nummaps;) {
1373 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl);
1376 for (q = &pci_quirks[0]; q->devid; q++) {
1377 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1378 && q->type == PCI_QUIRK_MAP_REG)
1379 pci_add_map(pcib, b, s, f, q->arg1, rl);
1382 if (cfg->intpin > 0 && cfg->intline != 255)
1383 resource_list_add(rl, SYS_RES_IRQ, 0,
1384 cfg->intline, cfg->intline, 1);
1388 pci_add_children(device_t dev, int busno, size_t dinfo_size)
1390 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
1391 device_t pcib = device_get_parent(dev);
1392 struct pci_devinfo *dinfo;
1394 int s, f, pcifunchigh;
1397 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo));
1399 maxslots = PCIB_MAXSLOTS(pcib);
1401 for (s = 0; s <= maxslots; s++) {
1404 hdrtype = REG(PCIR_HDRTYPE, 1);
1405 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1407 if (hdrtype & PCIM_MFDEV)
1408 pcifunchigh = PCI_FUNCMAX;
1409 for (f = 0; f <= pcifunchigh; f++) {
1410 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
1411 if (dinfo != NULL) {
1412 pci_add_child(dev, dinfo);
1420 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1424 pcib = device_get_parent(bus);
1425 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1426 device_set_ivars(dinfo->cfg.dev, dinfo);
1427 pci_add_resources(pcib, bus, dinfo->cfg.dev);
1428 pci_print_verbose(dinfo);
1432 * Probe the PCI bus. Note: probe code is not supposed to add children
1436 pci_probe(device_t dev)
1438 device_set_desc(dev, "PCI bus");
1440 /* Allow other subclasses to override this driver */
1445 pci_attach(device_t dev)
1448 int lunit = device_get_unit(dev);
1450 cdevsw_add(&pcicdev, -1, lunit);
1451 make_dev(&pcicdev, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit);
1454 * Since there can be multiple independantly numbered PCI
1455 * busses on some large alpha systems, we can't use the unit
1456 * number to decide what bus we are probing. We ask the parent
1457 * pcib what our bus number is.
1459 busno = pcib_get_bus(dev);
1461 device_printf(dev, "pci_attach() physical bus=%d\n", busno);
1463 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1465 return (bus_generic_attach(dev));
1469 pci_print_resources(struct resource_list *rl, const char *name, int type,
1472 struct resource_list_entry *rle;
1473 int printed, retval;
1477 /* Yes, this is kinda cheating */
1478 SLIST_FOREACH(rle, rl, link) {
1479 if (rle->type == type) {
1481 retval += printf(" %s ", name);
1482 else if (printed > 0)
1483 retval += printf(",");
1485 retval += printf(format, rle->start);
1486 if (rle->count > 1) {
1487 retval += printf("-");
1488 retval += printf(format, rle->start +
1497 pci_print_child(device_t dev, device_t child)
1499 struct pci_devinfo *dinfo;
1500 struct resource_list *rl;
1504 dinfo = device_get_ivars(child);
1506 rl = &dinfo->resources;
1508 retval += bus_print_child_header(dev, child);
1510 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1511 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1512 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1513 if (device_get_flags(dev))
1514 retval += printf(" flags %#x", device_get_flags(dev));
1516 retval += printf(" at device %d.%d", pci_get_slot(child),
1517 pci_get_function(child));
1519 retval += bus_print_child_footer(dev, child);
1525 pci_probe_nomatch(device_t dev, device_t child)
1527 struct pci_devinfo *dinfo;
1533 dinfo = device_get_ivars(child);
1535 desc = pci_ata_match(child);
1536 if (!desc) desc = pci_usb_match(child);
1537 if (!desc) desc = pci_vga_match(child);
1538 if (!desc) desc = pci_chip_match(child);
1540 desc = "unknown card";
1543 device_printf(dev, "<%s>", desc);
1544 if (bootverbose || unknown) {
1545 printf(" (vendor=0x%04x, dev=0x%04x)",
1550 pci_get_slot(child),
1551 pci_get_function(child));
1552 if (cfg->intpin > 0 && cfg->intline != 255) {
1553 printf(" irq %d", cfg->intline);
1561 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1563 struct pci_devinfo *dinfo;
1566 dinfo = device_get_ivars(child);
1570 case PCI_IVAR_SUBVENDOR:
1571 *result = cfg->subvendor;
1573 case PCI_IVAR_SUBDEVICE:
1574 *result = cfg->subdevice;
1576 case PCI_IVAR_VENDOR:
1577 *result = cfg->vendor;
1579 case PCI_IVAR_DEVICE:
1580 *result = cfg->device;
1582 case PCI_IVAR_DEVID:
1583 *result = (cfg->device << 16) | cfg->vendor;
1585 case PCI_IVAR_CLASS:
1586 *result = cfg->baseclass;
1588 case PCI_IVAR_SUBCLASS:
1589 *result = cfg->subclass;
1591 case PCI_IVAR_PROGIF:
1592 *result = cfg->progif;
1594 case PCI_IVAR_REVID:
1595 *result = cfg->revid;
1597 case PCI_IVAR_INTPIN:
1598 *result = cfg->intpin;
1601 *result = cfg->intline;
1607 *result = cfg->slot;
1609 case PCI_IVAR_FUNCTION:
1610 *result = cfg->func;
1612 case PCI_IVAR_SECONDARYBUS:
1613 *result = cfg->secondarybus;
1615 case PCI_IVAR_SUBORDINATEBUS:
1616 *result = cfg->subordinatebus;
1618 case PCI_IVAR_ETHADDR:
1620 * The generic accessor doesn't deal with failure, so
1621 * we set the return value, then return an error.
1632 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1634 struct pci_devinfo *dinfo;
1637 dinfo = device_get_ivars(child);
1641 case PCI_IVAR_SUBVENDOR:
1642 case PCI_IVAR_SUBDEVICE:
1643 case PCI_IVAR_VENDOR:
1644 case PCI_IVAR_DEVICE:
1645 case PCI_IVAR_DEVID:
1646 case PCI_IVAR_CLASS:
1647 case PCI_IVAR_SUBCLASS:
1648 case PCI_IVAR_PROGIF:
1649 case PCI_IVAR_REVID:
1650 case PCI_IVAR_INTPIN:
1654 case PCI_IVAR_FUNCTION:
1655 case PCI_IVAR_ETHADDR:
1656 return EINVAL; /* disallow for now */
1658 case PCI_IVAR_SECONDARYBUS:
1659 cfg->secondarybus = value;
1661 case PCI_IVAR_SUBORDINATEBUS:
1662 cfg->subordinatebus = value;
1671 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1672 u_long start, u_long end, u_long count, u_int flags)
1674 struct pci_devinfo *dinfo = device_get_ivars(child);
1675 struct resource_list *rl = &dinfo->resources;
1678 pcicfgregs *cfg = &dinfo->cfg;
1680 * Perform lazy resource allocation
1682 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY
1684 if (device_get_parent(child) == dev) {
1686 * If device doesn't have an interrupt routed, and is
1687 * deserving of an interrupt, try to assign it one.
1689 if ((type == SYS_RES_IRQ) &&
1690 (cfg->intline == 255 || cfg->intline == 0) &&
1691 (cfg->intpin != 0) && (start == 0) && (end == ~0UL)) {
1692 cfg->intline = PCIB_ROUTE_INTERRUPT(
1693 device_get_parent(dev), child,
1695 if (cfg->intline != 255) {
1696 pci_write_config(child, PCIR_INTLINE,
1698 resource_list_add(rl, SYS_RES_IRQ, 0,
1699 cfg->intline, cfg->intline, 1);
1704 return resource_list_alloc(rl, dev, child, type, rid,
1705 start, end, count, flags);
1709 pci_release_resource(device_t dev, device_t child, int type, int rid,
1712 struct pci_devinfo *dinfo = device_get_ivars(child);
1713 struct resource_list *rl = &dinfo->resources;
1715 return resource_list_release(rl, dev, child, type, rid, r);
1719 pci_set_resource(device_t dev, device_t child, int type, int rid,
1720 u_long start, u_long count)
1722 struct pci_devinfo *dinfo = device_get_ivars(child);
1723 struct resource_list *rl = &dinfo->resources;
1725 resource_list_add(rl, type, rid, start, start + count - 1, count);
1730 pci_get_resource(device_t dev, device_t child, int type, int rid,
1731 u_long *startp, u_long *countp)
1733 struct pci_devinfo *dinfo = device_get_ivars(child);
1734 struct resource_list *rl = &dinfo->resources;
1735 struct resource_list_entry *rle;
1737 rle = resource_list_find(rl, type, rid);
1742 *startp = rle->start;
1744 *countp = rle->count;
1750 pci_delete_resource(device_t dev, device_t child, int type, int rid)
1752 printf("pci_delete_resource: PCI resources can not be deleted\n");
1755 struct resource_list *
1756 pci_get_resource_list (device_t dev, device_t child)
1758 struct pci_devinfo * dinfo = device_get_ivars(child);
1759 struct resource_list * rl = &dinfo->resources;
1768 pci_read_config_method(device_t dev, device_t child, int reg, int width)
1770 struct pci_devinfo *dinfo = device_get_ivars(child);
1771 pcicfgregs *cfg = &dinfo->cfg;
1773 return PCIB_READ_CONFIG(device_get_parent(dev),
1774 cfg->bus, cfg->slot, cfg->func,
1779 pci_write_config_method(device_t dev, device_t child, int reg,
1780 u_int32_t val, int width)
1782 struct pci_devinfo *dinfo = device_get_ivars(child);
1783 pcicfgregs *cfg = &dinfo->cfg;
1785 PCIB_WRITE_CONFIG(device_get_parent(dev),
1786 cfg->bus, cfg->slot, cfg->func,
1791 pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
1794 struct pci_devinfo *dinfo;
1796 dinfo = device_get_ivars(child);
1797 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
1798 pci_get_function(child));
1803 pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
1806 struct pci_devinfo *dinfo;
1809 dinfo = device_get_ivars(child);
1811 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
1812 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
1813 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
1819 pci_assign_interrupt_method(device_t dev, device_t child)
1821 struct pci_devinfo *dinfo = device_get_ivars(child);
1822 pcicfgregs *cfg = &dinfo->cfg;
1824 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
1829 pci_modevent(module_t mod, int what, void *arg)
1833 STAILQ_INIT(&pci_devq);
1843 pci_resume(device_t dev)
1849 struct pci_devinfo *dinfo;
1852 device_get_children(dev, &children, &numdevs);
1854 for (i = 0; i < numdevs; i++) {
1855 child = children[i];
1857 dinfo = device_get_ivars(child);
1859 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
1860 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
1861 if (PCI_INTERRUPT_VALID(cfg->intline)) {
1862 pci_write_config(child, PCIR_INTLINE,
1868 free(children, M_TEMP);
1870 return (bus_generic_resume(dev));
1873 static device_method_t pci_methods[] = {
1874 /* Device interface */
1875 DEVMETHOD(device_probe, pci_probe),
1876 DEVMETHOD(device_attach, pci_attach),
1877 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1878 DEVMETHOD(device_suspend, bus_generic_suspend),
1879 DEVMETHOD(device_resume, pci_resume),
1882 DEVMETHOD(bus_print_child, pci_print_child),
1883 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
1884 DEVMETHOD(bus_read_ivar, pci_read_ivar),
1885 DEVMETHOD(bus_write_ivar, pci_write_ivar),
1886 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1887 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1888 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1890 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
1891 DEVMETHOD(bus_set_resource, pci_set_resource),
1892 DEVMETHOD(bus_get_resource, pci_get_resource),
1893 DEVMETHOD(bus_delete_resource, pci_delete_resource),
1894 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
1895 DEVMETHOD(bus_release_resource, pci_release_resource),
1896 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1897 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1898 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
1899 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
1902 DEVMETHOD(pci_read_config, pci_read_config_method),
1903 DEVMETHOD(pci_write_config, pci_write_config_method),
1904 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
1905 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
1906 DEVMETHOD(pci_enable_io, pci_enable_io_method),
1907 DEVMETHOD(pci_disable_io, pci_disable_io_method),
1908 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
1909 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
1910 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
1915 static driver_t pci_driver = {
1921 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
1922 MODULE_VERSION(pci, 1);