2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
28 * $DragonFly: src/sys/dev/netif/jme/if_jme.c,v 1.12 2008/11/26 11:55:18 sephe Exp $
31 #include "opt_polling.h"
34 #include <sys/param.h>
35 #include <sys/endian.h>
36 #include <sys/kernel.h>
38 #include <sys/interrupt.h>
39 #include <sys/malloc.h>
42 #include <sys/serialize.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
47 #include <net/ethernet.h>
50 #include <net/if_arp.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/ifq_var.h>
54 #include <net/vlan/if_vlan_var.h>
55 #include <net/vlan/if_vlan_ether.h>
57 #include <dev/netif/mii_layer/miivar.h>
58 #include <dev/netif/mii_layer/jmphyreg.h>
60 #include <bus/pci/pcireg.h>
61 #include <bus/pci/pcivar.h>
62 #include <bus/pci/pcidevs.h>
64 #include <dev/netif/jme/if_jmereg.h>
65 #include <dev/netif/jme/if_jmevar.h>
67 #include "miibus_if.h"
69 /* Define the following to disable printing Rx errors. */
70 #undef JME_SHOW_ERRORS
72 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
75 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
77 if ((sc)->jme_rss_debug > (lvl)) \
78 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
80 #else /* !JME_RSS_DEBUG */
81 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
82 #endif /* JME_RSS_DEBUG */
84 static int jme_probe(device_t);
85 static int jme_attach(device_t);
86 static int jme_detach(device_t);
87 static int jme_shutdown(device_t);
88 static int jme_suspend(device_t);
89 static int jme_resume(device_t);
91 static int jme_miibus_readreg(device_t, int, int);
92 static int jme_miibus_writereg(device_t, int, int, int);
93 static void jme_miibus_statchg(device_t);
95 static void jme_init(void *);
96 static int jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
97 static void jme_start(struct ifnet *);
98 static void jme_watchdog(struct ifnet *);
99 static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
100 static int jme_mediachange(struct ifnet *);
101 #ifdef DEVICE_POLLING
102 static void jme_poll(struct ifnet *, enum poll_cmd, int);
105 static void jme_intr(void *);
106 static void jme_txeof(struct jme_softc *);
107 static void jme_rxeof(struct jme_softc *, int);
108 static int jme_rxeof_chain(struct jme_softc *, int,
109 struct mbuf_chain *, int);
110 static void jme_rx_intr(struct jme_softc *, uint32_t);
112 static int jme_dma_alloc(struct jme_softc *);
113 static void jme_dma_free(struct jme_softc *);
114 static int jme_init_rx_ring(struct jme_softc *, int);
115 static void jme_init_tx_ring(struct jme_softc *);
116 static void jme_init_ssb(struct jme_softc *);
117 static int jme_newbuf(struct jme_softc *, int, struct jme_rxdesc *, int);
118 static int jme_encap(struct jme_softc *, struct mbuf **);
119 static void jme_rxpkt(struct jme_softc *, int, struct mbuf_chain *);
120 static int jme_rxring_dma_alloc(struct jme_softc *, int);
121 static int jme_rxbuf_dma_alloc(struct jme_softc *, int);
123 static void jme_tick(void *);
124 static void jme_stop(struct jme_softc *);
125 static void jme_reset(struct jme_softc *);
126 static void jme_set_vlan(struct jme_softc *);
127 static void jme_set_filter(struct jme_softc *);
128 static void jme_stop_tx(struct jme_softc *);
129 static void jme_stop_rx(struct jme_softc *);
130 static void jme_mac_config(struct jme_softc *);
131 static void jme_reg_macaddr(struct jme_softc *, uint8_t[]);
132 static int jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
133 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
135 static void jme_setwol(struct jme_softc *);
136 static void jme_setlinkspeed(struct jme_softc *);
138 static void jme_set_tx_coal(struct jme_softc *);
139 static void jme_set_rx_coal(struct jme_softc *);
140 static void jme_enable_rss(struct jme_softc *);
141 static void jme_disable_rss(struct jme_softc *);
143 static void jme_sysctl_node(struct jme_softc *);
144 static int jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
145 static int jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
146 static int jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
147 static int jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
150 * Devices supported by this driver.
152 static const struct jme_dev {
153 uint16_t jme_vendorid;
154 uint16_t jme_deviceid;
156 const char *jme_name;
158 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
160 "JMicron Inc, JMC250 Gigabit Ethernet" },
161 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
163 "JMicron Inc, JMC260 Fast Ethernet" },
167 static device_method_t jme_methods[] = {
168 /* Device interface. */
169 DEVMETHOD(device_probe, jme_probe),
170 DEVMETHOD(device_attach, jme_attach),
171 DEVMETHOD(device_detach, jme_detach),
172 DEVMETHOD(device_shutdown, jme_shutdown),
173 DEVMETHOD(device_suspend, jme_suspend),
174 DEVMETHOD(device_resume, jme_resume),
177 DEVMETHOD(bus_print_child, bus_generic_print_child),
178 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
181 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
182 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
183 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
188 static driver_t jme_driver = {
191 sizeof(struct jme_softc)
194 static devclass_t jme_devclass;
196 DECLARE_DUMMY_MODULE(if_jme);
197 MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
198 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, 0, 0);
199 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, 0, 0);
201 static const struct {
204 } jme_rx_status[JME_NRXRING_MAX] = {
205 { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP },
206 { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP },
207 { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP },
208 { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP }
211 static int jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
212 static int jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
213 static int jme_rx_ring_count = JME_NRXRING_DEF;
215 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
216 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
217 TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
220 * Read a PHY register on the MII of the JMC250.
223 jme_miibus_readreg(device_t dev, int phy, int reg)
225 struct jme_softc *sc = device_get_softc(dev);
229 /* For FPGA version, PHY address 0 should be ignored. */
230 if (sc->jme_caps & JME_CAP_FPGA) {
234 if (sc->jme_phyaddr != phy)
238 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
239 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
241 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
243 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
247 device_printf(sc->jme_dev, "phy read timeout: "
248 "phy %d, reg %d\n", phy, reg);
252 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
256 * Write a PHY register on the MII of the JMC250.
259 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
261 struct jme_softc *sc = device_get_softc(dev);
264 /* For FPGA version, PHY address 0 should be ignored. */
265 if (sc->jme_caps & JME_CAP_FPGA) {
269 if (sc->jme_phyaddr != phy)
273 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
274 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
275 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
277 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
279 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
283 device_printf(sc->jme_dev, "phy write timeout: "
284 "phy %d, reg %d\n", phy, reg);
291 * Callback from MII layer when media changes.
294 jme_miibus_statchg(device_t dev)
296 struct jme_softc *sc = device_get_softc(dev);
297 struct ifnet *ifp = &sc->arpcom.ac_if;
298 struct mii_data *mii;
299 struct jme_txdesc *txd;
303 ASSERT_SERIALIZED(ifp->if_serializer);
305 if ((ifp->if_flags & IFF_RUNNING) == 0)
308 mii = device_get_softc(sc->jme_miibus);
310 sc->jme_flags &= ~JME_FLAG_LINK;
311 if ((mii->mii_media_status & IFM_AVALID) != 0) {
312 switch (IFM_SUBTYPE(mii->mii_media_active)) {
315 sc->jme_flags |= JME_FLAG_LINK;
318 if (sc->jme_caps & JME_CAP_FASTETH)
320 sc->jme_flags |= JME_FLAG_LINK;
328 * Disabling Rx/Tx MACs have a side-effect of resetting
329 * JME_TXNDA/JME_RXNDA register to the first address of
330 * Tx/Rx descriptor address. So driver should reset its
331 * internal procucer/consumer pointer and reclaim any
332 * allocated resources. Note, just saving the value of
333 * JME_TXNDA and JME_RXNDA registers before stopping MAC
334 * and restoring JME_TXNDA/JME_RXNDA register is not
335 * sufficient to make sure correct MAC state because
336 * stopping MAC operation can take a while and hardware
337 * might have updated JME_TXNDA/JME_RXNDA registers
338 * during the stop operation.
341 /* Disable interrupts */
342 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
345 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
347 callout_stop(&sc->jme_tick_ch);
349 /* Stop receiver/transmitter. */
353 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
354 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
357 if (rdata->jme_rxhead != NULL)
358 m_freem(rdata->jme_rxhead);
359 JME_RXCHAIN_RESET(sc, r);
362 * Reuse configured Rx descriptors and reset
363 * procuder/consumer index.
365 rdata->jme_rx_cons = 0;
369 if (sc->jme_cdata.jme_tx_cnt != 0) {
370 /* Remove queued packets for transmit. */
371 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
372 txd = &sc->jme_cdata.jme_txdesc[i];
373 if (txd->tx_m != NULL) {
375 sc->jme_cdata.jme_tx_tag,
384 jme_init_tx_ring(sc);
386 /* Initialize shadow status block. */
389 /* Program MAC with resolved speed/duplex/flow-control. */
390 if (sc->jme_flags & JME_FLAG_LINK) {
393 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
395 /* Set Tx ring address to the hardware. */
396 paddr = sc->jme_cdata.jme_tx_ring_paddr;
397 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
398 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
400 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
401 CSR_WRITE_4(sc, JME_RXCSR,
402 sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
404 /* Set Rx ring address to the hardware. */
405 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
406 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
407 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
410 /* Restart receiver/transmitter. */
411 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
413 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
416 ifp->if_flags |= IFF_RUNNING;
417 ifp->if_flags &= ~IFF_OACTIVE;
418 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
420 #ifdef DEVICE_POLLING
421 if (!(ifp->if_flags & IFF_POLLING))
423 /* Reenable interrupts. */
424 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
428 * Get the current interface media status.
431 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
433 struct jme_softc *sc = ifp->if_softc;
434 struct mii_data *mii = device_get_softc(sc->jme_miibus);
436 ASSERT_SERIALIZED(ifp->if_serializer);
439 ifmr->ifm_status = mii->mii_media_status;
440 ifmr->ifm_active = mii->mii_media_active;
444 * Set hardware to newly-selected media.
447 jme_mediachange(struct ifnet *ifp)
449 struct jme_softc *sc = ifp->if_softc;
450 struct mii_data *mii = device_get_softc(sc->jme_miibus);
453 ASSERT_SERIALIZED(ifp->if_serializer);
455 if (mii->mii_instance != 0) {
456 struct mii_softc *miisc;
458 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
459 mii_phy_reset(miisc);
461 error = mii_mediachg(mii);
467 jme_probe(device_t dev)
469 const struct jme_dev *sp;
472 vid = pci_get_vendor(dev);
473 did = pci_get_device(dev);
474 for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
475 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
476 struct jme_softc *sc = device_get_softc(dev);
478 sc->jme_caps = sp->jme_caps;
479 device_set_desc(dev, sp->jme_name);
487 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
493 for (i = JME_TIMEOUT; i > 0; i--) {
494 reg = CSR_READ_4(sc, JME_SMBCSR);
495 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
501 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
505 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
506 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
507 for (i = JME_TIMEOUT; i > 0; i--) {
509 reg = CSR_READ_4(sc, JME_SMBINTF);
510 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
515 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
519 reg = CSR_READ_4(sc, JME_SMBINTF);
520 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
526 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
528 uint8_t fup, reg, val;
533 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
534 fup != JME_EEPROM_SIG0)
536 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
537 fup != JME_EEPROM_SIG1)
541 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
543 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
544 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
545 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0)
547 if (reg >= JME_PAR0 &&
548 reg < JME_PAR0 + ETHER_ADDR_LEN) {
549 if (jme_eeprom_read_byte(sc, offset + 2,
552 eaddr[reg - JME_PAR0] = val;
556 /* Check for the end of EEPROM descriptor. */
557 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
559 /* Try next eeprom descriptor. */
560 offset += JME_EEPROM_DESC_BYTES;
561 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
563 if (match == ETHER_ADDR_LEN)
570 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
574 /* Read station address. */
575 par0 = CSR_READ_4(sc, JME_PAR0);
576 par1 = CSR_READ_4(sc, JME_PAR1);
578 if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
579 device_printf(sc->jme_dev,
580 "generating fake ethernet address.\n");
581 par0 = karc4random();
582 /* Set OUI to JMicron. */
586 eaddr[3] = (par0 >> 16) & 0xff;
587 eaddr[4] = (par0 >> 8) & 0xff;
588 eaddr[5] = par0 & 0xff;
590 eaddr[0] = (par0 >> 0) & 0xFF;
591 eaddr[1] = (par0 >> 8) & 0xFF;
592 eaddr[2] = (par0 >> 16) & 0xFF;
593 eaddr[3] = (par0 >> 24) & 0xFF;
594 eaddr[4] = (par1 >> 0) & 0xFF;
595 eaddr[5] = (par1 >> 8) & 0xFF;
600 jme_attach(device_t dev)
602 struct jme_softc *sc = device_get_softc(dev);
603 struct ifnet *ifp = &sc->arpcom.ac_if;
606 uint8_t pcie_ptr, rev;
608 uint8_t eaddr[ETHER_ADDR_LEN];
610 sc->jme_rx_desc_cnt = roundup(jme_rx_desc_count, JME_NDESC_ALIGN);
611 if (sc->jme_rx_desc_cnt > JME_NDESC_MAX)
612 sc->jme_rx_desc_cnt = JME_NDESC_MAX;
614 sc->jme_tx_desc_cnt = roundup(jme_tx_desc_count, JME_NDESC_ALIGN);
615 if (sc->jme_tx_desc_cnt > JME_NDESC_MAX)
616 sc->jme_tx_desc_cnt = JME_NDESC_MAX;
618 sc->jme_rx_ring_cnt = jme_rx_ring_count;
619 if (sc->jme_rx_ring_cnt <= 0)
620 sc->jme_rx_ring_cnt = JME_NRXRING_1;
621 if (sc->jme_rx_ring_cnt > ncpus2)
622 sc->jme_rx_ring_cnt = ncpus2;
624 if (sc->jme_rx_ring_cnt >= JME_NRXRING_4)
625 sc->jme_rx_ring_cnt = JME_NRXRING_4;
626 else if (sc->jme_rx_ring_cnt >= JME_NRXRING_2)
627 sc->jme_rx_ring_cnt = JME_NRXRING_2;
629 if (sc->jme_rx_ring_cnt > JME_NRXRING_MIN) {
630 sc->jme_caps |= JME_CAP_RSS;
631 sc->jme_flags |= JME_FLAG_RSS;
633 sc->jme_rx_ring_inuse = sc->jme_rx_ring_cnt;
636 sc->jme_lowaddr = BUS_SPACE_MAXADDR;
638 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
640 callout_init(&sc->jme_tick_ch);
643 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
646 irq = pci_read_config(dev, PCIR_INTLINE, 4);
647 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
649 device_printf(dev, "chip is in D%d power mode "
650 "-- setting to D0\n", pci_get_powerstate(dev));
652 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
654 pci_write_config(dev, PCIR_INTLINE, irq, 4);
655 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
657 #endif /* !BURN_BRIDGE */
659 /* Enable bus mastering */
660 pci_enable_busmaster(dev);
665 * JMC250 supports both memory mapped and I/O register space
666 * access. Because I/O register access should use different
667 * BARs to access registers it's waste of time to use I/O
668 * register spce access. JMC250 uses 16K to map entire memory
671 sc->jme_mem_rid = JME_PCIR_BAR;
672 sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
673 &sc->jme_mem_rid, RF_ACTIVE);
674 if (sc->jme_mem_res == NULL) {
675 device_printf(dev, "can't allocate IO memory\n");
678 sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
679 sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
685 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
687 RF_SHAREABLE | RF_ACTIVE);
688 if (sc->jme_irq_res == NULL) {
689 device_printf(dev, "can't allocate irq\n");
697 reg = CSR_READ_4(sc, JME_CHIPMODE);
698 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
700 sc->jme_caps |= JME_CAP_FPGA;
702 device_printf(dev, "FPGA revision: 0x%04x\n",
703 (reg & CHIPMODE_FPGA_REV_MASK) >>
704 CHIPMODE_FPGA_REV_SHIFT);
708 /* NOTE: FM revision is put in the upper 4 bits */
709 rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
710 rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
712 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
714 did = pci_get_device(dev);
716 case PCI_PRODUCT_JMICRON_JMC250:
717 if (rev == JME_REV1_A2)
718 sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
721 case PCI_PRODUCT_JMICRON_JMC260:
723 sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
727 panic("unknown device id 0x%04x\n", did);
729 if (rev >= JME_REV2) {
730 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
731 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
732 GHC_TXMAC_CLKSRC_1000;
735 /* Reset the ethernet controller. */
738 /* Get station address. */
739 reg = CSR_READ_4(sc, JME_SMBCSR);
740 if (reg & SMBCSR_EEPROM_PRESENT)
741 error = jme_eeprom_macaddr(sc, eaddr);
742 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
743 if (error != 0 && (bootverbose)) {
744 device_printf(dev, "ethernet hardware address "
745 "not found in EEPROM.\n");
747 jme_reg_macaddr(sc, eaddr);
752 * Integrated JR0211 has fixed PHY address whereas FPGA version
753 * requires PHY probing to get correct PHY address.
755 if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
756 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
757 GPREG0_PHY_ADDR_MASK;
759 device_printf(dev, "PHY is at address %d.\n",
766 /* Set max allowable DMA size. */
767 pcie_ptr = pci_get_pciecap_ptr(dev);
771 sc->jme_caps |= JME_CAP_PCIE;
772 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
774 device_printf(dev, "Read request size : %d bytes.\n",
775 128 << ((ctrl >> 12) & 0x07));
776 device_printf(dev, "TLP payload size : %d bytes.\n",
777 128 << ((ctrl >> 5) & 0x07));
779 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
780 case PCIEM_DEVCTL_MAX_READRQ_128:
781 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
783 case PCIEM_DEVCTL_MAX_READRQ_256:
784 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
787 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
790 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
792 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
793 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
797 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
798 sc->jme_caps |= JME_CAP_PMCAP;
806 /* Allocate DMA stuffs */
807 error = jme_dma_alloc(sc);
812 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
813 ifp->if_init = jme_init;
814 ifp->if_ioctl = jme_ioctl;
815 ifp->if_start = jme_start;
816 #ifdef DEVICE_POLLING
817 ifp->if_poll = jme_poll;
819 ifp->if_watchdog = jme_watchdog;
820 ifq_set_maxlen(&ifp->if_snd, sc->jme_tx_desc_cnt - JME_TXD_RSVD);
821 ifq_set_ready(&ifp->if_snd);
823 /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
824 ifp->if_capabilities = IFCAP_HWCSUM |
826 IFCAP_VLAN_HWTAGGING;
827 ifp->if_hwassist = JME_CSUM_FEATURES;
828 ifp->if_capenable = ifp->if_capabilities;
830 /* Set up MII bus. */
831 error = mii_phy_probe(dev, &sc->jme_miibus,
832 jme_mediachange, jme_mediastatus);
834 device_printf(dev, "no PHY found!\n");
839 * Save PHYADDR for FPGA mode PHY.
841 if (sc->jme_caps & JME_CAP_FPGA) {
842 struct mii_data *mii = device_get_softc(sc->jme_miibus);
844 if (mii->mii_instance != 0) {
845 struct mii_softc *miisc;
847 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
848 if (miisc->mii_phy != 0) {
849 sc->jme_phyaddr = miisc->mii_phy;
853 if (sc->jme_phyaddr != 0) {
854 device_printf(sc->jme_dev,
855 "FPGA PHY is at %d\n", sc->jme_phyaddr);
857 jme_miibus_writereg(dev, sc->jme_phyaddr,
858 JMPHY_CONF, JMPHY_CONF_DEFFIFO);
860 /* XXX should we clear JME_WA_EXTFIFO */
865 ether_ifattach(ifp, eaddr, NULL);
867 /* Tell the upper layer(s) we support long frames. */
868 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
870 error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE, jme_intr, sc,
871 &sc->jme_irq_handle, ifp->if_serializer);
873 device_printf(dev, "could not set up interrupt handler.\n");
878 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->jme_irq_res));
879 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
887 jme_detach(device_t dev)
889 struct jme_softc *sc = device_get_softc(dev);
891 if (device_is_attached(dev)) {
892 struct ifnet *ifp = &sc->arpcom.ac_if;
894 lwkt_serialize_enter(ifp->if_serializer);
896 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle);
897 lwkt_serialize_exit(ifp->if_serializer);
902 if (sc->jme_sysctl_tree != NULL)
903 sysctl_ctx_free(&sc->jme_sysctl_ctx);
905 if (sc->jme_miibus != NULL)
906 device_delete_child(dev, sc->jme_miibus);
907 bus_generic_detach(dev);
909 if (sc->jme_irq_res != NULL) {
910 bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
914 if (sc->jme_mem_res != NULL) {
915 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
925 jme_sysctl_node(struct jme_softc *sc)
929 char rx_ring_pkt[32];
933 sysctl_ctx_init(&sc->jme_sysctl_ctx);
934 sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
935 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
936 device_get_nameunit(sc->jme_dev),
938 if (sc->jme_sysctl_tree == NULL) {
939 device_printf(sc->jme_dev, "can't add sysctl node\n");
943 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
944 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
945 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
946 sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
948 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
949 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
950 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
951 sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
953 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
954 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
955 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
956 sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
958 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
959 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
960 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
961 sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
963 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
964 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
965 "rx_desc_count", CTLFLAG_RD, &sc->jme_rx_desc_cnt,
967 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
968 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
969 "tx_desc_count", CTLFLAG_RD, &sc->jme_tx_desc_cnt,
971 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
972 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
973 "rx_ring_count", CTLFLAG_RD, &sc->jme_rx_ring_cnt,
975 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
976 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
977 "rx_ring_inuse", CTLFLAG_RD, &sc->jme_rx_ring_inuse,
978 0, "RX ring in use");
980 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
981 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
982 "rss_debug", CTLFLAG_RD, &sc->jme_rss_debug,
983 0, "RSS debug level");
984 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
985 ksnprintf(rx_ring_pkt, sizeof(rx_ring_pkt), "rx_ring%d_pkt", r);
986 SYSCTL_ADD_UINT(&sc->jme_sysctl_ctx,
987 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
988 rx_ring_pkt, CTLFLAG_RD,
989 &sc->jme_rx_ring_pkt[r],
995 * Set default coalesce valves
997 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
998 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
999 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
1000 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
1003 * Adjust coalesce valves, in case that the number of TX/RX
1004 * descs are set to small values by users.
1006 * NOTE: coal_max will not be zero, since number of descs
1007 * must aligned by JME_NDESC_ALIGN (16 currently)
1009 coal_max = sc->jme_tx_desc_cnt / 6;
1010 if (coal_max < sc->jme_tx_coal_pkt)
1011 sc->jme_tx_coal_pkt = coal_max;
1013 coal_max = sc->jme_rx_desc_cnt / 4;
1014 if (coal_max < sc->jme_rx_coal_pkt)
1015 sc->jme_rx_coal_pkt = coal_max;
1019 jme_dma_alloc(struct jme_softc *sc)
1021 struct jme_txdesc *txd;
1025 sc->jme_cdata.jme_txdesc =
1026 kmalloc(sc->jme_tx_desc_cnt * sizeof(struct jme_txdesc),
1027 M_DEVBUF, M_WAITOK | M_ZERO);
1028 for (i = 0; i < sc->jme_rx_ring_cnt; ++i) {
1029 sc->jme_cdata.jme_rx_data[i].jme_rxdesc =
1030 kmalloc(sc->jme_rx_desc_cnt * sizeof(struct jme_rxdesc),
1031 M_DEVBUF, M_WAITOK | M_ZERO);
1034 /* Create parent ring tag. */
1035 error = bus_dma_tag_create(NULL,/* parent */
1036 1, JME_RING_BOUNDARY, /* algnmnt, boundary */
1037 sc->jme_lowaddr, /* lowaddr */
1038 BUS_SPACE_MAXADDR, /* highaddr */
1039 NULL, NULL, /* filter, filterarg */
1040 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1042 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1044 &sc->jme_cdata.jme_ring_tag);
1046 device_printf(sc->jme_dev,
1047 "could not create parent ring DMA tag.\n");
1052 * Create DMA stuffs for TX ring
1054 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1055 JME_TX_RING_ALIGN, 0,
1056 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1057 JME_TX_RING_SIZE(sc),
1058 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1060 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
1063 sc->jme_cdata.jme_tx_ring_tag = dmem.dmem_tag;
1064 sc->jme_cdata.jme_tx_ring_map = dmem.dmem_map;
1065 sc->jme_cdata.jme_tx_ring = dmem.dmem_addr;
1066 sc->jme_cdata.jme_tx_ring_paddr = dmem.dmem_busaddr;
1069 * Create DMA stuffs for RX rings
1071 for (i = 0; i < sc->jme_rx_ring_cnt; ++i) {
1072 error = jme_rxring_dma_alloc(sc, i);
1077 /* Create parent buffer tag. */
1078 error = bus_dma_tag_create(NULL,/* parent */
1079 1, 0, /* algnmnt, boundary */
1080 sc->jme_lowaddr, /* lowaddr */
1081 BUS_SPACE_MAXADDR, /* highaddr */
1082 NULL, NULL, /* filter, filterarg */
1083 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1085 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1087 &sc->jme_cdata.jme_buffer_tag);
1089 device_printf(sc->jme_dev,
1090 "could not create parent buffer DMA tag.\n");
1095 * Create DMA stuffs for shadow status block
1097 error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
1098 JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1099 JME_SSB_SIZE, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1101 device_printf(sc->jme_dev,
1102 "could not create shadow status block.\n");
1105 sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1106 sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1107 sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1108 sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
1111 * Create DMA stuffs for TX buffers
1114 /* Create tag for Tx buffers. */
1115 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1116 1, 0, /* algnmnt, boundary */
1117 BUS_SPACE_MAXADDR, /* lowaddr */
1118 BUS_SPACE_MAXADDR, /* highaddr */
1119 NULL, NULL, /* filter, filterarg */
1120 JME_JUMBO_FRAMELEN, /* maxsize */
1121 JME_MAXTXSEGS, /* nsegments */
1122 JME_MAXSEGSIZE, /* maxsegsize */
1123 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
1124 &sc->jme_cdata.jme_tx_tag);
1126 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1130 /* Create DMA maps for Tx buffers. */
1131 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
1132 txd = &sc->jme_cdata.jme_txdesc[i];
1133 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag,
1134 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1139 device_printf(sc->jme_dev,
1140 "could not create %dth Tx dmamap.\n", i);
1142 for (j = 0; j < i; ++j) {
1143 txd = &sc->jme_cdata.jme_txdesc[j];
1144 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1147 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1148 sc->jme_cdata.jme_tx_tag = NULL;
1154 * Create DMA stuffs for RX buffers
1156 for (i = 0; i < sc->jme_rx_ring_cnt; ++i) {
1157 error = jme_rxbuf_dma_alloc(sc, i);
1165 jme_dma_free(struct jme_softc *sc)
1167 struct jme_txdesc *txd;
1168 struct jme_rxdesc *rxd;
1169 struct jme_rxdata *rdata;
1173 if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1174 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1175 sc->jme_cdata.jme_tx_ring_map);
1176 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1177 sc->jme_cdata.jme_tx_ring,
1178 sc->jme_cdata.jme_tx_ring_map);
1179 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1180 sc->jme_cdata.jme_tx_ring_tag = NULL;
1184 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1185 rdata = &sc->jme_cdata.jme_rx_data[r];
1186 if (rdata->jme_rx_ring_tag != NULL) {
1187 bus_dmamap_unload(rdata->jme_rx_ring_tag,
1188 rdata->jme_rx_ring_map);
1189 bus_dmamem_free(rdata->jme_rx_ring_tag,
1191 rdata->jme_rx_ring_map);
1192 bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1193 rdata->jme_rx_ring_tag = NULL;
1198 if (sc->jme_cdata.jme_tx_tag != NULL) {
1199 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
1200 txd = &sc->jme_cdata.jme_txdesc[i];
1201 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1204 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1205 sc->jme_cdata.jme_tx_tag = NULL;
1209 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1210 rdata = &sc->jme_cdata.jme_rx_data[r];
1211 if (rdata->jme_rx_tag != NULL) {
1212 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
1213 rxd = &rdata->jme_rxdesc[i];
1214 bus_dmamap_destroy(rdata->jme_rx_tag,
1217 bus_dmamap_destroy(rdata->jme_rx_tag,
1218 rdata->jme_rx_sparemap);
1219 bus_dma_tag_destroy(rdata->jme_rx_tag);
1220 rdata->jme_rx_tag = NULL;
1224 /* Shadow status block. */
1225 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1226 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1227 sc->jme_cdata.jme_ssb_map);
1228 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1229 sc->jme_cdata.jme_ssb_block,
1230 sc->jme_cdata.jme_ssb_map);
1231 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1232 sc->jme_cdata.jme_ssb_tag = NULL;
1235 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1236 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1237 sc->jme_cdata.jme_buffer_tag = NULL;
1239 if (sc->jme_cdata.jme_ring_tag != NULL) {
1240 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1241 sc->jme_cdata.jme_ring_tag = NULL;
1244 if (sc->jme_cdata.jme_txdesc != NULL) {
1245 kfree(sc->jme_cdata.jme_txdesc, M_DEVBUF);
1246 sc->jme_cdata.jme_txdesc = NULL;
1248 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1249 rdata = &sc->jme_cdata.jme_rx_data[r];
1250 if (rdata->jme_rxdesc != NULL) {
1251 kfree(rdata->jme_rxdesc, M_DEVBUF);
1252 rdata->jme_rxdesc = NULL;
1258 * Make sure the interface is stopped at reboot time.
1261 jme_shutdown(device_t dev)
1263 return jme_suspend(dev);
1268 * Unlike other ethernet controllers, JMC250 requires
1269 * explicit resetting link speed to 10/100Mbps as gigabit
1270 * link will cunsume more power than 375mA.
1271 * Note, we reset the link speed to 10/100Mbps with
1272 * auto-negotiation but we don't know whether that operation
1273 * would succeed or not as we have no control after powering
1274 * off. If the renegotiation fail WOL may not work. Running
1275 * at 1Gbps draws more power than 375mA at 3.3V which is
1276 * specified in PCI specification and that would result in
1277 * complete shutdowning power to ethernet controller.
1280 * Save current negotiated media speed/duplex/flow-control
1281 * to softc and restore the same link again after resuming.
1282 * PHY handling such as power down/resetting to 100Mbps
1283 * may be better handled in suspend method in phy driver.
1286 jme_setlinkspeed(struct jme_softc *sc)
1288 struct mii_data *mii;
1291 JME_LOCK_ASSERT(sc);
1293 mii = device_get_softc(sc->jme_miibus);
1296 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1297 switch IFM_SUBTYPE(mii->mii_media_active) {
1307 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1308 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1309 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1310 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1311 BMCR_AUTOEN | BMCR_STARTNEG);
1314 /* Poll link state until jme(4) get a 10/100 link. */
1315 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1317 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1318 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1328 pause("jmelnk", hz);
1331 if (i == MII_ANEGTICKS_GIGE)
1332 device_printf(sc->jme_dev, "establishing link failed, "
1333 "WOL may not work!");
1336 * No link, force MAC to have 100Mbps, full-duplex link.
1337 * This is the last resort and may/may not work.
1339 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1340 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1345 jme_setwol(struct jme_softc *sc)
1347 struct ifnet *ifp = &sc->arpcom.ac_if;
1352 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1353 /* No PME capability, PHY power down. */
1354 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1355 MII_BMCR, BMCR_PDOWN);
1359 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1360 pmcs = CSR_READ_4(sc, JME_PMCS);
1361 pmcs &= ~PMCS_WOL_ENB_MASK;
1362 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1363 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1364 /* Enable PME message. */
1365 gpr |= GPREG0_PME_ENB;
1366 /* For gigabit controllers, reset link speed to 10/100. */
1367 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
1368 jme_setlinkspeed(sc);
1371 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1372 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1375 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1376 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1377 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1378 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1379 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1380 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1381 /* No WOL, PHY power down. */
1382 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1383 MII_BMCR, BMCR_PDOWN);
1389 jme_suspend(device_t dev)
1391 struct jme_softc *sc = device_get_softc(dev);
1392 struct ifnet *ifp = &sc->arpcom.ac_if;
1394 lwkt_serialize_enter(ifp->if_serializer);
1399 lwkt_serialize_exit(ifp->if_serializer);
1405 jme_resume(device_t dev)
1407 struct jme_softc *sc = device_get_softc(dev);
1408 struct ifnet *ifp = &sc->arpcom.ac_if;
1413 lwkt_serialize_enter(ifp->if_serializer);
1416 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1419 pmstat = pci_read_config(sc->jme_dev,
1420 pmc + PCIR_POWER_STATUS, 2);
1421 /* Disable PME clear PME status. */
1422 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1423 pci_write_config(sc->jme_dev,
1424 pmc + PCIR_POWER_STATUS, pmstat, 2);
1428 if (ifp->if_flags & IFF_UP)
1431 lwkt_serialize_exit(ifp->if_serializer);
1437 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1439 struct jme_txdesc *txd;
1440 struct jme_desc *desc;
1442 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1444 int error, i, prod, symbol_desc;
1445 uint32_t cflags, flag64;
1447 M_ASSERTPKTHDR((*m_head));
1449 prod = sc->jme_cdata.jme_tx_prod;
1450 txd = &sc->jme_cdata.jme_txdesc[prod];
1452 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
1457 maxsegs = (sc->jme_tx_desc_cnt - sc->jme_cdata.jme_tx_cnt) -
1458 (JME_TXD_RSVD + symbol_desc);
1459 if (maxsegs > JME_MAXTXSEGS)
1460 maxsegs = JME_MAXTXSEGS;
1461 KASSERT(maxsegs >= (sc->jme_txd_spare - symbol_desc),
1462 ("not enough segments %d\n", maxsegs));
1464 error = bus_dmamap_load_mbuf_defrag(sc->jme_cdata.jme_tx_tag,
1465 txd->tx_dmamap, m_head,
1466 txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1470 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1471 BUS_DMASYNC_PREWRITE);
1476 /* Configure checksum offload. */
1477 if (m->m_pkthdr.csum_flags & CSUM_IP)
1478 cflags |= JME_TD_IPCSUM;
1479 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1480 cflags |= JME_TD_TCPCSUM;
1481 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1482 cflags |= JME_TD_UDPCSUM;
1484 /* Configure VLAN. */
1485 if (m->m_flags & M_VLANTAG) {
1486 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1487 cflags |= JME_TD_VLAN_TAG;
1490 desc = &sc->jme_cdata.jme_tx_ring[prod];
1491 desc->flags = htole32(cflags);
1492 desc->addr_hi = htole32(m->m_pkthdr.len);
1493 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1495 * Use 64bits TX desc chain format.
1497 * The first TX desc of the chain, which is setup here,
1498 * is just a symbol TX desc carrying no payload.
1500 flag64 = JME_TD_64BIT;
1504 /* No effective TX desc is consumed */
1508 * Use 32bits TX desc chain format.
1510 * The first TX desc of the chain, which is setup here,
1511 * is an effective TX desc carrying the first segment of
1515 desc->buflen = htole32(txsegs[0].ds_len);
1516 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1518 /* One effective TX desc is consumed */
1521 sc->jme_cdata.jme_tx_cnt++;
1522 KKASSERT(sc->jme_cdata.jme_tx_cnt - i <
1523 sc->jme_tx_desc_cnt - JME_TXD_RSVD);
1524 JME_DESC_INC(prod, sc->jme_tx_desc_cnt);
1526 txd->tx_ndesc = 1 - i;
1527 for (; i < nsegs; i++) {
1528 desc = &sc->jme_cdata.jme_tx_ring[prod];
1529 desc->flags = htole32(JME_TD_OWN | flag64);
1530 desc->buflen = htole32(txsegs[i].ds_len);
1531 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1532 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1534 sc->jme_cdata.jme_tx_cnt++;
1535 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
1536 sc->jme_tx_desc_cnt - JME_TXD_RSVD);
1537 JME_DESC_INC(prod, sc->jme_tx_desc_cnt);
1540 /* Update producer index. */
1541 sc->jme_cdata.jme_tx_prod = prod;
1543 * Finally request interrupt and give the first descriptor
1544 * owenership to hardware.
1546 desc = txd->tx_desc;
1547 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1550 txd->tx_ndesc += nsegs;
1560 jme_start(struct ifnet *ifp)
1562 struct jme_softc *sc = ifp->if_softc;
1563 struct mbuf *m_head;
1566 ASSERT_SERIALIZED(ifp->if_serializer);
1568 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1569 ifq_purge(&ifp->if_snd);
1573 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1576 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT(sc))
1579 while (!ifq_is_empty(&ifp->if_snd)) {
1581 * Check number of available TX descs, always
1582 * leave JME_TXD_RSVD free TX descs.
1584 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare >
1585 sc->jme_tx_desc_cnt - JME_TXD_RSVD) {
1586 ifp->if_flags |= IFF_OACTIVE;
1590 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1595 * Pack the data into the transmit ring. If we
1596 * don't have room, set the OACTIVE flag and wait
1597 * for the NIC to drain the ring.
1599 if (jme_encap(sc, &m_head)) {
1600 KKASSERT(m_head == NULL);
1602 ifp->if_flags |= IFF_OACTIVE;
1608 * If there's a BPF listener, bounce a copy of this frame
1611 ETHER_BPF_MTAP(ifp, m_head);
1616 * Reading TXCSR takes very long time under heavy load
1617 * so cache TXCSR value and writes the ORed value with
1618 * the kick command to the TXCSR. This saves one register
1621 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1622 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1623 /* Set a timeout in case the chip goes out to lunch. */
1624 ifp->if_timer = JME_TX_TIMEOUT;
1629 jme_watchdog(struct ifnet *ifp)
1631 struct jme_softc *sc = ifp->if_softc;
1633 ASSERT_SERIALIZED(ifp->if_serializer);
1635 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1636 if_printf(ifp, "watchdog timeout (missed link)\n");
1643 if (sc->jme_cdata.jme_tx_cnt == 0) {
1644 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1646 if (!ifq_is_empty(&ifp->if_snd))
1651 if_printf(ifp, "watchdog timeout\n");
1654 if (!ifq_is_empty(&ifp->if_snd))
1659 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1661 struct jme_softc *sc = ifp->if_softc;
1662 struct mii_data *mii = device_get_softc(sc->jme_miibus);
1663 struct ifreq *ifr = (struct ifreq *)data;
1664 int error = 0, mask;
1666 ASSERT_SERIALIZED(ifp->if_serializer);
1670 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1671 (!(sc->jme_caps & JME_CAP_JUMBO) &&
1672 ifr->ifr_mtu > JME_MAX_MTU)) {
1677 if (ifp->if_mtu != ifr->ifr_mtu) {
1679 * No special configuration is required when interface
1680 * MTU is changed but availability of Tx checksum
1681 * offload should be chcked against new MTU size as
1682 * FIFO size is just 2K.
1684 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1685 ifp->if_capenable &= ~IFCAP_TXCSUM;
1686 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1688 ifp->if_mtu = ifr->ifr_mtu;
1689 if (ifp->if_flags & IFF_RUNNING)
1695 if (ifp->if_flags & IFF_UP) {
1696 if (ifp->if_flags & IFF_RUNNING) {
1697 if ((ifp->if_flags ^ sc->jme_if_flags) &
1698 (IFF_PROMISC | IFF_ALLMULTI))
1704 if (ifp->if_flags & IFF_RUNNING)
1707 sc->jme_if_flags = ifp->if_flags;
1712 if (ifp->if_flags & IFF_RUNNING)
1718 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1722 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1724 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1725 if (IFCAP_TXCSUM & ifp->if_capabilities) {
1726 ifp->if_capenable ^= IFCAP_TXCSUM;
1727 if (IFCAP_TXCSUM & ifp->if_capenable)
1728 ifp->if_hwassist |= JME_CSUM_FEATURES;
1730 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1733 if ((mask & IFCAP_RXCSUM) &&
1734 (IFCAP_RXCSUM & ifp->if_capabilities)) {
1737 ifp->if_capenable ^= IFCAP_RXCSUM;
1738 reg = CSR_READ_4(sc, JME_RXMAC);
1739 reg &= ~RXMAC_CSUM_ENB;
1740 if (ifp->if_capenable & IFCAP_RXCSUM)
1741 reg |= RXMAC_CSUM_ENB;
1742 CSR_WRITE_4(sc, JME_RXMAC, reg);
1745 if ((mask & IFCAP_VLAN_HWTAGGING) &&
1746 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities)) {
1747 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1753 error = ether_ioctl(ifp, cmd, data);
1760 jme_mac_config(struct jme_softc *sc)
1762 struct mii_data *mii;
1763 uint32_t ghc, rxmac, txmac, txpause, gp1;
1764 int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
1766 mii = device_get_softc(sc->jme_miibus);
1768 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1770 CSR_WRITE_4(sc, JME_GHC, 0);
1772 rxmac = CSR_READ_4(sc, JME_RXMAC);
1773 rxmac &= ~RXMAC_FC_ENB;
1774 txmac = CSR_READ_4(sc, JME_TXMAC);
1775 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1776 txpause = CSR_READ_4(sc, JME_TXPFC);
1777 txpause &= ~TXPFC_PAUSE_ENB;
1778 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1779 ghc |= GHC_FULL_DUPLEX;
1780 rxmac &= ~RXMAC_COLL_DET_ENB;
1781 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1782 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1785 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1786 txpause |= TXPFC_PAUSE_ENB;
1787 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1788 rxmac |= RXMAC_FC_ENB;
1790 /* Disable retry transmit timer/retry limit. */
1791 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1792 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1794 rxmac |= RXMAC_COLL_DET_ENB;
1795 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1796 /* Enable retry transmit timer/retry limit. */
1797 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1798 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1802 * Reprogram Tx/Rx MACs with resolved speed/duplex.
1804 gp1 = CSR_READ_4(sc, JME_GPREG1);
1805 gp1 &= ~GPREG1_WA_HDX;
1807 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1810 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1812 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
1814 gp1 |= GPREG1_WA_HDX;
1818 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
1820 gp1 |= GPREG1_WA_HDX;
1823 * Use extended FIFO depth to workaround CRC errors
1824 * emitted by chips before JMC250B
1826 phyconf = JMPHY_CONF_EXTFIFO;
1830 if (sc->jme_caps & JME_CAP_FASTETH)
1833 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
1835 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1841 CSR_WRITE_4(sc, JME_GHC, ghc);
1842 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1843 CSR_WRITE_4(sc, JME_TXMAC, txmac);
1844 CSR_WRITE_4(sc, JME_TXPFC, txpause);
1846 if (sc->jme_workaround & JME_WA_EXTFIFO) {
1847 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1848 JMPHY_CONF, phyconf);
1850 if (sc->jme_workaround & JME_WA_HDX)
1851 CSR_WRITE_4(sc, JME_GPREG1, gp1);
1857 struct jme_softc *sc = xsc;
1858 struct ifnet *ifp = &sc->arpcom.ac_if;
1862 ASSERT_SERIALIZED(ifp->if_serializer);
1864 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
1865 if (status == 0 || status == 0xFFFFFFFF)
1868 /* Disable interrupts. */
1869 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
1871 status = CSR_READ_4(sc, JME_INTR_STATUS);
1872 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
1875 /* Reset PCC counter/timer and Ack interrupts. */
1876 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
1878 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
1879 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
1881 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
1882 if (status & jme_rx_status[r].jme_coal) {
1883 status |= jme_rx_status[r].jme_coal |
1884 jme_rx_status[r].jme_comp;
1888 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
1890 if (ifp->if_flags & IFF_RUNNING) {
1891 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
1892 jme_rx_intr(sc, status);
1894 if (status & INTR_RXQ_DESC_EMPTY) {
1896 * Notify hardware availability of new Rx buffers.
1897 * Reading RXCSR takes very long time under heavy
1898 * load so cache RXCSR value and writes the ORed
1899 * value with the kick command to the RXCSR. This
1900 * saves one register access cycle.
1902 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
1903 RXCSR_RX_ENB | RXCSR_RXQ_START);
1906 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
1908 if (!ifq_is_empty(&ifp->if_snd))
1913 /* Reenable interrupts. */
1914 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
1918 jme_txeof(struct jme_softc *sc)
1920 struct ifnet *ifp = &sc->arpcom.ac_if;
1921 struct jme_txdesc *txd;
1925 cons = sc->jme_cdata.jme_tx_cons;
1926 if (cons == sc->jme_cdata.jme_tx_prod)
1930 * Go through our Tx list and free mbufs for those
1931 * frames which have been transmitted.
1933 while (cons != sc->jme_cdata.jme_tx_prod) {
1934 txd = &sc->jme_cdata.jme_txdesc[cons];
1935 KASSERT(txd->tx_m != NULL,
1936 ("%s: freeing NULL mbuf!\n", __func__));
1938 status = le32toh(txd->tx_desc->flags);
1939 if ((status & JME_TD_OWN) == JME_TD_OWN)
1942 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
1946 if (status & JME_TD_COLLISION) {
1947 ifp->if_collisions +=
1948 le32toh(txd->tx_desc->buflen) &
1949 JME_TD_BUF_LEN_MASK;
1954 * Only the first descriptor of multi-descriptor
1955 * transmission is updated so driver have to skip entire
1956 * chained buffers for the transmiited frame. In other
1957 * words, JME_TD_OWN bit is valid only at the first
1958 * descriptor of a multi-descriptor transmission.
1960 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
1961 sc->jme_cdata.jme_tx_ring[cons].flags = 0;
1962 JME_DESC_INC(cons, sc->jme_tx_desc_cnt);
1965 /* Reclaim transferred mbufs. */
1966 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
1969 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
1970 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
1971 ("%s: Active Tx desc counter was garbled\n", __func__));
1974 sc->jme_cdata.jme_tx_cons = cons;
1976 if (sc->jme_cdata.jme_tx_cnt == 0)
1979 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare <=
1980 sc->jme_tx_desc_cnt - JME_TXD_RSVD)
1981 ifp->if_flags &= ~IFF_OACTIVE;
1984 static __inline void
1985 jme_discard_rxbufs(struct jme_softc *sc, int ring, int cons, int count)
1987 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
1990 for (i = 0; i < count; ++i) {
1991 struct jme_desc *desc = &rdata->jme_rx_ring[cons];
1993 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
1994 desc->buflen = htole32(MCLBYTES);
1995 JME_DESC_INC(cons, sc->jme_rx_desc_cnt);
1999 /* Receive a frame. */
2001 jme_rxpkt(struct jme_softc *sc, int ring, struct mbuf_chain *chain)
2003 struct ifnet *ifp = &sc->arpcom.ac_if;
2004 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2005 struct jme_desc *desc;
2006 struct jme_rxdesc *rxd;
2007 struct mbuf *mp, *m;
2008 uint32_t flags, status;
2009 int cons, count, nsegs;
2011 cons = rdata->jme_rx_cons;
2012 desc = &rdata->jme_rx_ring[cons];
2013 flags = le32toh(desc->flags);
2014 status = le32toh(desc->buflen);
2015 nsegs = JME_RX_NSEGS(status);
2017 JME_RSS_DPRINTF(sc, 10, "ring%d, flags 0x%08x, "
2018 "hash 0x%08x, hash type 0x%08x\n",
2019 ring, flags, desc->addr_hi, desc->addr_lo);
2021 if (status & JME_RX_ERR_STAT) {
2023 jme_discard_rxbufs(sc, ring, cons, nsegs);
2024 #ifdef JME_SHOW_ERRORS
2025 device_printf(sc->jme_dev, "%s : receive error = 0x%b\n",
2026 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2028 rdata->jme_rx_cons += nsegs;
2029 rdata->jme_rx_cons %= sc->jme_rx_desc_cnt;
2033 rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2034 for (count = 0; count < nsegs; count++,
2035 JME_DESC_INC(cons, sc->jme_rx_desc_cnt)) {
2036 rxd = &rdata->jme_rxdesc[cons];
2039 /* Add a new receive buffer to the ring. */
2040 if (jme_newbuf(sc, ring, rxd, 0) != 0) {
2043 jme_discard_rxbufs(sc, ring, cons, nsegs - count);
2044 if (rdata->jme_rxhead != NULL) {
2045 m_freem(rdata->jme_rxhead);
2046 JME_RXCHAIN_RESET(sc, ring);
2052 * Assume we've received a full sized frame.
2053 * Actual size is fixed when we encounter the end of
2054 * multi-segmented frame.
2056 mp->m_len = MCLBYTES;
2058 /* Chain received mbufs. */
2059 if (rdata->jme_rxhead == NULL) {
2060 rdata->jme_rxhead = mp;
2061 rdata->jme_rxtail = mp;
2064 * Receive processor can receive a maximum frame
2065 * size of 65535 bytes.
2067 mp->m_flags &= ~M_PKTHDR;
2068 rdata->jme_rxtail->m_next = mp;
2069 rdata->jme_rxtail = mp;
2072 if (count == nsegs - 1) {
2073 /* Last desc. for this frame. */
2074 m = rdata->jme_rxhead;
2075 /* XXX assert PKTHDR? */
2076 m->m_flags |= M_PKTHDR;
2077 m->m_pkthdr.len = rdata->jme_rxlen;
2079 /* Set first mbuf size. */
2080 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2081 /* Set last mbuf size. */
2082 mp->m_len = rdata->jme_rxlen -
2083 ((MCLBYTES - JME_RX_PAD_BYTES) +
2084 (MCLBYTES * (nsegs - 2)));
2086 m->m_len = rdata->jme_rxlen;
2088 m->m_pkthdr.rcvif = ifp;
2091 * Account for 10bytes auto padding which is used
2092 * to align IP header on 32bit boundary. Also note,
2093 * CRC bytes is automatically removed by the
2096 m->m_data += JME_RX_PAD_BYTES;
2098 /* Set checksum information. */
2099 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2100 (flags & JME_RD_IPV4)) {
2101 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2102 if (flags & JME_RD_IPCSUM)
2103 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2104 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2105 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2106 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2107 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2108 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2109 m->m_pkthdr.csum_flags |=
2110 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2111 m->m_pkthdr.csum_data = 0xffff;
2115 /* Check for VLAN tagged packets. */
2116 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2117 (flags & JME_RD_VLAN_TAG)) {
2118 m->m_pkthdr.ether_vlantag =
2119 flags & JME_RD_VLAN_MASK;
2120 m->m_flags |= M_VLANTAG;
2125 ether_input_chain(ifp, m, chain);
2127 /* Reset mbuf chains. */
2128 JME_RXCHAIN_RESET(sc, ring);
2129 #ifdef JME_RSS_DEBUG
2130 sc->jme_rx_ring_pkt[ring]++;
2135 rdata->jme_rx_cons += nsegs;
2136 rdata->jme_rx_cons %= sc->jme_rx_desc_cnt;
2140 jme_rxeof_chain(struct jme_softc *sc, int ring, struct mbuf_chain *chain,
2143 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2144 struct jme_desc *desc;
2145 int nsegs, prog, pktlen;
2149 #ifdef DEVICE_POLLING
2150 if (count >= 0 && count-- == 0)
2153 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
2154 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2156 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2160 * Check number of segments against received bytes.
2161 * Non-matching value would indicate that hardware
2162 * is still trying to update Rx descriptors. I'm not
2163 * sure whether this check is needed.
2165 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2166 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2167 if (nsegs != howmany(pktlen, MCLBYTES)) {
2168 if_printf(&sc->arpcom.ac_if, "RX fragment count(%d) "
2169 "and packet size(%d) mismach\n",
2174 /* Received a frame. */
2175 jme_rxpkt(sc, ring, chain);
2182 jme_rxeof(struct jme_softc *sc, int ring)
2184 struct mbuf_chain chain[MAXCPU];
2186 ether_input_chain_init(chain);
2187 if (jme_rxeof_chain(sc, ring, chain, -1))
2188 ether_input_dispatch(chain);
2194 struct jme_softc *sc = xsc;
2195 struct ifnet *ifp = &sc->arpcom.ac_if;
2196 struct mii_data *mii = device_get_softc(sc->jme_miibus);
2198 lwkt_serialize_enter(ifp->if_serializer);
2201 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2203 lwkt_serialize_exit(ifp->if_serializer);
2207 jme_reset(struct jme_softc *sc)
2210 /* Stop receiver, transmitter. */
2214 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2216 CSR_WRITE_4(sc, JME_GHC, 0);
2222 struct jme_softc *sc = xsc;
2223 struct ifnet *ifp = &sc->arpcom.ac_if;
2224 struct mii_data *mii;
2225 uint8_t eaddr[ETHER_ADDR_LEN];
2230 ASSERT_SERIALIZED(ifp->if_serializer);
2233 * Cancel any pending I/O.
2238 * Reset the chip to a known state.
2243 howmany(ifp->if_mtu + sizeof(struct ether_vlan_header), MCLBYTES);
2244 KKASSERT(sc->jme_txd_spare >= 1);
2247 * If we use 64bit address mode for transmitting, each Tx request
2248 * needs one more symbol descriptor.
2250 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
2251 sc->jme_txd_spare += 1;
2253 if (sc->jme_flags & JME_FLAG_RSS)
2256 jme_disable_rss(sc);
2258 /* Init RX descriptors */
2259 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
2260 error = jme_init_rx_ring(sc, r);
2262 if_printf(ifp, "initialization failed: "
2263 "no memory for %dth RX ring.\n", r);
2269 /* Init TX descriptors */
2270 jme_init_tx_ring(sc);
2272 /* Initialize shadow status block. */
2275 /* Reprogram the station address. */
2276 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2277 CSR_WRITE_4(sc, JME_PAR0,
2278 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2279 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2282 * Configure Tx queue.
2283 * Tx priority queue weight value : 0
2284 * Tx FIFO threshold for processing next packet : 16QW
2285 * Maximum Tx DMA length : 512
2286 * Allow Tx DMA burst.
2288 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2289 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2290 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2291 sc->jme_txcsr |= sc->jme_tx_dma_size;
2292 sc->jme_txcsr |= TXCSR_DMA_BURST;
2293 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2295 /* Set Tx descriptor counter. */
2296 CSR_WRITE_4(sc, JME_TXQDC, sc->jme_tx_desc_cnt);
2298 /* Set Tx ring address to the hardware. */
2299 paddr = sc->jme_cdata.jme_tx_ring_paddr;
2300 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2301 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2303 /* Configure TxMAC parameters. */
2304 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2305 reg |= TXMAC_THRESH_1_PKT;
2306 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2307 CSR_WRITE_4(sc, JME_TXMAC, reg);
2310 * Configure Rx queue.
2311 * FIFO full threshold for transmitting Tx pause packet : 128T
2312 * FIFO threshold for processing next packet : 128QW
2314 * Max Rx DMA length : 128
2315 * Rx descriptor retry : 32
2316 * Rx descriptor retry time gap : 256ns
2317 * Don't receive runt/bad frame.
2319 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2322 * Since Rx FIFO size is 4K bytes, receiving frames larger
2323 * than 4K bytes will suffer from Rx FIFO overruns. So
2324 * decrease FIFO threshold to reduce the FIFO overruns for
2325 * frames larger than 4000 bytes.
2326 * For best performance of standard MTU sized frames use
2327 * maximum allowable FIFO threshold, 128QW.
2329 if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2331 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2333 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2335 /* Improve PCI Express compatibility */
2336 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2338 sc->jme_rxcsr |= sc->jme_rx_dma_size;
2339 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2340 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2341 /* XXX TODO DROP_BAD */
2343 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
2344 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2346 /* Set Rx descriptor counter. */
2347 CSR_WRITE_4(sc, JME_RXQDC, sc->jme_rx_desc_cnt);
2349 /* Set Rx ring address to the hardware. */
2350 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
2351 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2352 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2355 /* Clear receive filter. */
2356 CSR_WRITE_4(sc, JME_RXMAC, 0);
2358 /* Set up the receive filter. */
2363 * Disable all WOL bits as WOL can interfere normal Rx
2364 * operation. Also clear WOL detection status bits.
2366 reg = CSR_READ_4(sc, JME_PMCS);
2367 reg &= ~PMCS_WOL_ENB_MASK;
2368 CSR_WRITE_4(sc, JME_PMCS, reg);
2371 * Pad 10bytes right before received frame. This will greatly
2372 * help Rx performance on strict-alignment architectures as
2373 * it does not need to copy the frame to align the payload.
2375 reg = CSR_READ_4(sc, JME_RXMAC);
2376 reg |= RXMAC_PAD_10BYTES;
2378 if (ifp->if_capenable & IFCAP_RXCSUM)
2379 reg |= RXMAC_CSUM_ENB;
2380 CSR_WRITE_4(sc, JME_RXMAC, reg);
2382 /* Configure general purpose reg0 */
2383 reg = CSR_READ_4(sc, JME_GPREG0);
2384 reg &= ~GPREG0_PCC_UNIT_MASK;
2385 /* Set PCC timer resolution to micro-seconds unit. */
2386 reg |= GPREG0_PCC_UNIT_US;
2388 * Disable all shadow register posting as we have to read
2389 * JME_INTR_STATUS register in jme_intr. Also it seems
2390 * that it's hard to synchronize interrupt status between
2391 * hardware and software with shadow posting due to
2392 * requirements of bus_dmamap_sync(9).
2394 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2395 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2396 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2397 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2398 /* Disable posting of DW0. */
2399 reg &= ~GPREG0_POST_DW0_ENB;
2400 /* Clear PME message. */
2401 reg &= ~GPREG0_PME_ENB;
2402 /* Set PHY address. */
2403 reg &= ~GPREG0_PHY_ADDR_MASK;
2404 reg |= sc->jme_phyaddr;
2405 CSR_WRITE_4(sc, JME_GPREG0, reg);
2407 /* Configure Tx queue 0 packet completion coalescing. */
2408 jme_set_tx_coal(sc);
2410 /* Configure Rx queue 0 packet completion coalescing. */
2411 jme_set_rx_coal(sc);
2413 /* Configure shadow status block but don't enable posting. */
2414 paddr = sc->jme_cdata.jme_ssb_block_paddr;
2415 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2416 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2418 /* Disable Timer 1 and Timer 2. */
2419 CSR_WRITE_4(sc, JME_TIMER1, 0);
2420 CSR_WRITE_4(sc, JME_TIMER2, 0);
2422 /* Configure retry transmit period, retry limit value. */
2423 CSR_WRITE_4(sc, JME_TXTRHD,
2424 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2425 TXTRHD_RT_PERIOD_MASK) |
2426 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2427 TXTRHD_RT_LIMIT_SHIFT));
2429 #ifdef DEVICE_POLLING
2430 if (!(ifp->if_flags & IFF_POLLING))
2432 /* Initialize the interrupt mask. */
2433 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2434 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2437 * Enabling Tx/Rx DMA engines and Rx queue processing is
2438 * done after detection of valid link in jme_miibus_statchg.
2440 sc->jme_flags &= ~JME_FLAG_LINK;
2442 /* Set the current media. */
2443 mii = device_get_softc(sc->jme_miibus);
2446 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2448 ifp->if_flags |= IFF_RUNNING;
2449 ifp->if_flags &= ~IFF_OACTIVE;
2453 jme_stop(struct jme_softc *sc)
2455 struct ifnet *ifp = &sc->arpcom.ac_if;
2456 struct jme_txdesc *txd;
2457 struct jme_rxdesc *rxd;
2458 struct jme_rxdata *rdata;
2461 ASSERT_SERIALIZED(ifp->if_serializer);
2464 * Mark the interface down and cancel the watchdog timer.
2466 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2469 callout_stop(&sc->jme_tick_ch);
2470 sc->jme_flags &= ~JME_FLAG_LINK;
2473 * Disable interrupts.
2475 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2476 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2478 /* Disable updating shadow status block. */
2479 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2480 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2482 /* Stop receiver, transmitter. */
2487 * Free partial finished RX segments
2489 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
2490 rdata = &sc->jme_cdata.jme_rx_data[r];
2491 if (rdata->jme_rxhead != NULL)
2492 m_freem(rdata->jme_rxhead);
2493 JME_RXCHAIN_RESET(sc, r);
2497 * Free RX and TX mbufs still in the queues.
2499 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
2500 rdata = &sc->jme_cdata.jme_rx_data[r];
2501 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
2502 rxd = &rdata->jme_rxdesc[i];
2503 if (rxd->rx_m != NULL) {
2504 bus_dmamap_unload(rdata->jme_rx_tag,
2511 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
2512 txd = &sc->jme_cdata.jme_txdesc[i];
2513 if (txd->tx_m != NULL) {
2514 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2524 jme_stop_tx(struct jme_softc *sc)
2529 reg = CSR_READ_4(sc, JME_TXCSR);
2530 if ((reg & TXCSR_TX_ENB) == 0)
2532 reg &= ~TXCSR_TX_ENB;
2533 CSR_WRITE_4(sc, JME_TXCSR, reg);
2534 for (i = JME_TIMEOUT; i > 0; i--) {
2536 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2540 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2544 jme_stop_rx(struct jme_softc *sc)
2549 reg = CSR_READ_4(sc, JME_RXCSR);
2550 if ((reg & RXCSR_RX_ENB) == 0)
2552 reg &= ~RXCSR_RX_ENB;
2553 CSR_WRITE_4(sc, JME_RXCSR, reg);
2554 for (i = JME_TIMEOUT; i > 0; i--) {
2556 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2560 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2564 jme_init_tx_ring(struct jme_softc *sc)
2566 struct jme_chain_data *cd;
2567 struct jme_txdesc *txd;
2570 sc->jme_cdata.jme_tx_prod = 0;
2571 sc->jme_cdata.jme_tx_cons = 0;
2572 sc->jme_cdata.jme_tx_cnt = 0;
2574 cd = &sc->jme_cdata;
2575 bzero(cd->jme_tx_ring, JME_TX_RING_SIZE(sc));
2576 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
2577 txd = &sc->jme_cdata.jme_txdesc[i];
2579 txd->tx_desc = &cd->jme_tx_ring[i];
2585 jme_init_ssb(struct jme_softc *sc)
2587 struct jme_chain_data *cd;
2589 cd = &sc->jme_cdata;
2590 bzero(cd->jme_ssb_block, JME_SSB_SIZE);
2594 jme_init_rx_ring(struct jme_softc *sc, int ring)
2596 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2597 struct jme_rxdesc *rxd;
2600 KKASSERT(rdata->jme_rxhead == NULL &&
2601 rdata->jme_rxtail == NULL &&
2602 rdata->jme_rxlen == 0);
2603 rdata->jme_rx_cons = 0;
2605 bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(sc));
2606 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
2609 rxd = &rdata->jme_rxdesc[i];
2611 rxd->rx_desc = &rdata->jme_rx_ring[i];
2612 error = jme_newbuf(sc, ring, rxd, 1);
2620 jme_newbuf(struct jme_softc *sc, int ring, struct jme_rxdesc *rxd, int init)
2622 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2623 struct jme_desc *desc;
2625 bus_dma_segment_t segs;
2629 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2633 * JMC250 has 64bit boundary alignment limitation so jme(4)
2634 * takes advantage of 10 bytes padding feature of hardware
2635 * in order not to copy entire frame to align IP header on
2638 m->m_len = m->m_pkthdr.len = MCLBYTES;
2640 error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
2641 rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
2646 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
2650 if (rxd->rx_m != NULL) {
2651 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
2652 BUS_DMASYNC_POSTREAD);
2653 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
2655 map = rxd->rx_dmamap;
2656 rxd->rx_dmamap = rdata->jme_rx_sparemap;
2657 rdata->jme_rx_sparemap = map;
2660 desc = rxd->rx_desc;
2661 desc->buflen = htole32(segs.ds_len);
2662 desc->addr_lo = htole32(JME_ADDR_LO(segs.ds_addr));
2663 desc->addr_hi = htole32(JME_ADDR_HI(segs.ds_addr));
2664 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2670 jme_set_vlan(struct jme_softc *sc)
2672 struct ifnet *ifp = &sc->arpcom.ac_if;
2675 ASSERT_SERIALIZED(ifp->if_serializer);
2677 reg = CSR_READ_4(sc, JME_RXMAC);
2678 reg &= ~RXMAC_VLAN_ENB;
2679 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2680 reg |= RXMAC_VLAN_ENB;
2681 CSR_WRITE_4(sc, JME_RXMAC, reg);
2685 jme_set_filter(struct jme_softc *sc)
2687 struct ifnet *ifp = &sc->arpcom.ac_if;
2688 struct ifmultiaddr *ifma;
2693 ASSERT_SERIALIZED(ifp->if_serializer);
2695 rxcfg = CSR_READ_4(sc, JME_RXMAC);
2696 rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
2700 * Always accept frames destined to our station address.
2701 * Always accept broadcast frames.
2703 rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
2705 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2706 if (ifp->if_flags & IFF_PROMISC)
2707 rxcfg |= RXMAC_PROMISC;
2708 if (ifp->if_flags & IFF_ALLMULTI)
2709 rxcfg |= RXMAC_ALLMULTI;
2710 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
2711 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
2712 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2717 * Set up the multicast address filter by passing all multicast
2718 * addresses through a CRC generator, and then using the low-order
2719 * 6 bits as an index into the 64 bit multicast hash table. The
2720 * high order bits select the register, while the rest of the bits
2721 * select the bit within the register.
2723 rxcfg |= RXMAC_MULTICAST;
2724 bzero(mchash, sizeof(mchash));
2726 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2727 if (ifma->ifma_addr->sa_family != AF_LINK)
2729 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2730 ifma->ifma_addr), ETHER_ADDR_LEN);
2732 /* Just want the 6 least significant bits. */
2735 /* Set the corresponding bit in the hash table. */
2736 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2739 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
2740 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
2741 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2745 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
2747 struct jme_softc *sc = arg1;
2748 struct ifnet *ifp = &sc->arpcom.ac_if;
2751 lwkt_serialize_enter(ifp->if_serializer);
2753 v = sc->jme_tx_coal_to;
2754 error = sysctl_handle_int(oidp, &v, 0, req);
2755 if (error || req->newptr == NULL)
2758 if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
2763 if (v != sc->jme_tx_coal_to) {
2764 sc->jme_tx_coal_to = v;
2765 if (ifp->if_flags & IFF_RUNNING)
2766 jme_set_tx_coal(sc);
2769 lwkt_serialize_exit(ifp->if_serializer);
2774 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
2776 struct jme_softc *sc = arg1;
2777 struct ifnet *ifp = &sc->arpcom.ac_if;
2780 lwkt_serialize_enter(ifp->if_serializer);
2782 v = sc->jme_tx_coal_pkt;
2783 error = sysctl_handle_int(oidp, &v, 0, req);
2784 if (error || req->newptr == NULL)
2787 if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
2792 if (v != sc->jme_tx_coal_pkt) {
2793 sc->jme_tx_coal_pkt = v;
2794 if (ifp->if_flags & IFF_RUNNING)
2795 jme_set_tx_coal(sc);
2798 lwkt_serialize_exit(ifp->if_serializer);
2803 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
2805 struct jme_softc *sc = arg1;
2806 struct ifnet *ifp = &sc->arpcom.ac_if;
2809 lwkt_serialize_enter(ifp->if_serializer);
2811 v = sc->jme_rx_coal_to;
2812 error = sysctl_handle_int(oidp, &v, 0, req);
2813 if (error || req->newptr == NULL)
2816 if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
2821 if (v != sc->jme_rx_coal_to) {
2822 sc->jme_rx_coal_to = v;
2823 if (ifp->if_flags & IFF_RUNNING)
2824 jme_set_rx_coal(sc);
2827 lwkt_serialize_exit(ifp->if_serializer);
2832 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
2834 struct jme_softc *sc = arg1;
2835 struct ifnet *ifp = &sc->arpcom.ac_if;
2838 lwkt_serialize_enter(ifp->if_serializer);
2840 v = sc->jme_rx_coal_pkt;
2841 error = sysctl_handle_int(oidp, &v, 0, req);
2842 if (error || req->newptr == NULL)
2845 if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
2850 if (v != sc->jme_rx_coal_pkt) {
2851 sc->jme_rx_coal_pkt = v;
2852 if (ifp->if_flags & IFF_RUNNING)
2853 jme_set_rx_coal(sc);
2856 lwkt_serialize_exit(ifp->if_serializer);
2861 jme_set_tx_coal(struct jme_softc *sc)
2865 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
2867 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
2868 PCCTX_COAL_PKT_MASK;
2869 reg |= PCCTX_COAL_TXQ0;
2870 CSR_WRITE_4(sc, JME_PCCTX, reg);
2874 jme_set_rx_coal(struct jme_softc *sc)
2879 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
2881 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
2882 PCCRX_COAL_PKT_MASK;
2883 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
2884 if (r < sc->jme_rx_ring_inuse)
2885 CSR_WRITE_4(sc, JME_PCCRX(r), reg);
2887 CSR_WRITE_4(sc, JME_PCCRX(r), 0);
2891 #ifdef DEVICE_POLLING
2894 jme_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2896 struct jme_softc *sc = ifp->if_softc;
2897 struct mbuf_chain chain[MAXCPU];
2901 ASSERT_SERIALIZED(ifp->if_serializer);
2905 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2908 case POLL_DEREGISTER:
2909 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2912 case POLL_AND_CHECK_STATUS:
2914 status = CSR_READ_4(sc, JME_INTR_STATUS);
2916 ether_input_chain_init(chain);
2917 for (r = 0; r < sc->jme_rx_ring_inuse; ++r)
2918 prog += jme_rxeof_chain(sc, r, chain, count);
2920 ether_input_dispatch(chain);
2922 if (status & INTR_RXQ_DESC_EMPTY) {
2923 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
2924 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
2925 RXCSR_RX_ENB | RXCSR_RXQ_START);
2929 if (!ifq_is_empty(&ifp->if_snd))
2935 #endif /* DEVICE_POLLING */
2938 jme_rxring_dma_alloc(struct jme_softc *sc, int ring)
2940 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2944 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
2945 JME_RX_RING_ALIGN, 0,
2946 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2947 JME_RX_RING_SIZE(sc),
2948 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
2950 device_printf(sc->jme_dev,
2951 "could not allocate %dth Rx ring.\n", ring);
2954 rdata->jme_rx_ring_tag = dmem.dmem_tag;
2955 rdata->jme_rx_ring_map = dmem.dmem_map;
2956 rdata->jme_rx_ring = dmem.dmem_addr;
2957 rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
2963 jme_rxbuf_dma_alloc(struct jme_softc *sc, int ring)
2965 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2968 /* Create tag for Rx buffers. */
2969 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
2970 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
2971 BUS_SPACE_MAXADDR, /* lowaddr */
2972 BUS_SPACE_MAXADDR, /* highaddr */
2973 NULL, NULL, /* filter, filterarg */
2974 MCLBYTES, /* maxsize */
2976 MCLBYTES, /* maxsegsize */
2977 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
2978 &rdata->jme_rx_tag);
2980 device_printf(sc->jme_dev,
2981 "could not create %dth Rx DMA tag.\n", ring);
2985 /* Create DMA maps for Rx buffers. */
2986 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
2987 &rdata->jme_rx_sparemap);
2989 device_printf(sc->jme_dev,
2990 "could not create %dth spare Rx dmamap.\n", ring);
2991 bus_dma_tag_destroy(rdata->jme_rx_tag);
2992 rdata->jme_rx_tag = NULL;
2995 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
2996 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
2998 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3003 device_printf(sc->jme_dev,
3004 "could not create %dth Rx dmamap "
3005 "for %dth RX ring.\n", i, ring);
3007 for (j = 0; j < i; ++j) {
3008 rxd = &rdata->jme_rxdesc[j];
3009 bus_dmamap_destroy(rdata->jme_rx_tag,
3012 bus_dmamap_destroy(rdata->jme_rx_tag,
3013 rdata->jme_rx_sparemap);
3014 bus_dma_tag_destroy(rdata->jme_rx_tag);
3015 rdata->jme_rx_tag = NULL;
3023 jme_rx_intr(struct jme_softc *sc, uint32_t status)
3025 struct mbuf_chain chain[MAXCPU];
3028 ether_input_chain_init(chain);
3029 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
3030 if (status & jme_rx_status[r].jme_coal)
3031 prog += jme_rxeof_chain(sc, r, chain, -1);
3034 ether_input_dispatch(chain);
3038 jme_enable_rss(struct jme_softc *sc)
3040 uint32_t rssc, key, ind;
3043 sc->jme_rx_ring_inuse = sc->jme_rx_ring_cnt;
3045 rssc = RSSC_HASH_64_ENTRY;
3046 rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP;
3047 rssc |= sc->jme_rx_ring_inuse >> 1;
3048 JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc);
3049 CSR_WRITE_4(sc, JME_RSSC, rssc);
3051 key = 0x6d5a6d5a; /* XXX */
3052 for (i = 0; i < RSSKEY_NREGS; ++i)
3053 CSR_WRITE_4(sc, RSSKEY_REG(i), key);
3056 if (sc->jme_rx_ring_inuse == JME_NRXRING_2) {
3058 } else if (sc->jme_rx_ring_inuse == JME_NRXRING_4) {
3061 panic("%s: invalid # of RX rings (%d)\n",
3062 sc->arpcom.ac_if.if_xname, sc->jme_rx_ring_inuse);
3064 JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind);
3065 for (i = 0; i < RSSTBL_NREGS; ++i)
3066 CSR_WRITE_4(sc, RSSTBL_REG(i), ind);
3070 jme_disable_rss(struct jme_softc *sc)
3072 sc->jme_rx_ring_inuse = JME_NRXRING_1;
3073 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);