2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
28 * $DragonFly: src/sys/dev/netif/jme/if_jme.c,v 1.12 2008/11/26 11:55:18 sephe Exp $
31 #include <sys/param.h>
32 #include <sys/endian.h>
33 #include <sys/kernel.h>
35 #include <sys/interrupt.h>
36 #include <sys/malloc.h>
39 #include <sys/serialize.h>
40 #include <sys/socket.h>
41 #include <sys/sockio.h>
42 #include <sys/sysctl.h>
44 #include <net/ethernet.h>
47 #include <net/if_arp.h>
48 #include <net/if_dl.h>
49 #include <net/if_media.h>
50 #include <net/ifq_var.h>
51 #include <net/vlan/if_vlan_var.h>
52 #include <net/vlan/if_vlan_ether.h>
54 #include <dev/netif/mii_layer/miivar.h>
55 #include <dev/netif/mii_layer/jmphyreg.h>
57 #include <bus/pci/pcireg.h>
58 #include <bus/pci/pcivar.h>
59 #include <bus/pci/pcidevs.h>
61 #include <dev/netif/jme/if_jmereg.h>
62 #include <dev/netif/jme/if_jmevar.h>
64 #include "miibus_if.h"
66 /* Define the following to disable printing Rx errors. */
67 #undef JME_SHOW_ERRORS
69 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
71 static int jme_probe(device_t);
72 static int jme_attach(device_t);
73 static int jme_detach(device_t);
74 static int jme_shutdown(device_t);
75 static int jme_suspend(device_t);
76 static int jme_resume(device_t);
78 static int jme_miibus_readreg(device_t, int, int);
79 static int jme_miibus_writereg(device_t, int, int, int);
80 static void jme_miibus_statchg(device_t);
82 static void jme_init(void *);
83 static int jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
84 static void jme_start(struct ifnet *);
85 static void jme_watchdog(struct ifnet *);
86 static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
87 static int jme_mediachange(struct ifnet *);
89 static void jme_intr(void *);
90 static void jme_txeof(struct jme_softc *);
91 static void jme_rxeof(struct jme_softc *);
93 static int jme_dma_alloc(struct jme_softc *);
94 static void jme_dma_free(struct jme_softc *, int);
95 static void jme_dmamap_ring_cb(void *, bus_dma_segment_t *, int, int);
96 static void jme_dmamap_buf_cb(void *, bus_dma_segment_t *, int,
98 static int jme_init_rx_ring(struct jme_softc *);
99 static void jme_init_tx_ring(struct jme_softc *);
100 static void jme_init_ssb(struct jme_softc *);
101 static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *, int);
102 static int jme_encap(struct jme_softc *, struct mbuf **);
103 static void jme_rxpkt(struct jme_softc *);
105 static void jme_tick(void *);
106 static void jme_stop(struct jme_softc *);
107 static void jme_reset(struct jme_softc *);
108 static void jme_set_vlan(struct jme_softc *);
109 static void jme_set_filter(struct jme_softc *);
110 static void jme_stop_tx(struct jme_softc *);
111 static void jme_stop_rx(struct jme_softc *);
112 static void jme_mac_config(struct jme_softc *);
113 static void jme_reg_macaddr(struct jme_softc *, uint8_t[]);
114 static int jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
115 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
117 static void jme_setwol(struct jme_softc *);
118 static void jme_setlinkspeed(struct jme_softc *);
120 static void jme_set_tx_coal(struct jme_softc *);
121 static void jme_set_rx_coal(struct jme_softc *);
123 static void jme_sysctl_node(struct jme_softc *);
124 static int jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
125 static int jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
126 static int jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
127 static int jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
130 * Devices supported by this driver.
132 static const struct jme_dev {
133 uint16_t jme_vendorid;
134 uint16_t jme_deviceid;
136 const char *jme_name;
138 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
140 "JMicron Inc, JMC250 Gigabit Ethernet" },
141 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
143 "JMicron Inc, JMC260 Fast Ethernet" },
147 static device_method_t jme_methods[] = {
148 /* Device interface. */
149 DEVMETHOD(device_probe, jme_probe),
150 DEVMETHOD(device_attach, jme_attach),
151 DEVMETHOD(device_detach, jme_detach),
152 DEVMETHOD(device_shutdown, jme_shutdown),
153 DEVMETHOD(device_suspend, jme_suspend),
154 DEVMETHOD(device_resume, jme_resume),
157 DEVMETHOD(bus_print_child, bus_generic_print_child),
158 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
161 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
162 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
163 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
168 static driver_t jme_driver = {
171 sizeof(struct jme_softc)
174 static devclass_t jme_devclass;
176 DECLARE_DUMMY_MODULE(if_jme);
177 MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
178 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, 0, 0);
179 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, 0, 0);
181 static int jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
182 static int jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
184 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
185 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
188 * Read a PHY register on the MII of the JMC250.
191 jme_miibus_readreg(device_t dev, int phy, int reg)
193 struct jme_softc *sc = device_get_softc(dev);
197 /* For FPGA version, PHY address 0 should be ignored. */
198 if (sc->jme_caps & JME_CAP_FPGA) {
202 if (sc->jme_phyaddr != phy)
206 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
207 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
209 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
211 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
215 device_printf(sc->jme_dev, "phy read timeout: "
216 "phy %d, reg %d\n", phy, reg);
220 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
224 * Write a PHY register on the MII of the JMC250.
227 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
229 struct jme_softc *sc = device_get_softc(dev);
232 /* For FPGA version, PHY address 0 should be ignored. */
233 if (sc->jme_caps & JME_CAP_FPGA) {
237 if (sc->jme_phyaddr != phy)
241 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
242 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
243 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
245 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
247 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
251 device_printf(sc->jme_dev, "phy write timeout: "
252 "phy %d, reg %d\n", phy, reg);
259 * Callback from MII layer when media changes.
262 jme_miibus_statchg(device_t dev)
264 struct jme_softc *sc = device_get_softc(dev);
265 struct ifnet *ifp = &sc->arpcom.ac_if;
266 struct mii_data *mii;
267 struct jme_txdesc *txd;
271 ASSERT_SERIALIZED(ifp->if_serializer);
273 if ((ifp->if_flags & IFF_RUNNING) == 0)
276 mii = device_get_softc(sc->jme_miibus);
278 sc->jme_flags &= ~JME_FLAG_LINK;
279 if ((mii->mii_media_status & IFM_AVALID) != 0) {
280 switch (IFM_SUBTYPE(mii->mii_media_active)) {
283 sc->jme_flags |= JME_FLAG_LINK;
286 if (sc->jme_caps & JME_CAP_FASTETH)
288 sc->jme_flags |= JME_FLAG_LINK;
296 * Disabling Rx/Tx MACs have a side-effect of resetting
297 * JME_TXNDA/JME_RXNDA register to the first address of
298 * Tx/Rx descriptor address. So driver should reset its
299 * internal procucer/consumer pointer and reclaim any
300 * allocated resources. Note, just saving the value of
301 * JME_TXNDA and JME_RXNDA registers before stopping MAC
302 * and restoring JME_TXNDA/JME_RXNDA register is not
303 * sufficient to make sure correct MAC state because
304 * stopping MAC operation can take a while and hardware
305 * might have updated JME_TXNDA/JME_RXNDA registers
306 * during the stop operation.
309 /* Disable interrupts */
310 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
313 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
315 callout_stop(&sc->jme_tick_ch);
317 /* Stop receiver/transmitter. */
322 if (sc->jme_cdata.jme_rxhead != NULL)
323 m_freem(sc->jme_cdata.jme_rxhead);
324 JME_RXCHAIN_RESET(sc);
327 if (sc->jme_cdata.jme_tx_cnt != 0) {
328 /* Remove queued packets for transmit. */
329 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
330 txd = &sc->jme_cdata.jme_txdesc[i];
331 if (txd->tx_m != NULL) {
333 sc->jme_cdata.jme_tx_tag,
344 * Reuse configured Rx descriptors and reset
345 * procuder/consumer index.
347 sc->jme_cdata.jme_rx_cons = 0;
349 jme_init_tx_ring(sc);
351 /* Initialize shadow status block. */
354 /* Program MAC with resolved speed/duplex/flow-control. */
355 if (sc->jme_flags & JME_FLAG_LINK) {
358 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr);
359 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
361 /* Set Tx ring address to the hardware. */
362 paddr = JME_TX_RING_ADDR(sc, 0);
363 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
364 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
366 /* Set Rx ring address to the hardware. */
367 paddr = JME_RX_RING_ADDR(sc, 0);
368 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
369 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
371 /* Restart receiver/transmitter. */
372 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
374 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
377 ifp->if_flags |= IFF_RUNNING;
378 ifp->if_flags &= ~IFF_OACTIVE;
379 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
381 /* Reenable interrupts. */
382 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
386 * Get the current interface media status.
389 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
391 struct jme_softc *sc = ifp->if_softc;
392 struct mii_data *mii = device_get_softc(sc->jme_miibus);
394 ASSERT_SERIALIZED(ifp->if_serializer);
397 ifmr->ifm_status = mii->mii_media_status;
398 ifmr->ifm_active = mii->mii_media_active;
402 * Set hardware to newly-selected media.
405 jme_mediachange(struct ifnet *ifp)
407 struct jme_softc *sc = ifp->if_softc;
408 struct mii_data *mii = device_get_softc(sc->jme_miibus);
411 ASSERT_SERIALIZED(ifp->if_serializer);
413 if (mii->mii_instance != 0) {
414 struct mii_softc *miisc;
416 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
417 mii_phy_reset(miisc);
419 error = mii_mediachg(mii);
425 jme_probe(device_t dev)
427 const struct jme_dev *sp;
430 vid = pci_get_vendor(dev);
431 did = pci_get_device(dev);
432 for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
433 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
434 struct jme_softc *sc = device_get_softc(dev);
436 sc->jme_caps = sp->jme_caps;
437 device_set_desc(dev, sp->jme_name);
445 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
451 for (i = JME_TIMEOUT; i > 0; i--) {
452 reg = CSR_READ_4(sc, JME_SMBCSR);
453 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
459 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
463 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
464 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
465 for (i = JME_TIMEOUT; i > 0; i--) {
467 reg = CSR_READ_4(sc, JME_SMBINTF);
468 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
473 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
477 reg = CSR_READ_4(sc, JME_SMBINTF);
478 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
484 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
486 uint8_t fup, reg, val;
491 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
492 fup != JME_EEPROM_SIG0)
494 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
495 fup != JME_EEPROM_SIG1)
499 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
501 /* Check for the end of EEPROM descriptor. */
502 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
504 if ((uint8_t)JME_EEPROM_MKDESC(JME_EEPROM_FUNC0,
505 JME_EEPROM_PAGE_BAR1) == fup) {
506 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0)
508 if (reg >= JME_PAR0 &&
509 reg < JME_PAR0 + ETHER_ADDR_LEN) {
510 if (jme_eeprom_read_byte(sc, offset + 2,
513 eaddr[reg - JME_PAR0] = val;
517 /* Try next eeprom descriptor. */
518 offset += JME_EEPROM_DESC_BYTES;
519 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
521 if (match == ETHER_ADDR_LEN)
528 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
532 /* Read station address. */
533 par0 = CSR_READ_4(sc, JME_PAR0);
534 par1 = CSR_READ_4(sc, JME_PAR1);
536 if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
537 device_printf(sc->jme_dev,
538 "generating fake ethernet address.\n");
539 par0 = karc4random();
540 /* Set OUI to JMicron. */
544 eaddr[3] = (par0 >> 16) & 0xff;
545 eaddr[4] = (par0 >> 8) & 0xff;
546 eaddr[5] = par0 & 0xff;
548 eaddr[0] = (par0 >> 0) & 0xFF;
549 eaddr[1] = (par0 >> 8) & 0xFF;
550 eaddr[2] = (par0 >> 16) & 0xFF;
551 eaddr[3] = (par0 >> 24) & 0xFF;
552 eaddr[4] = (par1 >> 0) & 0xFF;
553 eaddr[5] = (par1 >> 8) & 0xFF;
558 jme_attach(device_t dev)
560 struct jme_softc *sc = device_get_softc(dev);
561 struct ifnet *ifp = &sc->arpcom.ac_if;
564 uint8_t pcie_ptr, rev;
566 uint8_t eaddr[ETHER_ADDR_LEN];
568 sc->jme_rx_desc_cnt = roundup(jme_rx_desc_count, JME_NDESC_ALIGN);
569 if (sc->jme_rx_desc_cnt > JME_NDESC_MAX)
570 sc->jme_rx_desc_cnt = JME_NDESC_MAX;
572 sc->jme_tx_desc_cnt = roundup(jme_tx_desc_count, JME_NDESC_ALIGN);
573 if (sc->jme_tx_desc_cnt > JME_NDESC_MAX)
574 sc->jme_tx_desc_cnt = JME_NDESC_MAX;
577 sc->jme_lowaddr = BUS_SPACE_MAXADDR;
579 ifp = &sc->arpcom.ac_if;
580 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
582 callout_init(&sc->jme_tick_ch);
585 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
588 irq = pci_read_config(dev, PCIR_INTLINE, 4);
589 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
591 device_printf(dev, "chip is in D%d power mode "
592 "-- setting to D0\n", pci_get_powerstate(dev));
594 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
596 pci_write_config(dev, PCIR_INTLINE, irq, 4);
597 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
599 #endif /* !BURN_BRIDGE */
601 /* Enable bus mastering */
602 pci_enable_busmaster(dev);
607 * JMC250 supports both memory mapped and I/O register space
608 * access. Because I/O register access should use different
609 * BARs to access registers it's waste of time to use I/O
610 * register spce access. JMC250 uses 16K to map entire memory
613 sc->jme_mem_rid = JME_PCIR_BAR;
614 sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
615 &sc->jme_mem_rid, RF_ACTIVE);
616 if (sc->jme_mem_res == NULL) {
617 device_printf(dev, "can't allocate IO memory\n");
620 sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
621 sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
627 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
629 RF_SHAREABLE | RF_ACTIVE);
630 if (sc->jme_irq_res == NULL) {
631 device_printf(dev, "can't allocate irq\n");
639 reg = CSR_READ_4(sc, JME_CHIPMODE);
640 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
642 sc->jme_caps |= JME_CAP_FPGA;
644 device_printf(dev, "FPGA revision: 0x%04x\n",
645 (reg & CHIPMODE_FPGA_REV_MASK) >>
646 CHIPMODE_FPGA_REV_SHIFT);
650 /* NOTE: FM revision is put in the upper 4 bits */
651 rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
652 rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
654 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
656 did = pci_get_device(dev);
658 case PCI_PRODUCT_JMICRON_JMC250:
659 if (rev == JME_REV1_A2)
660 sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
663 case PCI_PRODUCT_JMICRON_JMC260:
665 sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
669 panic("unknown device id 0x%04x\n", did);
671 if (rev >= JME_REV2) {
672 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
673 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
674 GHC_TXMAC_CLKSRC_1000;
677 /* Reset the ethernet controller. */
680 /* Get station address. */
681 reg = CSR_READ_4(sc, JME_SMBCSR);
682 if (reg & SMBCSR_EEPROM_PRESENT)
683 error = jme_eeprom_macaddr(sc, eaddr);
684 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
685 if (error != 0 && (bootverbose)) {
686 device_printf(dev, "ethernet hardware address "
687 "not found in EEPROM.\n");
689 jme_reg_macaddr(sc, eaddr);
694 * Integrated JR0211 has fixed PHY address whereas FPGA version
695 * requires PHY probing to get correct PHY address.
697 if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
698 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
699 GPREG0_PHY_ADDR_MASK;
701 device_printf(dev, "PHY is at address %d.\n",
708 /* Set max allowable DMA size. */
709 pcie_ptr = pci_get_pciecap_ptr(dev);
713 sc->jme_caps |= JME_CAP_PCIE;
714 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
716 device_printf(dev, "Read request size : %d bytes.\n",
717 128 << ((ctrl >> 12) & 0x07));
718 device_printf(dev, "TLP payload size : %d bytes.\n",
719 128 << ((ctrl >> 5) & 0x07));
721 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
722 case PCIEM_DEVCTL_MAX_READRQ_128:
723 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
725 case PCIEM_DEVCTL_MAX_READRQ_256:
726 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
729 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
732 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
734 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
735 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
739 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
740 sc->jme_caps |= JME_CAP_PMCAP;
748 /* Allocate DMA stuffs */
749 error = jme_dma_alloc(sc);
754 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
755 ifp->if_init = jme_init;
756 ifp->if_ioctl = jme_ioctl;
757 ifp->if_start = jme_start;
758 ifp->if_watchdog = jme_watchdog;
759 ifq_set_maxlen(&ifp->if_snd, sc->jme_tx_desc_cnt - 1);
760 ifq_set_ready(&ifp->if_snd);
762 /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
763 ifp->if_capabilities = IFCAP_HWCSUM |
765 IFCAP_VLAN_HWTAGGING;
766 ifp->if_hwassist = JME_CSUM_FEATURES;
767 ifp->if_capenable = ifp->if_capabilities;
769 /* Set up MII bus. */
770 error = mii_phy_probe(dev, &sc->jme_miibus,
771 jme_mediachange, jme_mediastatus);
773 device_printf(dev, "no PHY found!\n");
778 * Save PHYADDR for FPGA mode PHY.
780 if (sc->jme_caps & JME_CAP_FPGA) {
781 struct mii_data *mii = device_get_softc(sc->jme_miibus);
783 if (mii->mii_instance != 0) {
784 struct mii_softc *miisc;
786 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
787 if (miisc->mii_phy != 0) {
788 sc->jme_phyaddr = miisc->mii_phy;
792 if (sc->jme_phyaddr != 0) {
793 device_printf(sc->jme_dev,
794 "FPGA PHY is at %d\n", sc->jme_phyaddr);
796 jme_miibus_writereg(dev, sc->jme_phyaddr,
797 JMPHY_CONF, JMPHY_CONF_DEFFIFO);
799 /* XXX should we clear JME_WA_EXTFIFO */
804 ether_ifattach(ifp, eaddr, NULL);
806 /* Tell the upper layer(s) we support long frames. */
807 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
809 error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE, jme_intr, sc,
810 &sc->jme_irq_handle, ifp->if_serializer);
812 device_printf(dev, "could not set up interrupt handler.\n");
817 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->jme_irq_res));
818 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
826 jme_detach(device_t dev)
828 struct jme_softc *sc = device_get_softc(dev);
830 if (device_is_attached(dev)) {
831 struct ifnet *ifp = &sc->arpcom.ac_if;
833 lwkt_serialize_enter(ifp->if_serializer);
835 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle);
836 lwkt_serialize_exit(ifp->if_serializer);
841 if (sc->jme_sysctl_tree != NULL)
842 sysctl_ctx_free(&sc->jme_sysctl_ctx);
844 if (sc->jme_miibus != NULL)
845 device_delete_child(dev, sc->jme_miibus);
846 bus_generic_detach(dev);
848 if (sc->jme_irq_res != NULL) {
849 bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
853 if (sc->jme_mem_res != NULL) {
854 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
864 jme_sysctl_node(struct jme_softc *sc)
868 sysctl_ctx_init(&sc->jme_sysctl_ctx);
869 sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
870 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
871 device_get_nameunit(sc->jme_dev),
873 if (sc->jme_sysctl_tree == NULL) {
874 device_printf(sc->jme_dev, "can't add sysctl node\n");
878 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
879 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
880 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
881 sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
883 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
884 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
885 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
886 sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
888 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
889 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
890 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
891 sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
893 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
894 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
895 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
896 sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
898 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
899 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
900 "rx_desc_count", CTLFLAG_RD, &sc->jme_rx_desc_cnt,
902 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
903 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
904 "tx_desc_count", CTLFLAG_RD, &sc->jme_tx_desc_cnt,
908 * Set default coalesce valves
910 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
911 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
912 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
913 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
916 * Adjust coalesce valves, in case that the number of TX/RX
917 * descs are set to small values by users.
919 * NOTE: coal_max will not be zero, since number of descs
920 * must aligned by JME_NDESC_ALIGN (16 currently)
922 coal_max = sc->jme_tx_desc_cnt / 6;
923 if (coal_max < sc->jme_tx_coal_pkt)
924 sc->jme_tx_coal_pkt = coal_max;
926 coal_max = sc->jme_rx_desc_cnt / 4;
927 if (coal_max < sc->jme_rx_coal_pkt)
928 sc->jme_rx_coal_pkt = coal_max;
932 jme_dmamap_ring_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
937 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
938 *((bus_addr_t *)arg) = segs->ds_addr;
942 jme_dmamap_buf_cb(void *xctx, bus_dma_segment_t *segs, int nsegs,
943 bus_size_t mapsz __unused, int error)
945 struct jme_dmamap_ctx *ctx = xctx;
951 if (nsegs > ctx->nsegs) {
957 for (i = 0; i < nsegs; ++i)
958 ctx->segs[i] = segs[i];
962 jme_dma_alloc(struct jme_softc *sc)
964 struct jme_txdesc *txd;
965 struct jme_rxdesc *rxd;
966 bus_addr_t busaddr, lowaddr;
969 sc->jme_cdata.jme_txdesc =
970 kmalloc(sc->jme_tx_desc_cnt * sizeof(struct jme_txdesc),
971 M_DEVBUF, M_WAITOK | M_ZERO);
972 sc->jme_cdata.jme_rxdesc =
973 kmalloc(sc->jme_rx_desc_cnt * sizeof(struct jme_rxdesc),
974 M_DEVBUF, M_WAITOK | M_ZERO);
976 lowaddr = sc->jme_lowaddr;
978 /* Create parent ring tag. */
979 error = bus_dma_tag_create(NULL,/* parent */
980 1, 0, /* algnmnt, boundary */
981 lowaddr, /* lowaddr */
982 BUS_SPACE_MAXADDR, /* highaddr */
983 NULL, NULL, /* filter, filterarg */
984 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
986 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
988 &sc->jme_cdata.jme_ring_tag);
990 device_printf(sc->jme_dev,
991 "could not create parent ring DMA tag.\n");
996 * Create DMA stuffs for TX ring
999 /* Create tag for Tx ring. */
1000 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */
1001 JME_TX_RING_ALIGN, 0, /* algnmnt, boundary */
1002 lowaddr, /* lowaddr */
1003 BUS_SPACE_MAXADDR, /* highaddr */
1004 NULL, NULL, /* filter, filterarg */
1005 JME_TX_RING_SIZE(sc), /* maxsize */
1007 JME_TX_RING_SIZE(sc), /* maxsegsize */
1009 &sc->jme_cdata.jme_tx_ring_tag);
1011 device_printf(sc->jme_dev,
1012 "could not allocate Tx ring DMA tag.\n");
1016 /* Allocate DMA'able memory for TX ring */
1017 error = bus_dmamem_alloc(sc->jme_cdata.jme_tx_ring_tag,
1018 (void **)&sc->jme_rdata.jme_tx_ring,
1019 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1020 &sc->jme_cdata.jme_tx_ring_map);
1022 device_printf(sc->jme_dev,
1023 "could not allocate DMA'able memory for Tx ring.\n");
1024 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1025 sc->jme_cdata.jme_tx_ring_tag = NULL;
1029 /* Load the DMA map for Tx ring. */
1030 error = bus_dmamap_load(sc->jme_cdata.jme_tx_ring_tag,
1031 sc->jme_cdata.jme_tx_ring_map, sc->jme_rdata.jme_tx_ring,
1032 JME_TX_RING_SIZE(sc), jme_dmamap_ring_cb, &busaddr, BUS_DMA_NOWAIT);
1034 device_printf(sc->jme_dev,
1035 "could not load DMA'able memory for Tx ring.\n");
1036 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1037 sc->jme_rdata.jme_tx_ring,
1038 sc->jme_cdata.jme_tx_ring_map);
1039 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1040 sc->jme_cdata.jme_tx_ring_tag = NULL;
1043 sc->jme_rdata.jme_tx_ring_paddr = busaddr;
1046 * Create DMA stuffs for RX ring
1049 /* Create tag for Rx ring. */
1050 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */
1051 JME_RX_RING_ALIGN, 0, /* algnmnt, boundary */
1052 lowaddr, /* lowaddr */
1053 BUS_SPACE_MAXADDR, /* highaddr */
1054 NULL, NULL, /* filter, filterarg */
1055 JME_RX_RING_SIZE(sc), /* maxsize */
1057 JME_RX_RING_SIZE(sc), /* maxsegsize */
1059 &sc->jme_cdata.jme_rx_ring_tag);
1061 device_printf(sc->jme_dev,
1062 "could not allocate Rx ring DMA tag.\n");
1066 /* Allocate DMA'able memory for RX ring */
1067 error = bus_dmamem_alloc(sc->jme_cdata.jme_rx_ring_tag,
1068 (void **)&sc->jme_rdata.jme_rx_ring,
1069 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1070 &sc->jme_cdata.jme_rx_ring_map);
1072 device_printf(sc->jme_dev,
1073 "could not allocate DMA'able memory for Rx ring.\n");
1074 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag);
1075 sc->jme_cdata.jme_rx_ring_tag = NULL;
1079 /* Load the DMA map for Rx ring. */
1080 error = bus_dmamap_load(sc->jme_cdata.jme_rx_ring_tag,
1081 sc->jme_cdata.jme_rx_ring_map, sc->jme_rdata.jme_rx_ring,
1082 JME_RX_RING_SIZE(sc), jme_dmamap_ring_cb, &busaddr, BUS_DMA_NOWAIT);
1084 device_printf(sc->jme_dev,
1085 "could not load DMA'able memory for Rx ring.\n");
1086 bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag,
1087 sc->jme_rdata.jme_rx_ring,
1088 sc->jme_cdata.jme_rx_ring_map);
1089 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag);
1090 sc->jme_cdata.jme_rx_ring_tag = NULL;
1093 sc->jme_rdata.jme_rx_ring_paddr = busaddr;
1095 if (lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1096 bus_addr_t rx_ring_end, tx_ring_end;
1098 /* Tx/Rx descriptor queue should reside within 4GB boundary. */
1099 tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr +
1100 JME_TX_RING_SIZE(sc);
1101 rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr +
1102 JME_RX_RING_SIZE(sc);
1103 if ((JME_ADDR_HI(tx_ring_end) !=
1104 JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) ||
1105 (JME_ADDR_HI(rx_ring_end) !=
1106 JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) {
1107 device_printf(sc->jme_dev, "4GB boundary crossed, "
1108 "switching to 32bit DMA address mode.\n");
1109 jme_dma_free(sc, 0);
1110 /* Limit DMA address space to 32bit and try again. */
1111 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1116 /* Create parent buffer tag. */
1117 error = bus_dma_tag_create(NULL,/* parent */
1118 1, 0, /* algnmnt, boundary */
1119 sc->jme_lowaddr, /* lowaddr */
1120 BUS_SPACE_MAXADDR, /* highaddr */
1121 NULL, NULL, /* filter, filterarg */
1122 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1124 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1126 &sc->jme_cdata.jme_buffer_tag);
1128 device_printf(sc->jme_dev,
1129 "could not create parent buffer DMA tag.\n");
1134 * Create DMA stuffs for shadow status block
1137 /* Create shadow status block tag. */
1138 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1139 JME_SSB_ALIGN, 0, /* algnmnt, boundary */
1140 sc->jme_lowaddr, /* lowaddr */
1141 BUS_SPACE_MAXADDR, /* highaddr */
1142 NULL, NULL, /* filter, filterarg */
1143 JME_SSB_SIZE, /* maxsize */
1145 JME_SSB_SIZE, /* maxsegsize */
1147 &sc->jme_cdata.jme_ssb_tag);
1149 device_printf(sc->jme_dev,
1150 "could not create shared status block DMA tag.\n");
1154 /* Allocate DMA'able memory for shared status block. */
1155 error = bus_dmamem_alloc(sc->jme_cdata.jme_ssb_tag,
1156 (void **)&sc->jme_rdata.jme_ssb_block,
1157 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1158 &sc->jme_cdata.jme_ssb_map);
1160 device_printf(sc->jme_dev, "could not allocate DMA'able "
1161 "memory for shared status block.\n");
1162 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1163 sc->jme_cdata.jme_ssb_tag = NULL;
1167 /* Load the DMA map for shared status block */
1168 error = bus_dmamap_load(sc->jme_cdata.jme_ssb_tag,
1169 sc->jme_cdata.jme_ssb_map, sc->jme_rdata.jme_ssb_block,
1170 JME_SSB_SIZE, jme_dmamap_ring_cb, &busaddr, BUS_DMA_NOWAIT);
1172 device_printf(sc->jme_dev, "could not load DMA'able memory "
1173 "for shared status block.\n");
1174 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1175 sc->jme_rdata.jme_ssb_block,
1176 sc->jme_cdata.jme_ssb_map);
1177 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1178 sc->jme_cdata.jme_ssb_tag = NULL;
1181 sc->jme_rdata.jme_ssb_block_paddr = busaddr;
1184 * Create DMA stuffs for TX buffers
1187 /* Create tag for Tx buffers. */
1188 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1189 1, 0, /* algnmnt, boundary */
1190 sc->jme_lowaddr, /* lowaddr */
1191 BUS_SPACE_MAXADDR, /* highaddr */
1192 NULL, NULL, /* filter, filterarg */
1193 JME_TSO_MAXSIZE, /* maxsize */
1194 JME_MAXTXSEGS, /* nsegments */
1195 JME_TSO_MAXSEGSIZE, /* maxsegsize */
1197 &sc->jme_cdata.jme_tx_tag);
1199 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1203 /* Create DMA maps for Tx buffers. */
1204 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
1205 txd = &sc->jme_cdata.jme_txdesc[i];
1206 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag, 0,
1211 device_printf(sc->jme_dev,
1212 "could not create %dth Tx dmamap.\n", i);
1214 for (j = 0; j < i; ++j) {
1215 txd = &sc->jme_cdata.jme_txdesc[j];
1216 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1219 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1220 sc->jme_cdata.jme_tx_tag = NULL;
1226 * Create DMA stuffs for RX buffers
1229 /* Create tag for Rx buffers. */
1230 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1231 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
1232 sc->jme_lowaddr, /* lowaddr */
1233 BUS_SPACE_MAXADDR, /* highaddr */
1234 NULL, NULL, /* filter, filterarg */
1235 MCLBYTES, /* maxsize */
1237 MCLBYTES, /* maxsegsize */
1239 &sc->jme_cdata.jme_rx_tag);
1241 device_printf(sc->jme_dev, "could not create Rx DMA tag.\n");
1245 /* Create DMA maps for Rx buffers. */
1246 error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0,
1247 &sc->jme_cdata.jme_rx_sparemap);
1249 device_printf(sc->jme_dev,
1250 "could not create spare Rx dmamap.\n");
1251 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag);
1252 sc->jme_cdata.jme_rx_tag = NULL;
1255 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
1256 rxd = &sc->jme_cdata.jme_rxdesc[i];
1257 error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0,
1262 device_printf(sc->jme_dev,
1263 "could not create %dth Rx dmamap.\n", i);
1265 for (j = 0; j < i; ++j) {
1266 rxd = &sc->jme_cdata.jme_rxdesc[j];
1267 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1270 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1271 sc->jme_cdata.jme_rx_sparemap);
1272 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag);
1273 sc->jme_cdata.jme_rx_tag = NULL;
1281 jme_dma_free(struct jme_softc *sc, int detach)
1283 struct jme_txdesc *txd;
1284 struct jme_rxdesc *rxd;
1288 if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1289 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1290 sc->jme_cdata.jme_tx_ring_map);
1291 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1292 sc->jme_rdata.jme_tx_ring,
1293 sc->jme_cdata.jme_tx_ring_map);
1294 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1295 sc->jme_cdata.jme_tx_ring_tag = NULL;
1299 if (sc->jme_cdata.jme_rx_ring_tag != NULL) {
1300 bus_dmamap_unload(sc->jme_cdata.jme_rx_ring_tag,
1301 sc->jme_cdata.jme_rx_ring_map);
1302 bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag,
1303 sc->jme_rdata.jme_rx_ring,
1304 sc->jme_cdata.jme_rx_ring_map);
1305 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag);
1306 sc->jme_cdata.jme_rx_ring_tag = NULL;
1310 if (sc->jme_cdata.jme_tx_tag != NULL) {
1311 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
1312 txd = &sc->jme_cdata.jme_txdesc[i];
1313 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1316 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1317 sc->jme_cdata.jme_tx_tag = NULL;
1321 if (sc->jme_cdata.jme_rx_tag != NULL) {
1322 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
1323 rxd = &sc->jme_cdata.jme_rxdesc[i];
1324 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1327 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1328 sc->jme_cdata.jme_rx_sparemap);
1329 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag);
1330 sc->jme_cdata.jme_rx_tag = NULL;
1333 /* Shadow status block. */
1334 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1335 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1336 sc->jme_cdata.jme_ssb_map);
1337 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1338 sc->jme_rdata.jme_ssb_block,
1339 sc->jme_cdata.jme_ssb_map);
1340 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1341 sc->jme_cdata.jme_ssb_tag = NULL;
1344 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1345 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1346 sc->jme_cdata.jme_buffer_tag = NULL;
1348 if (sc->jme_cdata.jme_ring_tag != NULL) {
1349 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1350 sc->jme_cdata.jme_ring_tag = NULL;
1354 if (sc->jme_cdata.jme_txdesc != NULL) {
1355 kfree(sc->jme_cdata.jme_txdesc, M_DEVBUF);
1356 sc->jme_cdata.jme_txdesc = NULL;
1358 if (sc->jme_cdata.jme_rxdesc != NULL) {
1359 kfree(sc->jme_cdata.jme_rxdesc, M_DEVBUF);
1360 sc->jme_cdata.jme_rxdesc = NULL;
1366 * Make sure the interface is stopped at reboot time.
1369 jme_shutdown(device_t dev)
1371 return jme_suspend(dev);
1376 * Unlike other ethernet controllers, JMC250 requires
1377 * explicit resetting link speed to 10/100Mbps as gigabit
1378 * link will cunsume more power than 375mA.
1379 * Note, we reset the link speed to 10/100Mbps with
1380 * auto-negotiation but we don't know whether that operation
1381 * would succeed or not as we have no control after powering
1382 * off. If the renegotiation fail WOL may not work. Running
1383 * at 1Gbps draws more power than 375mA at 3.3V which is
1384 * specified in PCI specification and that would result in
1385 * complete shutdowning power to ethernet controller.
1388 * Save current negotiated media speed/duplex/flow-control
1389 * to softc and restore the same link again after resuming.
1390 * PHY handling such as power down/resetting to 100Mbps
1391 * may be better handled in suspend method in phy driver.
1394 jme_setlinkspeed(struct jme_softc *sc)
1396 struct mii_data *mii;
1399 JME_LOCK_ASSERT(sc);
1401 mii = device_get_softc(sc->jme_miibus);
1404 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1405 switch IFM_SUBTYPE(mii->mii_media_active) {
1415 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1416 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1417 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1418 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1419 BMCR_AUTOEN | BMCR_STARTNEG);
1422 /* Poll link state until jme(4) get a 10/100 link. */
1423 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1425 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1426 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1436 pause("jmelnk", hz);
1439 if (i == MII_ANEGTICKS_GIGE)
1440 device_printf(sc->jme_dev, "establishing link failed, "
1441 "WOL may not work!");
1444 * No link, force MAC to have 100Mbps, full-duplex link.
1445 * This is the last resort and may/may not work.
1447 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1448 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1453 jme_setwol(struct jme_softc *sc)
1455 struct ifnet *ifp = &sc->arpcom.ac_if;
1460 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1461 /* No PME capability, PHY power down. */
1462 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1463 MII_BMCR, BMCR_PDOWN);
1467 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1468 pmcs = CSR_READ_4(sc, JME_PMCS);
1469 pmcs &= ~PMCS_WOL_ENB_MASK;
1470 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1471 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1472 /* Enable PME message. */
1473 gpr |= GPREG0_PME_ENB;
1474 /* For gigabit controllers, reset link speed to 10/100. */
1475 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
1476 jme_setlinkspeed(sc);
1479 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1480 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1483 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1484 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1485 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1486 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1487 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1488 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1489 /* No WOL, PHY power down. */
1490 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1491 MII_BMCR, BMCR_PDOWN);
1497 jme_suspend(device_t dev)
1499 struct jme_softc *sc = device_get_softc(dev);
1500 struct ifnet *ifp = &sc->arpcom.ac_if;
1502 lwkt_serialize_enter(ifp->if_serializer);
1507 lwkt_serialize_exit(ifp->if_serializer);
1513 jme_resume(device_t dev)
1515 struct jme_softc *sc = device_get_softc(dev);
1516 struct ifnet *ifp = &sc->arpcom.ac_if;
1521 lwkt_serialize_enter(ifp->if_serializer);
1524 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1527 pmstat = pci_read_config(sc->jme_dev,
1528 pmc + PCIR_POWER_STATUS, 2);
1529 /* Disable PME clear PME status. */
1530 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1531 pci_write_config(sc->jme_dev,
1532 pmc + PCIR_POWER_STATUS, pmstat, 2);
1536 if (ifp->if_flags & IFF_UP)
1539 lwkt_serialize_exit(ifp->if_serializer);
1545 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1547 struct jme_txdesc *txd;
1548 struct jme_desc *desc;
1550 struct jme_dmamap_ctx ctx;
1551 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1554 uint32_t cflags, flag64;
1556 M_ASSERTPKTHDR((*m_head));
1558 prod = sc->jme_cdata.jme_tx_prod;
1559 txd = &sc->jme_cdata.jme_txdesc[prod];
1561 maxsegs = (sc->jme_tx_desc_cnt - sc->jme_cdata.jme_tx_cnt) -
1563 if (maxsegs > JME_MAXTXSEGS)
1564 maxsegs = JME_MAXTXSEGS;
1565 KASSERT(maxsegs >= (sc->jme_txd_spare - 1),
1566 ("not enough segments %d\n", maxsegs));
1568 ctx.nsegs = maxsegs;
1570 error = bus_dmamap_load_mbuf(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1571 *m_head, jme_dmamap_buf_cb, &ctx,
1573 if (!error && ctx.nsegs == 0) {
1574 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
1577 if (error == EFBIG) {
1578 m = m_defrag(*m_head, MB_DONTWAIT);
1580 if_printf(&sc->arpcom.ac_if,
1581 "could not defrag TX mbuf\n");
1588 ctx.nsegs = maxsegs;
1590 error = bus_dmamap_load_mbuf(sc->jme_cdata.jme_tx_tag,
1591 txd->tx_dmamap, *m_head,
1592 jme_dmamap_buf_cb, &ctx,
1594 if (error || ctx.nsegs == 0) {
1595 if_printf(&sc->arpcom.ac_if,
1596 "could not load defragged TX mbuf\n");
1598 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
1607 if_printf(&sc->arpcom.ac_if, "could not load TX mbuf\n");
1614 /* Configure checksum offload. */
1615 if (m->m_pkthdr.csum_flags & CSUM_IP)
1616 cflags |= JME_TD_IPCSUM;
1617 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1618 cflags |= JME_TD_TCPCSUM;
1619 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1620 cflags |= JME_TD_UDPCSUM;
1622 /* Configure VLAN. */
1623 if (m->m_flags & M_VLANTAG) {
1624 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1625 cflags |= JME_TD_VLAN_TAG;
1628 desc = &sc->jme_rdata.jme_tx_ring[prod];
1629 desc->flags = htole32(cflags);
1630 desc->addr_hi = htole32(m->m_pkthdr.len);
1631 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1633 * Use 64bits TX desc chain format.
1635 * The first TX desc of the chain, which is setup here,
1636 * is just a symbol TX desc carrying no payload.
1638 flag64 = JME_TD_64BIT;
1642 /* No effective TX desc is consumed */
1646 * Use 32bits TX desc chain format.
1648 * The first TX desc of the chain, which is setup here,
1649 * is an effective TX desc carrying the first segment of
1653 desc->buflen = htole32(txsegs[0].ds_len);
1654 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1656 /* One effective TX desc is consumed */
1659 sc->jme_cdata.jme_tx_cnt++;
1660 KKASSERT(sc->jme_cdata.jme_tx_cnt < sc->jme_tx_desc_cnt - JME_TXD_RSVD);
1661 JME_DESC_INC(prod, sc->jme_tx_desc_cnt);
1663 txd->tx_ndesc = 1 - i;
1664 for (; i < ctx.nsegs; i++) {
1665 desc = &sc->jme_rdata.jme_tx_ring[prod];
1666 desc->flags = htole32(JME_TD_OWN | flag64);
1667 desc->buflen = htole32(txsegs[i].ds_len);
1668 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1669 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1671 sc->jme_cdata.jme_tx_cnt++;
1672 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
1673 sc->jme_tx_desc_cnt - JME_TXD_RSVD);
1674 JME_DESC_INC(prod, sc->jme_tx_desc_cnt);
1677 /* Update producer index. */
1678 sc->jme_cdata.jme_tx_prod = prod;
1680 * Finally request interrupt and give the first descriptor
1681 * owenership to hardware.
1683 desc = txd->tx_desc;
1684 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1687 txd->tx_ndesc += ctx.nsegs;
1689 /* Sync descriptors. */
1690 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1691 BUS_DMASYNC_PREWRITE);
1692 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
1693 sc->jme_cdata.jme_tx_ring_map, BUS_DMASYNC_PREWRITE);
1698 jme_start(struct ifnet *ifp)
1700 struct jme_softc *sc = ifp->if_softc;
1701 struct mbuf *m_head;
1704 ASSERT_SERIALIZED(ifp->if_serializer);
1706 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1707 ifq_purge(&ifp->if_snd);
1711 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1714 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT(sc))
1717 while (!ifq_is_empty(&ifp->if_snd)) {
1719 * Check number of available TX descs, always
1720 * leave JME_TXD_RSVD free TX descs.
1722 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare >
1723 sc->jme_tx_desc_cnt - JME_TXD_RSVD) {
1724 ifp->if_flags |= IFF_OACTIVE;
1728 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1733 * Pack the data into the transmit ring. If we
1734 * don't have room, set the OACTIVE flag and wait
1735 * for the NIC to drain the ring.
1737 if (jme_encap(sc, &m_head)) {
1738 if (m_head == NULL) {
1742 ifq_prepend(&ifp->if_snd, m_head);
1743 ifp->if_flags |= IFF_OACTIVE;
1749 * If there's a BPF listener, bounce a copy of this frame
1752 ETHER_BPF_MTAP(ifp, m_head);
1757 * Reading TXCSR takes very long time under heavy load
1758 * so cache TXCSR value and writes the ORed value with
1759 * the kick command to the TXCSR. This saves one register
1762 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1763 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1764 /* Set a timeout in case the chip goes out to lunch. */
1765 ifp->if_timer = JME_TX_TIMEOUT;
1770 jme_watchdog(struct ifnet *ifp)
1772 struct jme_softc *sc = ifp->if_softc;
1774 ASSERT_SERIALIZED(ifp->if_serializer);
1776 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1777 if_printf(ifp, "watchdog timeout (missed link)\n");
1784 if (sc->jme_cdata.jme_tx_cnt == 0) {
1785 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1787 if (!ifq_is_empty(&ifp->if_snd))
1792 if_printf(ifp, "watchdog timeout\n");
1795 if (!ifq_is_empty(&ifp->if_snd))
1800 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1802 struct jme_softc *sc = ifp->if_softc;
1803 struct mii_data *mii = device_get_softc(sc->jme_miibus);
1804 struct ifreq *ifr = (struct ifreq *)data;
1805 int error = 0, mask;
1807 ASSERT_SERIALIZED(ifp->if_serializer);
1811 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1812 (!(sc->jme_caps & JME_CAP_JUMBO) &&
1813 ifr->ifr_mtu > JME_MAX_MTU)) {
1818 if (ifp->if_mtu != ifr->ifr_mtu) {
1820 * No special configuration is required when interface
1821 * MTU is changed but availability of Tx checksum
1822 * offload should be chcked against new MTU size as
1823 * FIFO size is just 2K.
1825 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1826 ifp->if_capenable &= ~IFCAP_TXCSUM;
1827 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1829 ifp->if_mtu = ifr->ifr_mtu;
1830 if (ifp->if_flags & IFF_RUNNING)
1836 if (ifp->if_flags & IFF_UP) {
1837 if (ifp->if_flags & IFF_RUNNING) {
1838 if ((ifp->if_flags ^ sc->jme_if_flags) &
1839 (IFF_PROMISC | IFF_ALLMULTI))
1845 if (ifp->if_flags & IFF_RUNNING)
1848 sc->jme_if_flags = ifp->if_flags;
1853 if (ifp->if_flags & IFF_RUNNING)
1859 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1863 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1865 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1866 if (IFCAP_TXCSUM & ifp->if_capabilities) {
1867 ifp->if_capenable ^= IFCAP_TXCSUM;
1868 if (IFCAP_TXCSUM & ifp->if_capenable)
1869 ifp->if_hwassist |= JME_CSUM_FEATURES;
1871 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1874 if ((mask & IFCAP_RXCSUM) &&
1875 (IFCAP_RXCSUM & ifp->if_capabilities)) {
1878 ifp->if_capenable ^= IFCAP_RXCSUM;
1879 reg = CSR_READ_4(sc, JME_RXMAC);
1880 reg &= ~RXMAC_CSUM_ENB;
1881 if (ifp->if_capenable & IFCAP_RXCSUM)
1882 reg |= RXMAC_CSUM_ENB;
1883 CSR_WRITE_4(sc, JME_RXMAC, reg);
1886 if ((mask & IFCAP_VLAN_HWTAGGING) &&
1887 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities)) {
1888 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1894 error = ether_ioctl(ifp, cmd, data);
1901 jme_mac_config(struct jme_softc *sc)
1903 struct mii_data *mii;
1904 uint32_t ghc, rxmac, txmac, txpause, gp1;
1905 int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
1907 mii = device_get_softc(sc->jme_miibus);
1909 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1911 CSR_WRITE_4(sc, JME_GHC, 0);
1913 rxmac = CSR_READ_4(sc, JME_RXMAC);
1914 rxmac &= ~RXMAC_FC_ENB;
1915 txmac = CSR_READ_4(sc, JME_TXMAC);
1916 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1917 txpause = CSR_READ_4(sc, JME_TXPFC);
1918 txpause &= ~TXPFC_PAUSE_ENB;
1919 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1920 ghc |= GHC_FULL_DUPLEX;
1921 rxmac &= ~RXMAC_COLL_DET_ENB;
1922 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1923 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1926 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1927 txpause |= TXPFC_PAUSE_ENB;
1928 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1929 rxmac |= RXMAC_FC_ENB;
1931 /* Disable retry transmit timer/retry limit. */
1932 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1933 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1935 rxmac |= RXMAC_COLL_DET_ENB;
1936 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1937 /* Enable retry transmit timer/retry limit. */
1938 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1939 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1943 * Reprogram Tx/Rx MACs with resolved speed/duplex.
1945 gp1 = CSR_READ_4(sc, JME_GPREG1);
1946 gp1 &= ~GPREG1_WA_HDX;
1948 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1951 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1953 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
1955 gp1 |= GPREG1_WA_HDX;
1959 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
1961 gp1 |= GPREG1_WA_HDX;
1964 * Use extended FIFO depth to workaround CRC errors
1965 * emitted by chips before JMC250B
1967 phyconf = JMPHY_CONF_EXTFIFO;
1971 if (sc->jme_caps & JME_CAP_FASTETH)
1974 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
1976 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1982 CSR_WRITE_4(sc, JME_GHC, ghc);
1983 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1984 CSR_WRITE_4(sc, JME_TXMAC, txmac);
1985 CSR_WRITE_4(sc, JME_TXPFC, txpause);
1987 if (sc->jme_workaround & JME_WA_EXTFIFO) {
1988 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1989 JMPHY_CONF, phyconf);
1991 if (sc->jme_workaround & JME_WA_HDX)
1992 CSR_WRITE_4(sc, JME_GPREG1, gp1);
1998 struct jme_softc *sc = xsc;
1999 struct ifnet *ifp = &sc->arpcom.ac_if;
2002 ASSERT_SERIALIZED(ifp->if_serializer);
2004 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
2005 if (status == 0 || status == 0xFFFFFFFF)
2008 /* Disable interrupts. */
2009 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2011 status = CSR_READ_4(sc, JME_INTR_STATUS);
2012 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
2015 /* Reset PCC counter/timer and Ack interrupts. */
2016 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
2017 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
2018 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
2019 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
2020 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP;
2021 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
2023 if (ifp->if_flags & IFF_RUNNING) {
2024 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
2027 if (status & INTR_RXQ_DESC_EMPTY) {
2029 * Notify hardware availability of new Rx buffers.
2030 * Reading RXCSR takes very long time under heavy
2031 * load so cache RXCSR value and writes the ORed
2032 * value with the kick command to the RXCSR. This
2033 * saves one register access cycle.
2035 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
2036 RXCSR_RX_ENB | RXCSR_RXQ_START);
2039 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
2041 if (!ifq_is_empty(&ifp->if_snd))
2046 /* Reenable interrupts. */
2047 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2051 jme_txeof(struct jme_softc *sc)
2053 struct ifnet *ifp = &sc->arpcom.ac_if;
2054 struct jme_txdesc *txd;
2058 cons = sc->jme_cdata.jme_tx_cons;
2059 if (cons == sc->jme_cdata.jme_tx_prod)
2062 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2063 sc->jme_cdata.jme_tx_ring_map,
2064 BUS_DMASYNC_POSTREAD);
2067 * Go through our Tx list and free mbufs for those
2068 * frames which have been transmitted.
2070 while (cons != sc->jme_cdata.jme_tx_prod) {
2071 txd = &sc->jme_cdata.jme_txdesc[cons];
2072 KASSERT(txd->tx_m != NULL,
2073 ("%s: freeing NULL mbuf!\n", __func__));
2075 status = le32toh(txd->tx_desc->flags);
2076 if ((status & JME_TD_OWN) == JME_TD_OWN)
2079 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
2083 if (status & JME_TD_COLLISION) {
2084 ifp->if_collisions +=
2085 le32toh(txd->tx_desc->buflen) &
2086 JME_TD_BUF_LEN_MASK;
2091 * Only the first descriptor of multi-descriptor
2092 * transmission is updated so driver have to skip entire
2093 * chained buffers for the transmiited frame. In other
2094 * words, JME_TD_OWN bit is valid only at the first
2095 * descriptor of a multi-descriptor transmission.
2097 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2098 sc->jme_rdata.jme_tx_ring[cons].flags = 0;
2099 JME_DESC_INC(cons, sc->jme_tx_desc_cnt);
2102 /* Reclaim transferred mbufs. */
2103 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2106 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2107 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2108 ("%s: Active Tx desc counter was garbled\n", __func__));
2111 sc->jme_cdata.jme_tx_cons = cons;
2113 if (sc->jme_cdata.jme_tx_cnt == 0)
2116 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare <=
2117 sc->jme_tx_desc_cnt - JME_TXD_RSVD)
2118 ifp->if_flags &= ~IFF_OACTIVE;
2120 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2121 sc->jme_cdata.jme_tx_ring_map,
2122 BUS_DMASYNC_PREWRITE);
2125 static __inline void
2126 jme_discard_rxbufs(struct jme_softc *sc, int cons, int count)
2130 for (i = 0; i < count; ++i) {
2131 struct jme_desc *desc = &sc->jme_rdata.jme_rx_ring[cons];
2133 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2134 desc->buflen = htole32(MCLBYTES);
2135 JME_DESC_INC(cons, sc->jme_rx_desc_cnt);
2139 /* Receive a frame. */
2141 jme_rxpkt(struct jme_softc *sc)
2143 struct ifnet *ifp = &sc->arpcom.ac_if;
2144 struct jme_desc *desc;
2145 struct jme_rxdesc *rxd;
2146 struct mbuf *mp, *m;
2147 uint32_t flags, status;
2148 int cons, count, nsegs;
2150 cons = sc->jme_cdata.jme_rx_cons;
2151 desc = &sc->jme_rdata.jme_rx_ring[cons];
2152 flags = le32toh(desc->flags);
2153 status = le32toh(desc->buflen);
2154 nsegs = JME_RX_NSEGS(status);
2156 if (status & JME_RX_ERR_STAT) {
2158 jme_discard_rxbufs(sc, cons, nsegs);
2159 #ifdef JME_SHOW_ERRORS
2160 device_printf(sc->jme_dev, "%s : receive error = 0x%b\n",
2161 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2163 sc->jme_cdata.jme_rx_cons += nsegs;
2164 sc->jme_cdata.jme_rx_cons %= sc->jme_rx_desc_cnt;
2168 sc->jme_cdata.jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2169 for (count = 0; count < nsegs; count++,
2170 JME_DESC_INC(cons, sc->jme_rx_desc_cnt)) {
2171 rxd = &sc->jme_cdata.jme_rxdesc[cons];
2174 /* Add a new receive buffer to the ring. */
2175 if (jme_newbuf(sc, rxd, 0) != 0) {
2178 jme_discard_rxbufs(sc, cons, nsegs - count);
2179 if (sc->jme_cdata.jme_rxhead != NULL) {
2180 m_freem(sc->jme_cdata.jme_rxhead);
2181 JME_RXCHAIN_RESET(sc);
2187 * Assume we've received a full sized frame.
2188 * Actual size is fixed when we encounter the end of
2189 * multi-segmented frame.
2191 mp->m_len = MCLBYTES;
2193 /* Chain received mbufs. */
2194 if (sc->jme_cdata.jme_rxhead == NULL) {
2195 sc->jme_cdata.jme_rxhead = mp;
2196 sc->jme_cdata.jme_rxtail = mp;
2199 * Receive processor can receive a maximum frame
2200 * size of 65535 bytes.
2202 mp->m_flags &= ~M_PKTHDR;
2203 sc->jme_cdata.jme_rxtail->m_next = mp;
2204 sc->jme_cdata.jme_rxtail = mp;
2207 if (count == nsegs - 1) {
2208 /* Last desc. for this frame. */
2209 m = sc->jme_cdata.jme_rxhead;
2210 /* XXX assert PKTHDR? */
2211 m->m_flags |= M_PKTHDR;
2212 m->m_pkthdr.len = sc->jme_cdata.jme_rxlen;
2214 /* Set first mbuf size. */
2215 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2216 /* Set last mbuf size. */
2217 mp->m_len = sc->jme_cdata.jme_rxlen -
2218 ((MCLBYTES - JME_RX_PAD_BYTES) +
2219 (MCLBYTES * (nsegs - 2)));
2221 m->m_len = sc->jme_cdata.jme_rxlen;
2223 m->m_pkthdr.rcvif = ifp;
2226 * Account for 10bytes auto padding which is used
2227 * to align IP header on 32bit boundary. Also note,
2228 * CRC bytes is automatically removed by the
2231 m->m_data += JME_RX_PAD_BYTES;
2233 /* Set checksum information. */
2234 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2235 (flags & JME_RD_IPV4)) {
2236 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2237 if (flags & JME_RD_IPCSUM)
2238 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2239 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2240 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2241 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2242 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2243 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2244 m->m_pkthdr.csum_flags |=
2245 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2246 m->m_pkthdr.csum_data = 0xffff;
2250 /* Check for VLAN tagged packets. */
2251 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2252 (flags & JME_RD_VLAN_TAG)) {
2253 m->m_pkthdr.ether_vlantag =
2254 flags & JME_RD_VLAN_MASK;
2255 m->m_flags |= M_VLANTAG;
2260 ifp->if_input(ifp, m);
2262 /* Reset mbuf chains. */
2263 JME_RXCHAIN_RESET(sc);
2267 sc->jme_cdata.jme_rx_cons += nsegs;
2268 sc->jme_cdata.jme_rx_cons %= sc->jme_rx_desc_cnt;
2272 jme_rxeof(struct jme_softc *sc)
2274 struct jme_desc *desc;
2275 int nsegs, prog, pktlen;
2277 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2278 sc->jme_cdata.jme_rx_ring_map,
2279 BUS_DMASYNC_POSTREAD);
2283 desc = &sc->jme_rdata.jme_rx_ring[sc->jme_cdata.jme_rx_cons];
2284 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2286 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2290 * Check number of segments against received bytes.
2291 * Non-matching value would indicate that hardware
2292 * is still trying to update Rx descriptors. I'm not
2293 * sure whether this check is needed.
2295 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2296 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2297 if (nsegs != howmany(pktlen, MCLBYTES)) {
2298 if_printf(&sc->arpcom.ac_if, "RX fragment count(%d) "
2299 "and packet size(%d) mismach\n",
2304 /* Received a frame. */
2310 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2311 sc->jme_cdata.jme_rx_ring_map,
2312 BUS_DMASYNC_PREWRITE);
2319 struct jme_softc *sc = xsc;
2320 struct ifnet *ifp = &sc->arpcom.ac_if;
2321 struct mii_data *mii = device_get_softc(sc->jme_miibus);
2323 lwkt_serialize_enter(ifp->if_serializer);
2326 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2328 lwkt_serialize_exit(ifp->if_serializer);
2332 jme_reset(struct jme_softc *sc)
2335 /* Stop receiver, transmitter. */
2339 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2341 CSR_WRITE_4(sc, JME_GHC, 0);
2347 struct jme_softc *sc = xsc;
2348 struct ifnet *ifp = &sc->arpcom.ac_if;
2349 struct mii_data *mii;
2350 uint8_t eaddr[ETHER_ADDR_LEN];
2355 ASSERT_SERIALIZED(ifp->if_serializer);
2358 * Cancel any pending I/O.
2363 * Reset the chip to a known state.
2368 * Since we always use 64bit address mode for transmitting,
2369 * each Tx request requires one more dummy descriptor.
2372 howmany(ifp->if_mtu + sizeof(struct ether_vlan_header), MCLBYTES) + 1;
2373 KKASSERT(sc->jme_txd_spare >= 2);
2375 /* Init descriptors. */
2376 error = jme_init_rx_ring(sc);
2378 device_printf(sc->jme_dev,
2379 "%s: initialization failed: no memory for Rx buffers.\n",
2384 jme_init_tx_ring(sc);
2386 /* Initialize shadow status block. */
2389 /* Reprogram the station address. */
2390 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2391 CSR_WRITE_4(sc, JME_PAR0,
2392 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2393 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2396 * Configure Tx queue.
2397 * Tx priority queue weight value : 0
2398 * Tx FIFO threshold for processing next packet : 16QW
2399 * Maximum Tx DMA length : 512
2400 * Allow Tx DMA burst.
2402 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2403 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2404 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2405 sc->jme_txcsr |= sc->jme_tx_dma_size;
2406 sc->jme_txcsr |= TXCSR_DMA_BURST;
2407 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2409 /* Set Tx descriptor counter. */
2410 CSR_WRITE_4(sc, JME_TXQDC, sc->jme_tx_desc_cnt);
2412 /* Set Tx ring address to the hardware. */
2413 paddr = JME_TX_RING_ADDR(sc, 0);
2414 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2415 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2417 /* Configure TxMAC parameters. */
2418 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2419 reg |= TXMAC_THRESH_1_PKT;
2420 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2421 CSR_WRITE_4(sc, JME_TXMAC, reg);
2424 * Configure Rx queue.
2425 * FIFO full threshold for transmitting Tx pause packet : 128T
2426 * FIFO threshold for processing next packet : 128QW
2428 * Max Rx DMA length : 128
2429 * Rx descriptor retry : 32
2430 * Rx descriptor retry time gap : 256ns
2431 * Don't receive runt/bad frame.
2433 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2435 * Since Rx FIFO size is 4K bytes, receiving frames larger
2436 * than 4K bytes will suffer from Rx FIFO overruns. So
2437 * decrease FIFO threshold to reduce the FIFO overruns for
2438 * frames larger than 4000 bytes.
2439 * For best performance of standard MTU sized frames use
2440 * maximum allowable FIFO threshold, 128QW.
2442 if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2444 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2446 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2447 sc->jme_rxcsr |= sc->jme_rx_dma_size | RXCSR_RXQ_N_SEL(RXCSR_RXQ0);
2448 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2449 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2450 /* XXX TODO DROP_BAD */
2451 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr);
2453 /* Set Rx descriptor counter. */
2454 CSR_WRITE_4(sc, JME_RXQDC, sc->jme_rx_desc_cnt);
2456 /* Set Rx ring address to the hardware. */
2457 paddr = JME_RX_RING_ADDR(sc, 0);
2458 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2459 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2461 /* Clear receive filter. */
2462 CSR_WRITE_4(sc, JME_RXMAC, 0);
2464 /* Set up the receive filter. */
2469 * Disable all WOL bits as WOL can interfere normal Rx
2470 * operation. Also clear WOL detection status bits.
2472 reg = CSR_READ_4(sc, JME_PMCS);
2473 reg &= ~PMCS_WOL_ENB_MASK;
2474 CSR_WRITE_4(sc, JME_PMCS, reg);
2477 * Pad 10bytes right before received frame. This will greatly
2478 * help Rx performance on strict-alignment architectures as
2479 * it does not need to copy the frame to align the payload.
2481 reg = CSR_READ_4(sc, JME_RXMAC);
2482 reg |= RXMAC_PAD_10BYTES;
2484 if (ifp->if_capenable & IFCAP_RXCSUM)
2485 reg |= RXMAC_CSUM_ENB;
2486 CSR_WRITE_4(sc, JME_RXMAC, reg);
2488 /* Configure general purpose reg0 */
2489 reg = CSR_READ_4(sc, JME_GPREG0);
2490 reg &= ~GPREG0_PCC_UNIT_MASK;
2491 /* Set PCC timer resolution to micro-seconds unit. */
2492 reg |= GPREG0_PCC_UNIT_US;
2494 * Disable all shadow register posting as we have to read
2495 * JME_INTR_STATUS register in jme_intr. Also it seems
2496 * that it's hard to synchronize interrupt status between
2497 * hardware and software with shadow posting due to
2498 * requirements of bus_dmamap_sync(9).
2500 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2501 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2502 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2503 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2504 /* Disable posting of DW0. */
2505 reg &= ~GPREG0_POST_DW0_ENB;
2506 /* Clear PME message. */
2507 reg &= ~GPREG0_PME_ENB;
2508 /* Set PHY address. */
2509 reg &= ~GPREG0_PHY_ADDR_MASK;
2510 reg |= sc->jme_phyaddr;
2511 CSR_WRITE_4(sc, JME_GPREG0, reg);
2513 /* Configure Tx queue 0 packet completion coalescing. */
2514 jme_set_tx_coal(sc);
2516 /* Configure Rx queue 0 packet completion coalescing. */
2517 jme_set_rx_coal(sc);
2519 /* Configure shadow status block but don't enable posting. */
2520 paddr = sc->jme_rdata.jme_ssb_block_paddr;
2521 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2522 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2524 /* Disable Timer 1 and Timer 2. */
2525 CSR_WRITE_4(sc, JME_TIMER1, 0);
2526 CSR_WRITE_4(sc, JME_TIMER2, 0);
2528 /* Configure retry transmit period, retry limit value. */
2529 CSR_WRITE_4(sc, JME_TXTRHD,
2530 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2531 TXTRHD_RT_PERIOD_MASK) |
2532 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2533 TXTRHD_RT_LIMIT_SHIFT));
2536 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
2538 /* Initialize the interrupt mask. */
2539 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2540 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2543 * Enabling Tx/Rx DMA engines and Rx queue processing is
2544 * done after detection of valid link in jme_miibus_statchg.
2546 sc->jme_flags &= ~JME_FLAG_LINK;
2548 /* Set the current media. */
2549 mii = device_get_softc(sc->jme_miibus);
2552 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2554 ifp->if_flags |= IFF_RUNNING;
2555 ifp->if_flags &= ~IFF_OACTIVE;
2559 jme_stop(struct jme_softc *sc)
2561 struct ifnet *ifp = &sc->arpcom.ac_if;
2562 struct jme_txdesc *txd;
2563 struct jme_rxdesc *rxd;
2566 ASSERT_SERIALIZED(ifp->if_serializer);
2569 * Mark the interface down and cancel the watchdog timer.
2571 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2574 callout_stop(&sc->jme_tick_ch);
2575 sc->jme_flags &= ~JME_FLAG_LINK;
2578 * Disable interrupts.
2580 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2581 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2583 /* Disable updating shadow status block. */
2584 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2585 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2587 /* Stop receiver, transmitter. */
2592 /* Reclaim Rx/Tx buffers that have been completed. */
2594 if (sc->jme_cdata.jme_rxhead != NULL)
2595 m_freem(sc->jme_cdata.jme_rxhead);
2596 JME_RXCHAIN_RESET(sc);
2601 * Free partial finished RX segments
2603 if (sc->jme_cdata.jme_rxhead != NULL)
2604 m_freem(sc->jme_cdata.jme_rxhead);
2605 JME_RXCHAIN_RESET(sc);
2608 * Free RX and TX mbufs still in the queues.
2610 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
2611 rxd = &sc->jme_cdata.jme_rxdesc[i];
2612 if (rxd->rx_m != NULL) {
2613 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag,
2619 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
2620 txd = &sc->jme_cdata.jme_txdesc[i];
2621 if (txd->tx_m != NULL) {
2622 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2632 jme_stop_tx(struct jme_softc *sc)
2637 reg = CSR_READ_4(sc, JME_TXCSR);
2638 if ((reg & TXCSR_TX_ENB) == 0)
2640 reg &= ~TXCSR_TX_ENB;
2641 CSR_WRITE_4(sc, JME_TXCSR, reg);
2642 for (i = JME_TIMEOUT; i > 0; i--) {
2644 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2648 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2652 jme_stop_rx(struct jme_softc *sc)
2657 reg = CSR_READ_4(sc, JME_RXCSR);
2658 if ((reg & RXCSR_RX_ENB) == 0)
2660 reg &= ~RXCSR_RX_ENB;
2661 CSR_WRITE_4(sc, JME_RXCSR, reg);
2662 for (i = JME_TIMEOUT; i > 0; i--) {
2664 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2668 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2672 jme_init_tx_ring(struct jme_softc *sc)
2674 struct jme_ring_data *rd;
2675 struct jme_txdesc *txd;
2678 sc->jme_cdata.jme_tx_prod = 0;
2679 sc->jme_cdata.jme_tx_cons = 0;
2680 sc->jme_cdata.jme_tx_cnt = 0;
2682 rd = &sc->jme_rdata;
2683 bzero(rd->jme_tx_ring, JME_TX_RING_SIZE(sc));
2684 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
2685 txd = &sc->jme_cdata.jme_txdesc[i];
2687 txd->tx_desc = &rd->jme_tx_ring[i];
2691 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2692 sc->jme_cdata.jme_tx_ring_map,
2693 BUS_DMASYNC_PREWRITE);
2697 jme_init_ssb(struct jme_softc *sc)
2699 struct jme_ring_data *rd;
2701 rd = &sc->jme_rdata;
2702 bzero(rd->jme_ssb_block, JME_SSB_SIZE);
2703 bus_dmamap_sync(sc->jme_cdata.jme_ssb_tag, sc->jme_cdata.jme_ssb_map,
2704 BUS_DMASYNC_PREWRITE);
2708 jme_init_rx_ring(struct jme_softc *sc)
2710 struct jme_ring_data *rd;
2711 struct jme_rxdesc *rxd;
2714 KKASSERT(sc->jme_cdata.jme_rxhead == NULL &&
2715 sc->jme_cdata.jme_rxtail == NULL &&
2716 sc->jme_cdata.jme_rxlen == 0);
2717 sc->jme_cdata.jme_rx_cons = 0;
2719 rd = &sc->jme_rdata;
2720 bzero(rd->jme_rx_ring, JME_RX_RING_SIZE(sc));
2721 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
2724 rxd = &sc->jme_cdata.jme_rxdesc[i];
2726 rxd->rx_desc = &rd->jme_rx_ring[i];
2727 error = jme_newbuf(sc, rxd, 1);
2732 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2733 sc->jme_cdata.jme_rx_ring_map,
2734 BUS_DMASYNC_PREWRITE);
2739 jme_newbuf(struct jme_softc *sc, struct jme_rxdesc *rxd, int init)
2741 struct jme_desc *desc;
2743 struct jme_dmamap_ctx ctx;
2744 bus_dma_segment_t segs;
2748 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2752 * JMC250 has 64bit boundary alignment limitation so jme(4)
2753 * takes advantage of 10 bytes padding feature of hardware
2754 * in order not to copy entire frame to align IP header on
2757 m->m_len = m->m_pkthdr.len = MCLBYTES;
2761 error = bus_dmamap_load_mbuf(sc->jme_cdata.jme_rx_tag,
2762 sc->jme_cdata.jme_rx_sparemap,
2763 m, jme_dmamap_buf_cb, &ctx,
2765 if (error || ctx.nsegs == 0) {
2767 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag,
2768 sc->jme_cdata.jme_rx_sparemap);
2770 if_printf(&sc->arpcom.ac_if, "too many segments?!\n");
2775 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
2779 if (rxd->rx_m != NULL) {
2780 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap,
2781 BUS_DMASYNC_POSTREAD);
2782 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap);
2784 map = rxd->rx_dmamap;
2785 rxd->rx_dmamap = sc->jme_cdata.jme_rx_sparemap;
2786 sc->jme_cdata.jme_rx_sparemap = map;
2789 desc = rxd->rx_desc;
2790 desc->buflen = htole32(segs.ds_len);
2791 desc->addr_lo = htole32(JME_ADDR_LO(segs.ds_addr));
2792 desc->addr_hi = htole32(JME_ADDR_HI(segs.ds_addr));
2793 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2799 jme_set_vlan(struct jme_softc *sc)
2801 struct ifnet *ifp = &sc->arpcom.ac_if;
2804 ASSERT_SERIALIZED(ifp->if_serializer);
2806 reg = CSR_READ_4(sc, JME_RXMAC);
2807 reg &= ~RXMAC_VLAN_ENB;
2808 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2809 reg |= RXMAC_VLAN_ENB;
2810 CSR_WRITE_4(sc, JME_RXMAC, reg);
2814 jme_set_filter(struct jme_softc *sc)
2816 struct ifnet *ifp = &sc->arpcom.ac_if;
2817 struct ifmultiaddr *ifma;
2822 ASSERT_SERIALIZED(ifp->if_serializer);
2824 rxcfg = CSR_READ_4(sc, JME_RXMAC);
2825 rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
2829 * Always accept frames destined to our station address.
2830 * Always accept broadcast frames.
2832 rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
2834 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2835 if (ifp->if_flags & IFF_PROMISC)
2836 rxcfg |= RXMAC_PROMISC;
2837 if (ifp->if_flags & IFF_ALLMULTI)
2838 rxcfg |= RXMAC_ALLMULTI;
2839 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
2840 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
2841 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2846 * Set up the multicast address filter by passing all multicast
2847 * addresses through a CRC generator, and then using the low-order
2848 * 6 bits as an index into the 64 bit multicast hash table. The
2849 * high order bits select the register, while the rest of the bits
2850 * select the bit within the register.
2852 rxcfg |= RXMAC_MULTICAST;
2853 bzero(mchash, sizeof(mchash));
2855 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2856 if (ifma->ifma_addr->sa_family != AF_LINK)
2858 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2859 ifma->ifma_addr), ETHER_ADDR_LEN);
2861 /* Just want the 6 least significant bits. */
2864 /* Set the corresponding bit in the hash table. */
2865 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2868 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
2869 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
2870 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2874 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
2876 struct jme_softc *sc = arg1;
2877 struct ifnet *ifp = &sc->arpcom.ac_if;
2880 lwkt_serialize_enter(ifp->if_serializer);
2882 v = sc->jme_tx_coal_to;
2883 error = sysctl_handle_int(oidp, &v, 0, req);
2884 if (error || req->newptr == NULL)
2887 if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
2892 if (v != sc->jme_tx_coal_to) {
2893 sc->jme_tx_coal_to = v;
2894 if (ifp->if_flags & IFF_RUNNING)
2895 jme_set_tx_coal(sc);
2898 lwkt_serialize_exit(ifp->if_serializer);
2903 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
2905 struct jme_softc *sc = arg1;
2906 struct ifnet *ifp = &sc->arpcom.ac_if;
2909 lwkt_serialize_enter(ifp->if_serializer);
2911 v = sc->jme_tx_coal_pkt;
2912 error = sysctl_handle_int(oidp, &v, 0, req);
2913 if (error || req->newptr == NULL)
2916 if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
2921 if (v != sc->jme_tx_coal_pkt) {
2922 sc->jme_tx_coal_pkt = v;
2923 if (ifp->if_flags & IFF_RUNNING)
2924 jme_set_tx_coal(sc);
2927 lwkt_serialize_exit(ifp->if_serializer);
2932 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
2934 struct jme_softc *sc = arg1;
2935 struct ifnet *ifp = &sc->arpcom.ac_if;
2938 lwkt_serialize_enter(ifp->if_serializer);
2940 v = sc->jme_rx_coal_to;
2941 error = sysctl_handle_int(oidp, &v, 0, req);
2942 if (error || req->newptr == NULL)
2945 if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
2950 if (v != sc->jme_rx_coal_to) {
2951 sc->jme_rx_coal_to = v;
2952 if (ifp->if_flags & IFF_RUNNING)
2953 jme_set_rx_coal(sc);
2956 lwkt_serialize_exit(ifp->if_serializer);
2961 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
2963 struct jme_softc *sc = arg1;
2964 struct ifnet *ifp = &sc->arpcom.ac_if;
2967 lwkt_serialize_enter(ifp->if_serializer);
2969 v = sc->jme_rx_coal_pkt;
2970 error = sysctl_handle_int(oidp, &v, 0, req);
2971 if (error || req->newptr == NULL)
2974 if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
2979 if (v != sc->jme_rx_coal_pkt) {
2980 sc->jme_rx_coal_pkt = v;
2981 if (ifp->if_flags & IFF_RUNNING)
2982 jme_set_rx_coal(sc);
2985 lwkt_serialize_exit(ifp->if_serializer);
2990 jme_set_tx_coal(struct jme_softc *sc)
2994 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
2996 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
2997 PCCTX_COAL_PKT_MASK;
2998 reg |= PCCTX_COAL_TXQ0;
2999 CSR_WRITE_4(sc, JME_PCCTX, reg);
3003 jme_set_rx_coal(struct jme_softc *sc)
3007 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
3009 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
3010 PCCRX_COAL_PKT_MASK;
3011 CSR_WRITE_4(sc, JME_PCCRX0, reg);