2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
34 * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.87 2007/08/11 05:27:35 sephe Exp $
39 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
41 * Written by Bill Paul <wpaul@windriver.com>
42 * Senior Engineer, Wind River Systems
46 * The Broadcom BCM5700 is based on technology originally developed by
47 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
48 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
49 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
50 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
51 * frames, highly configurable RX filtering, and 16 RX and TX queues
52 * (which, along with RX filter rules, can be used for QOS applications).
53 * Other features, such as TCP segmentation, may be available as part
54 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
55 * firmware images can be stored in hardware and need not be compiled
58 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
59 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
61 * The BCM5701 is a single-chip solution incorporating both the BCM5700
62 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
63 * does not support external SSRAM.
65 * Broadcom also produces a variation of the BCM5700 under the "Altima"
66 * brand name, which is functionally similar but lacks PCI-X support.
68 * Without external SSRAM, you can only have at most 4 TX rings,
69 * and the use of the mini RX ring is disabled. This seems to imply
70 * that these features are simply not available on the BCM5701. As a
71 * result, this driver does not implement any support for the mini RX
75 #include "opt_polling.h"
76 #include <sys/param.h>
78 #include <sys/endian.h>
79 #include <sys/kernel.h>
82 #include <sys/malloc.h>
83 #include <sys/queue.h>
85 #include <sys/serialize.h>
86 #include <sys/socket.h>
87 #include <sys/sockio.h>
88 #include <sys/sysctl.h>
91 #include <net/ethernet.h>
93 #include <net/if_arp.h>
94 #include <net/if_dl.h>
95 #include <net/if_media.h>
96 #include <net/if_types.h>
97 #include <net/ifq_var.h>
98 #include <net/vlan/if_vlan_var.h>
100 #include <dev/netif/mii_layer/mii.h>
101 #include <dev/netif/mii_layer/miivar.h>
102 #include <dev/netif/mii_layer/brgphyreg.h>
104 #include <bus/pci/pcidevs.h>
105 #include <bus/pci/pcireg.h>
106 #include <bus/pci/pcivar.h>
108 #include <dev/netif/bge/if_bgereg.h>
110 /* "device miibus" required. See GENERIC if you get errors here. */
111 #include "miibus_if.h"
113 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
114 #define BGE_MIN_FRAME 60
117 * Various supported device vendors/types and their names. Note: the
118 * spec seems to indicate that the hardware still has Alteon's vendor
119 * ID burned into it, though it will always be overriden by the vendor
120 * ID in the EEPROM. Just to be safe, we cover all possibilities.
122 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */
124 static struct bge_type bge_devs[] = {
125 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
126 "3COM 3C996 Gigabit Ethernet" },
128 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
129 "Alteon BCM5700 Gigabit Ethernet" },
130 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
131 "Alteon BCM5701 Gigabit Ethernet" },
133 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
134 "Altima AC1000 Gigabit Ethernet" },
135 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
136 "Altima AC1002 Gigabit Ethernet" },
137 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
138 "Altima AC9100 Gigabit Ethernet" },
140 { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
141 "Apple BCM5701 Gigabit Ethernet" },
143 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
144 "Broadcom BCM5700 Gigabit Ethernet" },
145 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
146 "Broadcom BCM5701 Gigabit Ethernet" },
147 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
148 "Broadcom BCM5702 Gigabit Ethernet" },
149 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
150 "Broadcom BCM5702X Gigabit Ethernet" },
151 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
152 "Broadcom BCM5702 Gigabit Ethernet" },
153 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
154 "Broadcom BCM5703 Gigabit Ethernet" },
155 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
156 "Broadcom BCM5703X Gigabit Ethernet" },
157 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
158 "Broadcom BCM5703 Gigabit Ethernet" },
159 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
160 "Broadcom BCM5704C Dual Gigabit Ethernet" },
161 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
162 "Broadcom BCM5704S Dual Gigabit Ethernet" },
163 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
164 "Broadcom BCM5704S Dual Gigabit Ethernet" },
165 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
166 "Broadcom BCM5705 Gigabit Ethernet" },
167 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
168 "Broadcom BCM5705F Gigabit Ethernet" },
169 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
170 "Broadcom BCM5705K Gigabit Ethernet" },
171 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
172 "Broadcom BCM5705M Gigabit Ethernet" },
173 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
174 "Broadcom BCM5705M Gigabit Ethernet" },
175 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
176 "Broadcom BCM5714C Gigabit Ethernet" },
177 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
178 "Broadcom BCM5714S Gigabit Ethernet" },
179 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
180 "Broadcom BCM5715 Gigabit Ethernet" },
181 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
182 "Broadcom BCM5715S Gigabit Ethernet" },
183 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
184 "Broadcom BCM5720 Gigabit Ethernet" },
185 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
186 "Broadcom BCM5721 Gigabit Ethernet" },
187 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
188 "Broadcom BCM5722 Gigabit Ethernet" },
189 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
190 "Broadcom BCM5750 Gigabit Ethernet" },
191 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
192 "Broadcom BCM5750M Gigabit Ethernet" },
193 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
194 "Broadcom BCM5751 Gigabit Ethernet" },
195 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
196 "Broadcom BCM5751F Gigabit Ethernet" },
197 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
198 "Broadcom BCM5751M Gigabit Ethernet" },
199 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
200 "Broadcom BCM5752 Gigabit Ethernet" },
201 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
202 "Broadcom BCM5752M Gigabit Ethernet" },
203 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
204 "Broadcom BCM5753 Gigabit Ethernet" },
205 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
206 "Broadcom BCM5753F Gigabit Ethernet" },
207 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
208 "Broadcom BCM5753M Gigabit Ethernet" },
209 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
210 "Broadcom BCM5754 Gigabit Ethernet" },
211 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
212 "Broadcom BCM5754M Gigabit Ethernet" },
213 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
214 "Broadcom BCM5755 Gigabit Ethernet" },
215 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
216 "Broadcom BCM5755M Gigabit Ethernet" },
217 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
218 "Broadcom BCM5756 Gigabit Ethernet" },
219 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
220 "Broadcom BCM5780 Gigabit Ethernet" },
221 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
222 "Broadcom BCM5780S Gigabit Ethernet" },
223 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
224 "Broadcom BCM5781 Gigabit Ethernet" },
225 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
226 "Broadcom BCM5782 Gigabit Ethernet" },
227 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
228 "Broadcom BCM5786 Gigabit Ethernet" },
229 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
230 "Broadcom BCM5787 Gigabit Ethernet" },
231 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
232 "Broadcom BCM5787F Gigabit Ethernet" },
233 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
234 "Broadcom BCM5787M Gigabit Ethernet" },
235 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
236 "Broadcom BCM5788 Gigabit Ethernet" },
237 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
238 "Broadcom BCM5789 Gigabit Ethernet" },
239 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
240 "Broadcom BCM5901 Fast Ethernet" },
241 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
242 "Broadcom BCM5901A2 Fast Ethernet" },
243 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
244 "Broadcom BCM5903M Fast Ethernet" },
246 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
247 "SysKonnect Gigabit Ethernet" },
252 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
253 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
254 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
255 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
256 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
258 static int bge_probe(device_t);
259 static int bge_attach(device_t);
260 static int bge_detach(device_t);
261 static void bge_txeof(struct bge_softc *);
262 static void bge_rxeof(struct bge_softc *);
264 static void bge_tick(void *);
265 static void bge_stats_update(struct bge_softc *);
266 static void bge_stats_update_regs(struct bge_softc *);
267 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
269 #ifdef DEVICE_POLLING
270 static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
272 static void bge_intr(void *);
273 static void bge_enable_intr(struct bge_softc *);
274 static void bge_disable_intr(struct bge_softc *);
275 static void bge_start(struct ifnet *);
276 static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
277 static void bge_init(void *);
278 static void bge_stop(struct bge_softc *);
279 static void bge_watchdog(struct ifnet *);
280 static void bge_shutdown(device_t);
281 static int bge_suspend(device_t);
282 static int bge_resume(device_t);
283 static int bge_ifmedia_upd(struct ifnet *);
284 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
286 static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
287 static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
289 static void bge_setmulti(struct bge_softc *);
290 static void bge_setpromisc(struct bge_softc *);
292 static int bge_alloc_jumbo_mem(struct bge_softc *);
293 static void bge_free_jumbo_mem(struct bge_softc *);
294 static struct bge_jslot
295 *bge_jalloc(struct bge_softc *);
296 static void bge_jfree(void *);
297 static void bge_jref(void *);
298 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
299 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
300 static int bge_init_rx_ring_std(struct bge_softc *);
301 static void bge_free_rx_ring_std(struct bge_softc *);
302 static int bge_init_rx_ring_jumbo(struct bge_softc *);
303 static void bge_free_rx_ring_jumbo(struct bge_softc *);
304 static void bge_free_tx_ring(struct bge_softc *);
305 static int bge_init_tx_ring(struct bge_softc *);
307 static int bge_chipinit(struct bge_softc *);
308 static int bge_blockinit(struct bge_softc *);
310 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
311 static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
313 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
315 static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
316 static void bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
318 static int bge_miibus_readreg(device_t, int, int);
319 static int bge_miibus_writereg(device_t, int, int, int);
320 static void bge_miibus_statchg(device_t);
321 static void bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
322 static void bge_tbi_link_upd(struct bge_softc *, uint32_t);
323 static void bge_copper_link_upd(struct bge_softc *, uint32_t);
325 static void bge_reset(struct bge_softc *);
327 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
328 static void bge_dma_map_mbuf(void *, bus_dma_segment_t *, int,
330 static int bge_dma_alloc(struct bge_softc *);
331 static void bge_dma_free(struct bge_softc *);
332 static int bge_dma_block_alloc(struct bge_softc *, bus_size_t,
333 bus_dma_tag_t *, bus_dmamap_t *,
334 void **, bus_addr_t *);
335 static void bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
337 static void bge_coal_change(struct bge_softc *);
338 static int bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
339 static int bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
340 static int bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
341 static int bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
342 static int bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
345 * Set following tunable to 1 for some IBM blade servers with the DNLK
346 * switch module. Auto negotiation is broken for those configurations.
348 static int bge_fake_autoneg = 0;
349 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
351 /* Interrupt moderation control variables. */
352 static int bge_rx_coal_ticks = 150; /* usec */
353 static int bge_tx_coal_ticks = 1000000; /* usec */
354 static int bge_rx_max_coal_bds = 16;
355 static int bge_tx_max_coal_bds = 32;
357 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
358 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
359 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
360 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
362 #if !defined(KTR_IF_BGE)
363 #define KTR_IF_BGE KTR_ALL
365 KTR_INFO_MASTER(if_bge);
366 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr", 0);
367 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt", 0);
368 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt", 0);
369 #define logif(name) KTR_LOG(if_bge_ ## name)
371 static device_method_t bge_methods[] = {
372 /* Device interface */
373 DEVMETHOD(device_probe, bge_probe),
374 DEVMETHOD(device_attach, bge_attach),
375 DEVMETHOD(device_detach, bge_detach),
376 DEVMETHOD(device_shutdown, bge_shutdown),
377 DEVMETHOD(device_suspend, bge_suspend),
378 DEVMETHOD(device_resume, bge_resume),
381 DEVMETHOD(bus_print_child, bus_generic_print_child),
382 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
385 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
386 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
387 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
392 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
393 static devclass_t bge_devclass;
395 DECLARE_DUMMY_MODULE(if_bge);
396 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
397 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
400 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
402 device_t dev = sc->bge_dev;
405 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
406 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
407 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
412 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
414 device_t dev = sc->bge_dev;
416 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
417 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
418 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
423 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
425 device_t dev = sc->bge_dev;
427 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
428 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
433 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
435 device_t dev = sc->bge_dev;
437 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
438 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
442 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
444 CSR_WRITE_4(sc, off, val);
448 * Read a byte of data stored in the EEPROM at address 'addr.' The
449 * BCM570x supports both the traditional bitbang interface and an
450 * auto access interface for reading the EEPROM. We use the auto
454 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
460 * Enable use of auto EEPROM access so we can avoid
461 * having to use the bitbang method.
463 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
465 /* Reset the EEPROM, load the clock period. */
466 CSR_WRITE_4(sc, BGE_EE_ADDR,
467 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
470 /* Issue the read EEPROM command. */
471 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
473 /* Wait for completion */
474 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
476 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
480 if (i == BGE_TIMEOUT) {
481 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
486 byte = CSR_READ_4(sc, BGE_EE_DATA);
488 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
494 * Read a sequence of bytes from the EEPROM.
497 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
503 for (byte = 0, err = 0, i = 0; i < len; i++) {
504 err = bge_eeprom_getbyte(sc, off + i, &byte);
514 bge_miibus_readreg(device_t dev, int phy, int reg)
516 struct bge_softc *sc;
518 uint32_t val, autopoll;
521 sc = device_get_softc(dev);
522 ifp = &sc->arpcom.ac_if;
525 * Broadcom's own driver always assumes the internal
526 * PHY is at GMII address 1. On some chips, the PHY responds
527 * to accesses at all addresses, which could cause us to
528 * bogusly attach the PHY 32 times at probe type. Always
529 * restricting the lookup to address 1 is simpler than
530 * trying to figure out which chips revisions should be
536 /* Reading with autopolling on may trigger PCI errors */
537 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
538 if (autopoll & BGE_MIMODE_AUTOPOLL) {
539 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
543 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
544 BGE_MIPHY(phy)|BGE_MIREG(reg));
546 for (i = 0; i < BGE_TIMEOUT; i++) {
547 val = CSR_READ_4(sc, BGE_MI_COMM);
548 if (!(val & BGE_MICOMM_BUSY))
552 if (i == BGE_TIMEOUT) {
553 if_printf(ifp, "PHY read timed out\n");
558 val = CSR_READ_4(sc, BGE_MI_COMM);
561 if (autopoll & BGE_MIMODE_AUTOPOLL) {
562 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
566 if (val & BGE_MICOMM_READFAIL)
569 return(val & 0xFFFF);
573 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
575 struct bge_softc *sc;
579 sc = device_get_softc(dev);
581 /* Reading with autopolling on may trigger PCI errors */
582 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
583 if (autopoll & BGE_MIMODE_AUTOPOLL) {
584 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
588 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
589 BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
591 for (i = 0; i < BGE_TIMEOUT; i++) {
592 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
596 if (autopoll & BGE_MIMODE_AUTOPOLL) {
597 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
601 if (i == BGE_TIMEOUT) {
602 if_printf(&sc->arpcom.ac_if, "PHY read timed out\n");
610 bge_miibus_statchg(device_t dev)
612 struct bge_softc *sc;
613 struct mii_data *mii;
615 sc = device_get_softc(dev);
616 mii = device_get_softc(sc->bge_miibus);
618 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
619 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
620 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
622 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
625 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
626 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
628 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
633 * Memory management for jumbo frames.
636 bge_alloc_jumbo_mem(struct bge_softc *sc)
638 struct ifnet *ifp = &sc->arpcom.ac_if;
639 struct bge_jslot *entry;
645 * Create tag for jumbo mbufs.
646 * This is really a bit of a kludge. We allocate a special
647 * jumbo buffer pool which (thanks to the way our DMA
648 * memory allocation works) will consist of contiguous
649 * pages. This means that even though a jumbo buffer might
650 * be larger than a page size, we don't really need to
651 * map it into more than one DMA segment. However, the
652 * default mbuf tag will result in multi-segment mappings,
653 * so we have to create a special jumbo mbuf tag that
654 * lets us get away with mapping the jumbo buffers as
655 * a single segment. I think eventually the driver should
656 * be changed so that it uses ordinary mbufs and cluster
657 * buffers, i.e. jumbo frames can span multiple DMA
658 * descriptors. But that's a project for another day.
662 * Create DMA stuffs for jumbo RX ring.
664 error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
665 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
666 &sc->bge_cdata.bge_rx_jumbo_ring_map,
667 (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
668 &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
670 if_printf(ifp, "could not create jumbo RX ring\n");
675 * Create DMA stuffs for jumbo buffer block.
677 error = bge_dma_block_alloc(sc, BGE_JMEM,
678 &sc->bge_cdata.bge_jumbo_tag,
679 &sc->bge_cdata.bge_jumbo_map,
680 (void **)&sc->bge_ldata.bge_jumbo_buf,
683 if_printf(ifp, "could not create jumbo buffer\n");
687 SLIST_INIT(&sc->bge_jfree_listhead);
690 * Now divide it up into 9K pieces and save the addresses
691 * in an array. Note that we play an evil trick here by using
692 * the first few bytes in the buffer to hold the the address
693 * of the softc structure for this interface. This is because
694 * bge_jfree() needs it, but it is called by the mbuf management
695 * code which will not pass it to us explicitly.
697 for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
698 entry = &sc->bge_cdata.bge_jslots[i];
700 entry->bge_buf = ptr;
701 entry->bge_paddr = paddr;
702 entry->bge_inuse = 0;
704 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
713 bge_free_jumbo_mem(struct bge_softc *sc)
715 /* Destroy jumbo RX ring. */
716 bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
717 sc->bge_cdata.bge_rx_jumbo_ring_map,
718 sc->bge_ldata.bge_rx_jumbo_ring);
720 /* Destroy jumbo buffer block. */
721 bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
722 sc->bge_cdata.bge_jumbo_map,
723 sc->bge_ldata.bge_jumbo_buf);
727 * Allocate a jumbo buffer.
729 static struct bge_jslot *
730 bge_jalloc(struct bge_softc *sc)
732 struct bge_jslot *entry;
734 lwkt_serialize_enter(&sc->bge_jslot_serializer);
735 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
737 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
738 entry->bge_inuse = 1;
740 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
742 lwkt_serialize_exit(&sc->bge_jslot_serializer);
747 * Adjust usage count on a jumbo buffer.
752 struct bge_jslot *entry = (struct bge_jslot *)arg;
753 struct bge_softc *sc = entry->bge_sc;
756 panic("bge_jref: can't find softc pointer!");
758 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
759 panic("bge_jref: asked to reference buffer "
760 "that we don't manage!");
761 } else if (entry->bge_inuse == 0) {
762 panic("bge_jref: buffer already free!");
764 atomic_add_int(&entry->bge_inuse, 1);
769 * Release a jumbo buffer.
774 struct bge_jslot *entry = (struct bge_jslot *)arg;
775 struct bge_softc *sc = entry->bge_sc;
778 panic("bge_jfree: can't find softc pointer!");
780 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
781 panic("bge_jfree: asked to free buffer that we don't manage!");
782 } else if (entry->bge_inuse == 0) {
783 panic("bge_jfree: buffer already free!");
786 * Possible MP race to 0, use the serializer. The atomic insn
787 * is still needed for races against bge_jref().
789 lwkt_serialize_enter(&sc->bge_jslot_serializer);
790 atomic_subtract_int(&entry->bge_inuse, 1);
791 if (entry->bge_inuse == 0) {
792 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
795 lwkt_serialize_exit(&sc->bge_jslot_serializer);
801 * Intialize a standard receive ring descriptor.
804 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
806 struct mbuf *m_new = NULL;
807 struct bge_dmamap_arg ctx;
808 bus_dma_segment_t seg;
813 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
818 m_new->m_data = m_new->m_ext.ext_buf;
820 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
822 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
823 m_adj(m_new, ETHER_ALIGN);
827 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag,
828 sc->bge_cdata.bge_rx_std_dmamap[i],
829 m_new, bge_dma_map_mbuf, &ctx,
831 if (error || ctx.bge_maxsegs == 0) {
837 sc->bge_cdata.bge_rx_std_chain[i] = m_new;
839 r = &sc->bge_ldata.bge_rx_std_ring[i];
840 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[0].ds_addr);
841 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[0].ds_addr);
842 r->bge_flags = BGE_RXBDFLAG_END;
843 r->bge_len = m_new->m_len;
846 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
847 sc->bge_cdata.bge_rx_std_dmamap[i],
848 BUS_DMASYNC_PREREAD);
853 * Initialize a jumbo receive ring descriptor. This allocates
854 * a jumbo buffer from the pool managed internally by the driver.
857 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
859 struct mbuf *m_new = NULL;
860 struct bge_jslot *buf;
865 /* Allocate the mbuf. */
866 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
870 /* Allocate the jumbo buffer */
871 buf = bge_jalloc(sc);
874 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
875 "-- packet dropped!\n");
879 /* Attach the buffer to the mbuf. */
880 m_new->m_ext.ext_arg = buf;
881 m_new->m_ext.ext_buf = buf->bge_buf;
882 m_new->m_ext.ext_free = bge_jfree;
883 m_new->m_ext.ext_ref = bge_jref;
884 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
886 m_new->m_flags |= M_EXT;
888 KKASSERT(m->m_flags & M_EXT);
890 buf = m_new->m_ext.ext_arg;
892 m_new->m_data = m_new->m_ext.ext_buf;
893 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
895 paddr = buf->bge_paddr;
896 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
897 m_adj(m_new, ETHER_ALIGN);
898 paddr += ETHER_ALIGN;
901 /* Set up the descriptor. */
902 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
904 r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
905 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(paddr);
906 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(paddr);
907 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
908 r->bge_len = m_new->m_len;
915 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
916 * that's 1MB or memory, which is a lot. For now, we fill only the first
917 * 256 ring entries and hope that our CPU is fast enough to keep up with
921 bge_init_rx_ring_std(struct bge_softc *sc)
925 for (i = 0; i < BGE_SSLOTS; i++) {
926 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
930 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
931 sc->bge_cdata.bge_rx_std_ring_map,
932 BUS_DMASYNC_PREWRITE);
935 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
941 bge_free_rx_ring_std(struct bge_softc *sc)
945 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
946 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
947 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
948 sc->bge_cdata.bge_rx_std_dmamap[i]);
949 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
950 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
952 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
953 sizeof(struct bge_rx_bd));
958 bge_init_rx_ring_jumbo(struct bge_softc *sc)
963 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
964 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
968 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
969 sc->bge_cdata.bge_rx_jumbo_ring_map,
970 BUS_DMASYNC_PREWRITE);
972 sc->bge_jumbo = i - 1;
974 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
975 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
976 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
978 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
984 bge_free_rx_ring_jumbo(struct bge_softc *sc)
988 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
989 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
990 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
991 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
993 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
994 sizeof(struct bge_rx_bd));
999 bge_free_tx_ring(struct bge_softc *sc)
1003 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1004 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1005 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1006 sc->bge_cdata.bge_tx_dmamap[i]);
1007 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1008 sc->bge_cdata.bge_tx_chain[i] = NULL;
1010 bzero(&sc->bge_ldata.bge_tx_ring[i],
1011 sizeof(struct bge_tx_bd));
1016 bge_init_tx_ring(struct bge_softc *sc)
1019 sc->bge_tx_saved_considx = 0;
1020 sc->bge_tx_prodidx = 0;
1022 /* Initialize transmit producer index for host-memory send ring. */
1023 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1025 /* 5700 b2 errata */
1026 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1027 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
1029 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1030 /* 5700 b2 errata */
1031 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1032 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1038 bge_setmulti(struct bge_softc *sc)
1041 struct ifmultiaddr *ifma;
1042 uint32_t hashes[4] = { 0, 0, 0, 0 };
1045 ifp = &sc->arpcom.ac_if;
1047 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1048 for (i = 0; i < 4; i++)
1049 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1053 /* First, zot all the existing filters. */
1054 for (i = 0; i < 4; i++)
1055 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1057 /* Now program new ones. */
1058 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1059 if (ifma->ifma_addr->sa_family != AF_LINK)
1062 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1063 ETHER_ADDR_LEN) & 0x7f;
1064 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1067 for (i = 0; i < 4; i++)
1068 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1072 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1073 * self-test results.
1076 bge_chipinit(struct bge_softc *sc)
1079 uint32_t dma_rw_ctl;
1081 /* Set endian type before we access any non-PCI registers. */
1082 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1085 * Check the 'ROM failed' bit on the RX CPU to see if
1086 * self-tests passed.
1088 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1089 if_printf(&sc->arpcom.ac_if,
1090 "RX CPU self-diagnostics failed!\n");
1094 /* Clear the MAC control register */
1095 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1098 * Clear the MAC statistics block in the NIC's
1101 for (i = BGE_STATS_BLOCK;
1102 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1103 BGE_MEMWIN_WRITE(sc, i, 0);
1105 for (i = BGE_STATUS_BLOCK;
1106 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1107 BGE_MEMWIN_WRITE(sc, i, 0);
1109 /* Set up the PCI DMA control register. */
1110 if (sc->bge_flags & BGE_FLAG_PCIE) {
1112 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1113 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1114 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1115 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1117 if (BGE_IS_5714_FAMILY(sc)) {
1118 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1119 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1120 /* XXX magic values, Broadcom-supplied Linux driver */
1121 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1122 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1123 BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1125 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1127 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1129 * The 5704 uses a different encoding of read/write
1132 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1133 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1134 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1136 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1137 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1138 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1143 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1144 * for hardware bugs.
1146 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1147 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1150 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1151 if (tmp == 0x6 || tmp == 0x7)
1152 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1155 /* Conventional PCI bus */
1156 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1157 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1158 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1162 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1163 sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1164 sc->bge_asicrev == BGE_ASICREV_BCM5705)
1165 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1166 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1169 * Set up general mode register.
1171 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1172 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1173 BGE_MODECTL_TX_NO_PHDR_CSUM);
1176 * Disable memory write invalidate. Apparently it is not supported
1177 * properly by these devices.
1179 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1181 /* Set the timer prescaler (always 66Mhz) */
1182 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1188 bge_blockinit(struct bge_softc *sc)
1190 struct bge_rcb *rcb;
1197 * Initialize the memory window pointer register so that
1198 * we can access the first 32K of internal NIC RAM. This will
1199 * allow us to set up the TX send ring RCBs and the RX return
1200 * ring RCBs, plus other things which live in NIC memory.
1202 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1204 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1206 if (!BGE_IS_5705_PLUS(sc)) {
1207 /* Configure mbuf memory pool */
1208 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1209 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1210 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1212 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1214 /* Configure DMA resource pool */
1215 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1216 BGE_DMA_DESCRIPTORS);
1217 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1220 /* Configure mbuf pool watermarks */
1221 if (BGE_IS_5705_PLUS(sc)) {
1222 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1223 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1225 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1226 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1228 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1230 /* Configure DMA resource watermarks */
1231 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1232 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1234 /* Enable buffer manager */
1235 if (!BGE_IS_5705_PLUS(sc)) {
1236 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1237 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1239 /* Poll for buffer manager start indication */
1240 for (i = 0; i < BGE_TIMEOUT; i++) {
1241 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1246 if (i == BGE_TIMEOUT) {
1247 if_printf(&sc->arpcom.ac_if,
1248 "buffer manager failed to start\n");
1253 /* Enable flow-through queues */
1254 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1255 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1257 /* Wait until queue initialization is complete */
1258 for (i = 0; i < BGE_TIMEOUT; i++) {
1259 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1264 if (i == BGE_TIMEOUT) {
1265 if_printf(&sc->arpcom.ac_if,
1266 "flow-through queue init failed\n");
1270 /* Initialize the standard RX ring control block */
1271 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1272 rcb->bge_hostaddr.bge_addr_lo =
1273 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1274 rcb->bge_hostaddr.bge_addr_hi =
1275 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1276 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1277 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1278 if (BGE_IS_5705_PLUS(sc))
1279 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1281 rcb->bge_maxlen_flags =
1282 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1283 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1284 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1285 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1286 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1287 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1290 * Initialize the jumbo RX ring control block
1291 * We set the 'ring disabled' bit in the flags
1292 * field until we're actually ready to start
1293 * using this ring (i.e. once we set the MTU
1294 * high enough to require it).
1296 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1297 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1299 rcb->bge_hostaddr.bge_addr_lo =
1300 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1301 rcb->bge_hostaddr.bge_addr_hi =
1302 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1303 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1304 sc->bge_cdata.bge_rx_jumbo_ring_map,
1305 BUS_DMASYNC_PREREAD);
1306 rcb->bge_maxlen_flags =
1307 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1308 BGE_RCB_FLAG_RING_DISABLED);
1309 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1310 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1311 rcb->bge_hostaddr.bge_addr_hi);
1312 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1313 rcb->bge_hostaddr.bge_addr_lo);
1314 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1315 rcb->bge_maxlen_flags);
1316 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1318 /* Set up dummy disabled mini ring RCB */
1319 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1320 rcb->bge_maxlen_flags =
1321 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1322 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1323 rcb->bge_maxlen_flags);
1327 * Set the BD ring replentish thresholds. The recommended
1328 * values are 1/8th the number of descriptors allocated to
1331 if (BGE_IS_5705_PLUS(sc))
1334 val = BGE_STD_RX_RING_CNT / 8;
1335 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1336 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1339 * Disable all unused send rings by setting the 'ring disabled'
1340 * bit in the flags field of all the TX send ring control blocks.
1341 * These are located in NIC memory.
1343 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1344 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1345 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1346 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1347 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1348 vrcb += sizeof(struct bge_rcb);
1351 /* Configure TX RCB 0 (we use only the first ring) */
1352 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1353 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1354 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1355 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1356 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1357 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1358 if (!BGE_IS_5705_PLUS(sc)) {
1359 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1360 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1363 /* Disable all unused RX return rings */
1364 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1365 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1366 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1367 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1368 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1369 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1370 BGE_RCB_FLAG_RING_DISABLED));
1371 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1372 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1373 (i * (sizeof(uint64_t))), 0);
1374 vrcb += sizeof(struct bge_rcb);
1377 /* Initialize RX ring indexes */
1378 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1379 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1380 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1383 * Set up RX return ring 0
1384 * Note that the NIC address for RX return rings is 0x00000000.
1385 * The return rings live entirely within the host, so the
1386 * nicaddr field in the RCB isn't used.
1388 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1389 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1390 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1391 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1392 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1393 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1394 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1396 /* Set random backoff seed for TX */
1397 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1398 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1399 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1400 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1401 BGE_TX_BACKOFF_SEED_MASK);
1403 /* Set inter-packet gap */
1404 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1407 * Specify which ring to use for packets that don't match
1410 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1413 * Configure number of RX lists. One interrupt distribution
1414 * list, sixteen active lists, one bad frames class.
1416 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1418 /* Inialize RX list placement stats mask. */
1419 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1420 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1422 /* Disable host coalescing until we get it set up */
1423 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1425 /* Poll to make sure it's shut down. */
1426 for (i = 0; i < BGE_TIMEOUT; i++) {
1427 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1432 if (i == BGE_TIMEOUT) {
1433 if_printf(&sc->arpcom.ac_if,
1434 "host coalescing engine failed to idle\n");
1438 /* Set up host coalescing defaults */
1439 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1440 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1441 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1442 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1443 if (!BGE_IS_5705_PLUS(sc)) {
1444 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1445 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1447 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1448 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1450 /* Set up address of statistics block */
1451 if (!BGE_IS_5705_PLUS(sc)) {
1452 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1453 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1454 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1455 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1457 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1458 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1459 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1462 /* Set up address of status block */
1463 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1464 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1465 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1466 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1467 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1468 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1470 /* Turn on host coalescing state machine */
1471 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1473 /* Turn on RX BD completion state machine and enable attentions */
1474 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1475 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1477 /* Turn on RX list placement state machine */
1478 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1480 /* Turn on RX list selector state machine. */
1481 if (!BGE_IS_5705_PLUS(sc))
1482 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1484 /* Turn on DMA, clear stats */
1485 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1486 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1487 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1488 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1489 ((sc->bge_flags & BGE_FLAG_TBI) ?
1490 BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1492 /* Set misc. local control, enable interrupts on attentions */
1493 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1496 /* Assert GPIO pins for PHY reset */
1497 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1498 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1499 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1500 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1503 /* Turn on DMA completion state machine */
1504 if (!BGE_IS_5705_PLUS(sc))
1505 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1507 /* Turn on write DMA state machine */
1508 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1509 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1510 sc->bge_asicrev == BGE_ASICREV_BCM5787)
1511 val |= (1 << 29); /* Enable host coalescing bug fix. */
1512 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1514 /* Turn on read DMA state machine */
1515 CSR_WRITE_4(sc, BGE_RDMA_MODE,
1516 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1518 /* Turn on RX data completion state machine */
1519 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1521 /* Turn on RX BD initiator state machine */
1522 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1524 /* Turn on RX data and RX BD initiator state machine */
1525 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1527 /* Turn on Mbuf cluster free state machine */
1528 if (!BGE_IS_5705_PLUS(sc))
1529 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1531 /* Turn on send BD completion state machine */
1532 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1534 /* Turn on send data completion state machine */
1535 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1537 /* Turn on send data initiator state machine */
1538 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1540 /* Turn on send BD initiator state machine */
1541 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1543 /* Turn on send BD selector state machine */
1544 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1546 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1547 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1548 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1550 /* ack/clear link change events */
1551 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1552 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1553 BGE_MACSTAT_LINK_CHANGED);
1554 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1556 /* Enable PHY auto polling (for MII/GMII only) */
1557 if (sc->bge_flags & BGE_FLAG_TBI) {
1558 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1560 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1561 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1562 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1563 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1564 BGE_EVTENB_MI_INTERRUPT);
1569 * Clear any pending link state attention.
1570 * Otherwise some link state change events may be lost until attention
1571 * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1572 * It's not necessary on newer BCM chips - perhaps enabling link
1573 * state change attentions implies clearing pending attention.
1575 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1576 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1577 BGE_MACSTAT_LINK_CHANGED);
1579 /* Enable link state change attentions. */
1580 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1586 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1587 * against our list and return its name if we find a match. Note
1588 * that since the Broadcom controller contains VPD support, we
1589 * can get the device name string from the controller itself instead
1590 * of the compiled-in string. This is a little slow, but it guarantees
1591 * we'll always announce the right product name.
1594 bge_probe(device_t dev)
1596 struct bge_softc *sc;
1599 uint16_t product, vendor;
1601 product = pci_get_device(dev);
1602 vendor = pci_get_vendor(dev);
1604 for (t = bge_devs; t->bge_name != NULL; t++) {
1605 if (vendor == t->bge_vid && product == t->bge_did)
1609 if (t->bge_name == NULL)
1612 sc = device_get_softc(dev);
1613 descbuf = kmalloc(BGE_DEVDESC_MAX, M_TEMP, M_WAITOK);
1614 ksnprintf(descbuf, BGE_DEVDESC_MAX, "%s, ASIC rev. %#04x", t->bge_name,
1615 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1616 device_set_desc_copy(dev, descbuf);
1617 if (pci_get_subvendor(dev) == PCI_VENDOR_DELL)
1618 sc->bge_flags |= BGE_FLAG_NO_3LED;
1619 kfree(descbuf, M_TEMP);
1624 bge_attach(device_t dev)
1627 struct bge_softc *sc;
1629 uint32_t mac_addr = 0;
1631 uint8_t ether_addr[ETHER_ADDR_LEN];
1633 sc = device_get_softc(dev);
1635 callout_init(&sc->bge_stat_timer);
1636 lwkt_serialize_init(&sc->bge_jslot_serializer);
1639 * Map control/status registers.
1641 pci_enable_busmaster(dev);
1644 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1647 if (sc->bge_res == NULL) {
1648 device_printf(dev, "couldn't map memory\n");
1652 sc->bge_btag = rman_get_bustag(sc->bge_res);
1653 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1655 /* Save ASIC rev. */
1657 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1658 BGE_PCIMISCCTL_ASICREV;
1659 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1660 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1662 /* Save chipset family. */
1663 switch (sc->bge_asicrev) {
1664 case BGE_ASICREV_BCM5700:
1665 case BGE_ASICREV_BCM5701:
1666 case BGE_ASICREV_BCM5703:
1667 case BGE_ASICREV_BCM5704:
1668 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1671 case BGE_ASICREV_BCM5714_A0:
1672 case BGE_ASICREV_BCM5780:
1673 case BGE_ASICREV_BCM5714:
1674 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1677 case BGE_ASICREV_BCM5750:
1678 case BGE_ASICREV_BCM5752:
1679 case BGE_ASICREV_BCM5755:
1680 case BGE_ASICREV_BCM5787:
1681 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1684 case BGE_ASICREV_BCM5705:
1685 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1690 * Set various quirk flags.
1693 sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1694 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1695 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1696 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1697 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1698 sc->bge_asicrev == BGE_ASICREV_BCM5906)
1699 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1701 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1702 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1703 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1705 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1706 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1707 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1709 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1710 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1712 if (BGE_IS_5705_PLUS(sc)) {
1713 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1714 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1715 uint32_t product = pci_get_device(dev);
1717 if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
1718 product != PCI_PRODUCT_BROADCOM_BCM5756)
1719 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1720 if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1721 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1722 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1723 sc->bge_flags |= BGE_FLAG_BER_BUG;
1727 /* Allocate interrupt */
1730 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1731 RF_SHAREABLE | RF_ACTIVE);
1733 if (sc->bge_irq == NULL) {
1734 device_printf(dev, "couldn't map interrupt\n");
1740 * Check if this is a PCI-X or PCI Express device.
1742 if (BGE_IS_5705_PLUS(sc)) {
1745 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
1746 if ((reg & 0xff) == BGE_PCIE_CAPID)
1747 sc->bge_flags |= BGE_FLAG_PCIE;
1750 * Check if the device is in PCI-X Mode.
1751 * (This bit is not valid on PCI Express controllers.)
1753 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1754 BGE_PCISTATE_PCI_BUSMODE) == 0)
1755 sc->bge_flags |= BGE_FLAG_PCIX;
1758 ifp = &sc->arpcom.ac_if;
1759 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1761 /* Try to reset the chip. */
1764 if (bge_chipinit(sc)) {
1765 device_printf(dev, "chip initialization failed\n");
1771 * Get station address from the EEPROM.
1773 mac_addr = bge_readmem_ind(sc, 0x0c14);
1774 if ((mac_addr >> 16) == 0x484b) {
1775 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1776 ether_addr[1] = (uint8_t)mac_addr;
1777 mac_addr = bge_readmem_ind(sc, 0x0c18);
1778 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1779 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1780 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1781 ether_addr[5] = (uint8_t)mac_addr;
1782 } else if (bge_read_eeprom(sc, ether_addr,
1783 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1784 device_printf(dev, "failed to read station address\n");
1789 /* 5705/5750 limits RX return ring to 512 entries. */
1790 if (BGE_IS_5705_PLUS(sc))
1791 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1793 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1795 error = bge_dma_alloc(sc);
1799 /* Set default tuneable values. */
1800 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1801 sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
1802 sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
1803 sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
1804 sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
1806 /* Set up ifnet structure */
1808 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1809 ifp->if_ioctl = bge_ioctl;
1810 ifp->if_start = bge_start;
1811 #ifdef DEVICE_POLLING
1812 ifp->if_poll = bge_poll;
1814 ifp->if_watchdog = bge_watchdog;
1815 ifp->if_init = bge_init;
1816 ifp->if_mtu = ETHERMTU;
1817 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1818 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1819 ifq_set_ready(&ifp->if_snd);
1822 * 5700 B0 chips do not support checksumming correctly due
1825 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
1826 ifp->if_capabilities |= IFCAP_HWCSUM;
1827 ifp->if_hwassist = BGE_CSUM_FEATURES;
1829 ifp->if_capenable = ifp->if_capabilities;
1832 * Figure out what sort of media we have by checking the
1833 * hardware config word in the first 32k of NIC internal memory,
1834 * or fall back to examining the EEPROM if necessary.
1835 * Note: on some BCM5700 cards, this value appears to be unset.
1836 * If that's the case, we have to rely on identifying the NIC
1837 * by its PCI subsystem ID, as we do below for the SysKonnect
1840 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1841 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1843 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1845 device_printf(dev, "failed to read EEPROM\n");
1849 hwcfg = ntohl(hwcfg);
1852 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1853 sc->bge_flags |= BGE_FLAG_TBI;
1855 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1856 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1857 sc->bge_flags |= BGE_FLAG_TBI;
1859 if (sc->bge_flags & BGE_FLAG_TBI) {
1860 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1861 bge_ifmedia_upd, bge_ifmedia_sts);
1862 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1863 ifmedia_add(&sc->bge_ifmedia,
1864 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1865 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1866 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1867 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
1870 * Do transceiver setup.
1872 if (mii_phy_probe(dev, &sc->bge_miibus,
1873 bge_ifmedia_upd, bge_ifmedia_sts)) {
1874 device_printf(dev, "MII without any PHY!\n");
1881 * When using the BCM5701 in PCI-X mode, data corruption has
1882 * been observed in the first few bytes of some received packets.
1883 * Aligning the packet buffer in memory eliminates the corruption.
1884 * Unfortunately, this misaligns the packet payloads. On platforms
1885 * which do not support unaligned accesses, we will realign the
1886 * payloads by copying the received packets.
1888 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1889 (sc->bge_flags & BGE_FLAG_PCIX))
1890 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
1892 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1893 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1894 sc->bge_link_upd = bge_bcm5700_link_upd;
1895 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
1896 } else if (sc->bge_flags & BGE_FLAG_TBI) {
1897 sc->bge_link_upd = bge_tbi_link_upd;
1898 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1900 sc->bge_link_upd = bge_copper_link_upd;
1901 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1905 * Create sysctl nodes.
1907 sysctl_ctx_init(&sc->bge_sysctl_ctx);
1908 sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
1909 SYSCTL_STATIC_CHILDREN(_hw),
1911 device_get_nameunit(dev),
1913 if (sc->bge_sysctl_tree == NULL) {
1914 device_printf(dev, "can't add sysctl node\n");
1919 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1920 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1921 OID_AUTO, "rx_coal_ticks",
1922 CTLTYPE_INT | CTLFLAG_RW,
1923 sc, 0, bge_sysctl_rx_coal_ticks, "I",
1924 "Receive coalescing ticks (usec).");
1925 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1926 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1927 OID_AUTO, "tx_coal_ticks",
1928 CTLTYPE_INT | CTLFLAG_RW,
1929 sc, 0, bge_sysctl_tx_coal_ticks, "I",
1930 "Transmit coalescing ticks (usec).");
1931 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1932 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1933 OID_AUTO, "rx_max_coal_bds",
1934 CTLTYPE_INT | CTLFLAG_RW,
1935 sc, 0, bge_sysctl_rx_max_coal_bds, "I",
1936 "Receive max coalesced BD count.");
1937 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1938 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1939 OID_AUTO, "tx_max_coal_bds",
1940 CTLTYPE_INT | CTLFLAG_RW,
1941 sc, 0, bge_sysctl_tx_max_coal_bds, "I",
1942 "Transmit max coalesced BD count.");
1945 * Call MI attach routine.
1947 ether_ifattach(ifp, ether_addr, NULL);
1949 error = bus_setup_intr(dev, sc->bge_irq, INTR_NETSAFE,
1950 bge_intr, sc, &sc->bge_intrhand,
1951 ifp->if_serializer);
1953 ether_ifdetach(ifp);
1954 device_printf(dev, "couldn't set up irq\n");
1964 bge_detach(device_t dev)
1966 struct bge_softc *sc = device_get_softc(dev);
1968 if (device_is_attached(dev)) {
1969 struct ifnet *ifp = &sc->arpcom.ac_if;
1971 lwkt_serialize_enter(ifp->if_serializer);
1974 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1975 lwkt_serialize_exit(ifp->if_serializer);
1977 ether_ifdetach(ifp);
1980 if (sc->bge_flags & BGE_FLAG_TBI)
1981 ifmedia_removeall(&sc->bge_ifmedia);
1983 device_delete_child(dev, sc->bge_miibus);
1984 bus_generic_detach(dev);
1986 if (sc->bge_irq != NULL)
1987 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1989 if (sc->bge_res != NULL)
1990 bus_release_resource(dev, SYS_RES_MEMORY,
1991 BGE_PCI_BAR0, sc->bge_res);
1993 if (sc->bge_sysctl_tree != NULL)
1994 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2002 bge_reset(struct bge_softc *sc)
2005 uint32_t cachesize, command, pcistate, reset;
2006 void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2011 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc)) {
2012 if (sc->bge_flags & BGE_FLAG_PCIE)
2013 write_op = bge_writemem_direct;
2015 write_op = bge_writemem_ind;
2017 write_op = bge_writereg_ind;
2020 /* Save some important PCI state. */
2021 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2022 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2023 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2025 pci_write_config(dev, BGE_PCI_MISC_CTL,
2026 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2027 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2029 /* Disable fastboot on controllers that support it. */
2030 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2031 sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2032 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2034 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2035 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2039 * Write the magic number to SRAM at offset 0xB50.
2040 * When firmware finishes its initialization it will
2041 * write ~BGE_MAGIC_NUMBER to the same location.
2043 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2045 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2047 /* XXX: Broadcom Linux driver. */
2048 if (sc->bge_flags & BGE_FLAG_PCIE) {
2049 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */
2050 CSR_WRITE_4(sc, 0x7e2c, 0x20);
2051 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2052 /* Prevent PCIE link training during global reset */
2053 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2059 * Set GPHY Power Down Override to leave GPHY
2060 * powered up in D0 uninitialized.
2062 if (BGE_IS_5705_PLUS(sc))
2063 reset |= 0x04000000;
2065 /* Issue global reset */
2066 write_op(sc, BGE_MISC_CFG, reset);
2070 /* XXX: Broadcom Linux driver. */
2071 if (sc->bge_flags & BGE_FLAG_PCIE) {
2072 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2075 DELAY(500000); /* wait for link training to complete */
2076 v = pci_read_config(dev, 0xc4, 4);
2077 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2080 * Set PCIE max payload size to 128 bytes and
2081 * clear error status.
2083 pci_write_config(dev, 0xd8, 0xf5000, 4);
2086 /* Reset some of the PCI state that got zapped by reset */
2087 pci_write_config(dev, BGE_PCI_MISC_CTL,
2088 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2089 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2090 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2091 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2092 write_op(sc, BGE_MISC_CFG, (65 << 1));
2094 /* Enable memory arbiter. */
2095 if (BGE_IS_5714_FAMILY(sc)) {
2098 val = CSR_READ_4(sc, BGE_MARB_MODE);
2099 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2101 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2105 * Poll until we see the 1's complement of the magic number.
2106 * This indicates that the firmware initialization
2109 for (i = 0; i < BGE_TIMEOUT; i++) {
2110 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2111 if (val == ~BGE_MAGIC_NUMBER)
2116 if (i == BGE_TIMEOUT) {
2117 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out,"
2118 "found 0x%08x\n", val);
2123 * XXX Wait for the value of the PCISTATE register to
2124 * return to its original pre-reset state. This is a
2125 * fairly good indicator of reset completion. If we don't
2126 * wait for the reset to fully complete, trying to read
2127 * from the device's non-PCI registers may yield garbage
2130 for (i = 0; i < BGE_TIMEOUT; i++) {
2131 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2136 if (sc->bge_flags & BGE_FLAG_PCIE) {
2137 reset = bge_readmem_ind(sc, 0x7c00);
2138 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2141 /* Fix up byte swapping */
2142 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2143 BGE_MODECTL_BYTESWAP_DATA);
2145 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2148 * The 5704 in TBI mode apparently needs some special
2149 * adjustment to insure the SERDES drive level is set
2152 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2153 (sc->bge_flags & BGE_FLAG_TBI)) {
2156 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2157 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2158 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2161 /* XXX: Broadcom Linux driver. */
2162 if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2163 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2166 v = CSR_READ_4(sc, 0x7c00);
2167 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2174 * Frame reception handling. This is called if there's a frame
2175 * on the receive return list.
2177 * Note: we have to be able to handle two possibilities here:
2178 * 1) the frame is from the jumbo recieve ring
2179 * 2) the frame is from the standard receive ring
2183 bge_rxeof(struct bge_softc *sc)
2186 int stdcnt = 0, jumbocnt = 0;
2188 if (sc->bge_rx_saved_considx ==
2189 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2192 ifp = &sc->arpcom.ac_if;
2194 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2195 sc->bge_cdata.bge_rx_return_ring_map,
2196 BUS_DMASYNC_POSTREAD);
2197 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2198 sc->bge_cdata.bge_rx_std_ring_map,
2199 BUS_DMASYNC_POSTREAD);
2200 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2201 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2202 sc->bge_cdata.bge_rx_jumbo_ring_map,
2203 BUS_DMASYNC_POSTREAD);
2206 while (sc->bge_rx_saved_considx !=
2207 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2208 struct bge_rx_bd *cur_rx;
2210 struct mbuf *m = NULL;
2211 uint16_t vlan_tag = 0;
2215 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2217 rxidx = cur_rx->bge_idx;
2218 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2221 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2223 vlan_tag = cur_rx->bge_vlan_tag;
2226 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2227 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2228 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2229 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2231 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2233 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2236 if (bge_newbuf_jumbo(sc,
2237 sc->bge_jumbo, NULL) == ENOBUFS) {
2239 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2243 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2244 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2245 sc->bge_cdata.bge_rx_std_dmamap[rxidx],
2246 BUS_DMASYNC_POSTREAD);
2247 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2248 sc->bge_cdata.bge_rx_std_dmamap[rxidx]);
2249 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2250 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2252 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2254 bge_newbuf_std(sc, sc->bge_std, m);
2257 if (bge_newbuf_std(sc, sc->bge_std,
2260 bge_newbuf_std(sc, sc->bge_std, m);
2268 * The i386 allows unaligned accesses, but for other
2269 * platforms we must make sure the payload is aligned.
2271 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2272 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2274 m->m_data += ETHER_ALIGN;
2277 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2278 m->m_pkthdr.rcvif = ifp;
2280 if (ifp->if_capenable & IFCAP_RXCSUM) {
2281 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2282 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2283 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2284 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2286 if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2287 m->m_pkthdr.len >= BGE_MIN_FRAME) {
2288 m->m_pkthdr.csum_data =
2289 cur_rx->bge_tcp_udp_csum;
2290 m->m_pkthdr.csum_flags |=
2291 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2296 * If we received a packet with a vlan tag, pass it
2297 * to vlan_input() instead of ether_input().
2300 VLAN_INPUT_TAG(m, vlan_tag);
2301 have_tag = vlan_tag = 0;
2303 ifp->if_input(ifp, m);
2308 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2309 sc->bge_cdata.bge_rx_std_ring_map,
2310 BUS_DMASYNC_PREWRITE);
2313 if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) {
2314 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2315 sc->bge_cdata.bge_rx_jumbo_ring_map,
2316 BUS_DMASYNC_PREWRITE);
2319 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2321 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2323 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2327 bge_txeof(struct bge_softc *sc)
2329 struct bge_tx_bd *cur_tx = NULL;
2332 if (sc->bge_tx_saved_considx ==
2333 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2336 ifp = &sc->arpcom.ac_if;
2338 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
2339 sc->bge_cdata.bge_tx_ring_map,
2340 BUS_DMASYNC_POSTREAD);
2343 * Go through our tx ring and free mbufs for those
2344 * frames that have been sent.
2346 while (sc->bge_tx_saved_considx !=
2347 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2350 idx = sc->bge_tx_saved_considx;
2351 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2352 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2354 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2355 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2356 sc->bge_cdata.bge_tx_dmamap[idx],
2357 BUS_DMASYNC_POSTWRITE);
2358 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2359 sc->bge_cdata.bge_tx_dmamap[idx]);
2360 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2361 sc->bge_cdata.bge_tx_chain[idx] = NULL;
2364 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2368 if (cur_tx != NULL &&
2369 (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2370 (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2371 ifp->if_flags &= ~IFF_OACTIVE;
2373 if (sc->bge_txcnt == 0)
2376 if (!ifq_is_empty(&ifp->if_snd))
2380 #ifdef DEVICE_POLLING
2383 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2385 struct bge_softc *sc = ifp->if_softc;
2390 bge_disable_intr(sc);
2392 case POLL_DEREGISTER:
2393 bge_enable_intr(sc);
2395 case POLL_AND_CHECK_STATUS:
2396 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2397 sc->bge_cdata.bge_status_map,
2398 BUS_DMASYNC_POSTREAD);
2401 * Process link state changes.
2403 status = CSR_READ_4(sc, BGE_MAC_STS);
2404 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2405 sc->bge_link_evt = 0;
2406 sc->bge_link_upd(sc, status);
2410 if (ifp->if_flags & IFF_RUNNING) {
2423 struct bge_softc *sc = xsc;
2424 struct ifnet *ifp = &sc->arpcom.ac_if;
2430 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
2431 * disable interrupts by writing nonzero like we used to, since with
2432 * our current organization this just gives complications and
2433 * pessimizations for re-enabling interrupts. We used to have races
2434 * instead of the necessary complications. Disabling interrupts
2435 * would just reduce the chance of a status update while we are
2436 * running (by switching to the interrupt-mode coalescence
2437 * parameters), but this chance is already very low so it is more
2438 * efficient to get another interrupt than prevent it.
2440 * We do the ack first to ensure another interrupt if there is a
2441 * status update after the ack. We don't check for the status
2442 * changing later because it is more efficient to get another
2443 * interrupt than prevent it, not quite as above (not checking is
2444 * a smaller optimization than not toggling the interrupt enable,
2445 * since checking doesn't involve PCI accesses and toggling require
2446 * the status check). So toggling would probably be a pessimization
2447 * even with MSI. It would only be needed for using a task queue.
2449 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2451 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2452 sc->bge_cdata.bge_status_map,
2453 BUS_DMASYNC_POSTREAD);
2456 * Process link state changes.
2458 status = CSR_READ_4(sc, BGE_MAC_STS);
2459 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2460 sc->bge_link_evt = 0;
2461 sc->bge_link_upd(sc, status);
2464 if (ifp->if_flags & IFF_RUNNING) {
2465 /* Check RX return ring producer/consumer */
2468 /* Check TX ring producer/consumer */
2472 if (sc->bge_coal_chg)
2473 bge_coal_change(sc);
2479 struct bge_softc *sc = xsc;
2480 struct ifnet *ifp = &sc->arpcom.ac_if;
2482 lwkt_serialize_enter(ifp->if_serializer);
2484 if (BGE_IS_5705_PLUS(sc))
2485 bge_stats_update_regs(sc);
2487 bge_stats_update(sc);
2489 if (sc->bge_flags & BGE_FLAG_TBI) {
2491 * Since in TBI mode auto-polling can't be used we should poll
2492 * link status manually. Here we register pending link event
2493 * and trigger interrupt.
2496 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2497 } else if (!sc->bge_link) {
2498 mii_tick(device_get_softc(sc->bge_miibus));
2501 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2503 lwkt_serialize_exit(ifp->if_serializer);
2507 bge_stats_update_regs(struct bge_softc *sc)
2509 struct ifnet *ifp = &sc->arpcom.ac_if;
2510 struct bge_mac_stats_regs stats;
2514 s = (uint32_t *)&stats;
2515 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2516 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2520 ifp->if_collisions +=
2521 (stats.dot3StatsSingleCollisionFrames +
2522 stats.dot3StatsMultipleCollisionFrames +
2523 stats.dot3StatsExcessiveCollisions +
2524 stats.dot3StatsLateCollisions) -
2529 bge_stats_update(struct bge_softc *sc)
2531 struct ifnet *ifp = &sc->arpcom.ac_if;
2534 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2536 #define READ_STAT(sc, stats, stat) \
2537 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2539 ifp->if_collisions +=
2540 (READ_STAT(sc, stats,
2541 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2542 READ_STAT(sc, stats,
2543 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2544 READ_STAT(sc, stats,
2545 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2546 READ_STAT(sc, stats,
2547 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
2553 ifp->if_collisions +=
2554 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2555 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2556 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2557 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2563 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2564 * pointers to descriptors.
2567 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
2569 struct bge_tx_bd *d = NULL;
2570 uint16_t csum_flags = 0;
2571 struct ifvlan *ifv = NULL;
2572 struct bge_dmamap_arg ctx;
2573 bus_dma_segment_t segs[BGE_NSEG_NEW];
2575 int error, maxsegs, idx, i;
2576 struct mbuf *m_head = *m_head0;
2578 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2579 m_head->m_pkthdr.rcvif != NULL &&
2580 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2581 ifv = m_head->m_pkthdr.rcvif->if_softc;
2583 if (m_head->m_pkthdr.csum_flags) {
2584 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2585 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2586 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2587 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2588 if (m_head->m_flags & M_LASTFRAG)
2589 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2590 else if (m_head->m_flags & M_FRAG)
2591 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2595 map = sc->bge_cdata.bge_tx_dmamap[idx];
2597 maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2598 KASSERT(maxsegs >= BGE_NSEG_SPARE,
2599 ("not enough segments %d\n", maxsegs));
2601 if (maxsegs > BGE_NSEG_NEW)
2602 maxsegs = BGE_NSEG_NEW;
2605 * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2606 * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2607 * but when such padded frames employ the bge IP/TCP checksum
2608 * offload, the hardware checksum assist gives incorrect results
2609 * (possibly from incorporating its own padding into the UDP/TCP
2610 * checksum; who knows). If we pad such runts with zeros, the
2611 * onboard checksum comes out correct. We do this by pretending
2612 * the mbuf chain has too many fragments so the coalescing code
2613 * below can assemble the packet into a single buffer that's
2614 * padded out to the mininum frame size.
2616 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2617 m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2620 ctx.bge_segs = segs;
2621 ctx.bge_maxsegs = maxsegs;
2622 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2623 m_head, bge_dma_map_mbuf, &ctx,
2626 if (error == EFBIG || ctx.bge_maxsegs == 0) {
2629 m_new = m_defrag(m_head, MB_DONTWAIT);
2630 if (m_new == NULL) {
2631 if_printf(&sc->arpcom.ac_if,
2632 "could not defrag TX mbuf\n");
2641 * Manually pad short frames, and zero the pad space
2642 * to avoid leaking data.
2644 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2645 m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2646 int pad_len = BGE_MIN_FRAME - m_head->m_pkthdr.len;
2648 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
2650 m_head->m_pkthdr.len += pad_len;
2651 m_head->m_len = m_head->m_pkthdr.len;
2654 ctx.bge_segs = segs;
2655 ctx.bge_maxsegs = maxsegs;
2656 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2657 m_head, bge_dma_map_mbuf, &ctx,
2659 if (error || ctx.bge_maxsegs == 0) {
2660 if_printf(&sc->arpcom.ac_if,
2661 "could not defrag TX mbuf\n");
2667 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
2671 bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE);
2673 for (i = 0; ; i++) {
2674 d = &sc->bge_ldata.bge_tx_ring[idx];
2676 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[i].ds_addr);
2677 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[i].ds_addr);
2678 d->bge_len = segs[i].ds_len;
2679 d->bge_flags = csum_flags;
2681 if (i == ctx.bge_maxsegs - 1)
2683 BGE_INC(idx, BGE_TX_RING_CNT);
2685 /* Mark the last segment as end of packet... */
2686 d->bge_flags |= BGE_TXBDFLAG_END;
2688 /* Set vlan tag to the first segment of the packet. */
2689 d = &sc->bge_ldata.bge_tx_ring[*txidx];
2691 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2692 d->bge_vlan_tag = ifv->ifv_tag;
2694 d->bge_vlan_tag = 0;
2698 * Insure that the map for this transmission is placed at
2699 * the array index of the last descriptor in this chain.
2701 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2702 sc->bge_cdata.bge_tx_dmamap[idx] = map;
2703 sc->bge_cdata.bge_tx_chain[idx] = m_head;
2704 sc->bge_txcnt += ctx.bge_maxsegs;
2706 BGE_INC(idx, BGE_TX_RING_CNT);
2717 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2718 * to the mbuf data regions directly in the transmit descriptors.
2721 bge_start(struct ifnet *ifp)
2723 struct bge_softc *sc = ifp->if_softc;
2724 struct mbuf *m_head = NULL;
2728 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2731 prodidx = sc->bge_tx_prodidx;
2734 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2735 m_head = ifq_poll(&ifp->if_snd);
2741 * The code inside the if() block is never reached since we
2742 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2743 * requests to checksum TCP/UDP in a fragmented packet.
2746 * safety overkill. If this is a fragmented packet chain
2747 * with delayed TCP/UDP checksums, then only encapsulate
2748 * it if we have enough descriptors to handle the entire
2750 * (paranoia -- may not actually be needed)
2752 if (m_head->m_flags & M_FIRSTFRAG &&
2753 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2754 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2755 m_head->m_pkthdr.csum_data + 16) {
2756 ifp->if_flags |= IFF_OACTIVE;
2762 * Sanity check: avoid coming within BGE_NSEG_RSVD
2763 * descriptors of the end of the ring. Also make
2764 * sure there are BGE_NSEG_SPARE descriptors for
2765 * jumbo buffers' defragmentation.
2767 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2768 (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
2769 ifp->if_flags |= IFF_OACTIVE;
2774 * Dequeue the packet before encapsulation, since
2775 * bge_encap() may free the packet if error happens.
2777 ifq_dequeue(&ifp->if_snd, m_head);
2780 * Pack the data into the transmit ring. If we
2781 * don't have room, set the OACTIVE flag and wait
2782 * for the NIC to drain the ring.
2784 if (bge_encap(sc, &m_head, &prodidx)) {
2785 ifp->if_flags |= IFF_OACTIVE;
2790 BPF_MTAP(ifp, m_head);
2797 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2798 /* 5700 b2 errata */
2799 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2800 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2802 sc->bge_tx_prodidx = prodidx;
2805 * Set a timeout in case the chip goes out to lunch.
2813 struct bge_softc *sc = xsc;
2814 struct ifnet *ifp = &sc->arpcom.ac_if;
2817 ASSERT_SERIALIZED(ifp->if_serializer);
2819 if (ifp->if_flags & IFF_RUNNING)
2822 /* Cancel pending I/O and flush buffers. */
2828 * Init the various state machines, ring
2829 * control blocks and firmware.
2831 if (bge_blockinit(sc)) {
2832 if_printf(ifp, "initialization failure\n");
2837 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2838 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2840 /* Load our MAC address. */
2841 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2842 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2843 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2845 /* Enable or disable promiscuous mode as needed. */
2848 /* Program multicast filter. */
2852 bge_init_rx_ring_std(sc);
2855 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2856 * memory to insure that the chip has in fact read the first
2857 * entry of the ring.
2859 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2861 for (i = 0; i < 10; i++) {
2863 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2864 if (v == (MCLBYTES - ETHER_ALIGN))
2868 if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
2871 /* Init jumbo RX ring. */
2872 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2873 bge_init_rx_ring_jumbo(sc);
2875 /* Init our RX return ring index */
2876 sc->bge_rx_saved_considx = 0;
2879 bge_init_tx_ring(sc);
2881 /* Turn on transmitter */
2882 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2884 /* Turn on receiver */
2885 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2887 /* Tell firmware we're alive. */
2888 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2890 /* Enable host interrupts if polling(4) is not enabled. */
2891 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2892 #ifdef DEVICE_POLLING
2893 if (ifp->if_flags & IFF_POLLING)
2894 bge_disable_intr(sc);
2897 bge_enable_intr(sc);
2899 bge_ifmedia_upd(ifp);
2901 ifp->if_flags |= IFF_RUNNING;
2902 ifp->if_flags &= ~IFF_OACTIVE;
2904 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2908 * Set media options.
2911 bge_ifmedia_upd(struct ifnet *ifp)
2913 struct bge_softc *sc = ifp->if_softc;
2915 /* If this is a 1000baseX NIC, enable the TBI port. */
2916 if (sc->bge_flags & BGE_FLAG_TBI) {
2917 struct ifmedia *ifm = &sc->bge_ifmedia;
2919 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2922 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2925 * The BCM5704 ASIC appears to have a special
2926 * mechanism for programming the autoneg
2927 * advertisement registers in TBI mode.
2929 if (!bge_fake_autoneg &&
2930 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2933 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
2934 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
2935 sgdig |= BGE_SGDIGCFG_AUTO |
2936 BGE_SGDIGCFG_PAUSE_CAP |
2937 BGE_SGDIGCFG_ASYM_PAUSE;
2938 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
2939 sgdig | BGE_SGDIGCFG_SEND);
2941 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
2945 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2946 BGE_CLRBIT(sc, BGE_MAC_MODE,
2947 BGE_MACMODE_HALF_DUPLEX);
2949 BGE_SETBIT(sc, BGE_MAC_MODE,
2950 BGE_MACMODE_HALF_DUPLEX);
2957 struct mii_data *mii = device_get_softc(sc->bge_miibus);
2961 if (mii->mii_instance) {
2962 struct mii_softc *miisc;
2964 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2965 mii_phy_reset(miisc);
2973 * Report current media status.
2976 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2978 struct bge_softc *sc = ifp->if_softc;
2980 if (sc->bge_flags & BGE_FLAG_TBI) {
2981 ifmr->ifm_status = IFM_AVALID;
2982 ifmr->ifm_active = IFM_ETHER;
2983 if (CSR_READ_4(sc, BGE_MAC_STS) &
2984 BGE_MACSTAT_TBI_PCS_SYNCHED) {
2985 ifmr->ifm_status |= IFM_ACTIVE;
2987 ifmr->ifm_active |= IFM_NONE;
2991 ifmr->ifm_active |= IFM_1000_SX;
2992 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2993 ifmr->ifm_active |= IFM_HDX;
2995 ifmr->ifm_active |= IFM_FDX;
2997 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3000 ifmr->ifm_active = mii->mii_media_active;
3001 ifmr->ifm_status = mii->mii_media_status;
3006 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3008 struct bge_softc *sc = ifp->if_softc;
3009 struct ifreq *ifr = (struct ifreq *)data;
3010 int mask, error = 0;
3012 ASSERT_SERIALIZED(ifp->if_serializer);
3016 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3017 (BGE_IS_JUMBO_CAPABLE(sc) &&
3018 ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3020 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3021 ifp->if_mtu = ifr->ifr_mtu;
3022 ifp->if_flags &= ~IFF_RUNNING;
3027 if (ifp->if_flags & IFF_UP) {
3028 if (ifp->if_flags & IFF_RUNNING) {
3029 mask = ifp->if_flags ^ sc->bge_if_flags;
3032 * If only the state of the PROMISC flag
3033 * changed, then just use the 'set promisc
3034 * mode' command instead of reinitializing
3035 * the entire NIC. Doing a full re-init
3036 * means reloading the firmware and waiting
3037 * for it to start up, which may take a
3038 * second or two. Similarly for ALLMULTI.
3040 if (mask & IFF_PROMISC)
3042 if (mask & IFF_ALLMULTI)
3048 if (ifp->if_flags & IFF_RUNNING)
3051 sc->bge_if_flags = ifp->if_flags;
3055 if (ifp->if_flags & IFF_RUNNING)
3060 if (sc->bge_flags & BGE_FLAG_TBI) {
3061 error = ifmedia_ioctl(ifp, ifr,
3062 &sc->bge_ifmedia, command);
3064 struct mii_data *mii;
3066 mii = device_get_softc(sc->bge_miibus);
3067 error = ifmedia_ioctl(ifp, ifr,
3068 &mii->mii_media, command);
3072 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3073 if (mask & IFCAP_HWCSUM) {
3074 ifp->if_capenable ^= IFCAP_HWCSUM;
3075 if (IFCAP_HWCSUM & ifp->if_capenable)
3076 ifp->if_hwassist = BGE_CSUM_FEATURES;
3078 ifp->if_hwassist = 0;
3082 error = ether_ioctl(ifp, command, data);
3089 bge_watchdog(struct ifnet *ifp)
3091 struct bge_softc *sc = ifp->if_softc;
3093 if_printf(ifp, "watchdog timeout -- resetting\n");
3095 ifp->if_flags &= ~IFF_RUNNING;
3100 if (!ifq_is_empty(&ifp->if_snd))
3105 * Stop the adapter and free any mbufs allocated to the
3109 bge_stop(struct bge_softc *sc)
3111 struct ifnet *ifp = &sc->arpcom.ac_if;
3112 struct ifmedia_entry *ifm;
3113 struct mii_data *mii = NULL;
3116 ASSERT_SERIALIZED(ifp->if_serializer);
3118 if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
3119 mii = device_get_softc(sc->bge_miibus);
3121 callout_stop(&sc->bge_stat_timer);
3124 * Disable all of the receiver blocks
3126 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3127 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3128 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3129 if (!BGE_IS_5705_PLUS(sc))
3130 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3131 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3132 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3133 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3136 * Disable all of the transmit blocks
3138 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3139 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3140 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3141 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3142 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3143 if (!BGE_IS_5705_PLUS(sc))
3144 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3145 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3148 * Shut down all of the memory managers and related
3151 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3152 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3153 if (!BGE_IS_5705_PLUS(sc))
3154 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3155 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3156 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3157 if (!BGE_IS_5705_PLUS(sc)) {
3158 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3159 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3162 /* Disable host interrupts. */
3163 bge_disable_intr(sc);
3166 * Tell firmware we're shutting down.
3168 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3170 /* Free the RX lists. */
3171 bge_free_rx_ring_std(sc);
3173 /* Free jumbo RX list. */
3174 if (BGE_IS_JUMBO_CAPABLE(sc))
3175 bge_free_rx_ring_jumbo(sc);
3177 /* Free TX buffers. */
3178 bge_free_tx_ring(sc);
3181 * Isolate/power down the PHY, but leave the media selection
3182 * unchanged so that things will be put back to normal when
3183 * we bring the interface back up.
3185 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
3186 itmp = ifp->if_flags;
3187 ifp->if_flags |= IFF_UP;
3188 ifm = mii->mii_media.ifm_cur;
3189 mtmp = ifm->ifm_media;
3190 ifm->ifm_media = IFM_ETHER|IFM_NONE;
3192 ifm->ifm_media = mtmp;
3193 ifp->if_flags = itmp;
3197 sc->bge_coal_chg = 0;
3199 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3201 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3206 * Stop all chip I/O so that the kernel's probe routines don't
3207 * get confused by errant DMAs when rebooting.
3210 bge_shutdown(device_t dev)
3212 struct bge_softc *sc = device_get_softc(dev);
3213 struct ifnet *ifp = &sc->arpcom.ac_if;
3215 lwkt_serialize_enter(ifp->if_serializer);
3218 lwkt_serialize_exit(ifp->if_serializer);
3222 bge_suspend(device_t dev)
3224 struct bge_softc *sc = device_get_softc(dev);
3225 struct ifnet *ifp = &sc->arpcom.ac_if;
3227 lwkt_serialize_enter(ifp->if_serializer);
3229 lwkt_serialize_exit(ifp->if_serializer);
3235 bge_resume(device_t dev)
3237 struct bge_softc *sc = device_get_softc(dev);
3238 struct ifnet *ifp = &sc->arpcom.ac_if;
3240 lwkt_serialize_enter(ifp->if_serializer);
3242 if (ifp->if_flags & IFF_UP) {
3245 if (!ifq_is_empty(&ifp->if_snd))
3249 lwkt_serialize_exit(ifp->if_serializer);
3255 bge_setpromisc(struct bge_softc *sc)
3257 struct ifnet *ifp = &sc->arpcom.ac_if;
3259 if (ifp->if_flags & IFF_PROMISC)
3260 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3262 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3266 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3268 struct bge_dmamap_arg *ctx = arg;
3273 KASSERT(nsegs == 1 && ctx->bge_maxsegs == 1,
3274 ("only one segment is allowed\n"));
3276 ctx->bge_segs[0] = *segs;
3280 bge_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nsegs,
3281 bus_size_t mapsz __unused, int error)
3283 struct bge_dmamap_arg *ctx = arg;
3289 if (nsegs > ctx->bge_maxsegs) {
3290 ctx->bge_maxsegs = 0;
3294 ctx->bge_maxsegs = nsegs;
3295 for (i = 0; i < nsegs; ++i)
3296 ctx->bge_segs[i] = segs[i];
3300 bge_dma_free(struct bge_softc *sc)
3304 /* Destroy RX/TX mbuf DMA stuffs. */
3305 if (sc->bge_cdata.bge_mtag != NULL) {
3306 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3307 if (sc->bge_cdata.bge_rx_std_dmamap[i]) {
3308 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3309 sc->bge_cdata.bge_rx_std_dmamap[i]);
3313 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3314 if (sc->bge_cdata.bge_tx_dmamap[i]) {
3315 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3316 sc->bge_cdata.bge_tx_dmamap[i]);
3319 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3322 /* Destroy standard RX ring */
3323 bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3324 sc->bge_cdata.bge_rx_std_ring_map,
3325 sc->bge_ldata.bge_rx_std_ring);
3327 if (BGE_IS_JUMBO_CAPABLE(sc))
3328 bge_free_jumbo_mem(sc);
3330 /* Destroy RX return ring */
3331 bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3332 sc->bge_cdata.bge_rx_return_ring_map,
3333 sc->bge_ldata.bge_rx_return_ring);
3335 /* Destroy TX ring */
3336 bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3337 sc->bge_cdata.bge_tx_ring_map,
3338 sc->bge_ldata.bge_tx_ring);
3340 /* Destroy status block */
3341 bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3342 sc->bge_cdata.bge_status_map,
3343 sc->bge_ldata.bge_status_block);
3345 /* Destroy statistics block */
3346 bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3347 sc->bge_cdata.bge_stats_map,
3348 sc->bge_ldata.bge_stats);
3350 /* Destroy the parent tag */
3351 if (sc->bge_cdata.bge_parent_tag != NULL)
3352 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3356 bge_dma_alloc(struct bge_softc *sc)
3358 struct ifnet *ifp = &sc->arpcom.ac_if;
3362 * Allocate the parent bus DMA tag appropriate for PCI.
3364 error = bus_dma_tag_create(NULL, 1, 0,
3365 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3367 MAXBSIZE, BGE_NSEG_NEW,
3368 BUS_SPACE_MAXSIZE_32BIT,
3369 0, &sc->bge_cdata.bge_parent_tag);
3371 if_printf(ifp, "could not allocate parent dma tag\n");
3376 * Create DMA tag for mbufs.
3378 nseg = BGE_NSEG_NEW;
3379 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3380 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3382 MCLBYTES * nseg, nseg, MCLBYTES,
3383 BUS_DMA_ALLOCNOW, &sc->bge_cdata.bge_mtag);
3385 if_printf(ifp, "could not allocate mbuf dma tag\n");
3390 * Create DMA maps for TX/RX mbufs.
3392 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3393 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3394 &sc->bge_cdata.bge_rx_std_dmamap[i]);
3398 for (j = 0; j < i; ++j) {
3399 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3400 sc->bge_cdata.bge_rx_std_dmamap[j]);
3402 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3403 sc->bge_cdata.bge_mtag = NULL;
3405 if_printf(ifp, "could not create DMA map for RX\n");
3410 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3411 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3412 &sc->bge_cdata.bge_tx_dmamap[i]);
3416 for (j = 0; j < BGE_STD_RX_RING_CNT; ++j) {
3417 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3418 sc->bge_cdata.bge_rx_std_dmamap[j]);
3420 for (j = 0; j < i; ++j) {
3421 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3422 sc->bge_cdata.bge_tx_dmamap[j]);
3424 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3425 sc->bge_cdata.bge_mtag = NULL;
3427 if_printf(ifp, "could not create DMA map for TX\n");
3433 * Create DMA stuffs for standard RX ring.
3435 error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3436 &sc->bge_cdata.bge_rx_std_ring_tag,
3437 &sc->bge_cdata.bge_rx_std_ring_map,
3438 (void **)&sc->bge_ldata.bge_rx_std_ring,
3439 &sc->bge_ldata.bge_rx_std_ring_paddr);
3441 if_printf(ifp, "could not create std RX ring\n");
3446 * Create jumbo buffer pool.
3448 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3449 error = bge_alloc_jumbo_mem(sc);
3451 if_printf(ifp, "could not create jumbo buffer pool\n");
3457 * Create DMA stuffs for RX return ring.
3459 error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3460 &sc->bge_cdata.bge_rx_return_ring_tag,
3461 &sc->bge_cdata.bge_rx_return_ring_map,
3462 (void **)&sc->bge_ldata.bge_rx_return_ring,
3463 &sc->bge_ldata.bge_rx_return_ring_paddr);
3465 if_printf(ifp, "could not create RX ret ring\n");
3470 * Create DMA stuffs for TX ring.
3472 error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3473 &sc->bge_cdata.bge_tx_ring_tag,
3474 &sc->bge_cdata.bge_tx_ring_map,
3475 (void **)&sc->bge_ldata.bge_tx_ring,
3476 &sc->bge_ldata.bge_tx_ring_paddr);
3478 if_printf(ifp, "could not create TX ring\n");
3483 * Create DMA stuffs for status block.
3485 error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3486 &sc->bge_cdata.bge_status_tag,
3487 &sc->bge_cdata.bge_status_map,
3488 (void **)&sc->bge_ldata.bge_status_block,
3489 &sc->bge_ldata.bge_status_block_paddr);
3491 if_printf(ifp, "could not create status block\n");
3496 * Create DMA stuffs for statistics block.
3498 error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3499 &sc->bge_cdata.bge_stats_tag,
3500 &sc->bge_cdata.bge_stats_map,
3501 (void **)&sc->bge_ldata.bge_stats,
3502 &sc->bge_ldata.bge_stats_paddr);
3504 if_printf(ifp, "could not create stats block\n");
3511 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3512 bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3514 struct ifnet *ifp = &sc->arpcom.ac_if;
3515 struct bge_dmamap_arg ctx;
3516 bus_dma_segment_t seg;
3522 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3523 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3524 NULL, NULL, size, 1, size, 0, tag);
3526 if_printf(ifp, "could not allocate dma tag\n");
3531 * Allocate DMA'able memory
3533 error = bus_dmamem_alloc(*tag, addr, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3536 if_printf(ifp, "could not allocate dma memory\n");
3537 bus_dma_tag_destroy(*tag);
3543 * Load the DMA'able memory
3545 ctx.bge_maxsegs = 1;
3546 ctx.bge_segs = &seg;
3547 error = bus_dmamap_load(*tag, *map, *addr, size, bge_dma_map_addr, &ctx,
3550 if_printf(ifp, "could not load dma memory\n");
3551 bus_dmamem_free(*tag, *addr, *map);
3552 bus_dma_tag_destroy(*tag);
3556 *paddr = ctx.bge_segs[0].ds_addr;
3562 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3565 bus_dmamap_unload(tag, map);
3566 bus_dmamem_free(tag, addr, map);
3567 bus_dma_tag_destroy(tag);
3572 * Grrr. The link status word in the status block does
3573 * not work correctly on the BCM5700 rev AX and BX chips,
3574 * according to all available information. Hence, we have
3575 * to enable MII interrupts in order to properly obtain
3576 * async link changes. Unfortunately, this also means that
3577 * we have to read the MAC status register to detect link
3578 * changes, thereby adding an additional register access to
3579 * the interrupt handler.
3581 * XXX: perhaps link state detection procedure used for
3582 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3585 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3587 struct ifnet *ifp = &sc->arpcom.ac_if;
3588 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3592 if (!sc->bge_link &&
3593 (mii->mii_media_status & IFM_ACTIVE) &&
3594 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3597 if_printf(ifp, "link UP\n");
3598 } else if (sc->bge_link &&
3599 (!(mii->mii_media_status & IFM_ACTIVE) ||
3600 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3603 if_printf(ifp, "link DOWN\n");
3606 /* Clear the interrupt. */
3607 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
3608 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
3609 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
3613 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
3615 struct ifnet *ifp = &sc->arpcom.ac_if;
3617 #define PCS_ENCODE_ERR (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3620 * Sometimes PCS encoding errors are detected in
3621 * TBI mode (on fiber NICs), and for some reason
3622 * the chip will signal them as link changes.
3623 * If we get a link change event, but the 'PCS
3624 * encoding error' bit in the MAC status register
3625 * is set, don't bother doing a link check.
3626 * This avoids spurious "gigabit link up" messages
3627 * that sometimes appear on fiber NICs during
3628 * periods of heavy traffic.
3630 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3631 if (!sc->bge_link) {
3633 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3634 BGE_CLRBIT(sc, BGE_MAC_MODE,
3635 BGE_MACMODE_TBI_SEND_CFGS);
3637 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3640 if_printf(ifp, "link UP\n");
3642 ifp->if_link_state = LINK_STATE_UP;
3643 if_link_state_change(ifp);
3645 } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3650 if_printf(ifp, "link DOWN\n");
3652 ifp->if_link_state = LINK_STATE_DOWN;
3653 if_link_state_change(ifp);
3657 #undef PCS_ENCODE_ERR
3659 /* Clear the attention. */
3660 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3661 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3662 BGE_MACSTAT_LINK_CHANGED);
3666 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
3669 * Check that the AUTOPOLL bit is set before
3670 * processing the event as a real link change.
3671 * Turning AUTOPOLL on and off in the MII read/write
3672 * functions will often trigger a link status
3673 * interrupt for no reason.
3675 if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
3676 struct ifnet *ifp = &sc->arpcom.ac_if;
3677 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3681 if (!sc->bge_link &&
3682 (mii->mii_media_status & IFM_ACTIVE) &&
3683 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3686 if_printf(ifp, "link UP\n");
3687 } else if (sc->bge_link &&
3688 (!(mii->mii_media_status & IFM_ACTIVE) ||
3689 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3692 if_printf(ifp, "link DOWN\n");
3696 /* Clear the attention. */
3697 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3698 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3699 BGE_MACSTAT_LINK_CHANGED);
3703 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3705 struct bge_softc *sc = arg1;
3707 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3708 &sc->bge_rx_coal_ticks,
3709 BGE_RX_COAL_TICKS_CHG);
3713 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3715 struct bge_softc *sc = arg1;
3717 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3718 &sc->bge_tx_coal_ticks,
3719 BGE_TX_COAL_TICKS_CHG);
3723 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3725 struct bge_softc *sc = arg1;
3727 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3728 &sc->bge_rx_max_coal_bds,
3729 BGE_RX_MAX_COAL_BDS_CHG);
3733 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3735 struct bge_softc *sc = arg1;
3737 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3738 &sc->bge_tx_max_coal_bds,
3739 BGE_TX_MAX_COAL_BDS_CHG);
3743 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3744 uint32_t coal_chg_mask)
3746 struct bge_softc *sc = arg1;
3747 struct ifnet *ifp = &sc->arpcom.ac_if;
3750 lwkt_serialize_enter(ifp->if_serializer);
3753 error = sysctl_handle_int(oidp, &v, 0, req);
3754 if (!error && req->newptr != NULL) {
3759 sc->bge_coal_chg |= coal_chg_mask;
3763 lwkt_serialize_exit(ifp->if_serializer);
3768 bge_coal_change(struct bge_softc *sc)
3770 struct ifnet *ifp = &sc->arpcom.ac_if;
3773 ASSERT_SERIALIZED(ifp->if_serializer);
3775 if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
3776 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3777 sc->bge_rx_coal_ticks);
3779 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3782 if_printf(ifp, "rx_coal_ticks -> %u\n",
3783 sc->bge_rx_coal_ticks);
3787 if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
3788 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3789 sc->bge_tx_coal_ticks);
3791 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3794 if_printf(ifp, "tx_coal_ticks -> %u\n",
3795 sc->bge_tx_coal_ticks);
3799 if (sc->bge_coal_chg & BGE_RX_MAX_COAL_BDS_CHG) {
3800 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3801 sc->bge_rx_max_coal_bds);
3803 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3806 if_printf(ifp, "rx_max_coal_bds -> %u\n",
3807 sc->bge_rx_max_coal_bds);
3811 if (sc->bge_coal_chg & BGE_TX_MAX_COAL_BDS_CHG) {
3812 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3813 sc->bge_tx_max_coal_bds);
3815 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3818 if_printf(ifp, "tx_max_coal_bds -> %u\n",
3819 sc->bge_tx_max_coal_bds);
3823 sc->bge_coal_chg = 0;
3827 bge_enable_intr(struct bge_softc *sc)
3829 struct ifnet *ifp = &sc->arpcom.ac_if;
3831 lwkt_serialize_handler_enable(ifp->if_serializer);
3836 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
3839 * Unmask the interrupt when we stop polling.
3841 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3844 * Trigger another interrupt, since above writing
3845 * to interrupt mailbox0 may acknowledge pending
3848 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3852 bge_disable_intr(struct bge_softc *sc)
3854 struct ifnet *ifp = &sc->arpcom.ac_if;
3857 * Mask the interrupt when we start polling.
3859 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3862 * Acknowledge possible asserted interrupt.
3864 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3866 lwkt_serialize_handler_disable(ifp->if_serializer);