sys/dev/serial/rc/rc.c

   1 /*
   2  * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
   3  * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD: src/sys/i386/isa/rc.c,v 1.53.2.1 2001/02/26 04:23:10 jlemon Exp $
  28  * $DragonFly: src/sys/dev/serial/rc/rc.c,v 1.2 2003/06/17 04:28:37 dillon Exp $
  29  *
  30  */
  31
  32 /*
  33  * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver
  34  *
  35  */
  36
  37 #include "rc.h"
  38
  39 /*#define RCDEBUG*/
  40
  41 #include <sys/param.h>
  42 #include <sys/systm.h>
  43 #include <sys/tty.h>
  44 #include <sys/proc.h>
  45 #include <sys/conf.h>
  46 #include <sys/dkstat.h>
  47 #include <sys/fcntl.h>
  48 #include <sys/interrupt.h>
  49 #include <sys/kernel.h>
  50 #include <machine/clock.h>
  51 #include <machine/ipl.h>
  52
  53 #include <i386/isa/isa_device.h>
  54
  55 #include <i386/isa/ic/cd180.h>
  56 #include <i386/isa/rcreg.h>
  57
  58 /* Prototypes */
  59 static int     rcprobe         __P((struct isa_device *));
  60 static int     rcattach        __P((struct isa_device *));
  61
  62 #define rcin(port)      RC_IN  (nec, port)
  63 #define rcout(port,v)   RC_OUT (nec, port, v)
  64
  65 #define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__)
  66 #define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd))
  67
  68 #define RC_IBUFSIZE     256
  69 #define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE)
  70 #define RC_OBUFSIZE     512
  71 #define RC_IHIGHWATER   (3 * RC_IBUFSIZE / 4)
  72 #define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE)
  73 #define LOTS_OF_EVENTS  64
  74
  75 #define RC_FAKEID       0x10
  76
  77 #define RC_PROBED 1
  78 #define RC_ATTACHED 2
  79
  80 #define GET_UNIT(dev)   (minor(dev) & 0x3F)
  81 #define CALLOUT(dev)    (minor(dev) & 0x80)
  82
  83 /* For isa routines */
  84 struct isa_driver rcdriver = {
  85         rcprobe, rcattach, "rc"
  86 };
  87
  88 static  d_open_t        rcopen;
  89 static  d_close_t       rcclose;
  90 static  d_ioctl_t       rcioctl;
  91
  92 #define CDEV_MAJOR      63
  93 static struct cdevsw rc_cdevsw = {
  94         /* open */      rcopen,
  95         /* close */     rcclose,
  96         /* read */      ttyread,
  97         /* write */     ttywrite,
  98         /* ioctl */     rcioctl,
  99         /* poll */      ttypoll,
 100         /* mmap */      nommap,
 101         /* strategy */  nostrategy,
 102         /* name */      "rc",
 103         /* maj */       CDEV_MAJOR,
 104         /* dump */      nodump,
 105         /* psize */     nopsize,
 106         /* flags */     D_TTY | D_KQFILTER,
 107         /* bmaj */      -1,
 108         /* kqfilter */  ttykqfilter,
 109 };
 110
 111 /* Per-board structure */
 112 static struct rc_softc {
 113         u_int           rcb_probed;     /* 1 - probed, 2 - attached */
 114         u_int           rcb_addr;       /* Base I/O addr        */
 115         u_int           rcb_unit;       /* unit #               */
 116         u_char          rcb_dtr;        /* DTR status           */
 117         struct rc_chans *rcb_baserc;    /* base rc ptr          */
 118 } rc_softc[NRC];
 119
 120 /* Per-channel structure */
 121 static struct rc_chans  {
 122         struct rc_softc *rc_rcb;                /* back ptr             */
 123         u_short          rc_flags;              /* Misc. flags          */
 124         int              rc_chan;               /* Channel #            */
 125         u_char           rc_ier;                /* intr. enable reg     */
 126         u_char           rc_msvr;               /* modem sig. status    */
 127         u_char           rc_cor2;               /* options reg          */
 128         u_char           rc_pendcmd;            /* special cmd pending  */
 129         u_int            rc_dtrwait;            /* dtr timeout          */
 130         u_int            rc_dcdwaits;           /* how many waits DCD in open */
 131         u_char           rc_hotchar;            /* end packed optimize */
 132         struct tty      *rc_tp;                 /* tty struct           */
 133         u_char          *rc_iptr;               /* Chars input buffer         */
 134         u_char          *rc_hiwat;              /* hi-water mark        */
 135         u_char          *rc_bufend;             /* end of buffer        */
 136         u_char          *rc_optr;               /* ptr in output buf    */
 137         u_char          *rc_obufend;            /* end of output buf    */
 138         u_char           rc_ibuf[4 * RC_IBUFSIZE];  /* input buffer         */
 139         u_char           rc_obuf[RC_OBUFSIZE];  /* output buffer        */
 140 } rc_chans[NRC * CD180_NCHAN];
 141
 142 static int rc_scheduled_event = 0;
 143
 144 /* for pstat -t */
 145 static struct tty rc_tty[NRC * CD180_NCHAN];
 146 static const int  nrc_tty = NRC * CD180_NCHAN;
 147
 148 /* Flags */
 149 #define RC_DTR_OFF      0x0001          /* DTR wait, for close/open     */
 150 #define RC_ACTOUT       0x0002          /* Dial-out port active         */
 151 #define RC_RTSFLOW      0x0004          /* RTS flow ctl enabled         */
 152 #define RC_CTSFLOW      0x0008          /* CTS flow ctl enabled         */
 153 #define RC_DORXFER      0x0010          /* RXFER event planned          */
 154 #define RC_DOXXFER      0x0020          /* XXFER event planned          */
 155 #define RC_MODCHG       0x0040          /* Modem status changed         */
 156 #define RC_OSUSP        0x0080          /* Output suspended             */
 157 #define RC_OSBUSY       0x0100          /* start() routine in progress  */
 158 #define RC_WAS_BUFOVFL  0x0200          /* low-level buffer ovferflow   */
 159 #define RC_WAS_SILOVFL  0x0400          /* silo buffer overflow         */
 160 #define RC_SEND_RDY     0x0800          /* ready to send */
 161
 162 /* Table for translation of RCSR status bits to internal form */
 163 static int rc_rcsrt[16] = {
 164         0,             TTY_OE,               TTY_FE,
 165         TTY_FE|TTY_OE, TTY_PE,               TTY_PE|TTY_OE,
 166         TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI,
 167         TTY_BI|TTY_OE, TTY_BI|TTY_FE,        TTY_BI|TTY_FE|TTY_OE,
 168         TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE,
 169         TTY_BI|TTY_PE|TTY_FE|TTY_OE
 170 };
 171
 172 /* Static prototypes */
 173 static ointhand2_t rcintr;
 174 static void rc_hwreset          __P((int, int, unsigned int));
 175 static int  rc_test             __P((int, int));
 176 static void rc_discard_output   __P((struct rc_chans *));
 177 static void rc_hardclose        __P((struct rc_chans *));
 178 static int  rc_modctl           __P((struct rc_chans *, int, int));
 179 static void rc_start            __P((struct tty *));
 180 static void rc_stop              __P((struct tty *, int rw));
 181 static int  rc_param            __P((struct tty *, struct termios *));
 182 static swihand_t rcpoll;
 183 static void rc_reinit           __P((struct rc_softc *));
 184 #ifdef RCDEBUG
 185 static void printrcflags();
 186 #endif
 187 static timeout_t rc_dtrwakeup;
 188 static timeout_t rc_wakeup;
 189 static void disc_optim          __P((struct tty *tp, struct termios *t, struct rc_chans *));
 190 static void rc_wait0            __P((int nec, int unit, int chan, int line));
 191
 192 /**********************************************/
 193
 194 /* Quick device probing */
 195 static int
 196 rcprobe(dvp)
 197         struct  isa_device      *dvp;
 198 {
 199         int             irq = ffs(dvp->id_irq) - 1;
 200         register int    nec = dvp->id_iobase;
 201
 202         if (dvp->id_unit > NRC)
 203                 return 0;
 204         if (!RC_VALIDADDR(nec)) {
 205                 printf("rc%d: illegal base address %x\n", dvp->id_unit, nec);
 206                 return 0;
 207         }
 208         if (!RC_VALIDIRQ(irq)) {
 209                 printf("rc%d: illegal IRQ value %d\n", dvp->id_unit, irq);
 210                 return 0;
 211         }
 212         rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */
 213         rcout(CD180_PPRH, 0x11);
 214         if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11)
 215                 return 0;
 216         /* Now, test the board more thoroughly, with diagnostic */
 217         if (rc_test(nec, dvp->id_unit))
 218                 return 0;
 219         rc_softc[dvp->id_unit].rcb_probed = RC_PROBED;
 220
 221         return 0xF;
 222 }
 223
 224 static int
 225 rcattach(dvp)
 226         struct  isa_device      *dvp;
 227 {
 228         register int            chan, nec = dvp->id_iobase;
 229         struct rc_softc         *rcb = &rc_softc[dvp->id_unit];
 230         struct rc_chans         *rc  = &rc_chans[dvp->id_unit * CD180_NCHAN];
 231         static int              rc_started = 0;
 232         struct tty              *tp;
 233
 234         dvp->id_ointr = rcintr;
 235
 236         /* Thorooughly test the device */
 237         if (rcb->rcb_probed != RC_PROBED)
 238                 return 0;
 239         rcb->rcb_addr   = nec;
 240         rcb->rcb_dtr    = 0;
 241         rcb->rcb_baserc = rc;
 242         rcb->rcb_unit   = dvp->id_unit;
 243         /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/
 244         printf("rc%d: %d chans, firmware rev. %c\n", rcb->rcb_unit,
 245                 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A');
 246
 247         for (chan = 0; chan < CD180_NCHAN; chan++, rc++) {
 248                 rc->rc_rcb     = rcb;
 249                 rc->rc_chan    = chan;
 250                 rc->rc_iptr    = rc->rc_ibuf;
 251                 rc->rc_bufend  = &rc->rc_ibuf[RC_IBUFSIZE];
 252                 rc->rc_hiwat   = &rc->rc_ibuf[RC_IHIGHWATER];
 253                 rc->rc_flags   = rc->rc_ier = rc->rc_msvr = 0;
 254                 rc->rc_cor2    = rc->rc_pendcmd = 0;
 255                 rc->rc_optr    = rc->rc_obufend  = rc->rc_obuf;
 256                 rc->rc_dtrwait = 3 * hz;
 257                 rc->rc_dcdwaits= 0;
 258                 rc->rc_hotchar = 0;
 259                 tp = rc->rc_tp = &rc_tty[chan + (dvp->id_unit * CD180_NCHAN)];
 260                 ttychars(tp);
 261                 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0;
 262                 tp->t_cflag = TTYDEF_CFLAG;
 263                 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
 264         }
 265         rcb->rcb_probed = RC_ATTACHED;
 266         if (!rc_started) {
 267                 cdevsw_add(&rc_cdevsw);
 268                 register_swi(SWI_TTY, rcpoll);
 269                 rc_wakeup((void *)NULL);
 270                 rc_started = 1;
 271         }
 272         return 1;
 273 }
 274
 275 /* RC interrupt handling */
 276 static void
 277 rcintr(unit)
 278         int             unit;
 279 {
 280         register struct rc_softc        *rcb = &rc_softc[unit];
 281         register struct rc_chans        *rc;
 282         register int                    nec, resid;
 283         register u_char                 val, iack, bsr, ucnt, *optr;
 284         int                             good_data, t_state;
 285
 286         if (rcb->rcb_probed != RC_ATTACHED) {
 287                 printf("rc%d: bogus interrupt\n", unit);
 288                 return;
 289         }
 290         nec = rcb->rcb_addr;
 291
 292         bsr = ~(rcin(RC_BSR));
 293
 294         if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) {
 295                 printf("rc%d: extra interrupt\n", unit);
 296                 rcout(CD180_EOIR, 0);
 297                 return;
 298         }
 299
 300         while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) {
 301 #ifdef RCDEBUG_DETAILED
 302                 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr,
 303                         (bsr & RC_BSR_TOUT)?"TOUT ":"",
 304                         (bsr & RC_BSR_RXINT)?"RXINT ":"",
 305                         (bsr & RC_BSR_TXINT)?"TXINT ":"",
 306                         (bsr & RC_BSR_MOINT)?"MOINT":"");
 307 #endif
 308                 if (bsr & RC_BSR_TOUT) {
 309                         printf("rc%d: hardware failure, reset board\n", unit);
 310                         rcout(RC_CTOUT, 0);
 311                         rc_reinit(rcb);
 312                         return;
 313                 }
 314                 if (bsr & RC_BSR_RXINT) {
 315                         iack = rcin(RC_PILR_RX);
 316                         good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID));
 317                         if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) {
 318                                 printf("rc%d: fake rxint: %02x\n", unit, iack);
 319                                 goto more_intrs;
 320                         }
 321                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
 322                         t_state = rc->rc_tp->t_state;
 323                         /* Do RTS flow control stuff */
 324                         if (  (rc->rc_flags & RC_RTSFLOW)
 325                             || !(t_state & TS_ISOPEN)
 326                            ) {
 327                                 if (  (   !(t_state & TS_ISOPEN)
 328                                        || (t_state & TS_TBLOCK)
 329                                       )
 330                                     && (rc->rc_msvr & MSVR_RTS)
 331                                    )
 332                                         rcout(CD180_MSVR,
 333                                                 rc->rc_msvr &= ~MSVR_RTS);
 334                                 else if (!(rc->rc_msvr & MSVR_RTS))
 335                                         rcout(CD180_MSVR,
 336                                                 rc->rc_msvr |= MSVR_RTS);
 337                         }
 338                         ucnt  = rcin(CD180_RDCR) & 0xF;
 339                         resid = 0;
 340
 341                         if (t_state & TS_ISOPEN) {
 342                                 /* check for input buffer overflow */
 343                                 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) {
 344                                         resid  = ucnt;
 345                                         ucnt   = rc->rc_bufend - rc->rc_iptr;
 346                                         resid -= ucnt;
 347                                         if (!(rc->rc_flags & RC_WAS_BUFOVFL)) {
 348                                                 rc->rc_flags |= RC_WAS_BUFOVFL;
 349                                                 rc_scheduled_event++;
 350                                         }
 351                                 }
 352                                 optr = rc->rc_iptr;
 353                                 /* check foor good data */
 354                                 if (good_data) {
 355                                         while (ucnt-- > 0) {
 356                                                 val = rcin(CD180_RDR);
 357                                                 optr[0] = val;
 358                                                 optr[INPUT_FLAGS_SHIFT] = 0;
 359                                                 optr++;
 360                                                 rc_scheduled_event++;
 361                                                 if (val != 0 && val == rc->rc_hotchar)
 362                                                         setsofttty();
 363                                         }
 364                                 } else {
 365                                         /* Store also status data */
 366                                         while (ucnt-- > 0) {
 367                                                 iack = rcin(CD180_RCSR);
 368                                                 if (iack & RCSR_Timeout)
 369                                                         break;
 370                                                 if (   (iack & RCSR_OE)
 371                                                     && !(rc->rc_flags & RC_WAS_SILOVFL)) {
 372                                                         rc->rc_flags |= RC_WAS_SILOVFL;
 373                                                         rc_scheduled_event++;
 374                                                 }
 375                                                 val = rcin(CD180_RDR);
 376                                                 /*
 377                                                   Don't store PE if IGNPAR and BREAK if IGNBRK,
 378                                                   this hack allows "raw" tty optimization
 379                                                   works even if IGN* is set.
 380                                                 */
 381                                                 if (   !(iack & (RCSR_PE|RCSR_FE|RCSR_Break))
 382                                                     || ((!(iack & (RCSR_PE|RCSR_FE))
 383                                                     ||  !(rc->rc_tp->t_iflag & IGNPAR))
 384                                                     && (!(iack & RCSR_Break)
 385                                                     ||  !(rc->rc_tp->t_iflag & IGNBRK)))) {
 386                                                         if (   (iack & (RCSR_PE|RCSR_FE))
 387                                                             && (t_state & TS_CAN_BYPASS_L_RINT)
 388                                                             && ((iack & RCSR_FE)
 389                                                             ||  ((iack & RCSR_PE)
 390                                                             &&  (rc->rc_tp->t_iflag & INPCK))))
 391                                                                 val = 0;
 392                                                         else if (val != 0 && val == rc->rc_hotchar)
 393                                                                 setsofttty();
 394                                                         optr[0] = val;
 395                                                         optr[INPUT_FLAGS_SHIFT] = iack;
 396                                                         optr++;
 397                                                         rc_scheduled_event++;
 398                                                 }
 399                                         }
 400                                 }
 401                                 rc->rc_iptr = optr;
 402                                 rc->rc_flags |= RC_DORXFER;
 403                         } else
 404                                 resid = ucnt;
 405                         /* Clear FIFO if necessary */
 406                         while (resid-- > 0) {
 407                                 if (!good_data)
 408                                         iack = rcin(CD180_RCSR);
 409                                 else
 410                                         iack = 0;
 411                                 if (iack & RCSR_Timeout)
 412                                         break;
 413                                 (void) rcin(CD180_RDR);
 414                         }
 415                         goto more_intrs;
 416                 }
 417                 if (bsr & RC_BSR_MOINT) {
 418                         iack = rcin(RC_PILR_MODEM);
 419                         if (iack != (GIVR_IT_MSCI | RC_FAKEID)) {
 420                                 printf("rc%d: fake moint: %02x\n", unit, iack);
 421                                 goto more_intrs;
 422                         }
 423                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
 424                         iack = rcin(CD180_MCR);
 425                         rc->rc_msvr = rcin(CD180_MSVR);
 426                         rcout(CD180_MCR, 0);
 427 #ifdef RCDEBUG
 428                         printrcflags(rc, "moint");
 429 #endif
 430                         if (rc->rc_flags & RC_CTSFLOW) {
 431                                 if (rc->rc_msvr & MSVR_CTS)
 432                                         rc->rc_flags |= RC_SEND_RDY;
 433                                 else
 434                                         rc->rc_flags &= ~RC_SEND_RDY;
 435                         } else
 436                                 rc->rc_flags |= RC_SEND_RDY;
 437                         if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) {
 438                                 rc_scheduled_event += LOTS_OF_EVENTS;
 439                                 rc->rc_flags |= RC_MODCHG;
 440                                 setsofttty();
 441                         }
 442                         goto more_intrs;
 443                 }
 444                 if (bsr & RC_BSR_TXINT) {
 445                         iack = rcin(RC_PILR_TX);
 446                         if (iack != (GIVR_IT_TDI | RC_FAKEID)) {
 447                                 printf("rc%d: fake txint: %02x\n", unit, iack);
 448                                 goto more_intrs;
 449                         }
 450                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
 451                         if (    (rc->rc_flags & RC_OSUSP)
 452                             || !(rc->rc_flags & RC_SEND_RDY)
 453                            )
 454                                 goto more_intrs;
 455                         /* Handle breaks and other stuff */
 456                         if (rc->rc_pendcmd) {
 457                                 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC);
 458                                 rcout(CD180_TDR,  CD180_C_ESC);
 459                                 rcout(CD180_TDR,  rc->rc_pendcmd);
 460                                 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC);
 461                                 rc->rc_pendcmd = 0;
 462                                 goto more_intrs;
 463                         }
 464                         optr = rc->rc_optr;
 465                         resid = rc->rc_obufend - optr;
 466                         if (resid > CD180_NFIFO)
 467                                 resid = CD180_NFIFO;
 468                         while (resid-- > 0)
 469                                 rcout(CD180_TDR, *optr++);
 470                         rc->rc_optr = optr;
 471
 472                         /* output completed? */
 473                         if (optr >= rc->rc_obufend) {
 474                                 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy);
 475 #ifdef RCDEBUG
 476                                 printf("rc%d/%d: output completed\n", unit, rc->rc_chan);
 477 #endif
 478                                 if (!(rc->rc_flags & RC_DOXXFER)) {
 479                                         rc_scheduled_event += LOTS_OF_EVENTS;
 480                                         rc->rc_flags |= RC_DOXXFER;
 481                                         setsofttty();
 482                                 }
 483                         }
 484                 }
 485         more_intrs:
 486                 rcout(CD180_EOIR, 0);   /* end of interrupt */
 487                 rcout(RC_CTOUT, 0);
 488                 bsr = ~(rcin(RC_BSR));
 489         }
 490 }
 491
 492 /* Feed characters to output buffer */
 493 static void rc_start(tp)
 494 register struct tty *tp;
 495 {
 496         register struct rc_chans       *rc = &rc_chans[GET_UNIT(tp->t_dev)];
 497         register int                    nec = rc->rc_rcb->rcb_addr, s;
 498
 499         if (rc->rc_flags & RC_OSBUSY)
 500                 return;
 501         s = spltty();
 502         rc->rc_flags |= RC_OSBUSY;
 503         disable_intr();
 504         if (tp->t_state & TS_TTSTOP)
 505                 rc->rc_flags |= RC_OSUSP;
 506         else
 507                 rc->rc_flags &= ~RC_OSUSP;
 508         /* Do RTS flow control stuff */
 509         if (   (rc->rc_flags & RC_RTSFLOW)
 510             && (tp->t_state & TS_TBLOCK)
 511             && (rc->rc_msvr & MSVR_RTS)
 512            ) {
 513                 rcout(CD180_CAR, rc->rc_chan);
 514                 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS);
 515         } else if (!(rc->rc_msvr & MSVR_RTS)) {
 516                 rcout(CD180_CAR, rc->rc_chan);
 517                 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS);
 518         }
 519         enable_intr();
 520         if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP))
 521                 goto out;
 522 #ifdef RCDEBUG
 523         printrcflags(rc, "rcstart");
 524 #endif
 525         ttwwakeup(tp);
 526 #ifdef RCDEBUG
 527         printf("rcstart: outq = %d obuf = %d\n",
 528                 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr);
 529 #endif
 530         if (tp->t_state & TS_BUSY)
 531                 goto    out;    /* output still in progress ... */
 532
 533         if (tp->t_outq.c_cc > 0) {
 534                 u_int   ocnt;
 535
 536                 tp->t_state |= TS_BUSY;
 537                 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf);
 538                 disable_intr();
 539                 rc->rc_optr = rc->rc_obuf;
 540                 rc->rc_obufend = rc->rc_optr + ocnt;
 541                 enable_intr();
 542                 if (!(rc->rc_ier & IER_TxRdy)) {
 543 #ifdef RCDEBUG
 544                         printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan);
 545 #endif
 546                         rcout(CD180_CAR, rc->rc_chan);
 547                         rcout(CD180_IER, rc->rc_ier |= IER_TxRdy);
 548                 }
 549         }
 550 out:
 551         rc->rc_flags &= ~RC_OSBUSY;
 552         (void) splx(s);
 553 }
 554
 555 /* Handle delayed events. */
 556 void rcpoll()
 557 {
 558         register struct rc_chans *rc;
 559         register struct rc_softc *rcb;
 560         register u_char        *tptr, *eptr;
 561         register struct tty    *tp;
 562         register int            chan, icnt, nec, unit;
 563
 564         if (rc_scheduled_event == 0)
 565                 return;
 566 repeat:
 567         for (unit = 0; unit < NRC; unit++) {
 568                 rcb = &rc_softc[unit];
 569                 rc = rcb->rcb_baserc;
 570                 nec = rc->rc_rcb->rcb_addr;
 571                 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) {
 572                         tp = rc->rc_tp;
 573 #ifdef RCDEBUG
 574                         if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG|
 575                             RC_WAS_BUFOVFL|RC_WAS_SILOVFL))
 576                                 printrcflags(rc, "rcevent");
 577 #endif
 578                         if (rc->rc_flags & RC_WAS_BUFOVFL) {
 579                                 disable_intr();
 580                                 rc->rc_flags &= ~RC_WAS_BUFOVFL;
 581                                 rc_scheduled_event--;
 582                                 enable_intr();
 583                                 printf("rc%d/%d: interrupt-level buffer overflow\n",
 584                                         unit, chan);
 585                         }
 586                         if (rc->rc_flags & RC_WAS_SILOVFL) {
 587                                 disable_intr();
 588                                 rc->rc_flags &= ~RC_WAS_SILOVFL;
 589                                 rc_scheduled_event--;
 590                                 enable_intr();
 591                                 printf("rc%d/%d: silo overflow\n",
 592                                         unit, chan);
 593                         }
 594                         if (rc->rc_flags & RC_MODCHG) {
 595                                 disable_intr();
 596                                 rc->rc_flags &= ~RC_MODCHG;
 597                                 rc_scheduled_event -= LOTS_OF_EVENTS;
 598                                 enable_intr();
 599                                 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD));
 600                         }
 601                         if (rc->rc_flags & RC_DORXFER) {
 602                                 disable_intr();
 603                                 rc->rc_flags &= ~RC_DORXFER;
 604                                 eptr = rc->rc_iptr;
 605                                 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE])
 606                                         tptr = &rc->rc_ibuf[RC_IBUFSIZE];
 607                                 else
 608                                         tptr = rc->rc_ibuf;
 609                                 icnt = eptr - tptr;
 610                                 if (icnt > 0) {
 611                                         if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
 612                                                 rc->rc_iptr   = rc->rc_ibuf;
 613                                                 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
 614                                                 rc->rc_hiwat  = &rc->rc_ibuf[RC_IHIGHWATER];
 615                                         } else {
 616                                                 rc->rc_iptr   = &rc->rc_ibuf[RC_IBUFSIZE];
 617                                                 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE];
 618                                                 rc->rc_hiwat  =
 619                                                         &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER];
 620                                         }
 621                                         if (   (rc->rc_flags & RC_RTSFLOW)
 622                                             && (tp->t_state & TS_ISOPEN)
 623                                             && !(tp->t_state & TS_TBLOCK)
 624                                             && !(rc->rc_msvr & MSVR_RTS)
 625                                             ) {
 626                                                 rcout(CD180_CAR, chan);
 627                                                 rcout(CD180_MSVR,
 628                                                         rc->rc_msvr |= MSVR_RTS);
 629                                         }
 630                                         rc_scheduled_event -= icnt;
 631                                 }
 632                                 enable_intr();
 633
 634                                 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN))
 635                                         goto done1;
 636
 637                                 if (   (tp->t_state & TS_CAN_BYPASS_L_RINT)
 638                                     && !(tp->t_state & TS_LOCAL)) {
 639                                         if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER
 640                                             && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF))
 641                                             && !(tp->t_state & TS_TBLOCK))
 642                                                 ttyblock(tp);
 643                                         tk_nin += icnt;
 644                                         tk_rawcc += icnt;
 645                                         tp->t_rawcc += icnt;
 646                                         if (b_to_q(tptr, icnt, &tp->t_rawq))
 647                                                 printf("rc%d/%d: tty-level buffer overflow\n",
 648                                                         unit, chan);
 649                                         ttwakeup(tp);
 650                                         if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY)
 651                                             || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) {
 652                                                 tp->t_state &= ~TS_TTSTOP;
 653                                                 tp->t_lflag &= ~FLUSHO;
 654                                                 rc_start(tp);
 655                                         }
 656                                 } else {
 657                                         for (; tptr < eptr; tptr++)
 658                                                 (*linesw[tp->t_line].l_rint)
 659                                                     (tptr[0] |
 660                                                     rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp);
 661                                 }
 662 done1: ;
 663                         }
 664                         if (rc->rc_flags & RC_DOXXFER) {
 665                                 disable_intr();
 666                                 rc_scheduled_event -= LOTS_OF_EVENTS;
 667                                 rc->rc_flags &= ~RC_DOXXFER;
 668                                 rc->rc_tp->t_state &= ~TS_BUSY;
 669                                 enable_intr();
 670                                 (*linesw[tp->t_line].l_start)(tp);
 671                         }
 672                 }
 673                 if (rc_scheduled_event == 0)
 674                         break;
 675         }
 676         if (rc_scheduled_event >= LOTS_OF_EVENTS)
 677                 goto repeat;
 678 }
 679
 680 static  void
 681 rc_stop(tp, rw)
 682         register struct tty     *tp;
 683         int                     rw;
 684 {
 685         register struct rc_chans        *rc = &rc_chans[GET_UNIT(tp->t_dev)];
 686         u_char *tptr, *eptr;
 687
 688 #ifdef RCDEBUG
 689         printf("rc%d/%d: rc_stop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan,
 690                 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":"");
 691 #endif
 692         if (rw & FWRITE)
 693                 rc_discard_output(rc);
 694         disable_intr();
 695         if (rw & FREAD) {
 696                 rc->rc_flags &= ~RC_DORXFER;
 697                 eptr = rc->rc_iptr;
 698                 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
 699                         tptr = &rc->rc_ibuf[RC_IBUFSIZE];
 700                         rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
 701                 } else {
 702                         tptr = rc->rc_ibuf;
 703                         rc->rc_iptr = rc->rc_ibuf;
 704                 }
 705                 rc_scheduled_event -= eptr - tptr;
 706         }
 707         if (tp->t_state & TS_TTSTOP)
 708                 rc->rc_flags |= RC_OSUSP;
 709         else
 710                 rc->rc_flags &= ~RC_OSUSP;
 711         enable_intr();
 712 }
 713
 714 static  int
 715 rcopen(dev, flag, mode, p)
 716         dev_t           dev;
 717         int             flag, mode;
 718         struct proc    *p;
 719 {
 720         register struct rc_chans *rc;
 721         register struct tty      *tp;
 722         int             unit, nec, s, error = 0;
 723
 724         unit = GET_UNIT(dev);
 725         if (unit >= NRC * CD180_NCHAN)
 726                 return ENXIO;
 727         if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED)
 728                 return ENXIO;
 729         rc  = &rc_chans[unit];
 730         tp  = rc->rc_tp;
 731         dev->si_tty = tp;
 732         nec = rc->rc_rcb->rcb_addr;
 733 #ifdef RCDEBUG
 734         printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
 735 #endif
 736         s = spltty();
 737
 738 again:
 739         while (rc->rc_flags & RC_DTR_OFF) {
 740                 error = tsleep(&(rc->rc_dtrwait), TTIPRI | PCATCH, "rcdtr", 0);
 741                 if (error != 0)
 742                         goto out;
 743         }
 744         if (tp->t_state & TS_ISOPEN) {
 745                 if (CALLOUT(dev)) {
 746                         if (!(rc->rc_flags & RC_ACTOUT)) {
 747                                 error = EBUSY;
 748                                 goto out;
 749                         }
 750                 } else {
 751                         if (rc->rc_flags & RC_ACTOUT) {
 752                                 if (flag & O_NONBLOCK) {
 753                                         error = EBUSY;
 754                                         goto out;
 755                                 }
 756                                 error = tsleep(&rc->rc_rcb,
 757                                      TTIPRI|PCATCH, "rcbi", 0);
 758                                 if (error)
 759                                         goto out;
 760                                 goto again;
 761                         }
 762                 }
 763                 if (tp->t_state & TS_XCLUDE &&
 764                     suser(p)) {
 765                         error = EBUSY;
 766                         goto out;
 767                 }
 768         } else {
 769                 tp->t_oproc   = rc_start;
 770                 tp->t_param   = rc_param;
 771                 tp->t_stop    = rc_stop;
 772                 tp->t_dev     = dev;
 773
 774                 if (CALLOUT(dev))
 775                         tp->t_cflag |= CLOCAL;
 776                 else
 777                         tp->t_cflag &= ~CLOCAL;
 778
 779                 error = rc_param(tp, &tp->t_termios);
 780                 if (error)
 781                         goto out;
 782                 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET);
 783
 784                 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev))
 785                         (*linesw[tp->t_line].l_modem)(tp, 1);
 786         }
 787         if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev)
 788             && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
 789                 rc->rc_dcdwaits++;
 790                 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "rcdcd", 0);
 791                 rc->rc_dcdwaits--;
 792                 if (error != 0)
 793                         goto out;
 794                 goto again;
 795         }
 796         error = (*linesw[tp->t_line].l_open)(dev, tp);
 797         disc_optim(tp, &tp->t_termios, rc);
 798         if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev))
 799                 rc->rc_flags |= RC_ACTOUT;
 800 out:
 801         (void) splx(s);
 802
 803         if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN))
 804                 rc_hardclose(rc);
 805
 806         return error;
 807 }
 808
 809 static  int
 810 rcclose(dev, flag, mode, p)
 811         dev_t           dev;
 812         int             flag, mode;
 813         struct proc    *p;
 814 {
 815         register struct rc_chans *rc;
 816         register struct tty      *tp;
 817         int  s, unit = GET_UNIT(dev);
 818
 819         if (unit >= NRC * CD180_NCHAN)
 820                 return ENXIO;
 821         rc  = &rc_chans[unit];
 822         tp  = rc->rc_tp;
 823 #ifdef RCDEBUG
 824         printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
 825 #endif
 826         s = spltty();
 827         (*linesw[tp->t_line].l_close)(tp, flag);
 828         disc_optim(tp, &tp->t_termios, rc);
 829         rc_stop(tp, FREAD | FWRITE);
 830         rc_hardclose(rc);
 831         ttyclose(tp);
 832         splx(s);
 833         return 0;
 834 }
 835
 836 static void rc_hardclose(rc)
 837 register struct rc_chans *rc;
 838 {
 839         register int s, nec = rc->rc_rcb->rcb_addr;
 840         register struct tty *tp = rc->rc_tp;
 841
 842         s = spltty();
 843         rcout(CD180_CAR, rc->rc_chan);
 844
 845         /* Disable rx/tx intrs */
 846         rcout(CD180_IER, rc->rc_ier = 0);
 847         if (   (tp->t_cflag & HUPCL)
 848             || (!(rc->rc_flags & RC_ACTOUT)
 849                && !(rc->rc_msvr & MSVR_CD)
 850                && !(tp->t_cflag & CLOCAL))
 851             || !(tp->t_state & TS_ISOPEN)
 852            ) {
 853                 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
 854                 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
 855                 (void) rc_modctl(rc, TIOCM_RTS, DMSET);
 856                 if (rc->rc_dtrwait) {
 857                         timeout(rc_dtrwakeup, rc, rc->rc_dtrwait);
 858                         rc->rc_flags |= RC_DTR_OFF;
 859                 }
 860         }
 861         rc->rc_flags &= ~RC_ACTOUT;
 862         wakeup((caddr_t) &rc->rc_rcb);  /* wake bi */
 863         wakeup(TSA_CARR_ON(tp));
 864         (void) splx(s);
 865 }
 866
 867 /* Reset the bastard */
 868 static void rc_hwreset(unit, nec, chipid)
 869         register int    unit, nec;
 870         unsigned int    chipid;
 871 {
 872         CCRCMD(unit, -1, CCR_HWRESET);            /* Hardware reset */
 873         DELAY(20000);
 874         WAITFORCCR(unit, -1);
 875
 876         rcout(RC_CTOUT, 0);             /* Clear timeout  */
 877         rcout(CD180_GIVR,  chipid);
 878         rcout(CD180_GICR,  0);
 879
 880         /* Set Prescaler Registers (1 msec) */
 881         rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF);
 882         rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8);
 883
 884         /* Initialize Priority Interrupt Level Registers */
 885         rcout(CD180_PILR1, RC_PILR_MODEM);
 886         rcout(CD180_PILR2, RC_PILR_TX);
 887         rcout(CD180_PILR3, RC_PILR_RX);
 888
 889         /* Reset DTR */
 890         rcout(RC_DTREG, ~0);
 891 }
 892
 893 /* Set channel parameters */
 894 static int rc_param(tp, ts)
 895         register struct  tty    *tp;
 896         struct termios          *ts;
 897 {
 898         register struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
 899         register int    nec = rc->rc_rcb->rcb_addr;
 900         int      idivs, odivs, s, val, cflag, iflag, lflag, inpflow;
 901
 902         if (   ts->c_ospeed < 0 || ts->c_ospeed > 76800
 903             || ts->c_ispeed < 0 || ts->c_ispeed > 76800
 904            )
 905                 return (EINVAL);
 906         if (ts->c_ispeed == 0)
 907                 ts->c_ispeed = ts->c_ospeed;
 908         odivs = RC_BRD(ts->c_ospeed);
 909         idivs = RC_BRD(ts->c_ispeed);
 910
 911         s = spltty();
 912
 913         /* Select channel */
 914         rcout(CD180_CAR, rc->rc_chan);
 915
 916         /* If speed == 0, hangup line */
 917         if (ts->c_ospeed == 0) {
 918                 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
 919                 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
 920                 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
 921         }
 922
 923         tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
 924         cflag = ts->c_cflag;
 925         iflag = ts->c_iflag;
 926         lflag = ts->c_lflag;
 927
 928         if (idivs > 0) {
 929                 rcout(CD180_RBPRL, idivs & 0xFF);
 930                 rcout(CD180_RBPRH, idivs >> 8);
 931         }
 932         if (odivs > 0) {
 933                 rcout(CD180_TBPRL, odivs & 0xFF);
 934                 rcout(CD180_TBPRH, odivs >> 8);
 935         }
 936
 937         /* set timeout value */
 938         if (ts->c_ispeed > 0) {
 939                 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1;
 940
 941                 if (   !(lflag & ICANON)
 942                     && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0
 943                     && ts->c_cc[VTIME] * 10 > itm)
 944                         itm = ts->c_cc[VTIME] * 10;
 945
 946                 rcout(CD180_RTPR, itm <= 255 ? itm : 255);
 947         }
 948
 949         switch (cflag & CSIZE) {
 950                 case CS5:       val = COR1_5BITS;      break;
 951                 case CS6:       val = COR1_6BITS;      break;
 952                 case CS7:       val = COR1_7BITS;      break;
 953                 default:
 954                 case CS8:       val = COR1_8BITS;      break;
 955         }
 956         if (cflag & PARENB) {
 957                 val |= COR1_NORMPAR;
 958                 if (cflag & PARODD)
 959                         val |= COR1_ODDP;
 960                 if (!(cflag & INPCK))
 961                         val |= COR1_Ignore;
 962         } else
 963                 val |= COR1_Ignore;
 964         if (cflag & CSTOPB)
 965                 val |= COR1_2SB;
 966         rcout(CD180_COR1, val);
 967
 968         /* Set FIFO threshold */
 969         val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2;
 970         inpflow = 0;
 971         if (   (iflag & IXOFF)
 972             && (   ts->c_cc[VSTOP] != _POSIX_VDISABLE
 973                 && (   ts->c_cc[VSTART] != _POSIX_VDISABLE
 974                     || (iflag & IXANY)
 975                    )
 976                )
 977            ) {
 978                 inpflow = 1;
 979                 val |= COR3_SCDE|COR3_FCT;
 980         }
 981         rcout(CD180_COR3, val);
 982
 983         /* Initialize on-chip automatic flow control */
 984         val = 0;
 985         rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY);
 986         if (cflag & CCTS_OFLOW) {
 987                 rc->rc_flags |= RC_CTSFLOW;
 988                 val |= COR2_CtsAE;
 989         } else
 990                 rc->rc_flags |= RC_SEND_RDY;
 991         if (tp->t_state & TS_TTSTOP)
 992                 rc->rc_flags |= RC_OSUSP;
 993         else
 994                 rc->rc_flags &= ~RC_OSUSP;
 995         if (cflag & CRTS_IFLOW)
 996                 rc->rc_flags |= RC_RTSFLOW;
 997         else
 998                 rc->rc_flags &= ~RC_RTSFLOW;
 999
1000         if (inpflow) {
1001                 if (ts->c_cc[VSTART] != _POSIX_VDISABLE)
1002                         rcout(CD180_SCHR1, ts->c_cc[VSTART]);
1003                 rcout(CD180_SCHR2, ts->c_cc[VSTOP]);
1004                 val |= COR2_TxIBE;
1005                 if (iflag & IXANY)
1006                         val |= COR2_IXM;
1007         }
1008
1009         rcout(CD180_COR2, rc->rc_cor2 = val);
1010
1011         CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1012                 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1013
1014         disc_optim(tp, ts, rc);
1015
1016         /* modem ctl */
1017         val = cflag & CLOCAL ? 0 : MCOR1_CDzd;
1018         if (cflag & CCTS_OFLOW)
1019                 val |= MCOR1_CTSzd;
1020         rcout(CD180_MCOR1, val);
1021
1022         val = cflag & CLOCAL ? 0 : MCOR2_CDod;
1023         if (cflag & CCTS_OFLOW)
1024                 val |= MCOR2_CTSod;
1025         rcout(CD180_MCOR2, val);
1026
1027         /* enable i/o and interrupts */
1028         CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1029                 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS));
1030         WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
1031
1032         rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD;
1033         if (cflag & CCTS_OFLOW)
1034                 rc->rc_ier |= IER_CTS;
1035         if (cflag & CREAD)
1036                 rc->rc_ier |= IER_RxData;
1037         if (tp->t_state & TS_BUSY)
1038                 rc->rc_ier |= IER_TxRdy;
1039         if (ts->c_ospeed != 0)
1040                 rc_modctl(rc, TIOCM_DTR, DMBIS);
1041         if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS))
1042                 rc->rc_flags |= RC_SEND_RDY;
1043         rcout(CD180_IER, rc->rc_ier);
1044         (void) splx(s);
1045         return 0;
1046 }
1047
1048 /* Re-initialize board after bogus interrupts */
1049 static void rc_reinit(rcb)
1050 struct rc_softc         *rcb;
1051 {
1052         register struct rc_chans       *rc, *rce;
1053         register int                    nec;
1054
1055         nec = rcb->rcb_addr;
1056         rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID);
1057         rc  = &rc_chans[rcb->rcb_unit * CD180_NCHAN];
1058         rce = rc + CD180_NCHAN;
1059         for (; rc < rce; rc++)
1060                 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios);
1061 }
1062
1063 static  int
1064 rcioctl(dev, cmd, data, flag, p)
1065 dev_t           dev;
1066 u_long          cmd;
1067 int             flag;
1068 caddr_t         data;
1069 struct proc     *p;
1070 {
1071         register struct rc_chans       *rc = &rc_chans[GET_UNIT(dev)];
1072         register int                    s, error;
1073         struct tty                     *tp = rc->rc_tp;
1074
1075         error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
1076         if (error != ENOIOCTL)
1077                 return (error);
1078         error = ttioctl(tp, cmd, data, flag);
1079         disc_optim(tp, &tp->t_termios, rc);
1080         if (error != ENOIOCTL)
1081                 return (error);
1082         s = spltty();
1083
1084         switch (cmd) {
1085             case TIOCSBRK:
1086                 rc->rc_pendcmd = CD180_C_SBRK;
1087                 break;
1088
1089             case TIOCCBRK:
1090                 rc->rc_pendcmd = CD180_C_EBRK;
1091                 break;
1092
1093             case TIOCSDTR:
1094                 (void) rc_modctl(rc, TIOCM_DTR, DMBIS);
1095                 break;
1096
1097             case TIOCCDTR:
1098                 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
1099                 break;
1100
1101             case TIOCMGET:
1102                 *(int *) data = rc_modctl(rc, 0, DMGET);
1103                 break;
1104
1105             case TIOCMSET:
1106                 (void) rc_modctl(rc, *(int *) data, DMSET);
1107                 break;
1108
1109             case TIOCMBIC:
1110                 (void) rc_modctl(rc, *(int *) data, DMBIC);
1111                 break;
1112
1113             case TIOCMBIS:
1114                 (void) rc_modctl(rc, *(int *) data, DMBIS);
1115                 break;
1116
1117             case TIOCMSDTRWAIT:
1118                 error = suser(p);
1119                 if (error != 0) {
1120                         splx(s);
1121                         return (error);
1122                 }
1123                 rc->rc_dtrwait = *(int *)data * hz / 100;
1124                 break;
1125
1126             case TIOCMGDTRWAIT:
1127                 *(int *)data = rc->rc_dtrwait * 100 / hz;
1128                 break;
1129
1130             default:
1131                 (void) splx(s);
1132                 return ENOTTY;
1133         }
1134         (void) splx(s);
1135         return 0;
1136 }
1137
1138
1139 /* Modem control routines */
1140
1141 static int rc_modctl(rc, bits, cmd)
1142 register struct rc_chans       *rc;
1143 int                             bits, cmd;
1144 {
1145         register int    nec = rc->rc_rcb->rcb_addr;
1146         u_char         *dtr = &rc->rc_rcb->rcb_dtr, msvr;
1147
1148         rcout(CD180_CAR, rc->rc_chan);
1149
1150         switch (cmd) {
1151             case DMSET:
1152                 rcout(RC_DTREG, (bits & TIOCM_DTR) ?
1153                                 ~(*dtr |= 1 << rc->rc_chan) :
1154                                 ~(*dtr &= ~(1 << rc->rc_chan)));
1155                 msvr = rcin(CD180_MSVR);
1156                 if (bits & TIOCM_RTS)
1157                         msvr |= MSVR_RTS;
1158                 else
1159                         msvr &= ~MSVR_RTS;
1160                 if (bits & TIOCM_DTR)
1161                         msvr |= MSVR_DTR;
1162                 else
1163                         msvr &= ~MSVR_DTR;
1164                 rcout(CD180_MSVR, msvr);
1165                 break;
1166
1167             case DMBIS:
1168                 if (bits & TIOCM_DTR)
1169                         rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan));
1170                 msvr = rcin(CD180_MSVR);
1171                 if (bits & TIOCM_RTS)
1172                         msvr |= MSVR_RTS;
1173                 if (bits & TIOCM_DTR)
1174                         msvr |= MSVR_DTR;
1175                 rcout(CD180_MSVR, msvr);
1176                 break;
1177
1178             case DMGET:
1179                 bits = TIOCM_LE;
1180                 msvr = rc->rc_msvr = rcin(CD180_MSVR);
1181
1182                 if (msvr & MSVR_RTS)
1183                         bits |= TIOCM_RTS;
1184                 if (msvr & MSVR_CTS)
1185                         bits |= TIOCM_CTS;
1186                 if (msvr & MSVR_DSR)
1187                         bits |= TIOCM_DSR;
1188                 if (msvr & MSVR_DTR)
1189                         bits |= TIOCM_DTR;
1190                 if (msvr & MSVR_CD)
1191                         bits |= TIOCM_CD;
1192                 if (~rcin(RC_RIREG) & (1 << rc->rc_chan))
1193                         bits |= TIOCM_RI;
1194                 return bits;
1195
1196             case DMBIC:
1197                 if (bits & TIOCM_DTR)
1198                         rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan)));
1199                 msvr = rcin(CD180_MSVR);
1200                 if (bits & TIOCM_RTS)
1201                         msvr &= ~MSVR_RTS;
1202                 if (bits & TIOCM_DTR)
1203                         msvr &= ~MSVR_DTR;
1204                 rcout(CD180_MSVR, msvr);
1205                 break;
1206         }
1207         rc->rc_msvr = rcin(CD180_MSVR);
1208         return 0;
1209 }
1210
1211 /* Test the board. */
1212 int rc_test(nec, unit)
1213         register int    nec;
1214         int             unit;
1215 {
1216         int     chan = 0;
1217         int     i = 0, rcnt, old_level;
1218         unsigned int    iack, chipid;
1219         unsigned short  divs;
1220         static  u_char  ctest[] = "\377\125\252\045\244\0\377";
1221 #define CTLEN   8
1222 #define ERR(s)  { \
1223                 printf("rc%d: ", unit); printf s ; printf("\n"); \
1224                 (void) splx(old_level); return 1; }
1225
1226         struct rtest {
1227                 u_char  txbuf[CD180_NFIFO];     /* TX buffer  */
1228                 u_char  rxbuf[CD180_NFIFO];     /* RX buffer  */
1229                 int     rxptr;                  /* RX pointer */
1230                 int     txptr;                  /* TX pointer */
1231         } tchans[CD180_NCHAN];
1232
1233         old_level = spltty();
1234
1235         chipid = RC_FAKEID;
1236
1237         /* First, reset board to inital state */
1238         rc_hwreset(unit, nec, chipid);
1239
1240         divs = RC_BRD(19200);
1241
1242         /* Initialize channels */
1243         for (chan = 0; chan < CD180_NCHAN; chan++) {
1244
1245                 /* Select and reset channel */
1246                 rcout(CD180_CAR, chan);
1247                 CCRCMD(unit, chan, CCR_ResetChan);
1248                 WAITFORCCR(unit, chan);
1249
1250                 /* Set speed */
1251                 rcout(CD180_RBPRL, divs & 0xFF);
1252                 rcout(CD180_RBPRH, divs >> 8);
1253                 rcout(CD180_TBPRL, divs & 0xFF);
1254                 rcout(CD180_TBPRH, divs >> 8);
1255
1256                 /* set timeout value */
1257                 rcout(CD180_RTPR,  0);
1258
1259                 /* Establish local loopback */
1260                 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB);
1261                 rcout(CD180_COR2, COR2_LLM);
1262                 rcout(CD180_COR3, CD180_NFIFO);
1263                 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1264                 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN);
1265                 WAITFORCCR(unit, chan);
1266                 rcout(CD180_MSVR, MSVR_RTS);
1267
1268                 /* Fill TXBUF with test data */
1269                 for (i = 0; i < CD180_NFIFO; i++) {
1270                         tchans[chan].txbuf[i] = ctest[i];
1271                         tchans[chan].rxbuf[i] = 0;
1272                 }
1273                 tchans[chan].txptr = tchans[chan].rxptr = 0;
1274
1275                 /* Now, start transmit */
1276                 rcout(CD180_IER, IER_TxMpty|IER_RxData);
1277         }
1278         /* Pseudo-interrupt poll stuff */
1279         for (rcnt = 10000; rcnt-- > 0; rcnt--) {
1280                 i = ~(rcin(RC_BSR));
1281                 if (i & RC_BSR_TOUT)
1282                         ERR(("BSR timeout bit set\n"))
1283                 else if (i & RC_BSR_TXINT) {
1284                         iack = rcin(RC_PILR_TX);
1285                         if (iack != (GIVR_IT_TDI | chipid))
1286                                 ERR(("Bad TX intr ack (%02x != %02x)\n",
1287                                         iack, GIVR_IT_TDI | chipid));
1288                         chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1289                         /* If no more data to transmit, disable TX intr */
1290                         if (tchans[chan].txptr >= CD180_NFIFO) {
1291                                 iack = rcin(CD180_IER);
1292                                 rcout(CD180_IER, iack & ~IER_TxMpty);
1293                         } else {
1294                                 for (iack = tchans[chan].txptr;
1295                                     iack < CD180_NFIFO; iack++)
1296                                         rcout(CD180_TDR,
1297                                             tchans[chan].txbuf[iack]);
1298                                 tchans[chan].txptr = iack;
1299                         }
1300                         rcout(CD180_EOIR, 0);
1301                 } else if (i & RC_BSR_RXINT) {
1302                         u_char ucnt;
1303
1304                         iack = rcin(RC_PILR_RX);
1305                         if (iack != (GIVR_IT_RGDI | chipid) &&
1306                             iack != (GIVR_IT_REI  | chipid))
1307                                 ERR(("Bad RX intr ack (%02x != %02x)\n",
1308                                         iack, GIVR_IT_RGDI | chipid))
1309                         chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1310                         ucnt = rcin(CD180_RDCR) & 0xF;
1311                         while (ucnt-- > 0) {
1312                                 iack = rcin(CD180_RCSR);
1313                                 if (iack & RCSR_Timeout)
1314                                         break;
1315                                 if (iack & 0xF)
1316                                         ERR(("Bad char chan %d (RCSR = %02X)\n",
1317                                             chan, iack))
1318                                 if (tchans[chan].rxptr > CD180_NFIFO)
1319                                         ERR(("Got extra chars chan %d\n",
1320                                             chan))
1321                                 tchans[chan].rxbuf[tchans[chan].rxptr++] =
1322                                         rcin(CD180_RDR);
1323                         }
1324                         rcout(CD180_EOIR, 0);
1325                 }
1326                 rcout(RC_CTOUT, 0);
1327                 for (iack = chan = 0; chan < CD180_NCHAN; chan++)
1328                         if (tchans[chan].rxptr >= CD180_NFIFO)
1329                                 iack++;
1330                 if (iack == CD180_NCHAN)
1331                         break;
1332         }
1333         for (chan = 0; chan < CD180_NCHAN; chan++) {
1334                 /* Select and reset channel */
1335                 rcout(CD180_CAR, chan);
1336                 CCRCMD(unit, chan, CCR_ResetChan);
1337         }
1338
1339         if (!rcnt)
1340                 ERR(("looses characters during local loopback\n"))
1341         /* Now, check data */
1342         for (chan = 0; chan < CD180_NCHAN; chan++)
1343                 for (i = 0; i < CD180_NFIFO; i++)
1344                         if (ctest[i] != tchans[chan].rxbuf[i])
1345                                 ERR(("data mismatch chan %d ptr %d (%d != %d)\n",
1346                                     chan, i, ctest[i], tchans[chan].rxbuf[i]))
1347         (void) splx(old_level);
1348         return 0;
1349 }
1350
1351 #ifdef RCDEBUG
1352 static void printrcflags(rc, comment)
1353 struct rc_chans  *rc;
1354 char             *comment;
1355 {
1356         u_short f = rc->rc_flags;
1357         register int    nec = rc->rc_rcb->rcb_addr;
1358
1359         printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n",
1360                 rc->rc_rcb->rcb_unit, rc->rc_chan, comment,
1361                 (f & RC_DTR_OFF)?"DTR_OFF " :"",
1362                 (f & RC_ACTOUT) ?"ACTOUT " :"",
1363                 (f & RC_RTSFLOW)?"RTSFLOW " :"",
1364                 (f & RC_CTSFLOW)?"CTSFLOW " :"",
1365                 (f & RC_DORXFER)?"DORXFER " :"",
1366                 (f & RC_DOXXFER)?"DOXXFER " :"",
1367                 (f & RC_MODCHG) ?"MODCHG "  :"",
1368                 (f & RC_OSUSP)  ?"OSUSP " :"",
1369                 (f & RC_OSBUSY) ?"OSBUSY " :"",
1370                 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"",
1371                 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"",
1372                 (f & RC_SEND_RDY) ?"SEND_RDY":"");
1373
1374         rcout(CD180_CAR, rc->rc_chan);
1375
1376         printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n",
1377                 rc->rc_rcb->rcb_unit, rc->rc_chan,
1378                 rcin(CD180_MSVR),
1379                 rcin(CD180_IER),
1380                 rcin(CD180_CCSR));
1381 }
1382 #endif /* RCDEBUG */
1383
1384 static void
1385 rc_dtrwakeup(chan)
1386         void    *chan;
1387 {
1388         struct rc_chans  *rc;
1389
1390         rc = (struct rc_chans *)chan;
1391         rc->rc_flags &= ~RC_DTR_OFF;
1392         wakeup(&rc->rc_dtrwait);
1393 }
1394
1395 static void
1396 rc_discard_output(rc)
1397         struct rc_chans  *rc;
1398 {
1399         disable_intr();
1400         if (rc->rc_flags & RC_DOXXFER) {
1401                 rc_scheduled_event -= LOTS_OF_EVENTS;
1402                 rc->rc_flags &= ~RC_DOXXFER;
1403         }
1404         rc->rc_optr = rc->rc_obufend;
1405         rc->rc_tp->t_state &= ~TS_BUSY;
1406         enable_intr();
1407         ttwwakeup(rc->rc_tp);
1408 }
1409
1410 static void
1411 rc_wakeup(chan)
1412         void    *chan;
1413 {
1414         timeout(rc_wakeup, (caddr_t)NULL, 1);
1415
1416         if (rc_scheduled_event != 0) {
1417                 int     s;
1418
1419                 s = splsofttty();
1420                 rcpoll();
1421                 splx(s);
1422         }
1423 }
1424
1425 static void
1426 disc_optim(tp, t, rc)
1427         struct tty      *tp;
1428         struct termios  *t;
1429         struct rc_chans *rc;
1430 {
1431
1432         if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
1433             && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
1434             && (!(t->c_iflag & PARMRK)
1435                 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
1436             && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
1437             && linesw[tp->t_line].l_rint == ttyinput)
1438                 tp->t_state |= TS_CAN_BYPASS_L_RINT;
1439         else
1440                 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
1441         rc->rc_hotchar = linesw[tp->t_line].l_hotchar;
1442 }
1443
1444 static void
1445 rc_wait0(nec, unit, chan, line)
1446         int     nec, unit, chan, line;
1447 {
1448         int rcnt;
1449
1450         for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--)
1451                 DELAY(30);
1452         if (rcnt == 0)
1453                 printf("rc%d/%d: channel command timeout, rc.c line: %d\n",
1454                       unit, chan, line);
1455 }