3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.42 2004/05/24 19:39:23 jhb Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_revar.h,v 1.27 2008/10/17 14:12:23 sephe Exp $
39 #define RE_RX_DESC_CNT_8139CP 64
40 #define RE_TX_DESC_CNT_8139CP 64
42 #define RE_RX_DESC_CNT_DEF 256
43 #define RE_TX_DESC_CNT_DEF 256
44 #define RE_RX_DESC_CNT_MAX 1024
45 #define RE_TX_DESC_CNT_MAX 1024
47 #define RE_RX_LIST_SZ(sc) ((sc)->re_rx_desc_cnt * sizeof(struct re_desc))
48 #define RE_TX_LIST_SZ(sc) ((sc)->re_tx_desc_cnt * sizeof(struct re_desc))
49 #define RE_RING_ALIGN 256
50 #define RE_IFQ_MAXLEN 512
52 #define RE_TXDESC_SPARE 4
53 #define RE_JBUF_COUNT(sc) (((sc)->re_rx_desc_cnt * 3) / 2)
55 #define RE_RXDESC_INC(sc, x) (x = (x + 1) % (sc)->re_rx_desc_cnt)
56 #define RE_TXDESC_INC(sc, x) (x = (x + 1) % (sc)->re_tx_desc_cnt)
57 #define RE_OWN(x) (le32toh((x)->re_cmdstat) & RE_RDESC_STAT_OWN)
58 #define RE_RXBYTES(x) (le32toh((x)->re_cmdstat) & sc->re_rxlenmask)
59 #define RE_PKTSZ(x) ((x)/* >> 3*/)
61 #define RE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
62 #define RE_ADDR_HI(y) ((uint64_t) (y) >> 32)
64 #define RE_JUMBO_FRAMELEN 7440
65 #define RE_JUMBO_MTU (RE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
66 #define RE_FRAMELEN_2K 2048
67 #define RE_FRAMELEN(mtu) (mtu + ETHER_HDR_LEN + ETHER_CRC_LEN)
68 #define RE_SWCSUM_LIM_8169 2038
70 #define RE_BUF_ALIGN 8
71 #define RE_JUMBO_FRAME_9K 9022
72 #define RE_JBUF_SIZE roundup2(RE_JUMBO_FRAME_9K, RE_BUF_ALIGN)
74 #define RE_TIMEOUT 1000
78 uint32_t re_macver; /* see RE_MACVER_ */
79 uint32_t re_caps; /* see RE_C_ */
82 #define RE_MACVER_UNKN 0
83 #define RE_MACVER_03 0x03
84 #define RE_MACVER_04 0x04
85 #define RE_MACVER_05 0x05
86 #define RE_MACVER_06 0x06
87 #define RE_MACVER_11 0x11
88 #define RE_MACVER_12 0x12
89 #define RE_MACVER_13 0x13
90 #define RE_MACVER_14 0x14
91 #define RE_MACVER_15 0x15
92 #define RE_MACVER_16 0x16
93 #define RE_MACVER_21 0x21
94 #define RE_MACVER_22 0x22
95 #define RE_MACVER_23 0x23
96 #define RE_MACVER_24 0x24
97 #define RE_MACVER_25 0x25
98 #define RE_MACVER_26 0x26
99 #define RE_MACVER_27 0x27
100 #define RE_MACVER_28 0x28
101 #define RE_MACVER_29 0x29
102 #define RE_MACVER_2A 0x2a
103 #define RE_MACVER_2B 0x2b
105 struct re_dmaload_arg {
107 bus_dma_segment_t *re_segs;
112 struct re_softc *re_sc;
117 SLIST_ENTRY(re_jbuf) re_link;
120 struct re_list_data {
121 struct mbuf **re_tx_mbuf;
122 struct mbuf **re_rx_mbuf;
123 bus_addr_t *re_rx_paddr;
128 bus_dmamap_t *re_tx_dmamap;
129 bus_dmamap_t *re_rx_dmamap;
130 bus_dmamap_t re_rx_spare;
131 bus_dma_tag_t re_mtag; /* mbuf mapping tag */
132 bus_dma_tag_t re_stag; /* stats mapping tag */
133 bus_dmamap_t re_smap; /* stats map */
134 struct re_stats *re_stats;
135 bus_addr_t re_stats_addr;
136 bus_dma_tag_t re_rx_list_tag;
137 bus_dmamap_t re_rx_list_map;
138 struct re_desc *re_rx_list;
139 bus_addr_t re_rx_list_addr;
140 bus_dma_tag_t re_tx_list_tag;
141 bus_dmamap_t re_tx_list_map;
142 struct re_desc *re_tx_list;
143 bus_addr_t re_tx_list_addr;
145 bus_dma_tag_t re_jpool_tag;
146 bus_dmamap_t re_jpool_map;
148 struct re_jbuf *re_jbuf;
149 struct lwkt_serialize re_jbuf_serializer;
150 SLIST_HEAD(, re_jbuf) re_jbuf_free;
154 struct arpcom arpcom; /* interface info */
156 bus_space_handle_t re_bhandle; /* bus space handle */
157 bus_space_tag_t re_btag; /* bus space tag */
158 struct resource *re_res;
159 struct resource *re_irq;
162 bus_dma_tag_t re_parent_tag;
163 bus_dma_tag_t re_tag;
165 uint8_t re_stats_no_timeout;
168 struct re_list_data re_ldata;
169 struct callout re_timer;
170 struct mbuf *re_head;
171 struct mbuf *re_tail;
173 uint32_t re_caps; /* see RE_C_ */
174 uint32_t re_macver; /* see RE_MACVER_ */
175 uint32_t re_rxlenmask;
178 int suspended; /* 0 = normal 1 = suspended */
188 int (*re_newbuf)(struct re_softc *, int, int);
190 uint32_t re_flags; /* see RE_F_ */
192 struct sysctl_ctx_list re_sysctl_ctx;
193 struct sysctl_oid *re_sysctl_tree;
200 int re_imtype; /* see RE_IMTYPE_ */
202 uint32_t saved_maps[5]; /* pci data */
203 uint32_t saved_biosaddr;
204 uint8_t saved_intline;
205 uint8_t saved_cachelnsz;
206 uint8_t saved_lattimer;
209 #define RE_C_PCIE 0x1 /* PCI-E */
210 #define RE_C_PCI64 0x2 /* PCI-X */
211 #define RE_C_HWIM 0x4 /* hardware interrupt moderation */
212 #define RE_C_HWCSUM 0x8 /* hardware csum offload */
213 #define RE_C_JUMBO 0x10 /* jumbo frame */
214 #define RE_C_8139CP 0x20 /* is 8139C+ */
215 #define RE_C_MAC2 0x40 /* MAC style 2 */
216 #define RE_C_PHYPMGT 0x80 /* PHY supports power mgmt */
217 #define RE_C_8169 0x100 /* is 8110/8169 */
218 #define RE_C_AUTOPAD 0x200 /* hardware auto-pad short frames */
219 #define RE_C_CONTIGRX 0x400 /* need contig buf to RX jumbo frames */
221 #define RE_IS_8139CP(sc) ((sc)->re_caps & RE_C_8139CP)
223 /* Interrupt moderation types */
224 #define RE_IMTYPE_NONE 0
225 #define RE_IMTYPE_SIM 1 /* simulated */
226 #define RE_IMTYPE_HW 2 /* hardware based */
228 #define RE_F_TIMER_INTR 0x1
229 #define RE_F_USE_JPOOL 0x2
232 * register space access macros
234 #define CSR_WRITE_STREAM_4(sc, reg, val) \
235 bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val)
236 #define CSR_WRITE_4(sc, reg, val) \
237 bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val)
238 #define CSR_WRITE_2(sc, reg, val) \
239 bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val)
240 #define CSR_WRITE_1(sc, reg, val) \
241 bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val)
243 #define CSR_READ_4(sc, reg) \
244 bus_space_read_4(sc->re_btag, sc->re_bhandle, reg)
245 #define CSR_READ_2(sc, reg) \
246 bus_space_read_2(sc->re_btag, sc->re_bhandle, reg)
247 #define CSR_READ_1(sc, reg) \
248 bus_space_read_1(sc->re_btag, sc->re_bhandle, reg)
250 #define CSR_SETBIT_1(sc, reg, val) \
251 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (val))
252 #define CSR_CLRBIT_1(sc, reg, val) \
253 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(val))