2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_ti.c,v 1.25.2.14 2002/02/15 04:20:20 silby Exp $
33 * $DragonFly: src/sys/dev/netif/ti/if_ti.c,v 1.31 2005/06/14 13:41:15 joerg Exp $
37 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
38 * Manuals, sample driver and firmware source kits are available
39 * from http://www.alteon.com/support/openkits.
41 * Written by Bill Paul <wpaul@ctr.columbia.edu>
42 * Electrical Engineering Department
43 * Columbia University, New York City
47 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
48 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
49 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
50 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
51 * filtering and jumbo (9014 byte) frames. The hardware is largely
52 * controlled by firmware, which must be loaded into the NIC during
55 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
56 * revision, which supports new features such as extended commands,
57 * extended jumbo receive ring desciptors and a mini receive ring.
59 * Alteon Networks is to be commended for releasing such a vast amount
60 * of development material for the Tigon NIC without requiring an NDA
61 * (although they really should have done it a long time ago). With
62 * any luck, the other vendors will finally wise up and follow Alteon's
65 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
66 * this driver by #including it as a C header file. This bloats the
67 * driver somewhat, but it's the easiest method considering that the
68 * driver code and firmware code need to be kept in sync. The source
69 * for the firmware is not provided with the FreeBSD distribution since
70 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
72 * The following people deserve special thanks:
73 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
75 * - Raymond Lee of Netgear, for providing a pair of Netgear
76 * GA620 Tigon 2 boards for testing
77 * - Ulf Zimmermann, for bringing the GA260 to my attention and
78 * convincing me to write this driver.
79 * - Andrew Gallatin for providing FreeBSD/Alpha support.
82 #include <sys/param.h>
83 #include <sys/systm.h>
84 #include <sys/sockio.h>
86 #include <sys/malloc.h>
87 #include <sys/kernel.h>
88 #include <sys/socket.h>
89 #include <sys/queue.h>
90 #include <sys/thread2.h>
93 #include <net/ifq_var.h>
94 #include <net/if_arp.h>
95 #include <net/ethernet.h>
96 #include <net/if_dl.h>
97 #include <net/if_media.h>
98 #include <net/if_types.h>
99 #include <net/vlan/if_vlan_var.h>
103 #include <netinet/in_systm.h>
104 #include <netinet/in.h>
105 #include <netinet/ip.h>
107 #include <vm/vm.h> /* for vtophys */
108 #include <vm/pmap.h> /* for vtophys */
109 #include <machine/bus.h>
110 #include <machine/resource.h>
112 #include <sys/rman.h>
114 #include <bus/pci/pcireg.h>
115 #include <bus/pci/pcivar.h>
117 #include "if_tireg.h"
122 * Temporarily disable the checksum offload support for now.
123 * Tests with ftp.freesoftware.com show that after about 12 hours,
124 * the firmware will begin calculating completely bogus TX checksums
125 * and refuse to stop until the interface is reset. Unfortunately,
126 * there isn't enough time to fully debug this before the 4.1
127 * release, so this will need to stay off for now.
130 #define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
132 #define TI_CSUM_FEATURES 0
136 * Various supported device vendors/types and their names.
139 static struct ti_type ti_devs[] = {
140 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
141 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
142 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
143 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
144 { TC_VENDORID, TC_DEVICEID_3C985,
145 "3Com 3c985-SX Gigabit Ethernet" },
146 { NG_VENDORID, NG_DEVICEID_GA620,
147 "Netgear GA620 1000baseSX Gigabit Ethernet" },
148 { NG_VENDORID, NG_DEVICEID_GA620T,
149 "Netgear GA620 1000baseT Gigabit Ethernet" },
150 { SGI_VENDORID, SGI_DEVICEID_TIGON,
151 "Silicon Graphics Gigabit Ethernet" },
152 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
153 "Farallon PN9000SX Gigabit Ethernet" },
157 static int ti_probe(device_t);
158 static int ti_attach(device_t);
159 static int ti_detach(device_t);
160 static void ti_txeof(struct ti_softc *);
161 static void ti_rxeof(struct ti_softc *);
163 static void ti_stats_update(struct ti_softc *);
164 static int ti_encap(struct ti_softc *, struct mbuf *, uint32_t *);
166 static void ti_intr(void *);
167 static void ti_start(struct ifnet *);
168 static int ti_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
169 static void ti_init(void *);
170 static void ti_init2(struct ti_softc *);
171 static void ti_stop(struct ti_softc *);
172 static void ti_watchdog(struct ifnet *);
173 static void ti_shutdown(device_t);
174 static int ti_ifmedia_upd(struct ifnet *);
175 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
177 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int);
178 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *);
179 static int ti_read_eeprom(struct ti_softc *, caddr_t, int, int);
181 static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
182 static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
183 static void ti_setmulti(struct ti_softc *);
185 static void ti_mem(struct ti_softc *, uint32_t, uint32_t, caddr_t);
186 static void ti_loadfw(struct ti_softc *);
187 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
188 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *,
190 static void ti_handle_events(struct ti_softc *);
191 static int ti_alloc_jumbo_mem(struct ti_softc *);
192 static struct ti_jslot *
193 ti_jalloc(struct ti_softc *);
194 static void ti_jfree(void *);
195 static void ti_jref(void *);
196 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *);
197 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *);
198 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
199 static int ti_init_rx_ring_std(struct ti_softc *);
200 static void ti_free_rx_ring_std(struct ti_softc *);
201 static int ti_init_rx_ring_jumbo(struct ti_softc *);
202 static void ti_free_rx_ring_jumbo(struct ti_softc *);
203 static int ti_init_rx_ring_mini(struct ti_softc *);
204 static void ti_free_rx_ring_mini(struct ti_softc *);
205 static void ti_free_tx_ring(struct ti_softc *);
206 static int ti_init_tx_ring(struct ti_softc *);
208 static int ti_64bitslot_war(struct ti_softc *);
209 static int ti_chipinit(struct ti_softc *);
210 static int ti_gibinit(struct ti_softc *);
212 static device_method_t ti_methods[] = {
213 /* Device interface */
214 DEVMETHOD(device_probe, ti_probe),
215 DEVMETHOD(device_attach, ti_attach),
216 DEVMETHOD(device_detach, ti_detach),
217 DEVMETHOD(device_shutdown, ti_shutdown),
222 static DEFINE_CLASS_0(ti, ti_driver, ti_methods, sizeof(struct ti_softc));
223 static devclass_t ti_devclass;
225 DECLARE_DUMMY_MODULE(if_ti);
226 DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0);
229 * Send an instruction or address to the EEPROM, check for ACK.
232 ti_eeprom_putbyte(struct ti_softc *sc, int byte)
237 * Make sure we're in TX mode.
239 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
242 * Feed in each bit and stobe the clock.
244 for (i = 0x80; i; i >>= 1) {
246 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
248 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
250 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
252 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
258 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
263 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
264 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
265 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
271 * Read a byte of data stored in the EEPROM at address 'addr.'
272 * We have to send two address bytes since the EEPROM can hold
273 * more than 256 bytes of data.
276 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest)
278 struct ifnet *ifp = &sc->arpcom.ac_if;
285 * Send write control code to EEPROM.
287 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
288 if_printf(ifp, "failed to send write command, status: %x\n",
289 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
294 * Send first byte of address of byte we want to read.
296 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
297 if_printf(ifp, "failed to send address, status: %x\n",
298 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
302 * Send second byte address of byte we want to read.
304 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
305 if_printf(ifp, "failed to send address, status: %x\n",
306 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
313 * Send read control code to EEPROM.
315 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
316 if_printf(ifp, "failed to send read command, status: %x\n",
317 CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
322 * Start reading bits from EEPROM.
324 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
325 for (i = 0x80; i; i >>= 1) {
326 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
328 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
330 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
337 * No ACK generated for read, so just return byte.
346 * Read a sequence of bytes from the EEPROM.
349 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt)
354 for (i = 0; i < cnt; i++) {
355 err = ti_eeprom_getbyte(sc, off + i, &byte);
365 * NIC memory access function. Can be used to either clear a section
366 * of NIC local memory or (if buf is non-NULL) copy data into it.
369 ti_mem(struct ti_softc *sc, uint32_t addr, uint32_t len, caddr_t buf)
371 int cnt, segptr, segsize;
372 caddr_t ti_winbase, ptr;
376 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
383 segsize = TI_WINLEN - (segptr % TI_WINLEN);
384 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
386 bzero((char *)ti_winbase + (segptr &
387 (TI_WINLEN - 1)), segsize);
389 bcopy((char *)ptr, (char *)ti_winbase +
390 (segptr & (TI_WINLEN - 1)), segsize);
399 * Load firmware image into the NIC. Check that the firmware revision
400 * is acceptable and see if we want the firmware for the Tigon 1 or
404 ti_loadfw(struct ti_softc *sc)
406 struct ifnet *ifp = &sc->arpcom.ac_if;
408 switch(sc->ti_hwrev) {
410 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
411 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
412 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
413 if_printf(ifp, "firmware revision mismatch; want "
414 "%d.%d.%d, got %d.%d.%d\n",
415 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
416 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
417 tigonFwReleaseMinor, tigonFwReleaseFix);
420 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
421 (caddr_t)tigonFwText);
422 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
423 (caddr_t)tigonFwData);
424 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
425 (caddr_t)tigonFwRodata);
426 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
427 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
428 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
430 case TI_HWREV_TIGON_II:
431 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
432 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
433 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
434 if_printf(ifp, "firmware revision mismatch; want "
435 "%d.%d.%d, got %d.%d.%d\n",
436 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
437 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
438 tigon2FwReleaseMinor, tigon2FwReleaseFix);
441 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
442 (caddr_t)tigon2FwText);
443 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
444 (caddr_t)tigon2FwData);
445 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
446 (caddr_t)tigon2FwRodata);
447 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
448 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
449 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
452 if_printf(ifp, "can't load firmware: unknown hardware rev\n");
458 * Send the NIC a command via the command ring.
461 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd)
465 if (sc->ti_rdata->ti_cmd_ring == NULL)
468 index = sc->ti_cmd_saved_prodidx;
469 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
470 TI_INC(index, TI_CMD_RING_CNT);
471 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
472 sc->ti_cmd_saved_prodidx = index;
476 * Send the NIC an extended command. The 'len' parameter specifies the
477 * number of command slots to include after the initial command.
480 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg, int len)
485 if (sc->ti_rdata->ti_cmd_ring == NULL)
488 index = sc->ti_cmd_saved_prodidx;
489 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
490 TI_INC(index, TI_CMD_RING_CNT);
491 for (i = 0; i < len; i++) {
492 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
493 *(uint32_t *)(&arg[i * 4]));
494 TI_INC(index, TI_CMD_RING_CNT);
496 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
497 sc->ti_cmd_saved_prodidx = index;
501 * Handle events that have triggered interrupts.
504 ti_handle_events(struct ti_softc *sc)
506 struct ifnet *ifp = &sc->arpcom.ac_if;
507 struct ti_event_desc *e;
509 if (sc->ti_rdata->ti_event_ring == NULL)
512 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
513 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
514 switch(e->ti_event) {
515 case TI_EV_LINKSTAT_CHANGED:
516 sc->ti_linkstat = e->ti_code;
517 if (e->ti_code == TI_EV_CODE_LINK_UP) {
518 if_printf(ifp, "10/100 link up\n");
519 } else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) {
520 if_printf(ifp, "gigabit link up\n");
521 } else if (e->ti_code == TI_EV_CODE_LINK_DOWN) {
522 if_printf(ifp, "link down\n");
526 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) {
527 if_printf(ifp, "invalid command\n");
528 } else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) {
529 if_printf(ifp, "unknown command\n");
530 } else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) {
531 if_printf(ifp, "bad config data\n");
534 case TI_EV_FIRMWARE_UP:
537 case TI_EV_STATS_UPDATED:
540 case TI_EV_RESET_JUMBO_RING:
541 case TI_EV_MCAST_UPDATED:
545 if_printf(ifp, "unknown event: %d\n", e->ti_event);
548 /* Advance the consumer index. */
549 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
550 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
555 * Memory management for the jumbo receive ring is a pain in the
556 * butt. We need to allocate at least 9018 bytes of space per frame,
557 * _and_ it has to be contiguous (unless you use the extended
558 * jumbo descriptor format). Using malloc() all the time won't
559 * work: malloc() allocates memory in powers of two, which means we
560 * would end up wasting a considerable amount of space by allocating
561 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
562 * to do our own memory management.
564 * The driver needs to allocate a contiguous chunk of memory at boot
565 * time. We then chop this up ourselves into 9K pieces and use them
566 * as external mbuf storage.
568 * One issue here is how much memory to allocate. The jumbo ring has
569 * 256 slots in it, but at 9K per slot than can consume over 2MB of
570 * RAM. This is a bit much, especially considering we also need
571 * RAM for the standard ring and mini ring (on the Tigon 2). To
572 * save space, we only actually allocate enough memory for 64 slots
573 * by default, which works out to between 500 and 600K. This can
574 * be tuned by changing a #define in if_tireg.h.
578 ti_alloc_jumbo_mem(struct ti_softc *sc)
580 struct ti_jslot *entry;
584 /* Grab a big chunk o' storage. */
585 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF,
586 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
588 if (sc->ti_cdata.ti_jumbo_buf == NULL) {
589 if_printf(&sc->arpcom.ac_if, "no memory for jumbo buffers!\n");
593 SLIST_INIT(&sc->ti_jfree_listhead);
596 * Now divide it up into 9K pieces and save the addresses
597 * in an array. Note that we play an evil trick here by using
598 * the first few bytes in the buffer to hold the the address
599 * of the softc structure for this interface. This is because
600 * ti_jfree() needs it, but it is called by the mbuf management
601 * code which will not pass it to us explicitly.
603 ptr = sc->ti_cdata.ti_jumbo_buf;
604 for (i = 0; i < TI_JSLOTS; i++) {
605 entry = &sc->ti_cdata.ti_jslots[i];
610 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jslot_link);
618 * Allocate a jumbo buffer.
620 static struct ti_jslot *
621 ti_jalloc(struct ti_softc *sc)
623 struct ti_jslot *entry;
625 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
628 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
632 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jslot_link);
638 * Adjust usage count on a jumbo buffer. In general this doesn't
639 * get used much because our jumbo buffers don't get passed around
640 * too much, but it's implemented for correctness.
645 struct ti_jslot *entry = (struct ti_jslot *)arg;
646 struct ti_softc *sc = entry->ti_sc;
649 panic("ti_jref: can't find softc pointer!");
651 if (&sc->ti_cdata.ti_jslots[entry->ti_slot] != entry)
652 panic("ti_jref: asked to reference buffer "
653 "that we don't manage!");
654 if (entry->ti_inuse == 0)
655 panic("ti_jref: buffer already free!");
660 * Release a jumbo buffer.
665 struct ti_jslot *entry = (struct ti_jslot *)arg;
666 struct ti_softc *sc = entry->ti_sc;
669 panic("ti_jref: can't find softc pointer!");
671 if (&sc->ti_cdata.ti_jslots[entry->ti_slot] != entry)
672 panic("ti_jref: asked to reference buffer "
673 "that we don't manage!");
674 if (entry->ti_inuse == 0)
675 panic("ti_jref: buffer already free!");
676 if (--entry->ti_inuse == 0)
677 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jslot_link);
682 * Intialize a standard receive ring descriptor.
685 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m)
688 struct ti_rx_desc *r;
691 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
694 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
697 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
698 m_new->m_data = m_new->m_ext.ext_buf;
702 m_adj(m_new, ETHER_ALIGN);
703 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
704 r = &sc->ti_rdata->ti_rx_std_ring[i];
705 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
706 r->ti_type = TI_BDTYPE_RECV_BD;
708 if (sc->arpcom.ac_if.if_hwassist)
709 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
710 r->ti_len = m_new->m_len;
717 * Intialize a mini receive ring descriptor. This only applies to
721 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m)
724 struct ti_rx_desc *r;
727 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
731 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
734 m_new->m_data = m_new->m_pktdat;
735 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
738 m_adj(m_new, ETHER_ALIGN);
739 r = &sc->ti_rdata->ti_rx_mini_ring[i];
740 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
741 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
742 r->ti_type = TI_BDTYPE_RECV_BD;
743 r->ti_flags = TI_BDFLAG_MINI_RING;
744 if (sc->arpcom.ac_if.if_hwassist)
745 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
746 r->ti_len = m_new->m_len;
753 * Initialize a jumbo receive ring descriptor. This allocates
754 * a jumbo buffer from the pool managed internally by the driver.
757 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m)
760 struct ti_rx_desc *r;
761 struct ti_jslot *buf;
764 /* Allocate the mbuf. */
765 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
770 /* Allocate the jumbo buffer */
774 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
775 "-- packet dropped!\n");
779 /* Attach the buffer to the mbuf. */
780 m_new->m_ext.ext_arg = buf;
781 m_new->m_ext.ext_free = ti_jfree;
782 m_new->m_ext.ext_ref = ti_jref;
783 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
785 m_new->m_data = m_new->m_ext.ext_buf;
786 m_new->m_flags |= M_EXT;
787 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
790 m_new->m_data = m_new->m_ext.ext_buf;
791 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
794 m_adj(m_new, ETHER_ALIGN);
795 /* Set up the descriptor. */
796 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
797 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
798 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
799 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
800 r->ti_flags = TI_BDFLAG_JUMBO_RING;
801 if (sc->arpcom.ac_if.if_hwassist)
802 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
803 r->ti_len = m_new->m_len;
810 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
811 * that's 1MB or memory, which is a lot. For now, we fill only the first
812 * 256 ring entries and hope that our CPU is fast enough to keep up with
816 ti_init_rx_ring_std(struct ti_softc *sc)
819 struct ti_cmd_desc cmd;
821 for (i = 0; i < TI_SSLOTS; i++) {
822 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
826 TI_UPDATE_STDPROD(sc, i - 1);
833 ti_free_rx_ring_std(struct ti_softc *sc)
837 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
838 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
839 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
840 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
842 bzero(&sc->ti_rdata->ti_rx_std_ring[i],
843 sizeof(struct ti_rx_desc));
848 ti_init_rx_ring_jumbo(struct ti_softc *sc)
851 struct ti_cmd_desc cmd;
853 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
854 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
858 TI_UPDATE_JUMBOPROD(sc, i - 1);
859 sc->ti_jumbo = i - 1;
865 ti_free_rx_ring_jumbo(struct ti_softc *sc)
869 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
870 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
871 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
872 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
874 bzero(&sc->ti_rdata->ti_rx_jumbo_ring[i],
875 sizeof(struct ti_rx_desc));
880 ti_init_rx_ring_mini(struct ti_softc *sc)
884 for (i = 0; i < TI_MSLOTS; i++) {
885 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
889 TI_UPDATE_MINIPROD(sc, i - 1);
896 ti_free_rx_ring_mini(struct ti_softc *sc)
900 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
901 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
902 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
903 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
905 bzero(&sc->ti_rdata->ti_rx_mini_ring[i],
906 sizeof(struct ti_rx_desc));
911 ti_free_tx_ring(struct ti_softc *sc)
915 if (sc->ti_rdata->ti_tx_ring == NULL)
918 for (i = 0; i < TI_TX_RING_CNT; i++) {
919 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
920 m_freem(sc->ti_cdata.ti_tx_chain[i]);
921 sc->ti_cdata.ti_tx_chain[i] = NULL;
923 bzero(&sc->ti_rdata->ti_tx_ring[i],
924 sizeof(struct ti_tx_desc));
929 ti_init_tx_ring(struct ti_softc *sc)
932 sc->ti_tx_saved_considx = 0;
933 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
938 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
939 * but we have to support the old way too so that Tigon 1 cards will
943 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr)
945 struct ti_cmd_desc cmd;
947 uint32_t ext[2] = {0, 0};
949 m = (uint16_t *)&addr->octet[0];
951 switch(sc->ti_hwrev) {
953 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
954 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
955 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
957 case TI_HWREV_TIGON_II:
958 ext[0] = htons(m[0]);
959 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
960 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
963 if_printf(&sc->arpcom.ac_if, "unknown hwrev\n");
969 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr)
971 struct ti_cmd_desc cmd;
973 uint32_t ext[2] = {0, 0};
975 m = (uint16_t *)&addr->octet[0];
977 switch(sc->ti_hwrev) {
979 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
980 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
981 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
983 case TI_HWREV_TIGON_II:
984 ext[0] = htons(m[0]);
985 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
986 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
989 if_printf(&sc->arpcom.ac_if, "unknown hwrev\n");
995 * Configure the Tigon's multicast address filter.
997 * The actual multicast table management is a bit of a pain, thanks to
998 * slight brain damage on the part of both Alteon and us. With our
999 * multicast code, we are only alerted when the multicast address table
1000 * changes and at that point we only have the current list of addresses:
1001 * we only know the current state, not the previous state, so we don't
1002 * actually know what addresses were removed or added. The firmware has
1003 * state, but we can't get our grubby mits on it, and there is no 'delete
1004 * all multicast addresses' command. Hence, we have to maintain our own
1005 * state so we know what addresses have been programmed into the NIC at
1009 ti_setmulti(struct ti_softc *sc)
1011 struct ifnet *ifp = &sc->arpcom.ac_if;
1012 struct ifmultiaddr *ifma;
1013 struct ti_cmd_desc cmd;
1014 struct ti_mc_entry *mc;
1017 if (ifp->if_flags & IFF_ALLMULTI) {
1018 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1022 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1024 /* Disable interrupts. */
1025 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1026 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1028 /* First, zot all the existing filters. */
1029 while (sc->ti_mc_listhead.slh_first != NULL) {
1030 mc = sc->ti_mc_listhead.slh_first;
1031 ti_del_mcast(sc, &mc->mc_addr);
1032 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1036 /* Now program new ones. */
1037 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1038 if (ifma->ifma_addr->sa_family != AF_LINK)
1040 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_INTWAIT);
1041 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1042 &mc->mc_addr, ETHER_ADDR_LEN);
1043 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1044 ti_add_mcast(sc, &mc->mc_addr);
1047 /* Re-enable interrupts. */
1048 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1052 * Check to see if the BIOS has configured us for a 64 bit slot when
1053 * we aren't actually in one. If we detect this condition, we can work
1054 * around it on the Tigon 2 by setting a bit in the PCI state register,
1055 * but for the Tigon 1 we must give up and abort the interface attach.
1058 ti_64bitslot_war(struct ti_softc *sc)
1060 if ((CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS) == 0) {
1061 CSR_WRITE_4(sc, 0x600, 0);
1062 CSR_WRITE_4(sc, 0x604, 0);
1063 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1064 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1065 if (sc->ti_hwrev == TI_HWREV_TIGON)
1067 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_32BIT_BUS);
1076 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1077 * self-test results.
1080 ti_chipinit(struct ti_softc *sc)
1082 struct ifnet *ifp = &sc->arpcom.ac_if;
1084 uint32_t pci_writemax = 0;
1086 /* Initialize link to down state. */
1087 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1089 if (ifp->if_capenable & IFCAP_HWCSUM)
1090 ifp->if_hwassist = TI_CSUM_FEATURES;
1092 ifp->if_hwassist = 0;
1094 /* Set endianness before we access any non-PCI registers. */
1095 #if BYTE_ORDER == BIG_ENDIAN
1096 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1097 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1099 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1100 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1103 /* Check the ROM failed bit to see if self-tests passed. */
1104 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1105 if_printf(ifp, "board self-diagnostics failed!\n");
1110 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1112 /* Figure out the hardware revision. */
1113 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1114 case TI_REV_TIGON_I:
1115 sc->ti_hwrev = TI_HWREV_TIGON;
1117 case TI_REV_TIGON_II:
1118 sc->ti_hwrev = TI_HWREV_TIGON_II;
1121 if_printf(ifp, "unsupported chip revision\n");
1125 /* Do special setup for Tigon 2. */
1126 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1127 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1128 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1129 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1132 /* Set up the PCI state register. */
1133 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1134 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1135 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1138 /* Clear the read/write max DMA parameters. */
1139 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1140 TI_PCISTATE_READ_MAXDMA));
1142 /* Get cache line size. */
1143 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1146 * If the system has set enabled the PCI memory write
1147 * and invalidate command in the command register, set
1148 * the write max parameter accordingly. This is necessary
1149 * to use MWI with the Tigon 2.
1151 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1161 /* Disable PCI memory write and invalidate. */
1163 if_printf(ifp, "cache line size %d not "
1164 "supported; disabling PCI MWI\n",
1167 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1168 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1173 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1175 /* This sets the min dma param all the way up (0xff). */
1176 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1178 /* Configure DMA variables. */
1179 #if BYTE_ORDER == BIG_ENDIAN
1180 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1181 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1182 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1183 TI_OPMODE_DONT_FRAG_JUMBO);
1185 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1186 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1187 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB);
1191 * Only allow 1 DMA channel to be active at a time.
1192 * I don't think this is a good idea, but without it
1193 * the firmware racks up lots of nicDmaReadRingFull
1194 * errors. This is not compatible with hardware checksums.
1196 if (ifp->if_hwassist == 0)
1197 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1199 /* Recommended settings from Tigon manual. */
1200 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1201 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1203 if (ti_64bitslot_war(sc)) {
1204 if_printf(ifp, "bios thinks we're in a 64 bit slot, "
1213 * Initialize the general information block and firmware, and
1214 * start the CPU(s) running.
1217 ti_gibinit(struct ti_softc *sc)
1219 struct ifnet *ifp = &sc->arpcom.ac_if;
1223 /* Disable interrupts for now. */
1224 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1226 /* Tell the chip where to find the general information block. */
1227 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
1228 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info));
1230 /* Load the firmware into SRAM. */
1233 /* Set up the contents of the general info and ring control blocks. */
1235 /* Set up the event ring and producer pointer. */
1236 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
1238 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring);
1240 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
1241 vtophys(&sc->ti_ev_prodidx);
1242 sc->ti_ev_prodidx.ti_idx = 0;
1243 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
1244 sc->ti_ev_saved_considx = 0;
1246 /* Set up the command ring and producer mailbox. */
1247 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
1249 sc->ti_rdata->ti_cmd_ring =
1250 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING);
1251 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
1253 rcb->ti_max_len = 0;
1254 for (i = 0; i < TI_CMD_RING_CNT; i++)
1255 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
1256 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
1257 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
1258 sc->ti_cmd_saved_prodidx = 0;
1261 * Assign the address of the stats refresh buffer.
1262 * We re-use the current stats buffer for this to
1265 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
1266 vtophys(&sc->ti_rdata->ti_info.ti_stats);
1268 /* Set up the standard receive ring. */
1269 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
1270 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring);
1271 rcb->ti_max_len = TI_FRAMELEN;
1273 if (ifp->if_hwassist)
1274 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1275 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1276 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1278 /* Set up the jumbo receive ring. */
1279 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
1280 TI_HOSTADDR(rcb->ti_hostaddr) =
1281 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring);
1282 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
1284 if (ifp->if_hwassist)
1285 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1286 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1287 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1290 * Set up the mini ring. Only activated on the
1291 * Tigon 2 but the slot in the config block is
1292 * still there on the Tigon 1.
1294 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
1295 TI_HOSTADDR(rcb->ti_hostaddr) =
1296 vtophys(&sc->ti_rdata->ti_rx_mini_ring);
1297 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
1298 if (sc->ti_hwrev == TI_HWREV_TIGON)
1299 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
1302 if (ifp->if_hwassist)
1303 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1304 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1305 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1308 * Set up the receive return ring.
1310 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
1311 TI_HOSTADDR(rcb->ti_hostaddr) =
1312 vtophys(&sc->ti_rdata->ti_rx_return_ring);
1314 rcb->ti_max_len = TI_RETURN_RING_CNT;
1315 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
1316 vtophys(&sc->ti_return_prodidx);
1319 * Set up the tx ring. Note: for the Tigon 2, we have the option
1320 * of putting the transmit ring in the host's address space and
1321 * letting the chip DMA it instead of leaving the ring in the NIC's
1322 * memory and accessing it through the shared memory region. We
1323 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
1324 * so we have to revert to the shared memory scheme if we detect
1327 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
1328 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1329 sc->ti_rdata->ti_tx_ring_nic =
1330 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
1332 bzero(sc->ti_rdata->ti_tx_ring,
1333 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
1334 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
1335 if (sc->ti_hwrev == TI_HWREV_TIGON)
1338 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
1339 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1340 if (ifp->if_hwassist)
1341 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1342 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1343 rcb->ti_max_len = TI_TX_RING_CNT;
1344 if (sc->ti_hwrev == TI_HWREV_TIGON)
1345 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
1347 TI_HOSTADDR(rcb->ti_hostaddr) =
1348 vtophys(&sc->ti_rdata->ti_tx_ring);
1349 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
1350 vtophys(&sc->ti_tx_considx);
1352 /* Set up tuneables */
1353 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
1354 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
1355 (sc->ti_rx_coal_ticks / 10));
1357 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
1358 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
1359 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
1360 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
1361 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
1362 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
1364 /* Turn interrupts on. */
1365 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
1366 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1369 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
1375 * Probe for a Tigon chip. Check the PCI vendor and device IDs
1376 * against our list and return its name if we find a match.
1379 ti_probe(device_t dev)
1382 uint16_t vendor, product;
1384 vendor = pci_get_vendor(dev);
1385 product = pci_get_device(dev);
1387 for (t = ti_devs; t->ti_name != NULL; t++) {
1388 if (vendor == t->ti_vid && product == t->ti_did) {
1389 device_set_desc(dev, t->ti_name);
1398 ti_attach(device_t dev)
1400 struct ti_softc *sc;
1405 sc = device_get_softc(dev);
1406 ifp = &sc->arpcom.ac_if;
1407 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1408 ifp->if_capabilities = IFCAP_HWCSUM;
1409 ifp->if_capenable = ifp->if_capabilities;
1412 * Map control/status registers.
1414 pci_enable_busmaster(dev);
1415 pci_enable_io(dev, SYS_RES_MEMORY);
1416 command = pci_read_config(dev, PCIR_COMMAND, 4);
1418 if ((command & PCIM_CMD_MEMEN) == 0) {
1419 device_printf(dev, "failed to enable memory mapping!\n");
1425 * Initialize media before any possible error may occur,
1426 * so we can destroy it unconditionally, if an error occurs later on.
1428 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
1431 sc->ti_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1434 if (sc->ti_res == NULL) {
1435 device_printf(dev, "couldn't map memory\n");
1440 sc->ti_btag = rman_get_bustag(sc->ti_res);
1441 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
1442 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res);
1444 /* Allocate interrupt */
1446 sc->ti_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1447 RF_SHAREABLE | RF_ACTIVE);
1448 if (sc->ti_irq == NULL) {
1449 device_printf(dev, "couldn't map interrupt\n");
1454 if (ti_chipinit(sc)) {
1455 device_printf(dev, "chip initialization failed\n");
1460 /* Zero out the NIC's on-board SRAM. */
1461 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
1463 /* Init again -- zeroing memory may have clobbered some registers. */
1464 if (ti_chipinit(sc)) {
1465 device_printf(dev, "chip initialization failed\n");
1471 * Get station address from the EEPROM. Note: the manual states
1472 * that the MAC address is at offset 0x8c, however the data is
1473 * stored as two longwords (since that's how it's loaded into
1474 * the NIC). This means the MAC address is actually preceeded
1475 * by two zero bytes. We need to skip over those.
1477 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1478 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1479 device_printf(dev, "failed to read station address\n");
1484 /* Allocate the general information block and ring buffers. */
1485 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF,
1486 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1488 if (sc->ti_rdata == NULL) {
1489 device_printf(dev, "no memory for list buffers!\n");
1494 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
1496 /* Try to allocate memory for jumbo buffers. */
1497 if (ti_alloc_jumbo_mem(sc)) {
1498 device_printf(dev, "jumbo buffer allocation failed\n");
1504 * We really need a better way to tell a 1000baseTX card
1505 * from a 1000baseSX one, since in theory there could be
1506 * OEMed 1000baseTX cards from lame vendors who aren't
1507 * clever enough to change the PCI ID. For the moment
1508 * though, the AceNIC is the only copper card available.
1510 if (pci_get_vendor(dev) == ALT_VENDORID &&
1511 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
1513 /* Ok, it's not the only copper card available. */
1514 if (pci_get_vendor(dev) == NG_VENDORID &&
1515 pci_get_device(dev) == NG_DEVICEID_GA620T)
1518 /* Set default tuneable values. */
1519 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
1520 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
1521 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
1522 sc->ti_rx_max_coal_bds = 64;
1523 sc->ti_tx_max_coal_bds = 128;
1524 sc->ti_tx_buf_ratio = 21;
1526 /* Set up ifnet structure */
1528 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1529 ifp->if_ioctl = ti_ioctl;
1530 ifp->if_start = ti_start;
1531 ifp->if_watchdog = ti_watchdog;
1532 ifp->if_init = ti_init;
1533 ifp->if_mtu = ETHERMTU;
1534 ifq_set_maxlen(&ifp->if_snd, TI_TX_RING_CNT - 1);
1535 ifq_set_ready(&ifp->if_snd);
1537 /* Set up ifmedia support. */
1538 if (sc->ti_copper) {
1540 * Copper cards allow manual 10/100 mode selection,
1541 * but not manual 1000baseTX mode selection. Why?
1542 * Becuase currently there's no way to specify the
1543 * master/slave setting through the firmware interface,
1544 * so Alteon decided to just bag it and handle it
1545 * via autonegotiation.
1547 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1548 ifmedia_add(&sc->ifmedia,
1549 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1550 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
1551 ifmedia_add(&sc->ifmedia,
1552 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
1553 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
1554 ifmedia_add(&sc->ifmedia,
1555 IFM_ETHER|IFM_1000_T | IFM_FDX, 0, NULL);
1557 /* Fiber cards don't support 10/100 modes. */
1558 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1559 ifmedia_add(&sc->ifmedia,
1560 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1562 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1563 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
1566 * Call MI attach routine.
1568 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
1570 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET,
1571 ti_intr, sc, &sc->ti_intrhand, NULL);
1573 device_printf(dev, "couldn't set up irq\n");
1574 ether_ifdetach(ifp);
1585 ti_detach(device_t dev)
1587 struct ti_softc *sc = device_get_softc(dev);
1588 struct ifnet *ifp = &sc->arpcom.ac_if;
1592 if (device_is_attached(dev)) {
1593 if (bus_child_present(dev))
1595 ether_ifdetach(ifp);
1598 if (sc->ti_intrhand != NULL)
1599 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1603 if (sc->ti_irq != NULL)
1604 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1605 if (sc->ti_res != NULL) {
1606 bus_release_resource(dev, SYS_RES_MEMORY,
1607 TI_PCI_LOMEM, sc->ti_res);
1609 if (sc->ti_cdata.ti_jumbo_buf != NULL)
1610 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF);
1611 if (sc->ti_rdata != NULL)
1612 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF);
1613 ifmedia_removeall(&sc->ifmedia);
1619 * Frame reception handling. This is called if there's a frame
1620 * on the receive return list.
1622 * Note: we have to be able to handle three possibilities here:
1623 * 1) the frame is from the mini receive ring (can only happen)
1624 * on Tigon 2 boards)
1625 * 2) the frame is from the jumbo recieve ring
1626 * 3) the frame is from the standard receive ring
1629 ti_rxeof(struct ti_softc *sc)
1631 struct ifnet *ifp = &sc->arpcom.ac_if;
1632 struct ti_cmd_desc cmd;
1634 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
1635 struct ti_rx_desc *cur_rx;
1638 uint16_t vlan_tag = 0;
1642 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
1643 rxidx = cur_rx->ti_idx;
1644 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
1646 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
1648 vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
1651 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
1652 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
1653 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
1654 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
1655 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1657 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1660 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
1662 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1665 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
1666 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
1667 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
1668 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
1669 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1671 ti_newbuf_mini(sc, sc->ti_mini, m);
1674 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
1676 ti_newbuf_mini(sc, sc->ti_mini, m);
1680 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
1681 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
1682 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
1683 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1685 ti_newbuf_std(sc, sc->ti_std, m);
1688 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
1690 ti_newbuf_std(sc, sc->ti_std, m);
1695 m->m_pkthdr.len = m->m_len = cur_rx->ti_len;
1697 m->m_pkthdr.rcvif = ifp;
1699 if (ifp->if_hwassist) {
1700 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1702 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
1703 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1704 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
1708 * If we received a packet with a vlan tag, pass it
1709 * to vlan_input() instead of ether_input().
1712 VLAN_INPUT_TAG(m, vlan_tag);
1714 (*ifp->if_input)(ifp, m);
1717 /* Only necessary on the Tigon 1. */
1718 if (sc->ti_hwrev == TI_HWREV_TIGON)
1719 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
1720 sc->ti_rx_saved_considx);
1722 TI_UPDATE_STDPROD(sc, sc->ti_std);
1723 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
1724 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
1728 ti_txeof(struct ti_softc *sc)
1730 struct ifnet *ifp = &sc->arpcom.ac_if;
1731 struct ti_tx_desc *cur_tx = NULL;
1734 * Go through our tx ring and free mbufs for those
1735 * frames that have been sent.
1737 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
1740 idx = sc->ti_tx_saved_considx;
1741 if (sc->ti_hwrev != TI_HWREV_TIGON) {
1743 CSR_WRITE_4(sc, TI_WINBASE,
1744 TI_TX_RING_BASE + 6144);
1746 CSR_WRITE_4(sc, TI_WINBASE,
1747 TI_TX_RING_BASE + 4096);
1749 CSR_WRITE_4(sc, TI_WINBASE,
1750 TI_TX_RING_BASE + 2048);
1752 CSR_WRITE_4(sc, TI_WINBASE,
1754 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
1756 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
1757 if (cur_tx->ti_flags & TI_BDFLAG_END)
1759 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
1760 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
1761 sc->ti_cdata.ti_tx_chain[idx] = NULL;
1764 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
1769 ifp->if_flags &= ~IFF_OACTIVE;
1775 struct ti_softc *sc = xsc;
1776 struct ifnet *ifp = &sc->arpcom.ac_if;
1779 /* Avoid this for now -- checking this register is expensive. */
1780 /* Make sure this is really our interrupt. */
1781 if ((CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE) == 0)
1785 /* Ack interrupt and stop others from occuring. */
1786 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1788 if (ifp->if_flags & IFF_RUNNING) {
1789 /* Check RX return ring producer/consumer */
1792 /* Check TX ring producer/consumer */
1796 ti_handle_events(sc);
1798 /* Re-enable interrupts. */
1799 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1801 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
1806 ti_stats_update(struct ti_softc *sc)
1808 struct ifnet *ifp = &sc->arpcom.ac_if;
1810 ifp->if_collisions +=
1811 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
1812 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
1813 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
1814 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
1819 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
1820 * pointers to descriptors.
1823 ti_encap(struct ti_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1825 struct ti_tx_desc *f = NULL;
1827 struct ifvlan *ifv = NULL;
1828 uint32_t cnt = 0, cur, frag;
1829 uint16_t csum_flags = 0;
1831 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1832 m_head->m_pkthdr.rcvif != NULL &&
1833 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1834 ifv = m_head->m_pkthdr.rcvif->if_softc;
1837 cur = frag = *txidx;
1839 if (m_head->m_pkthdr.csum_flags) {
1840 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1841 csum_flags |= TI_BDFLAG_IP_CKSUM;
1842 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
1843 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
1844 if (m_head->m_flags & M_LASTFRAG)
1845 csum_flags |= TI_BDFLAG_IP_FRAG_END;
1846 else if (m_head->m_flags & M_FRAG)
1847 csum_flags |= TI_BDFLAG_IP_FRAG;
1850 * Start packing the mbufs in this chain into
1851 * the fragment pointers. Stop when we run out
1852 * of fragments or hit the end of the mbuf chain.
1854 for (m = m_head; m != NULL; m = m->m_next) {
1855 if (m->m_len != 0) {
1856 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1858 CSR_WRITE_4(sc, TI_WINBASE,
1859 TI_TX_RING_BASE + 6144);
1860 else if (frag > 255)
1861 CSR_WRITE_4(sc, TI_WINBASE,
1862 TI_TX_RING_BASE + 4096);
1863 else if (frag > 127)
1864 CSR_WRITE_4(sc, TI_WINBASE,
1865 TI_TX_RING_BASE + 2048);
1867 CSR_WRITE_4(sc, TI_WINBASE,
1869 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
1871 f = &sc->ti_rdata->ti_tx_ring[frag];
1872 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
1874 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
1875 f->ti_len = m->m_len;
1876 f->ti_flags = csum_flags;
1879 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
1880 f->ti_vlan_tag = ifv->ifv_tag & 0xfff;
1886 * Sanity check: avoid coming within 16 descriptors
1887 * of the end of the ring.
1889 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
1892 TI_INC(frag, TI_TX_RING_CNT);
1900 if (frag == sc->ti_tx_saved_considx)
1903 if (sc->ti_hwrev == TI_HWREV_TIGON)
1904 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
1907 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
1908 sc->ti_cdata.ti_tx_chain[cur] = m_head;
1909 sc->ti_txcnt += cnt;
1917 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1918 * to the mbuf data regions directly in the transmit descriptors.
1921 ti_start(struct ifnet *ifp)
1923 struct ti_softc *sc = ifp->if_softc;
1924 struct mbuf *m_head = NULL;
1925 uint32_t prodidx = 0;
1927 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
1929 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
1930 m_head = ifq_poll(&ifp->if_snd);
1936 * safety overkill. If this is a fragmented packet chain
1937 * with delayed TCP/UDP checksums, then only encapsulate
1938 * it if we have enough descriptors to handle the entire
1940 * (paranoia -- may not actually be needed)
1942 if (m_head->m_flags & M_FIRSTFRAG &&
1943 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
1944 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
1945 m_head->m_pkthdr.csum_data + 16) {
1946 ifp->if_flags |= IFF_OACTIVE;
1952 * Pack the data into the transmit ring. If we
1953 * don't have room, set the OACTIVE flag and wait
1954 * for the NIC to drain the ring.
1956 if (ti_encap(sc, m_head, &prodidx)) {
1957 ifp->if_flags |= IFF_OACTIVE;
1961 m_head = ifq_dequeue(&ifp->if_snd);
1962 BPF_MTAP(ifp, m_head);
1966 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
1969 * Set a timeout in case the chip goes out to lunch.
1977 struct ti_softc *sc = xsc;
1981 /* Cancel pending I/O and flush buffers. */
1984 /* Init the gen info block, ring control blocks and firmware. */
1985 if (ti_gibinit(sc)) {
1986 if_printf(&sc->arpcom.ac_if, "initialization failure\n");
1995 ti_init2(struct ti_softc *sc)
1997 struct ifnet *ifp = &sc->arpcom.ac_if;
1998 struct ti_cmd_desc cmd;
2000 struct ifmedia *ifm;
2003 /* Specify MTU and interface index. */
2004 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_dunit);
2005 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
2006 ETHER_HDR_LEN + ETHER_CRC_LEN);
2007 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
2009 /* Load our MAC address. */
2010 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2011 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
2012 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
2013 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
2015 /* Enable or disable promiscuous mode as needed. */
2016 if (ifp->if_flags & IFF_PROMISC)
2017 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
2019 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
2021 /* Program multicast filter. */
2025 * If this is a Tigon 1, we should tell the
2026 * firmware to use software packet filtering.
2028 if (sc->ti_hwrev == TI_HWREV_TIGON)
2029 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
2032 ti_init_rx_ring_std(sc);
2034 /* Init jumbo RX ring. */
2035 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2036 ti_init_rx_ring_jumbo(sc);
2039 * If this is a Tigon 2, we can also configure the
2042 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
2043 ti_init_rx_ring_mini(sc);
2045 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2046 sc->ti_rx_saved_considx = 0;
2049 ti_init_tx_ring(sc);
2051 /* Tell firmware we're alive. */
2052 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
2054 /* Enable host interrupts. */
2055 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2057 ifp->if_flags |= IFF_RUNNING;
2058 ifp->if_flags &= ~IFF_OACTIVE;
2061 * Make sure to set media properly. We have to do this
2062 * here since we have to issue commands in order to set
2063 * the link negotiation and we can't issue commands until
2064 * the firmware is running.
2067 tmp = ifm->ifm_media;
2068 ifm->ifm_media = ifm->ifm_cur->ifm_media;
2069 ti_ifmedia_upd(ifp);
2070 ifm->ifm_media = tmp;
2074 * Set media options.
2077 ti_ifmedia_upd(struct ifnet *ifp)
2079 struct ti_softc *sc = ifp->if_softc;
2080 struct ifmedia *ifm = &sc->ifmedia;
2081 struct ti_cmd_desc cmd;
2083 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2086 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2088 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF | TI_GLNK_1000MB |
2089 TI_GLNK_FULL_DUPLEX | TI_GLNK_RX_FLOWCTL_Y |
2090 TI_GLNK_AUTONEGENB | TI_GLNK_ENB);
2091 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB | TI_LNK_10MB |
2092 TI_LNK_FULL_DUPLEX | TI_LNK_HALF_DUPLEX |
2093 TI_LNK_AUTONEGENB | TI_LNK_ENB);
2094 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2095 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
2099 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB |
2100 TI_GLNK_RX_FLOWCTL_Y | TI_GLNK_ENB);
2101 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
2102 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
2103 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
2104 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2105 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
2111 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
2112 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB | TI_LNK_PREF);
2113 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
2114 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX)
2115 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
2117 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
2118 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
2119 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
2121 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
2122 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2123 TI_CMD_CODE_NEGOTIATE_10_100, 0);
2131 * Report current media status.
2134 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2136 struct ti_softc *sc = ifp->if_softc;
2139 ifmr->ifm_status = IFM_AVALID;
2140 ifmr->ifm_active = IFM_ETHER;
2142 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
2145 ifmr->ifm_status |= IFM_ACTIVE;
2147 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
2148 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
2150 ifmr->ifm_active |= IFM_1000_T;
2152 ifmr->ifm_active |= IFM_1000_SX;
2153 if (media & TI_GLNK_FULL_DUPLEX)
2154 ifmr->ifm_active |= IFM_FDX;
2156 ifmr->ifm_active |= IFM_HDX;
2157 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
2158 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
2159 if (sc->ti_copper) {
2160 if (media & TI_LNK_100MB)
2161 ifmr->ifm_active |= IFM_100_TX;
2162 if (media & TI_LNK_10MB)
2163 ifmr->ifm_active |= IFM_10_T;
2165 if (media & TI_LNK_100MB)
2166 ifmr->ifm_active |= IFM_100_FX;
2167 if (media & TI_LNK_10MB)
2168 ifmr->ifm_active |= IFM_10_FL;
2170 if (media & TI_LNK_FULL_DUPLEX)
2171 ifmr->ifm_active |= IFM_FDX;
2172 if (media & TI_LNK_HALF_DUPLEX)
2173 ifmr->ifm_active |= IFM_HDX;
2178 ti_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2180 struct ti_softc *sc = ifp->if_softc;
2181 struct ifreq *ifr = (struct ifreq *) data;
2182 struct ti_cmd_desc cmd;
2183 int error = 0, mask;
2189 if (ifr->ifr_mtu > TI_JUMBO_MTU)
2192 ifp->if_mtu = ifr->ifr_mtu;
2197 if (ifp->if_flags & IFF_UP) {
2199 * If only the state of the PROMISC flag changed,
2200 * then just use the 'set promisc mode' command
2201 * instead of reinitializing the entire NIC. Doing
2202 * a full re-init means reloading the firmware and
2203 * waiting for it to start up, which may take a
2206 if (ifp->if_flags & IFF_RUNNING &&
2207 ifp->if_flags & IFF_PROMISC &&
2208 !(sc->ti_if_flags & IFF_PROMISC)) {
2209 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2210 TI_CMD_CODE_PROMISC_ENB, 0);
2211 } else if (ifp->if_flags & IFF_RUNNING &&
2212 !(ifp->if_flags & IFF_PROMISC) &&
2213 sc->ti_if_flags & IFF_PROMISC) {
2214 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2215 TI_CMD_CODE_PROMISC_DIS, 0);
2218 } else if (ifp->if_flags & IFF_RUNNING) {
2221 sc->ti_if_flags = ifp->if_flags;
2226 if (ifp->if_flags & IFF_RUNNING) {
2233 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2236 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2237 if (mask & IFCAP_HWCSUM) {
2238 if (IFCAP_HWCSUM & ifp->if_capenable)
2239 ifp->if_capenable &= ~IFCAP_HWCSUM;
2241 ifp->if_capenable |= IFCAP_HWCSUM;
2242 if (ifp->if_flags & IFF_RUNNING)
2248 error = ether_ioctl(ifp, command, data);
2258 ti_watchdog(struct ifnet *ifp)
2260 struct ti_softc *sc = ifp->if_softc;
2262 if_printf(ifp, "watchdog timeout -- resetting\n");
2270 * Stop the adapter and free any mbufs allocated to the
2274 ti_stop(struct ti_softc *sc)
2276 struct ifnet *ifp = &sc->arpcom.ac_if;
2277 struct ti_cmd_desc cmd;
2279 /* Disable host interrupts. */
2280 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2282 * Tell firmware we're shutting down.
2284 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
2286 /* Halt and reinitialize. */
2288 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
2291 /* Free the RX lists. */
2292 ti_free_rx_ring_std(sc);
2294 /* Free jumbo RX list. */
2295 ti_free_rx_ring_jumbo(sc);
2297 /* Free mini RX list. */
2298 ti_free_rx_ring_mini(sc);
2300 /* Free TX buffers. */
2301 ti_free_tx_ring(sc);
2303 sc->ti_ev_prodidx.ti_idx = 0;
2304 sc->ti_return_prodidx.ti_idx = 0;
2305 sc->ti_tx_considx.ti_idx = 0;
2306 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
2308 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2312 * Stop all chip I/O so that the kernel's probe routines don't
2313 * get confused by errant DMAs when rebooting.
2316 ti_shutdown(device_t dev)
2318 struct ti_softc *sc = device_get_softc(dev);