2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
34 * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.105 2008/08/17 04:32:32 sephe Exp $
39 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
41 * Written by Bill Paul <wpaul@windriver.com>
42 * Senior Engineer, Wind River Systems
46 * The Broadcom BCM5700 is based on technology originally developed by
47 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
48 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
49 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
50 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
51 * frames, highly configurable RX filtering, and 16 RX and TX queues
52 * (which, along with RX filter rules, can be used for QOS applications).
53 * Other features, such as TCP segmentation, may be available as part
54 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
55 * firmware images can be stored in hardware and need not be compiled
58 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
59 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
61 * The BCM5701 is a single-chip solution incorporating both the BCM5700
62 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
63 * does not support external SSRAM.
65 * Broadcom also produces a variation of the BCM5700 under the "Altima"
66 * brand name, which is functionally similar but lacks PCI-X support.
68 * Without external SSRAM, you can only have at most 4 TX rings,
69 * and the use of the mini RX ring is disabled. This seems to imply
70 * that these features are simply not available on the BCM5701. As a
71 * result, this driver does not implement any support for the mini RX
75 #include "opt_polling.h"
76 #include "opt_ethernet.h"
78 #include <sys/param.h>
80 #include <sys/endian.h>
81 #include <sys/kernel.h>
83 #include <sys/interrupt.h>
85 #include <sys/malloc.h>
86 #include <sys/queue.h>
88 #include <sys/serialize.h>
89 #include <sys/socket.h>
90 #include <sys/sockio.h>
91 #include <sys/sysctl.h>
94 #include <net/ethernet.h>
96 #include <net/if_arp.h>
97 #include <net/if_dl.h>
98 #include <net/if_media.h>
99 #include <net/if_types.h>
100 #include <net/ifq_var.h>
101 #include <net/vlan/if_vlan_var.h>
102 #include <net/vlan/if_vlan_ether.h>
104 #include <dev/netif/mii_layer/mii.h>
105 #include <dev/netif/mii_layer/miivar.h>
106 #include <dev/netif/mii_layer/brgphyreg.h>
108 #include <bus/pci/pcidevs.h>
109 #include <bus/pci/pcireg.h>
110 #include <bus/pci/pcivar.h>
112 #include <dev/netif/bge/if_bgereg.h>
114 /* "device miibus" required. See GENERIC if you get errors here. */
115 #include "miibus_if.h"
117 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
118 #define BGE_MIN_FRAME 60
120 static const struct bge_type bge_devs[] = {
121 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
122 "3COM 3C996 Gigabit Ethernet" },
124 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
125 "Alteon BCM5700 Gigabit Ethernet" },
126 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
127 "Alteon BCM5701 Gigabit Ethernet" },
129 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
130 "Altima AC1000 Gigabit Ethernet" },
131 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
132 "Altima AC1002 Gigabit Ethernet" },
133 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
134 "Altima AC9100 Gigabit Ethernet" },
136 { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
137 "Apple BCM5701 Gigabit Ethernet" },
139 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
140 "Broadcom BCM5700 Gigabit Ethernet" },
141 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
142 "Broadcom BCM5701 Gigabit Ethernet" },
143 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
144 "Broadcom BCM5702 Gigabit Ethernet" },
145 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
146 "Broadcom BCM5702X Gigabit Ethernet" },
147 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
148 "Broadcom BCM5702 Gigabit Ethernet" },
149 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
150 "Broadcom BCM5703 Gigabit Ethernet" },
151 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
152 "Broadcom BCM5703X Gigabit Ethernet" },
153 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
154 "Broadcom BCM5703 Gigabit Ethernet" },
155 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
156 "Broadcom BCM5704C Dual Gigabit Ethernet" },
157 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
158 "Broadcom BCM5704S Dual Gigabit Ethernet" },
159 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
160 "Broadcom BCM5704S Dual Gigabit Ethernet" },
161 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
162 "Broadcom BCM5705 Gigabit Ethernet" },
163 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
164 "Broadcom BCM5705F Gigabit Ethernet" },
165 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
166 "Broadcom BCM5705K Gigabit Ethernet" },
167 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
168 "Broadcom BCM5705M Gigabit Ethernet" },
169 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
170 "Broadcom BCM5705M Gigabit Ethernet" },
171 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
172 "Broadcom BCM5714C Gigabit Ethernet" },
173 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
174 "Broadcom BCM5714S Gigabit Ethernet" },
175 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
176 "Broadcom BCM5715 Gigabit Ethernet" },
177 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
178 "Broadcom BCM5715S Gigabit Ethernet" },
179 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
180 "Broadcom BCM5720 Gigabit Ethernet" },
181 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
182 "Broadcom BCM5721 Gigabit Ethernet" },
183 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
184 "Broadcom BCM5722 Gigabit Ethernet" },
185 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
186 "Broadcom BCM5750 Gigabit Ethernet" },
187 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
188 "Broadcom BCM5750M Gigabit Ethernet" },
189 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
190 "Broadcom BCM5751 Gigabit Ethernet" },
191 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
192 "Broadcom BCM5751F Gigabit Ethernet" },
193 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
194 "Broadcom BCM5751M Gigabit Ethernet" },
195 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
196 "Broadcom BCM5752 Gigabit Ethernet" },
197 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
198 "Broadcom BCM5752M Gigabit Ethernet" },
199 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
200 "Broadcom BCM5753 Gigabit Ethernet" },
201 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
202 "Broadcom BCM5753F Gigabit Ethernet" },
203 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
204 "Broadcom BCM5753M Gigabit Ethernet" },
205 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
206 "Broadcom BCM5754 Gigabit Ethernet" },
207 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
208 "Broadcom BCM5754M Gigabit Ethernet" },
209 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
210 "Broadcom BCM5755 Gigabit Ethernet" },
211 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
212 "Broadcom BCM5755M Gigabit Ethernet" },
213 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
214 "Broadcom BCM5756 Gigabit Ethernet" },
215 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
216 "Broadcom BCM5780 Gigabit Ethernet" },
217 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
218 "Broadcom BCM5780S Gigabit Ethernet" },
219 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
220 "Broadcom BCM5781 Gigabit Ethernet" },
221 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
222 "Broadcom BCM5782 Gigabit Ethernet" },
223 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
224 "Broadcom BCM5786 Gigabit Ethernet" },
225 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
226 "Broadcom BCM5787 Gigabit Ethernet" },
227 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
228 "Broadcom BCM5787F Gigabit Ethernet" },
229 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
230 "Broadcom BCM5787M Gigabit Ethernet" },
231 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
232 "Broadcom BCM5788 Gigabit Ethernet" },
233 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
234 "Broadcom BCM5789 Gigabit Ethernet" },
235 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
236 "Broadcom BCM5901 Fast Ethernet" },
237 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
238 "Broadcom BCM5901A2 Fast Ethernet" },
239 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
240 "Broadcom BCM5903M Fast Ethernet" },
242 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
243 "SysKonnect Gigabit Ethernet" },
248 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
249 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
250 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
251 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
252 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
254 static int bge_probe(device_t);
255 static int bge_attach(device_t);
256 static int bge_detach(device_t);
257 static void bge_txeof(struct bge_softc *);
258 static void bge_rxeof(struct bge_softc *);
260 static void bge_tick(void *);
261 static void bge_stats_update(struct bge_softc *);
262 static void bge_stats_update_regs(struct bge_softc *);
263 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
265 #ifdef DEVICE_POLLING
266 static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
268 static void bge_intr(void *);
269 static void bge_enable_intr(struct bge_softc *);
270 static void bge_disable_intr(struct bge_softc *);
271 static void bge_start(struct ifnet *);
272 static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
273 static void bge_init(void *);
274 static void bge_stop(struct bge_softc *);
275 static void bge_watchdog(struct ifnet *);
276 static void bge_shutdown(device_t);
277 static int bge_suspend(device_t);
278 static int bge_resume(device_t);
279 static int bge_ifmedia_upd(struct ifnet *);
280 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
282 static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
283 static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
285 static void bge_setmulti(struct bge_softc *);
286 static void bge_setpromisc(struct bge_softc *);
288 static int bge_alloc_jumbo_mem(struct bge_softc *);
289 static void bge_free_jumbo_mem(struct bge_softc *);
290 static struct bge_jslot
291 *bge_jalloc(struct bge_softc *);
292 static void bge_jfree(void *);
293 static void bge_jref(void *);
294 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
295 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
296 static int bge_init_rx_ring_std(struct bge_softc *);
297 static void bge_free_rx_ring_std(struct bge_softc *);
298 static int bge_init_rx_ring_jumbo(struct bge_softc *);
299 static void bge_free_rx_ring_jumbo(struct bge_softc *);
300 static void bge_free_tx_ring(struct bge_softc *);
301 static int bge_init_tx_ring(struct bge_softc *);
303 static int bge_chipinit(struct bge_softc *);
304 static int bge_blockinit(struct bge_softc *);
306 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
307 static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
309 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
311 static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
312 static void bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
313 static void bge_set_max_readrq(struct bge_softc *);
315 static int bge_miibus_readreg(device_t, int, int);
316 static int bge_miibus_writereg(device_t, int, int, int);
317 static void bge_miibus_statchg(device_t);
318 static void bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
319 static void bge_tbi_link_upd(struct bge_softc *, uint32_t);
320 static void bge_copper_link_upd(struct bge_softc *, uint32_t);
322 static void bge_reset(struct bge_softc *);
324 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
325 static void bge_dma_map_mbuf(void *, bus_dma_segment_t *, int,
327 static int bge_dma_alloc(struct bge_softc *);
328 static void bge_dma_free(struct bge_softc *);
329 static int bge_dma_block_alloc(struct bge_softc *, bus_size_t,
330 bus_dma_tag_t *, bus_dmamap_t *,
331 void **, bus_addr_t *);
332 static void bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
334 static void bge_coal_change(struct bge_softc *);
335 static int bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
336 static int bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
337 static int bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
338 static int bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
339 static int bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
342 * Set following tunable to 1 for some IBM blade servers with the DNLK
343 * switch module. Auto negotiation is broken for those configurations.
345 static int bge_fake_autoneg = 0;
346 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
348 /* Interrupt moderation control variables. */
349 static int bge_rx_coal_ticks = 150; /* usec */
350 static int bge_tx_coal_ticks = 1023; /* usec */
351 static int bge_rx_max_coal_bds = 80;
352 static int bge_tx_max_coal_bds = 128;
354 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
355 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
356 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
357 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
359 #if !defined(KTR_IF_BGE)
360 #define KTR_IF_BGE KTR_ALL
362 KTR_INFO_MASTER(if_bge);
363 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr", 0);
364 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt", 0);
365 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt", 0);
366 #define logif(name) KTR_LOG(if_bge_ ## name)
368 static device_method_t bge_methods[] = {
369 /* Device interface */
370 DEVMETHOD(device_probe, bge_probe),
371 DEVMETHOD(device_attach, bge_attach),
372 DEVMETHOD(device_detach, bge_detach),
373 DEVMETHOD(device_shutdown, bge_shutdown),
374 DEVMETHOD(device_suspend, bge_suspend),
375 DEVMETHOD(device_resume, bge_resume),
378 DEVMETHOD(bus_print_child, bus_generic_print_child),
379 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
382 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
383 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
384 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
389 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
390 static devclass_t bge_devclass;
392 DECLARE_DUMMY_MODULE(if_bge);
393 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
394 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
397 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
399 device_t dev = sc->bge_dev;
402 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
403 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
404 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
409 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
411 device_t dev = sc->bge_dev;
413 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
414 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
415 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
422 bge_set_max_readrq(struct bge_softc *sc)
424 device_t dev = sc->bge_dev;
428 KKASSERT((sc->bge_flags & BGE_FLAG_PCIE) && sc->bge_expr_ptr != 0);
429 expr_ptr = sc->bge_expr_ptr;
431 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
432 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) !=
433 PCIEM_DEVCTL_MAX_READRQ_4096) {
434 device_printf(dev, "adjust device control 0x%04x ", val);
436 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
437 val |= PCIEM_DEVCTL_MAX_READRQ_4096;
438 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
440 kprintf("-> 0x%04x\n", val);
446 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
448 device_t dev = sc->bge_dev;
450 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
451 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
456 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
458 device_t dev = sc->bge_dev;
460 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
461 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
465 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
467 CSR_WRITE_4(sc, off, val);
471 * Read a byte of data stored in the EEPROM at address 'addr.' The
472 * BCM570x supports both the traditional bitbang interface and an
473 * auto access interface for reading the EEPROM. We use the auto
477 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
483 * Enable use of auto EEPROM access so we can avoid
484 * having to use the bitbang method.
486 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
488 /* Reset the EEPROM, load the clock period. */
489 CSR_WRITE_4(sc, BGE_EE_ADDR,
490 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
493 /* Issue the read EEPROM command. */
494 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
496 /* Wait for completion */
497 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
499 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
503 if (i == BGE_TIMEOUT) {
504 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
509 byte = CSR_READ_4(sc, BGE_EE_DATA);
511 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
517 * Read a sequence of bytes from the EEPROM.
520 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
526 for (byte = 0, err = 0, i = 0; i < len; i++) {
527 err = bge_eeprom_getbyte(sc, off + i, &byte);
537 bge_miibus_readreg(device_t dev, int phy, int reg)
539 struct bge_softc *sc = device_get_softc(dev);
540 struct ifnet *ifp = &sc->arpcom.ac_if;
541 uint32_t val, autopoll;
545 * Broadcom's own driver always assumes the internal
546 * PHY is at GMII address 1. On some chips, the PHY responds
547 * to accesses at all addresses, which could cause us to
548 * bogusly attach the PHY 32 times at probe type. Always
549 * restricting the lookup to address 1 is simpler than
550 * trying to figure out which chips revisions should be
556 /* Reading with autopolling on may trigger PCI errors */
557 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
558 if (autopoll & BGE_MIMODE_AUTOPOLL) {
559 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
563 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
564 BGE_MIPHY(phy)|BGE_MIREG(reg));
566 for (i = 0; i < BGE_TIMEOUT; i++) {
568 val = CSR_READ_4(sc, BGE_MI_COMM);
569 if (!(val & BGE_MICOMM_BUSY))
573 if (i == BGE_TIMEOUT) {
574 if_printf(ifp, "PHY read timed out "
575 "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
581 val = CSR_READ_4(sc, BGE_MI_COMM);
584 if (autopoll & BGE_MIMODE_AUTOPOLL) {
585 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
589 if (val & BGE_MICOMM_READFAIL)
592 return(val & 0xFFFF);
596 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
598 struct bge_softc *sc = device_get_softc(dev);
603 * See the related comment in bge_miibus_readreg()
608 /* Reading with autopolling on may trigger PCI errors */
609 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
610 if (autopoll & BGE_MIMODE_AUTOPOLL) {
611 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
615 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
616 BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
618 for (i = 0; i < BGE_TIMEOUT; i++) {
620 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
622 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
627 if (autopoll & BGE_MIMODE_AUTOPOLL) {
628 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
632 if (i == BGE_TIMEOUT) {
633 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
634 "(phy %d, reg %d, val %d)\n", phy, reg, val);
642 bge_miibus_statchg(device_t dev)
644 struct bge_softc *sc;
645 struct mii_data *mii;
647 sc = device_get_softc(dev);
648 mii = device_get_softc(sc->bge_miibus);
650 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
651 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
652 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
654 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
657 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
658 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
660 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
665 * Memory management for jumbo frames.
668 bge_alloc_jumbo_mem(struct bge_softc *sc)
670 struct ifnet *ifp = &sc->arpcom.ac_if;
671 struct bge_jslot *entry;
677 * Create tag for jumbo mbufs.
678 * This is really a bit of a kludge. We allocate a special
679 * jumbo buffer pool which (thanks to the way our DMA
680 * memory allocation works) will consist of contiguous
681 * pages. This means that even though a jumbo buffer might
682 * be larger than a page size, we don't really need to
683 * map it into more than one DMA segment. However, the
684 * default mbuf tag will result in multi-segment mappings,
685 * so we have to create a special jumbo mbuf tag that
686 * lets us get away with mapping the jumbo buffers as
687 * a single segment. I think eventually the driver should
688 * be changed so that it uses ordinary mbufs and cluster
689 * buffers, i.e. jumbo frames can span multiple DMA
690 * descriptors. But that's a project for another day.
694 * Create DMA stuffs for jumbo RX ring.
696 error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
697 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
698 &sc->bge_cdata.bge_rx_jumbo_ring_map,
699 (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
700 &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
702 if_printf(ifp, "could not create jumbo RX ring\n");
707 * Create DMA stuffs for jumbo buffer block.
709 error = bge_dma_block_alloc(sc, BGE_JMEM,
710 &sc->bge_cdata.bge_jumbo_tag,
711 &sc->bge_cdata.bge_jumbo_map,
712 (void **)&sc->bge_ldata.bge_jumbo_buf,
715 if_printf(ifp, "could not create jumbo buffer\n");
719 SLIST_INIT(&sc->bge_jfree_listhead);
722 * Now divide it up into 9K pieces and save the addresses
723 * in an array. Note that we play an evil trick here by using
724 * the first few bytes in the buffer to hold the the address
725 * of the softc structure for this interface. This is because
726 * bge_jfree() needs it, but it is called by the mbuf management
727 * code which will not pass it to us explicitly.
729 for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
730 entry = &sc->bge_cdata.bge_jslots[i];
732 entry->bge_buf = ptr;
733 entry->bge_paddr = paddr;
734 entry->bge_inuse = 0;
736 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
745 bge_free_jumbo_mem(struct bge_softc *sc)
747 /* Destroy jumbo RX ring. */
748 bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
749 sc->bge_cdata.bge_rx_jumbo_ring_map,
750 sc->bge_ldata.bge_rx_jumbo_ring);
752 /* Destroy jumbo buffer block. */
753 bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
754 sc->bge_cdata.bge_jumbo_map,
755 sc->bge_ldata.bge_jumbo_buf);
759 * Allocate a jumbo buffer.
761 static struct bge_jslot *
762 bge_jalloc(struct bge_softc *sc)
764 struct bge_jslot *entry;
766 lwkt_serialize_enter(&sc->bge_jslot_serializer);
767 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
769 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
770 entry->bge_inuse = 1;
772 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
774 lwkt_serialize_exit(&sc->bge_jslot_serializer);
779 * Adjust usage count on a jumbo buffer.
784 struct bge_jslot *entry = (struct bge_jslot *)arg;
785 struct bge_softc *sc = entry->bge_sc;
788 panic("bge_jref: can't find softc pointer!");
790 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
791 panic("bge_jref: asked to reference buffer "
792 "that we don't manage!");
793 } else if (entry->bge_inuse == 0) {
794 panic("bge_jref: buffer already free!");
796 atomic_add_int(&entry->bge_inuse, 1);
801 * Release a jumbo buffer.
806 struct bge_jslot *entry = (struct bge_jslot *)arg;
807 struct bge_softc *sc = entry->bge_sc;
810 panic("bge_jfree: can't find softc pointer!");
812 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
813 panic("bge_jfree: asked to free buffer that we don't manage!");
814 } else if (entry->bge_inuse == 0) {
815 panic("bge_jfree: buffer already free!");
818 * Possible MP race to 0, use the serializer. The atomic insn
819 * is still needed for races against bge_jref().
821 lwkt_serialize_enter(&sc->bge_jslot_serializer);
822 atomic_subtract_int(&entry->bge_inuse, 1);
823 if (entry->bge_inuse == 0) {
824 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
827 lwkt_serialize_exit(&sc->bge_jslot_serializer);
833 * Intialize a standard receive ring descriptor.
836 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
838 struct mbuf *m_new = NULL;
839 struct bge_dmamap_arg ctx;
840 bus_dma_segment_t seg;
845 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
850 m_new->m_data = m_new->m_ext.ext_buf;
852 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
854 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
855 m_adj(m_new, ETHER_ALIGN);
859 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag,
860 sc->bge_cdata.bge_rx_std_dmamap[i],
861 m_new, bge_dma_map_mbuf, &ctx,
863 if (error || ctx.bge_maxsegs == 0) {
865 if_printf(&sc->arpcom.ac_if, "too many segments?!\n");
866 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
867 sc->bge_cdata.bge_rx_std_dmamap[i]);
874 sc->bge_cdata.bge_rx_std_chain[i] = m_new;
876 r = &sc->bge_ldata.bge_rx_std_ring[i];
877 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[0].ds_addr);
878 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[0].ds_addr);
879 r->bge_flags = BGE_RXBDFLAG_END;
880 r->bge_len = m_new->m_len;
883 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
884 sc->bge_cdata.bge_rx_std_dmamap[i],
885 BUS_DMASYNC_PREREAD);
890 * Initialize a jumbo receive ring descriptor. This allocates
891 * a jumbo buffer from the pool managed internally by the driver.
894 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
896 struct mbuf *m_new = NULL;
897 struct bge_jslot *buf;
902 /* Allocate the mbuf. */
903 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
907 /* Allocate the jumbo buffer */
908 buf = bge_jalloc(sc);
911 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
912 "-- packet dropped!\n");
916 /* Attach the buffer to the mbuf. */
917 m_new->m_ext.ext_arg = buf;
918 m_new->m_ext.ext_buf = buf->bge_buf;
919 m_new->m_ext.ext_free = bge_jfree;
920 m_new->m_ext.ext_ref = bge_jref;
921 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
923 m_new->m_flags |= M_EXT;
925 KKASSERT(m->m_flags & M_EXT);
927 buf = m_new->m_ext.ext_arg;
929 m_new->m_data = m_new->m_ext.ext_buf;
930 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
932 paddr = buf->bge_paddr;
933 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
934 m_adj(m_new, ETHER_ALIGN);
935 paddr += ETHER_ALIGN;
938 /* Set up the descriptor. */
939 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
941 r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
942 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(paddr);
943 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(paddr);
944 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
945 r->bge_len = m_new->m_len;
952 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
953 * that's 1MB or memory, which is a lot. For now, we fill only the first
954 * 256 ring entries and hope that our CPU is fast enough to keep up with
958 bge_init_rx_ring_std(struct bge_softc *sc)
962 for (i = 0; i < BGE_SSLOTS; i++) {
963 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
967 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
968 sc->bge_cdata.bge_rx_std_ring_map,
969 BUS_DMASYNC_PREWRITE);
972 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
978 bge_free_rx_ring_std(struct bge_softc *sc)
982 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
983 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
984 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
985 sc->bge_cdata.bge_rx_std_dmamap[i]);
986 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
987 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
989 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
990 sizeof(struct bge_rx_bd));
995 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1000 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1001 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1005 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1006 sc->bge_cdata.bge_rx_jumbo_ring_map,
1007 BUS_DMASYNC_PREWRITE);
1009 sc->bge_jumbo = i - 1;
1011 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1012 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1013 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1015 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1021 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1025 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1026 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1027 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1028 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1030 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1031 sizeof(struct bge_rx_bd));
1036 bge_free_tx_ring(struct bge_softc *sc)
1040 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1041 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1042 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1043 sc->bge_cdata.bge_tx_dmamap[i]);
1044 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1045 sc->bge_cdata.bge_tx_chain[i] = NULL;
1047 bzero(&sc->bge_ldata.bge_tx_ring[i],
1048 sizeof(struct bge_tx_bd));
1053 bge_init_tx_ring(struct bge_softc *sc)
1056 sc->bge_tx_saved_considx = 0;
1057 sc->bge_tx_prodidx = 0;
1059 /* Initialize transmit producer index for host-memory send ring. */
1060 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1062 /* 5700 b2 errata */
1063 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1064 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
1066 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1067 /* 5700 b2 errata */
1068 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1069 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1075 bge_setmulti(struct bge_softc *sc)
1078 struct ifmultiaddr *ifma;
1079 uint32_t hashes[4] = { 0, 0, 0, 0 };
1082 ifp = &sc->arpcom.ac_if;
1084 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1085 for (i = 0; i < 4; i++)
1086 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1090 /* First, zot all the existing filters. */
1091 for (i = 0; i < 4; i++)
1092 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1094 /* Now program new ones. */
1095 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1096 if (ifma->ifma_addr->sa_family != AF_LINK)
1099 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1100 ETHER_ADDR_LEN) & 0x7f;
1101 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1104 for (i = 0; i < 4; i++)
1105 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1109 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1110 * self-test results.
1113 bge_chipinit(struct bge_softc *sc)
1116 uint32_t dma_rw_ctl;
1118 /* Set endian type before we access any non-PCI registers. */
1119 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1122 * Check the 'ROM failed' bit on the RX CPU to see if
1123 * self-tests passed.
1125 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1126 if_printf(&sc->arpcom.ac_if,
1127 "RX CPU self-diagnostics failed!\n");
1131 /* Clear the MAC control register */
1132 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1135 * Clear the MAC statistics block in the NIC's
1138 for (i = BGE_STATS_BLOCK;
1139 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1140 BGE_MEMWIN_WRITE(sc, i, 0);
1142 for (i = BGE_STATUS_BLOCK;
1143 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1144 BGE_MEMWIN_WRITE(sc, i, 0);
1146 /* Set up the PCI DMA control register. */
1147 if (sc->bge_flags & BGE_FLAG_PCIE) {
1149 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1150 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1151 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1152 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1154 if (BGE_IS_5714_FAMILY(sc)) {
1155 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1156 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1157 /* XXX magic values, Broadcom-supplied Linux driver */
1158 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1159 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1160 BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1162 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1164 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1166 * The 5704 uses a different encoding of read/write
1169 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1170 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1171 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1173 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1174 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1175 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1180 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1181 * for hardware bugs.
1183 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1184 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1187 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1188 if (tmp == 0x6 || tmp == 0x7)
1189 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1192 /* Conventional PCI bus */
1193 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1194 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1195 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1199 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1200 sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1201 sc->bge_asicrev == BGE_ASICREV_BCM5705)
1202 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1203 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1206 * Set up general mode register.
1208 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1209 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1210 BGE_MODECTL_TX_NO_PHDR_CSUM);
1213 * Disable memory write invalidate. Apparently it is not supported
1214 * properly by these devices.
1216 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1218 /* Set the timer prescaler (always 66Mhz) */
1219 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1225 bge_blockinit(struct bge_softc *sc)
1227 struct bge_rcb *rcb;
1234 * Initialize the memory window pointer register so that
1235 * we can access the first 32K of internal NIC RAM. This will
1236 * allow us to set up the TX send ring RCBs and the RX return
1237 * ring RCBs, plus other things which live in NIC memory.
1239 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1241 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1243 if (!BGE_IS_5705_PLUS(sc)) {
1244 /* Configure mbuf memory pool */
1245 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1246 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1247 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1249 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1251 /* Configure DMA resource pool */
1252 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1253 BGE_DMA_DESCRIPTORS);
1254 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1257 /* Configure mbuf pool watermarks */
1258 if (BGE_IS_5705_PLUS(sc)) {
1259 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1260 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1262 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1263 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1265 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1267 /* Configure DMA resource watermarks */
1268 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1269 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1271 /* Enable buffer manager */
1272 if (!BGE_IS_5705_PLUS(sc)) {
1273 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1274 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1276 /* Poll for buffer manager start indication */
1277 for (i = 0; i < BGE_TIMEOUT; i++) {
1278 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1283 if (i == BGE_TIMEOUT) {
1284 if_printf(&sc->arpcom.ac_if,
1285 "buffer manager failed to start\n");
1290 /* Enable flow-through queues */
1291 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1292 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1294 /* Wait until queue initialization is complete */
1295 for (i = 0; i < BGE_TIMEOUT; i++) {
1296 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1301 if (i == BGE_TIMEOUT) {
1302 if_printf(&sc->arpcom.ac_if,
1303 "flow-through queue init failed\n");
1307 /* Initialize the standard RX ring control block */
1308 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1309 rcb->bge_hostaddr.bge_addr_lo =
1310 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1311 rcb->bge_hostaddr.bge_addr_hi =
1312 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1313 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1314 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1315 if (BGE_IS_5705_PLUS(sc))
1316 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1318 rcb->bge_maxlen_flags =
1319 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1320 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1321 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1322 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1323 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1324 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1327 * Initialize the jumbo RX ring control block
1328 * We set the 'ring disabled' bit in the flags
1329 * field until we're actually ready to start
1330 * using this ring (i.e. once we set the MTU
1331 * high enough to require it).
1333 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1334 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1336 rcb->bge_hostaddr.bge_addr_lo =
1337 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1338 rcb->bge_hostaddr.bge_addr_hi =
1339 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1340 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1341 sc->bge_cdata.bge_rx_jumbo_ring_map,
1342 BUS_DMASYNC_PREREAD);
1343 rcb->bge_maxlen_flags =
1344 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1345 BGE_RCB_FLAG_RING_DISABLED);
1346 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1347 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1348 rcb->bge_hostaddr.bge_addr_hi);
1349 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1350 rcb->bge_hostaddr.bge_addr_lo);
1351 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1352 rcb->bge_maxlen_flags);
1353 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1355 /* Set up dummy disabled mini ring RCB */
1356 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1357 rcb->bge_maxlen_flags =
1358 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1359 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1360 rcb->bge_maxlen_flags);
1364 * Set the BD ring replentish thresholds. The recommended
1365 * values are 1/8th the number of descriptors allocated to
1368 if (BGE_IS_5705_PLUS(sc))
1371 val = BGE_STD_RX_RING_CNT / 8;
1372 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1373 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1376 * Disable all unused send rings by setting the 'ring disabled'
1377 * bit in the flags field of all the TX send ring control blocks.
1378 * These are located in NIC memory.
1380 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1381 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1382 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1383 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1384 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1385 vrcb += sizeof(struct bge_rcb);
1388 /* Configure TX RCB 0 (we use only the first ring) */
1389 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1390 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1391 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1392 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1393 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1394 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1395 if (!BGE_IS_5705_PLUS(sc)) {
1396 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1397 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1400 /* Disable all unused RX return rings */
1401 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1402 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1403 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1404 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1405 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1406 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1407 BGE_RCB_FLAG_RING_DISABLED));
1408 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1409 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1410 (i * (sizeof(uint64_t))), 0);
1411 vrcb += sizeof(struct bge_rcb);
1414 /* Initialize RX ring indexes */
1415 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1416 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1417 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1420 * Set up RX return ring 0
1421 * Note that the NIC address for RX return rings is 0x00000000.
1422 * The return rings live entirely within the host, so the
1423 * nicaddr field in the RCB isn't used.
1425 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1426 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1427 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1428 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1429 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1430 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1431 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1433 /* Set random backoff seed for TX */
1434 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1435 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1436 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1437 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1438 BGE_TX_BACKOFF_SEED_MASK);
1440 /* Set inter-packet gap */
1441 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1444 * Specify which ring to use for packets that don't match
1447 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1450 * Configure number of RX lists. One interrupt distribution
1451 * list, sixteen active lists, one bad frames class.
1453 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1455 /* Inialize RX list placement stats mask. */
1456 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1457 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1459 /* Disable host coalescing until we get it set up */
1460 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1462 /* Poll to make sure it's shut down. */
1463 for (i = 0; i < BGE_TIMEOUT; i++) {
1464 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1469 if (i == BGE_TIMEOUT) {
1470 if_printf(&sc->arpcom.ac_if,
1471 "host coalescing engine failed to idle\n");
1475 /* Set up host coalescing defaults */
1476 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1477 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1478 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1479 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1480 if (!BGE_IS_5705_PLUS(sc)) {
1481 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1482 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1484 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1485 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1487 /* Set up address of statistics block */
1488 if (!BGE_IS_5705_PLUS(sc)) {
1489 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1490 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1491 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1492 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1494 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1495 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1496 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1499 /* Set up address of status block */
1500 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1501 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1502 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1503 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1504 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1505 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1507 /* Turn on host coalescing state machine */
1508 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1510 /* Turn on RX BD completion state machine and enable attentions */
1511 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1512 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1514 /* Turn on RX list placement state machine */
1515 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1517 /* Turn on RX list selector state machine. */
1518 if (!BGE_IS_5705_PLUS(sc))
1519 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1521 /* Turn on DMA, clear stats */
1522 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1523 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1524 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1525 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1526 ((sc->bge_flags & BGE_FLAG_TBI) ?
1527 BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1529 /* Set misc. local control, enable interrupts on attentions */
1530 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1533 /* Assert GPIO pins for PHY reset */
1534 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1535 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1536 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1537 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1540 /* Turn on DMA completion state machine */
1541 if (!BGE_IS_5705_PLUS(sc))
1542 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1544 /* Turn on write DMA state machine */
1545 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1546 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1547 sc->bge_asicrev == BGE_ASICREV_BCM5787)
1548 val |= (1 << 29); /* Enable host coalescing bug fix. */
1549 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1552 /* Turn on read DMA state machine */
1553 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1554 if (sc->bge_flags & BGE_FLAG_PCIE)
1555 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1556 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1559 /* Turn on RX data completion state machine */
1560 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1562 /* Turn on RX BD initiator state machine */
1563 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1565 /* Turn on RX data and RX BD initiator state machine */
1566 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1568 /* Turn on Mbuf cluster free state machine */
1569 if (!BGE_IS_5705_PLUS(sc))
1570 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1572 /* Turn on send BD completion state machine */
1573 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1575 /* Turn on send data completion state machine */
1576 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1578 /* Turn on send data initiator state machine */
1579 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1581 /* Turn on send BD initiator state machine */
1582 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1584 /* Turn on send BD selector state machine */
1585 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1587 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1588 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1589 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1591 /* ack/clear link change events */
1592 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1593 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1594 BGE_MACSTAT_LINK_CHANGED);
1595 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1597 /* Enable PHY auto polling (for MII/GMII only) */
1598 if (sc->bge_flags & BGE_FLAG_TBI) {
1599 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1601 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1602 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1603 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1604 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1605 BGE_EVTENB_MI_INTERRUPT);
1610 * Clear any pending link state attention.
1611 * Otherwise some link state change events may be lost until attention
1612 * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1613 * It's not necessary on newer BCM chips - perhaps enabling link
1614 * state change attentions implies clearing pending attention.
1616 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1617 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1618 BGE_MACSTAT_LINK_CHANGED);
1620 /* Enable link state change attentions. */
1621 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1627 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1628 * against our list and return its name if we find a match. Note
1629 * that since the Broadcom controller contains VPD support, we
1630 * can get the device name string from the controller itself instead
1631 * of the compiled-in string. This is a little slow, but it guarantees
1632 * we'll always announce the right product name.
1635 bge_probe(device_t dev)
1637 const struct bge_type *t;
1638 uint16_t product, vendor;
1640 product = pci_get_device(dev);
1641 vendor = pci_get_vendor(dev);
1643 for (t = bge_devs; t->bge_name != NULL; t++) {
1644 if (vendor == t->bge_vid && product == t->bge_did)
1647 if (t->bge_name == NULL)
1650 device_set_desc(dev, t->bge_name);
1651 if (pci_get_subvendor(dev) == PCI_VENDOR_DELL) {
1652 struct bge_softc *sc = device_get_softc(dev);
1653 sc->bge_flags |= BGE_FLAG_NO_3LED;
1659 bge_attach(device_t dev)
1662 struct bge_softc *sc;
1664 uint32_t mac_addr = 0;
1666 uint8_t ether_addr[ETHER_ADDR_LEN];
1668 sc = device_get_softc(dev);
1670 callout_init(&sc->bge_stat_timer);
1671 lwkt_serialize_init(&sc->bge_jslot_serializer);
1674 * Map control/status registers.
1676 pci_enable_busmaster(dev);
1679 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1682 if (sc->bge_res == NULL) {
1683 device_printf(dev, "couldn't map memory\n");
1687 sc->bge_btag = rman_get_bustag(sc->bge_res);
1688 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1690 /* Save various chip information */
1692 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1693 BGE_PCIMISCCTL_ASICREV;
1694 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1695 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1697 /* Save chipset family. */
1698 switch (sc->bge_asicrev) {
1699 case BGE_ASICREV_BCM5700:
1700 case BGE_ASICREV_BCM5701:
1701 case BGE_ASICREV_BCM5703:
1702 case BGE_ASICREV_BCM5704:
1703 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1706 case BGE_ASICREV_BCM5714_A0:
1707 case BGE_ASICREV_BCM5780:
1708 case BGE_ASICREV_BCM5714:
1709 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1712 case BGE_ASICREV_BCM5750:
1713 case BGE_ASICREV_BCM5752:
1714 case BGE_ASICREV_BCM5755:
1715 case BGE_ASICREV_BCM5787:
1716 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1719 case BGE_ASICREV_BCM5705:
1720 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1725 * Set various quirk flags.
1728 sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1729 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1730 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1731 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1732 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1733 sc->bge_asicrev == BGE_ASICREV_BCM5906)
1734 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1736 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1737 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1738 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1740 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1741 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1742 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1744 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1745 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1747 if (BGE_IS_5705_PLUS(sc)) {
1748 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1749 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1750 uint32_t product = pci_get_device(dev);
1752 if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
1753 product != PCI_PRODUCT_BROADCOM_BCM5756)
1754 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1755 if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1756 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1757 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1758 sc->bge_flags |= BGE_FLAG_BER_BUG;
1762 /* Allocate interrupt */
1765 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1766 RF_SHAREABLE | RF_ACTIVE);
1768 if (sc->bge_irq == NULL) {
1769 device_printf(dev, "couldn't map interrupt\n");
1775 * Check if this is a PCI-X or PCI Express device.
1777 if (BGE_IS_5705_PLUS(sc)) {
1778 sc->bge_expr_ptr = pci_get_pciecap_ptr(dev);
1780 if (sc->bge_expr_ptr != 0) {
1781 sc->bge_flags |= BGE_FLAG_PCIE;
1782 bge_set_max_readrq(sc);
1786 * Check if the device is in PCI-X Mode.
1787 * (This bit is not valid on PCI Express controllers.)
1789 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1790 BGE_PCISTATE_PCI_BUSMODE) == 0)
1791 sc->bge_flags |= BGE_FLAG_PCIX;
1794 device_printf(dev, "CHIP ID 0x%08x; "
1795 "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
1796 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
1797 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
1798 : ((sc->bge_flags & BGE_FLAG_PCIE) ?
1801 ifp = &sc->arpcom.ac_if;
1802 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1804 /* Try to reset the chip. */
1807 if (bge_chipinit(sc)) {
1808 device_printf(dev, "chip initialization failed\n");
1814 * Get station address from the EEPROM.
1816 mac_addr = bge_readmem_ind(sc, 0x0c14);
1817 if ((mac_addr >> 16) == 0x484b) {
1818 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1819 ether_addr[1] = (uint8_t)mac_addr;
1820 mac_addr = bge_readmem_ind(sc, 0x0c18);
1821 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1822 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1823 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1824 ether_addr[5] = (uint8_t)mac_addr;
1825 } else if (bge_read_eeprom(sc, ether_addr,
1826 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1827 device_printf(dev, "failed to read station address\n");
1832 /* 5705/5750 limits RX return ring to 512 entries. */
1833 if (BGE_IS_5705_PLUS(sc))
1834 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1836 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1838 error = bge_dma_alloc(sc);
1842 /* Set default tuneable values. */
1843 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1844 sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
1845 sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
1846 sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
1847 sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
1849 /* Set up ifnet structure */
1851 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1852 ifp->if_ioctl = bge_ioctl;
1853 ifp->if_start = bge_start;
1854 #ifdef DEVICE_POLLING
1855 ifp->if_poll = bge_poll;
1857 ifp->if_watchdog = bge_watchdog;
1858 ifp->if_init = bge_init;
1859 ifp->if_mtu = ETHERMTU;
1860 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1861 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1862 ifq_set_ready(&ifp->if_snd);
1865 * 5700 B0 chips do not support checksumming correctly due
1868 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
1869 ifp->if_capabilities |= IFCAP_HWCSUM;
1870 ifp->if_hwassist = BGE_CSUM_FEATURES;
1872 ifp->if_capenable = ifp->if_capabilities;
1875 * Figure out what sort of media we have by checking the
1876 * hardware config word in the first 32k of NIC internal memory,
1877 * or fall back to examining the EEPROM if necessary.
1878 * Note: on some BCM5700 cards, this value appears to be unset.
1879 * If that's the case, we have to rely on identifying the NIC
1880 * by its PCI subsystem ID, as we do below for the SysKonnect
1883 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1884 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1886 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1888 device_printf(dev, "failed to read EEPROM\n");
1892 hwcfg = ntohl(hwcfg);
1895 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1896 sc->bge_flags |= BGE_FLAG_TBI;
1898 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1899 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1900 sc->bge_flags |= BGE_FLAG_TBI;
1902 if (sc->bge_flags & BGE_FLAG_TBI) {
1903 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1904 bge_ifmedia_upd, bge_ifmedia_sts);
1905 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1906 ifmedia_add(&sc->bge_ifmedia,
1907 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1908 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1909 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1910 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
1913 * Do transceiver setup.
1915 if (mii_phy_probe(dev, &sc->bge_miibus,
1916 bge_ifmedia_upd, bge_ifmedia_sts)) {
1917 device_printf(dev, "MII without any PHY!\n");
1924 * When using the BCM5701 in PCI-X mode, data corruption has
1925 * been observed in the first few bytes of some received packets.
1926 * Aligning the packet buffer in memory eliminates the corruption.
1927 * Unfortunately, this misaligns the packet payloads. On platforms
1928 * which do not support unaligned accesses, we will realign the
1929 * payloads by copying the received packets.
1931 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1932 (sc->bge_flags & BGE_FLAG_PCIX))
1933 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
1935 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1936 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1937 sc->bge_link_upd = bge_bcm5700_link_upd;
1938 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
1939 } else if (sc->bge_flags & BGE_FLAG_TBI) {
1940 sc->bge_link_upd = bge_tbi_link_upd;
1941 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1943 sc->bge_link_upd = bge_copper_link_upd;
1944 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1948 * Create sysctl nodes.
1950 sysctl_ctx_init(&sc->bge_sysctl_ctx);
1951 sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
1952 SYSCTL_STATIC_CHILDREN(_hw),
1954 device_get_nameunit(dev),
1956 if (sc->bge_sysctl_tree == NULL) {
1957 device_printf(dev, "can't add sysctl node\n");
1962 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1963 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1964 OID_AUTO, "rx_coal_ticks",
1965 CTLTYPE_INT | CTLFLAG_RW,
1966 sc, 0, bge_sysctl_rx_coal_ticks, "I",
1967 "Receive coalescing ticks (usec).");
1968 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1969 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1970 OID_AUTO, "tx_coal_ticks",
1971 CTLTYPE_INT | CTLFLAG_RW,
1972 sc, 0, bge_sysctl_tx_coal_ticks, "I",
1973 "Transmit coalescing ticks (usec).");
1974 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1975 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1976 OID_AUTO, "rx_max_coal_bds",
1977 CTLTYPE_INT | CTLFLAG_RW,
1978 sc, 0, bge_sysctl_rx_max_coal_bds, "I",
1979 "Receive max coalesced BD count.");
1980 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1981 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1982 OID_AUTO, "tx_max_coal_bds",
1983 CTLTYPE_INT | CTLFLAG_RW,
1984 sc, 0, bge_sysctl_tx_max_coal_bds, "I",
1985 "Transmit max coalesced BD count.");
1988 * Call MI attach routine.
1990 ether_ifattach(ifp, ether_addr, NULL);
1992 error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE,
1993 bge_intr, sc, &sc->bge_intrhand,
1994 ifp->if_serializer);
1996 ether_ifdetach(ifp);
1997 device_printf(dev, "couldn't set up irq\n");
2001 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bge_irq));
2002 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2011 bge_detach(device_t dev)
2013 struct bge_softc *sc = device_get_softc(dev);
2015 if (device_is_attached(dev)) {
2016 struct ifnet *ifp = &sc->arpcom.ac_if;
2018 lwkt_serialize_enter(ifp->if_serializer);
2021 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2022 lwkt_serialize_exit(ifp->if_serializer);
2024 ether_ifdetach(ifp);
2027 if (sc->bge_flags & BGE_FLAG_TBI)
2028 ifmedia_removeall(&sc->bge_ifmedia);
2030 device_delete_child(dev, sc->bge_miibus);
2031 bus_generic_detach(dev);
2033 if (sc->bge_irq != NULL)
2034 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2036 if (sc->bge_res != NULL)
2037 bus_release_resource(dev, SYS_RES_MEMORY,
2038 BGE_PCI_BAR0, sc->bge_res);
2040 if (sc->bge_sysctl_tree != NULL)
2041 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2049 bge_reset(struct bge_softc *sc)
2052 uint32_t cachesize, command, pcistate, reset;
2053 void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2058 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc)) {
2059 if (sc->bge_flags & BGE_FLAG_PCIE)
2060 write_op = bge_writemem_direct;
2062 write_op = bge_writemem_ind;
2064 write_op = bge_writereg_ind;
2067 /* Save some important PCI state. */
2068 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2069 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2070 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2072 pci_write_config(dev, BGE_PCI_MISC_CTL,
2073 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2074 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2076 /* Disable fastboot on controllers that support it. */
2077 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2078 sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2079 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2081 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2082 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2086 * Write the magic number to SRAM at offset 0xB50.
2087 * When firmware finishes its initialization it will
2088 * write ~BGE_MAGIC_NUMBER to the same location.
2090 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2092 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2094 /* XXX: Broadcom Linux driver. */
2095 if (sc->bge_flags & BGE_FLAG_PCIE) {
2096 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */
2097 CSR_WRITE_4(sc, 0x7e2c, 0x20);
2098 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2099 /* Prevent PCIE link training during global reset */
2100 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2106 * Set GPHY Power Down Override to leave GPHY
2107 * powered up in D0 uninitialized.
2109 if (BGE_IS_5705_PLUS(sc))
2110 reset |= 0x04000000;
2112 /* Issue global reset */
2113 write_op(sc, BGE_MISC_CFG, reset);
2117 /* XXX: Broadcom Linux driver. */
2118 if (sc->bge_flags & BGE_FLAG_PCIE) {
2119 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2122 DELAY(500000); /* wait for link training to complete */
2123 v = pci_read_config(dev, 0xc4, 4);
2124 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2127 * Set PCIE max payload size to 128 bytes and
2128 * clear error status.
2130 pci_write_config(dev, 0xd8, 0xf5000, 4);
2133 /* Reset some of the PCI state that got zapped by reset */
2134 pci_write_config(dev, BGE_PCI_MISC_CTL,
2135 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2136 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2137 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2138 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2139 write_op(sc, BGE_MISC_CFG, (65 << 1));
2141 /* Enable memory arbiter. */
2142 if (BGE_IS_5714_FAMILY(sc)) {
2145 val = CSR_READ_4(sc, BGE_MARB_MODE);
2146 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2148 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2152 * Poll until we see the 1's complement of the magic number.
2153 * This indicates that the firmware initialization
2156 for (i = 0; i < BGE_TIMEOUT; i++) {
2157 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2158 if (val == ~BGE_MAGIC_NUMBER)
2163 if (i == BGE_TIMEOUT) {
2164 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out,"
2165 "found 0x%08x\n", val);
2170 * XXX Wait for the value of the PCISTATE register to
2171 * return to its original pre-reset state. This is a
2172 * fairly good indicator of reset completion. If we don't
2173 * wait for the reset to fully complete, trying to read
2174 * from the device's non-PCI registers may yield garbage
2177 for (i = 0; i < BGE_TIMEOUT; i++) {
2178 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2183 if (sc->bge_flags & BGE_FLAG_PCIE) {
2184 reset = bge_readmem_ind(sc, 0x7c00);
2185 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2188 /* Fix up byte swapping */
2189 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2190 BGE_MODECTL_BYTESWAP_DATA);
2192 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2195 * The 5704 in TBI mode apparently needs some special
2196 * adjustment to insure the SERDES drive level is set
2199 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2200 (sc->bge_flags & BGE_FLAG_TBI)) {
2203 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2204 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2205 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2208 /* XXX: Broadcom Linux driver. */
2209 if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2210 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2213 v = CSR_READ_4(sc, 0x7c00);
2214 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2221 * Frame reception handling. This is called if there's a frame
2222 * on the receive return list.
2224 * Note: we have to be able to handle two possibilities here:
2225 * 1) the frame is from the jumbo recieve ring
2226 * 2) the frame is from the standard receive ring
2230 bge_rxeof(struct bge_softc *sc)
2233 int stdcnt = 0, jumbocnt = 0;
2234 #ifdef ETHER_INPUT_CHAIN
2235 struct mbuf_chain chain[MAXCPU];
2238 if (sc->bge_rx_saved_considx ==
2239 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2242 #ifdef ETHER_INPUT_CHAIN
2243 ether_input_chain_init(chain);
2246 ifp = &sc->arpcom.ac_if;
2248 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2249 sc->bge_cdata.bge_rx_return_ring_map,
2250 BUS_DMASYNC_POSTREAD);
2251 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2252 sc->bge_cdata.bge_rx_std_ring_map,
2253 BUS_DMASYNC_POSTREAD);
2254 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2255 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2256 sc->bge_cdata.bge_rx_jumbo_ring_map,
2257 BUS_DMASYNC_POSTREAD);
2260 while (sc->bge_rx_saved_considx !=
2261 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2262 struct bge_rx_bd *cur_rx;
2264 struct mbuf *m = NULL;
2265 uint16_t vlan_tag = 0;
2269 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2271 rxidx = cur_rx->bge_idx;
2272 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2275 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2277 vlan_tag = cur_rx->bge_vlan_tag;
2280 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2281 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2282 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2283 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2285 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2287 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2290 if (bge_newbuf_jumbo(sc,
2291 sc->bge_jumbo, NULL) == ENOBUFS) {
2293 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2297 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2298 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2299 sc->bge_cdata.bge_rx_std_dmamap[rxidx],
2300 BUS_DMASYNC_POSTREAD);
2301 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2302 sc->bge_cdata.bge_rx_std_dmamap[rxidx]);
2303 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2304 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2306 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2308 bge_newbuf_std(sc, sc->bge_std, m);
2311 if (bge_newbuf_std(sc, sc->bge_std,
2314 bge_newbuf_std(sc, sc->bge_std, m);
2322 * The i386 allows unaligned accesses, but for other
2323 * platforms we must make sure the payload is aligned.
2325 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2326 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2328 m->m_data += ETHER_ALIGN;
2331 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2332 m->m_pkthdr.rcvif = ifp;
2334 if (ifp->if_capenable & IFCAP_RXCSUM) {
2335 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2336 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2337 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2338 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2340 if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2341 m->m_pkthdr.len >= BGE_MIN_FRAME) {
2342 m->m_pkthdr.csum_data =
2343 cur_rx->bge_tcp_udp_csum;
2344 m->m_pkthdr.csum_flags |=
2345 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2350 * If we received a packet with a vlan tag, pass it
2351 * to vlan_input() instead of ether_input().
2354 m->m_flags |= M_VLANTAG;
2355 m->m_pkthdr.ether_vlantag = vlan_tag;
2356 have_tag = vlan_tag = 0;
2358 #ifdef ETHER_INPUT_CHAIN
2359 ether_input_chain2(ifp, m, chain);
2361 ifp->if_input(ifp, m);
2365 #ifdef ETHER_INPUT_CHAIN
2366 ether_input_dispatch(chain);
2370 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2371 sc->bge_cdata.bge_rx_std_ring_map,
2372 BUS_DMASYNC_PREWRITE);
2375 if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) {
2376 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2377 sc->bge_cdata.bge_rx_jumbo_ring_map,
2378 BUS_DMASYNC_PREWRITE);
2381 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2383 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2385 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2389 bge_txeof(struct bge_softc *sc)
2391 struct bge_tx_bd *cur_tx = NULL;
2394 if (sc->bge_tx_saved_considx ==
2395 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2398 ifp = &sc->arpcom.ac_if;
2400 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
2401 sc->bge_cdata.bge_tx_ring_map,
2402 BUS_DMASYNC_POSTREAD);
2405 * Go through our tx ring and free mbufs for those
2406 * frames that have been sent.
2408 while (sc->bge_tx_saved_considx !=
2409 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2412 idx = sc->bge_tx_saved_considx;
2413 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2414 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2416 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2417 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2418 sc->bge_cdata.bge_tx_dmamap[idx],
2419 BUS_DMASYNC_POSTWRITE);
2420 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2421 sc->bge_cdata.bge_tx_dmamap[idx]);
2422 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2423 sc->bge_cdata.bge_tx_chain[idx] = NULL;
2426 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2430 if (cur_tx != NULL &&
2431 (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2432 (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2433 ifp->if_flags &= ~IFF_OACTIVE;
2435 if (sc->bge_txcnt == 0)
2438 if (!ifq_is_empty(&ifp->if_snd))
2442 #ifdef DEVICE_POLLING
2445 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2447 struct bge_softc *sc = ifp->if_softc;
2452 bge_disable_intr(sc);
2454 case POLL_DEREGISTER:
2455 bge_enable_intr(sc);
2457 case POLL_AND_CHECK_STATUS:
2458 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2459 sc->bge_cdata.bge_status_map,
2460 BUS_DMASYNC_POSTREAD);
2463 * Process link state changes.
2465 status = CSR_READ_4(sc, BGE_MAC_STS);
2466 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2467 sc->bge_link_evt = 0;
2468 sc->bge_link_upd(sc, status);
2472 if (ifp->if_flags & IFF_RUNNING) {
2485 struct bge_softc *sc = xsc;
2486 struct ifnet *ifp = &sc->arpcom.ac_if;
2492 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
2493 * disable interrupts by writing nonzero like we used to, since with
2494 * our current organization this just gives complications and
2495 * pessimizations for re-enabling interrupts. We used to have races
2496 * instead of the necessary complications. Disabling interrupts
2497 * would just reduce the chance of a status update while we are
2498 * running (by switching to the interrupt-mode coalescence
2499 * parameters), but this chance is already very low so it is more
2500 * efficient to get another interrupt than prevent it.
2502 * We do the ack first to ensure another interrupt if there is a
2503 * status update after the ack. We don't check for the status
2504 * changing later because it is more efficient to get another
2505 * interrupt than prevent it, not quite as above (not checking is
2506 * a smaller optimization than not toggling the interrupt enable,
2507 * since checking doesn't involve PCI accesses and toggling require
2508 * the status check). So toggling would probably be a pessimization
2509 * even with MSI. It would only be needed for using a task queue.
2511 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2513 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2514 sc->bge_cdata.bge_status_map,
2515 BUS_DMASYNC_POSTREAD);
2518 * Process link state changes.
2520 status = CSR_READ_4(sc, BGE_MAC_STS);
2521 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2522 sc->bge_link_evt = 0;
2523 sc->bge_link_upd(sc, status);
2526 if (ifp->if_flags & IFF_RUNNING) {
2527 /* Check RX return ring producer/consumer */
2530 /* Check TX ring producer/consumer */
2534 if (sc->bge_coal_chg)
2535 bge_coal_change(sc);
2541 struct bge_softc *sc = xsc;
2542 struct ifnet *ifp = &sc->arpcom.ac_if;
2544 lwkt_serialize_enter(ifp->if_serializer);
2546 if (BGE_IS_5705_PLUS(sc))
2547 bge_stats_update_regs(sc);
2549 bge_stats_update(sc);
2551 if (sc->bge_flags & BGE_FLAG_TBI) {
2553 * Since in TBI mode auto-polling can't be used we should poll
2554 * link status manually. Here we register pending link event
2555 * and trigger interrupt.
2558 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2559 } else if (!sc->bge_link) {
2560 mii_tick(device_get_softc(sc->bge_miibus));
2563 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2565 lwkt_serialize_exit(ifp->if_serializer);
2569 bge_stats_update_regs(struct bge_softc *sc)
2571 struct ifnet *ifp = &sc->arpcom.ac_if;
2572 struct bge_mac_stats_regs stats;
2576 s = (uint32_t *)&stats;
2577 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2578 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2582 ifp->if_collisions +=
2583 (stats.dot3StatsSingleCollisionFrames +
2584 stats.dot3StatsMultipleCollisionFrames +
2585 stats.dot3StatsExcessiveCollisions +
2586 stats.dot3StatsLateCollisions) -
2591 bge_stats_update(struct bge_softc *sc)
2593 struct ifnet *ifp = &sc->arpcom.ac_if;
2596 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2598 #define READ_STAT(sc, stats, stat) \
2599 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2601 ifp->if_collisions +=
2602 (READ_STAT(sc, stats,
2603 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2604 READ_STAT(sc, stats,
2605 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2606 READ_STAT(sc, stats,
2607 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2608 READ_STAT(sc, stats,
2609 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
2615 ifp->if_collisions +=
2616 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2617 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2618 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2619 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2625 bge_cksum_pad(struct mbuf *pkt)
2627 struct mbuf *last = NULL;
2630 padlen = BGE_MIN_FRAME - pkt->m_pkthdr.len;
2632 /* if there's only the packet-header and we can pad there, use it. */
2633 if (pkt->m_pkthdr.len == pkt->m_len &&
2634 M_TRAILINGSPACE(pkt) >= padlen) {
2638 * Walk packet chain to find last mbuf. We will either
2639 * pad there, or append a new mbuf and pad it
2640 * (thus perhaps avoiding the bcm5700 dma-min bug).
2642 for (last = pkt; last->m_next != NULL; last = last->m_next)
2645 /* `last' now points to last in chain. */
2646 if (M_TRAILINGSPACE(last) < padlen) {
2647 /* Allocate new empty mbuf, pad it. Compact later. */
2649 MGET(n, MB_DONTWAIT, MT_DATA);
2657 KKASSERT(M_TRAILINGSPACE(last) >= padlen);
2658 KKASSERT(M_WRITABLE(last));
2660 /* Now zero the pad area, to avoid the bge cksum-assist bug */
2661 bzero(mtod(last, char *) + last->m_len, padlen);
2662 last->m_len += padlen;
2663 pkt->m_pkthdr.len += padlen;
2668 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2669 * pointers to descriptors.
2672 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
2674 struct bge_tx_bd *d = NULL;
2675 uint16_t csum_flags = 0;
2676 struct bge_dmamap_arg ctx;
2677 bus_dma_segment_t segs[BGE_NSEG_NEW];
2679 int error, maxsegs, idx, i;
2680 struct mbuf *m_head = *m_head0;
2682 if (m_head->m_pkthdr.csum_flags) {
2683 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2684 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2685 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2686 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2687 if (m_head->m_flags & M_LASTFRAG)
2688 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2689 else if (m_head->m_flags & M_FRAG)
2690 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2694 map = sc->bge_cdata.bge_tx_dmamap[idx];
2696 maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2697 KASSERT(maxsegs >= BGE_NSEG_SPARE,
2698 ("not enough segments %d\n", maxsegs));
2700 if (maxsegs > BGE_NSEG_NEW)
2701 maxsegs = BGE_NSEG_NEW;
2704 * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2705 * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2706 * but when such padded frames employ the bge IP/TCP checksum
2707 * offload, the hardware checksum assist gives incorrect results
2708 * (possibly from incorporating its own padding into the UDP/TCP
2709 * checksum; who knows). If we pad such runts with zeros, the
2710 * onboard checksum comes out correct.
2712 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2713 m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2714 error = bge_cksum_pad(m_head);
2719 ctx.bge_segs = segs;
2720 ctx.bge_maxsegs = maxsegs;
2721 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map, m_head,
2722 bge_dma_map_mbuf, &ctx, BUS_DMA_NOWAIT);
2723 if (error == EFBIG || ctx.bge_maxsegs == 0) {
2727 bus_dmamap_unload(sc->bge_cdata.bge_mtag, map);
2729 m_new = m_defrag(m_head, MB_DONTWAIT);
2730 if (m_new == NULL) {
2731 if_printf(&sc->arpcom.ac_if,
2732 "could not defrag TX mbuf\n");
2740 ctx.bge_segs = segs;
2741 ctx.bge_maxsegs = maxsegs;
2742 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2743 m_head, bge_dma_map_mbuf, &ctx,
2745 if (error || ctx.bge_maxsegs == 0) {
2746 if_printf(&sc->arpcom.ac_if,
2747 "could not defrag TX mbuf\n");
2749 bus_dmamap_unload(sc->bge_cdata.bge_mtag, map);
2755 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
2759 bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE);
2761 for (i = 0; ; i++) {
2762 d = &sc->bge_ldata.bge_tx_ring[idx];
2764 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[i].ds_addr);
2765 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[i].ds_addr);
2766 d->bge_len = segs[i].ds_len;
2767 d->bge_flags = csum_flags;
2769 if (i == ctx.bge_maxsegs - 1)
2771 BGE_INC(idx, BGE_TX_RING_CNT);
2773 /* Mark the last segment as end of packet... */
2774 d->bge_flags |= BGE_TXBDFLAG_END;
2776 /* Set vlan tag to the first segment of the packet. */
2777 d = &sc->bge_ldata.bge_tx_ring[*txidx];
2778 if (m_head->m_flags & M_VLANTAG) {
2779 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2780 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
2782 d->bge_vlan_tag = 0;
2786 * Insure that the map for this transmission is placed at
2787 * the array index of the last descriptor in this chain.
2789 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2790 sc->bge_cdata.bge_tx_dmamap[idx] = map;
2791 sc->bge_cdata.bge_tx_chain[idx] = m_head;
2792 sc->bge_txcnt += ctx.bge_maxsegs;
2794 BGE_INC(idx, BGE_TX_RING_CNT);
2805 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2806 * to the mbuf data regions directly in the transmit descriptors.
2809 bge_start(struct ifnet *ifp)
2811 struct bge_softc *sc = ifp->if_softc;
2812 struct mbuf *m_head = NULL;
2816 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2819 prodidx = sc->bge_tx_prodidx;
2822 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2823 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2829 * The code inside the if() block is never reached since we
2830 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2831 * requests to checksum TCP/UDP in a fragmented packet.
2834 * safety overkill. If this is a fragmented packet chain
2835 * with delayed TCP/UDP checksums, then only encapsulate
2836 * it if we have enough descriptors to handle the entire
2838 * (paranoia -- may not actually be needed)
2840 if ((m_head->m_flags & M_FIRSTFRAG) &&
2841 (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
2842 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2843 m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
2844 ifp->if_flags |= IFF_OACTIVE;
2845 ifq_prepend(&ifp->if_snd, m_head);
2851 * Sanity check: avoid coming within BGE_NSEG_RSVD
2852 * descriptors of the end of the ring. Also make
2853 * sure there are BGE_NSEG_SPARE descriptors for
2854 * jumbo buffers' defragmentation.
2856 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2857 (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
2858 ifp->if_flags |= IFF_OACTIVE;
2859 ifq_prepend(&ifp->if_snd, m_head);
2864 * Pack the data into the transmit ring. If we
2865 * don't have room, set the OACTIVE flag and wait
2866 * for the NIC to drain the ring.
2868 if (bge_encap(sc, &m_head, &prodidx)) {
2869 ifp->if_flags |= IFF_OACTIVE;
2875 ETHER_BPF_MTAP(ifp, m_head);
2882 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2883 /* 5700 b2 errata */
2884 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2885 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2887 sc->bge_tx_prodidx = prodidx;
2890 * Set a timeout in case the chip goes out to lunch.
2898 struct bge_softc *sc = xsc;
2899 struct ifnet *ifp = &sc->arpcom.ac_if;
2902 ASSERT_SERIALIZED(ifp->if_serializer);
2904 if (ifp->if_flags & IFF_RUNNING)
2907 /* Cancel pending I/O and flush buffers. */
2913 * Init the various state machines, ring
2914 * control blocks and firmware.
2916 if (bge_blockinit(sc)) {
2917 if_printf(ifp, "initialization failure\n");
2922 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2923 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2925 /* Load our MAC address. */
2926 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2927 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2928 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2930 /* Enable or disable promiscuous mode as needed. */
2933 /* Program multicast filter. */
2937 bge_init_rx_ring_std(sc);
2940 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2941 * memory to insure that the chip has in fact read the first
2942 * entry of the ring.
2944 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2946 for (i = 0; i < 10; i++) {
2948 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2949 if (v == (MCLBYTES - ETHER_ALIGN))
2953 if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
2956 /* Init jumbo RX ring. */
2957 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2958 bge_init_rx_ring_jumbo(sc);
2960 /* Init our RX return ring index */
2961 sc->bge_rx_saved_considx = 0;
2964 bge_init_tx_ring(sc);
2966 /* Turn on transmitter */
2967 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2969 /* Turn on receiver */
2970 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2972 /* Tell firmware we're alive. */
2973 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2975 /* Enable host interrupts if polling(4) is not enabled. */
2976 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2977 #ifdef DEVICE_POLLING
2978 if (ifp->if_flags & IFF_POLLING)
2979 bge_disable_intr(sc);
2982 bge_enable_intr(sc);
2984 bge_ifmedia_upd(ifp);
2986 ifp->if_flags |= IFF_RUNNING;
2987 ifp->if_flags &= ~IFF_OACTIVE;
2989 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2993 * Set media options.
2996 bge_ifmedia_upd(struct ifnet *ifp)
2998 struct bge_softc *sc = ifp->if_softc;
3000 /* If this is a 1000baseX NIC, enable the TBI port. */
3001 if (sc->bge_flags & BGE_FLAG_TBI) {
3002 struct ifmedia *ifm = &sc->bge_ifmedia;
3004 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3007 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3010 * The BCM5704 ASIC appears to have a special
3011 * mechanism for programming the autoneg
3012 * advertisement registers in TBI mode.
3014 if (!bge_fake_autoneg &&
3015 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3018 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3019 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3020 sgdig |= BGE_SGDIGCFG_AUTO |
3021 BGE_SGDIGCFG_PAUSE_CAP |
3022 BGE_SGDIGCFG_ASYM_PAUSE;
3023 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3024 sgdig | BGE_SGDIGCFG_SEND);
3026 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3030 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3031 BGE_CLRBIT(sc, BGE_MAC_MODE,
3032 BGE_MACMODE_HALF_DUPLEX);
3034 BGE_SETBIT(sc, BGE_MAC_MODE,
3035 BGE_MACMODE_HALF_DUPLEX);
3042 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3046 if (mii->mii_instance) {
3047 struct mii_softc *miisc;
3049 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3050 mii_phy_reset(miisc);
3058 * Report current media status.
3061 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3063 struct bge_softc *sc = ifp->if_softc;
3065 if (sc->bge_flags & BGE_FLAG_TBI) {
3066 ifmr->ifm_status = IFM_AVALID;
3067 ifmr->ifm_active = IFM_ETHER;
3068 if (CSR_READ_4(sc, BGE_MAC_STS) &
3069 BGE_MACSTAT_TBI_PCS_SYNCHED) {
3070 ifmr->ifm_status |= IFM_ACTIVE;
3072 ifmr->ifm_active |= IFM_NONE;
3076 ifmr->ifm_active |= IFM_1000_SX;
3077 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3078 ifmr->ifm_active |= IFM_HDX;
3080 ifmr->ifm_active |= IFM_FDX;
3082 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3085 ifmr->ifm_active = mii->mii_media_active;
3086 ifmr->ifm_status = mii->mii_media_status;
3091 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3093 struct bge_softc *sc = ifp->if_softc;
3094 struct ifreq *ifr = (struct ifreq *)data;
3095 int mask, error = 0;
3097 ASSERT_SERIALIZED(ifp->if_serializer);
3101 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3102 (BGE_IS_JUMBO_CAPABLE(sc) &&
3103 ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3105 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3106 ifp->if_mtu = ifr->ifr_mtu;
3107 ifp->if_flags &= ~IFF_RUNNING;
3112 if (ifp->if_flags & IFF_UP) {
3113 if (ifp->if_flags & IFF_RUNNING) {
3114 mask = ifp->if_flags ^ sc->bge_if_flags;
3117 * If only the state of the PROMISC flag
3118 * changed, then just use the 'set promisc
3119 * mode' command instead of reinitializing
3120 * the entire NIC. Doing a full re-init
3121 * means reloading the firmware and waiting
3122 * for it to start up, which may take a
3123 * second or two. Similarly for ALLMULTI.
3125 if (mask & IFF_PROMISC)
3127 if (mask & IFF_ALLMULTI)
3133 if (ifp->if_flags & IFF_RUNNING)
3136 sc->bge_if_flags = ifp->if_flags;
3140 if (ifp->if_flags & IFF_RUNNING)
3145 if (sc->bge_flags & BGE_FLAG_TBI) {
3146 error = ifmedia_ioctl(ifp, ifr,
3147 &sc->bge_ifmedia, command);
3149 struct mii_data *mii;
3151 mii = device_get_softc(sc->bge_miibus);
3152 error = ifmedia_ioctl(ifp, ifr,
3153 &mii->mii_media, command);
3157 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3158 if (mask & IFCAP_HWCSUM) {
3159 ifp->if_capenable ^= IFCAP_HWCSUM;
3160 if (IFCAP_HWCSUM & ifp->if_capenable)
3161 ifp->if_hwassist = BGE_CSUM_FEATURES;
3163 ifp->if_hwassist = 0;
3167 error = ether_ioctl(ifp, command, data);
3174 bge_watchdog(struct ifnet *ifp)
3176 struct bge_softc *sc = ifp->if_softc;
3178 if_printf(ifp, "watchdog timeout -- resetting\n");
3180 ifp->if_flags &= ~IFF_RUNNING;
3185 if (!ifq_is_empty(&ifp->if_snd))
3190 * Stop the adapter and free any mbufs allocated to the
3194 bge_stop(struct bge_softc *sc)
3196 struct ifnet *ifp = &sc->arpcom.ac_if;
3197 struct ifmedia_entry *ifm;
3198 struct mii_data *mii = NULL;
3201 ASSERT_SERIALIZED(ifp->if_serializer);
3203 if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
3204 mii = device_get_softc(sc->bge_miibus);
3206 callout_stop(&sc->bge_stat_timer);
3209 * Disable all of the receiver blocks
3211 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3212 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3213 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3214 if (!BGE_IS_5705_PLUS(sc))
3215 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3216 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3217 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3218 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3221 * Disable all of the transmit blocks
3223 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3224 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3225 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3226 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3227 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3228 if (!BGE_IS_5705_PLUS(sc))
3229 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3230 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3233 * Shut down all of the memory managers and related
3236 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3237 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3238 if (!BGE_IS_5705_PLUS(sc))
3239 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3240 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3241 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3242 if (!BGE_IS_5705_PLUS(sc)) {
3243 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3244 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3247 /* Disable host interrupts. */
3248 bge_disable_intr(sc);
3251 * Tell firmware we're shutting down.
3253 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3255 /* Free the RX lists. */
3256 bge_free_rx_ring_std(sc);
3258 /* Free jumbo RX list. */
3259 if (BGE_IS_JUMBO_CAPABLE(sc))
3260 bge_free_rx_ring_jumbo(sc);
3262 /* Free TX buffers. */
3263 bge_free_tx_ring(sc);
3266 * Isolate/power down the PHY, but leave the media selection
3267 * unchanged so that things will be put back to normal when
3268 * we bring the interface back up.
3270 * 'mii' may be NULL in the following cases:
3271 * - The device uses TBI.
3272 * - bge_stop() is called by bge_detach().
3275 itmp = ifp->if_flags;
3276 ifp->if_flags |= IFF_UP;
3277 ifm = mii->mii_media.ifm_cur;
3278 mtmp = ifm->ifm_media;
3279 ifm->ifm_media = IFM_ETHER|IFM_NONE;
3281 ifm->ifm_media = mtmp;
3282 ifp->if_flags = itmp;
3286 sc->bge_coal_chg = 0;
3288 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3290 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3295 * Stop all chip I/O so that the kernel's probe routines don't
3296 * get confused by errant DMAs when rebooting.
3299 bge_shutdown(device_t dev)
3301 struct bge_softc *sc = device_get_softc(dev);
3302 struct ifnet *ifp = &sc->arpcom.ac_if;
3304 lwkt_serialize_enter(ifp->if_serializer);
3307 lwkt_serialize_exit(ifp->if_serializer);
3311 bge_suspend(device_t dev)
3313 struct bge_softc *sc = device_get_softc(dev);
3314 struct ifnet *ifp = &sc->arpcom.ac_if;
3316 lwkt_serialize_enter(ifp->if_serializer);
3318 lwkt_serialize_exit(ifp->if_serializer);
3324 bge_resume(device_t dev)
3326 struct bge_softc *sc = device_get_softc(dev);
3327 struct ifnet *ifp = &sc->arpcom.ac_if;
3329 lwkt_serialize_enter(ifp->if_serializer);
3331 if (ifp->if_flags & IFF_UP) {
3334 if (!ifq_is_empty(&ifp->if_snd))
3338 lwkt_serialize_exit(ifp->if_serializer);
3344 bge_setpromisc(struct bge_softc *sc)
3346 struct ifnet *ifp = &sc->arpcom.ac_if;
3348 if (ifp->if_flags & IFF_PROMISC)
3349 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3351 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3355 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3357 struct bge_dmamap_arg *ctx = arg;
3362 KASSERT(nsegs == 1 && ctx->bge_maxsegs == 1,
3363 ("only one segment is allowed\n"));
3365 ctx->bge_segs[0] = *segs;
3369 bge_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nsegs,
3370 bus_size_t mapsz __unused, int error)
3372 struct bge_dmamap_arg *ctx = arg;
3378 if (nsegs > ctx->bge_maxsegs) {
3379 ctx->bge_maxsegs = 0;
3383 ctx->bge_maxsegs = nsegs;
3384 for (i = 0; i < nsegs; ++i)
3385 ctx->bge_segs[i] = segs[i];
3389 bge_dma_free(struct bge_softc *sc)
3393 /* Destroy RX/TX mbuf DMA stuffs. */
3394 if (sc->bge_cdata.bge_mtag != NULL) {
3395 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3396 if (sc->bge_cdata.bge_rx_std_dmamap[i]) {
3397 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3398 sc->bge_cdata.bge_rx_std_dmamap[i]);
3402 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3403 if (sc->bge_cdata.bge_tx_dmamap[i]) {
3404 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3405 sc->bge_cdata.bge_tx_dmamap[i]);
3408 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3411 /* Destroy standard RX ring */
3412 bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3413 sc->bge_cdata.bge_rx_std_ring_map,
3414 sc->bge_ldata.bge_rx_std_ring);
3416 if (BGE_IS_JUMBO_CAPABLE(sc))
3417 bge_free_jumbo_mem(sc);
3419 /* Destroy RX return ring */
3420 bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3421 sc->bge_cdata.bge_rx_return_ring_map,
3422 sc->bge_ldata.bge_rx_return_ring);
3424 /* Destroy TX ring */
3425 bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3426 sc->bge_cdata.bge_tx_ring_map,
3427 sc->bge_ldata.bge_tx_ring);
3429 /* Destroy status block */
3430 bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3431 sc->bge_cdata.bge_status_map,
3432 sc->bge_ldata.bge_status_block);
3434 /* Destroy statistics block */
3435 bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3436 sc->bge_cdata.bge_stats_map,
3437 sc->bge_ldata.bge_stats);
3439 /* Destroy the parent tag */
3440 if (sc->bge_cdata.bge_parent_tag != NULL)
3441 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3445 bge_dma_alloc(struct bge_softc *sc)
3447 struct ifnet *ifp = &sc->arpcom.ac_if;
3451 * Allocate the parent bus DMA tag appropriate for PCI.
3453 error = bus_dma_tag_create(NULL, 1, 0,
3454 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3456 MAXBSIZE, BGE_NSEG_NEW,
3457 BUS_SPACE_MAXSIZE_32BIT,
3458 0, &sc->bge_cdata.bge_parent_tag);
3460 if_printf(ifp, "could not allocate parent dma tag\n");
3465 * Create DMA tag for mbufs.
3467 nseg = BGE_NSEG_NEW;
3468 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3469 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3471 MCLBYTES * nseg, nseg, MCLBYTES,
3472 BUS_DMA_ALLOCNOW, &sc->bge_cdata.bge_mtag);
3474 if_printf(ifp, "could not allocate mbuf dma tag\n");
3479 * Create DMA maps for TX/RX mbufs.
3481 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3482 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3483 &sc->bge_cdata.bge_rx_std_dmamap[i]);
3487 for (j = 0; j < i; ++j) {
3488 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3489 sc->bge_cdata.bge_rx_std_dmamap[j]);
3491 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3492 sc->bge_cdata.bge_mtag = NULL;
3494 if_printf(ifp, "could not create DMA map for RX\n");
3499 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3500 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3501 &sc->bge_cdata.bge_tx_dmamap[i]);
3505 for (j = 0; j < BGE_STD_RX_RING_CNT; ++j) {
3506 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3507 sc->bge_cdata.bge_rx_std_dmamap[j]);
3509 for (j = 0; j < i; ++j) {
3510 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3511 sc->bge_cdata.bge_tx_dmamap[j]);
3513 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3514 sc->bge_cdata.bge_mtag = NULL;
3516 if_printf(ifp, "could not create DMA map for TX\n");
3522 * Create DMA stuffs for standard RX ring.
3524 error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3525 &sc->bge_cdata.bge_rx_std_ring_tag,
3526 &sc->bge_cdata.bge_rx_std_ring_map,
3527 (void **)&sc->bge_ldata.bge_rx_std_ring,
3528 &sc->bge_ldata.bge_rx_std_ring_paddr);
3530 if_printf(ifp, "could not create std RX ring\n");
3535 * Create jumbo buffer pool.
3537 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3538 error = bge_alloc_jumbo_mem(sc);
3540 if_printf(ifp, "could not create jumbo buffer pool\n");
3546 * Create DMA stuffs for RX return ring.
3548 error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3549 &sc->bge_cdata.bge_rx_return_ring_tag,
3550 &sc->bge_cdata.bge_rx_return_ring_map,
3551 (void **)&sc->bge_ldata.bge_rx_return_ring,
3552 &sc->bge_ldata.bge_rx_return_ring_paddr);
3554 if_printf(ifp, "could not create RX ret ring\n");
3559 * Create DMA stuffs for TX ring.
3561 error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3562 &sc->bge_cdata.bge_tx_ring_tag,
3563 &sc->bge_cdata.bge_tx_ring_map,
3564 (void **)&sc->bge_ldata.bge_tx_ring,
3565 &sc->bge_ldata.bge_tx_ring_paddr);
3567 if_printf(ifp, "could not create TX ring\n");
3572 * Create DMA stuffs for status block.
3574 error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3575 &sc->bge_cdata.bge_status_tag,
3576 &sc->bge_cdata.bge_status_map,
3577 (void **)&sc->bge_ldata.bge_status_block,
3578 &sc->bge_ldata.bge_status_block_paddr);
3580 if_printf(ifp, "could not create status block\n");
3585 * Create DMA stuffs for statistics block.
3587 error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3588 &sc->bge_cdata.bge_stats_tag,
3589 &sc->bge_cdata.bge_stats_map,
3590 (void **)&sc->bge_ldata.bge_stats,
3591 &sc->bge_ldata.bge_stats_paddr);
3593 if_printf(ifp, "could not create stats block\n");
3600 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3601 bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3603 struct ifnet *ifp = &sc->arpcom.ac_if;
3604 struct bge_dmamap_arg ctx;
3605 bus_dma_segment_t seg;
3611 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3612 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3613 NULL, NULL, size, 1, size, 0, tag);
3615 if_printf(ifp, "could not allocate dma tag\n");
3620 * Allocate DMA'able memory
3622 error = bus_dmamem_alloc(*tag, addr, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3625 if_printf(ifp, "could not allocate dma memory\n");
3626 bus_dma_tag_destroy(*tag);
3632 * Load the DMA'able memory
3634 ctx.bge_maxsegs = 1;
3635 ctx.bge_segs = &seg;
3636 error = bus_dmamap_load(*tag, *map, *addr, size, bge_dma_map_addr, &ctx,
3639 if_printf(ifp, "could not load dma memory\n");
3640 bus_dmamem_free(*tag, *addr, *map);
3641 bus_dma_tag_destroy(*tag);
3645 *paddr = ctx.bge_segs[0].ds_addr;
3651 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3654 bus_dmamap_unload(tag, map);
3655 bus_dmamem_free(tag, addr, map);
3656 bus_dma_tag_destroy(tag);
3661 * Grrr. The link status word in the status block does
3662 * not work correctly on the BCM5700 rev AX and BX chips,
3663 * according to all available information. Hence, we have
3664 * to enable MII interrupts in order to properly obtain
3665 * async link changes. Unfortunately, this also means that
3666 * we have to read the MAC status register to detect link
3667 * changes, thereby adding an additional register access to
3668 * the interrupt handler.
3670 * XXX: perhaps link state detection procedure used for
3671 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3674 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3676 struct ifnet *ifp = &sc->arpcom.ac_if;
3677 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3681 if (!sc->bge_link &&
3682 (mii->mii_media_status & IFM_ACTIVE) &&
3683 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3686 if_printf(ifp, "link UP\n");
3687 } else if (sc->bge_link &&
3688 (!(mii->mii_media_status & IFM_ACTIVE) ||
3689 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3692 if_printf(ifp, "link DOWN\n");
3695 /* Clear the interrupt. */
3696 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
3697 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
3698 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
3702 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
3704 struct ifnet *ifp = &sc->arpcom.ac_if;
3706 #define PCS_ENCODE_ERR (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3709 * Sometimes PCS encoding errors are detected in
3710 * TBI mode (on fiber NICs), and for some reason
3711 * the chip will signal them as link changes.
3712 * If we get a link change event, but the 'PCS
3713 * encoding error' bit in the MAC status register
3714 * is set, don't bother doing a link check.
3715 * This avoids spurious "gigabit link up" messages
3716 * that sometimes appear on fiber NICs during
3717 * periods of heavy traffic.
3719 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3720 if (!sc->bge_link) {
3722 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3723 BGE_CLRBIT(sc, BGE_MAC_MODE,
3724 BGE_MACMODE_TBI_SEND_CFGS);
3726 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3729 if_printf(ifp, "link UP\n");
3731 ifp->if_link_state = LINK_STATE_UP;
3732 if_link_state_change(ifp);
3734 } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3739 if_printf(ifp, "link DOWN\n");
3741 ifp->if_link_state = LINK_STATE_DOWN;
3742 if_link_state_change(ifp);
3746 #undef PCS_ENCODE_ERR
3748 /* Clear the attention. */
3749 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3750 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3751 BGE_MACSTAT_LINK_CHANGED);
3755 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
3758 * Check that the AUTOPOLL bit is set before
3759 * processing the event as a real link change.
3760 * Turning AUTOPOLL on and off in the MII read/write
3761 * functions will often trigger a link status
3762 * interrupt for no reason.
3764 if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
3765 struct ifnet *ifp = &sc->arpcom.ac_if;
3766 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3770 if (!sc->bge_link &&
3771 (mii->mii_media_status & IFM_ACTIVE) &&
3772 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3775 if_printf(ifp, "link UP\n");
3776 } else if (sc->bge_link &&
3777 (!(mii->mii_media_status & IFM_ACTIVE) ||
3778 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3781 if_printf(ifp, "link DOWN\n");
3785 /* Clear the attention. */
3786 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3787 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3788 BGE_MACSTAT_LINK_CHANGED);
3792 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3794 struct bge_softc *sc = arg1;
3796 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3797 &sc->bge_rx_coal_ticks,
3798 BGE_RX_COAL_TICKS_CHG);
3802 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3804 struct bge_softc *sc = arg1;
3806 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3807 &sc->bge_tx_coal_ticks,
3808 BGE_TX_COAL_TICKS_CHG);
3812 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3814 struct bge_softc *sc = arg1;
3816 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3817 &sc->bge_rx_max_coal_bds,
3818 BGE_RX_MAX_COAL_BDS_CHG);
3822 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3824 struct bge_softc *sc = arg1;
3826 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3827 &sc->bge_tx_max_coal_bds,
3828 BGE_TX_MAX_COAL_BDS_CHG);
3832 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3833 uint32_t coal_chg_mask)
3835 struct bge_softc *sc = arg1;
3836 struct ifnet *ifp = &sc->arpcom.ac_if;
3839 lwkt_serialize_enter(ifp->if_serializer);
3842 error = sysctl_handle_int(oidp, &v, 0, req);
3843 if (!error && req->newptr != NULL) {
3848 sc->bge_coal_chg |= coal_chg_mask;
3852 lwkt_serialize_exit(ifp->if_serializer);
3857 bge_coal_change(struct bge_softc *sc)
3859 struct ifnet *ifp = &sc->arpcom.ac_if;
3862 ASSERT_SERIALIZED(ifp->if_serializer);
3864 if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
3865 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3866 sc->bge_rx_coal_ticks);
3868 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3871 if_printf(ifp, "rx_coal_ticks -> %u\n",
3872 sc->bge_rx_coal_ticks);
3876 if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
3877 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3878 sc->bge_tx_coal_ticks);
3880 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3883 if_printf(ifp, "tx_coal_ticks -> %u\n",
3884 sc->bge_tx_coal_ticks);
3888 if (sc->bge_coal_chg & BGE_RX_MAX_COAL_BDS_CHG) {
3889 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3890 sc->bge_rx_max_coal_bds);
3892 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3895 if_printf(ifp, "rx_max_coal_bds -> %u\n",
3896 sc->bge_rx_max_coal_bds);
3900 if (sc->bge_coal_chg & BGE_TX_MAX_COAL_BDS_CHG) {
3901 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3902 sc->bge_tx_max_coal_bds);
3904 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3907 if_printf(ifp, "tx_max_coal_bds -> %u\n",
3908 sc->bge_tx_max_coal_bds);
3912 sc->bge_coal_chg = 0;
3916 bge_enable_intr(struct bge_softc *sc)
3918 struct ifnet *ifp = &sc->arpcom.ac_if;
3920 lwkt_serialize_handler_enable(ifp->if_serializer);
3925 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
3928 * Unmask the interrupt when we stop polling.
3930 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3933 * Trigger another interrupt, since above writing
3934 * to interrupt mailbox0 may acknowledge pending
3937 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3941 bge_disable_intr(struct bge_softc *sc)
3943 struct ifnet *ifp = &sc->arpcom.ac_if;
3946 * Mask the interrupt when we start polling.
3948 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3951 * Acknowledge possible asserted interrupt.
3953 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3955 lwkt_serialize_handler_disable(ifp->if_serializer);