3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.99 2008/10/30 11:27:40 sephe Exp $
40 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
51 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
64 * o TCP/IP checksum offload for both RX and TX
66 * o High and normal priority transmit DMA rings
68 * o VLAN tag insertion and extraction
70 * o TCP large send (segmentation offload)
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
85 * o GMII and TBI ports/registers for interfacing with copper
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
91 * o Slight differences in register layout from the 8139C+
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7440, so the max MTU possible with this
111 * driver is 7422 bytes.
116 #include "opt_polling.h"
118 #include <sys/param.h>
120 #include <sys/endian.h>
121 #include <sys/kernel.h>
122 #include <sys/in_cksum.h>
123 #include <sys/interrupt.h>
124 #include <sys/malloc.h>
125 #include <sys/mbuf.h>
126 #include <sys/rman.h>
127 #include <sys/serialize.h>
128 #include <sys/socket.h>
129 #include <sys/sockio.h>
130 #include <sys/sysctl.h>
133 #include <net/ethernet.h>
135 #include <net/ifq_var.h>
136 #include <net/if_arp.h>
137 #include <net/if_dl.h>
138 #include <net/if_media.h>
139 #include <net/if_types.h>
140 #include <net/vlan/if_vlan_var.h>
141 #include <net/vlan/if_vlan_ether.h>
143 #include <netinet/ip.h>
145 #include <dev/netif/mii_layer/mii.h>
146 #include <dev/netif/mii_layer/miivar.h>
148 #include <bus/pci/pcidevs.h>
149 #include <bus/pci/pcireg.h>
150 #include <bus/pci/pcivar.h>
152 /* "device miibus" required. See GENERIC if you get errors here. */
153 #include "miibus_if.h"
155 #include <dev/netif/re/if_rereg.h>
156 #include <dev/netif/re/if_revar.h>
158 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
161 * Various supported device vendors/types and their names.
163 static const struct re_type {
168 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T,
169 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
171 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139,
172 "RealTek 8139C+ 10/100BaseTX" },
174 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E,
175 "RealTek 810x PCIe 10/100baseTX" },
177 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168,
178 "RealTek 8111/8168 PCIe Gigabit Ethernet" },
180 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169,
181 "RealTek 8110/8169 Gigabit Ethernet" },
183 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC,
184 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
186 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT,
187 "Corega CG-LAPCIGT Gigabit Ethernet" },
189 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032,
190 "Linksys EG1032 Gigabit Ethernet" },
192 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902,
193 "US Robotics 997902 Gigabit Ethernet" },
195 { PCI_VENDOR_TTTECH, PCI_PRODUCT_TTTECH_MC322,
196 "TTTech MC322 Gigabit Ethernet" },
201 static const struct re_hwrev re_hwrevs[] = {
202 { RE_HWREV_8139CPLUS, RE_MACVER_UNKN, ETHERMTU,
203 RE_C_HWCSUM | RE_C_8139CP | RE_C_FASTE },
205 { RE_HWREV_8169, RE_MACVER_UNKN, ETHERMTU,
206 RE_C_HWCSUM | RE_C_8169 },
208 { RE_HWREV_8110S, RE_MACVER_03, RE_MTU_6K,
209 RE_C_HWCSUM | RE_C_8169 },
211 { RE_HWREV_8169S, RE_MACVER_03, RE_MTU_6K,
212 RE_C_HWCSUM | RE_C_8169 },
214 { RE_HWREV_8169SB, RE_MACVER_04, RE_MTU_6K,
215 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
217 { RE_HWREV_8169SC1, RE_MACVER_05, RE_MTU_6K,
218 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
220 { RE_HWREV_8169SC2, RE_MACVER_06, RE_MTU_6K,
221 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
223 { RE_HWREV_8168B1, RE_MACVER_21, RE_MTU_6K,
224 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT },
226 { RE_HWREV_8168B2, RE_MACVER_23, RE_MTU_6K,
227 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD },
229 { RE_HWREV_8168B3, RE_MACVER_23, RE_MTU_6K,
230 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD },
232 { RE_HWREV_8168C, RE_MACVER_29, RE_MTU_6K,
233 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
234 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
236 { RE_HWREV_8168CP, RE_MACVER_2B, RE_MTU_6K,
237 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
238 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
240 { RE_HWREV_8168D, RE_MACVER_2A, RE_MTU_9K,
241 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
242 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
244 { RE_HWREV_8100E, RE_MACVER_UNKN, ETHERMTU,
245 RE_C_HWCSUM | RE_C_FASTE },
247 { RE_HWREV_8101E1, RE_MACVER_16, ETHERMTU,
248 RE_C_HWCSUM | RE_C_FASTE },
250 { RE_HWREV_8101E2, RE_MACVER_16, ETHERMTU,
251 RE_C_HWCSUM | RE_C_FASTE },
253 { RE_HWREV_8102E, RE_MACVER_15, ETHERMTU,
254 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX |
257 { RE_HWREV_8102EL, RE_MACVER_15, ETHERMTU,
258 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX |
261 { RE_HWREV_NULL, 0, 0, 0 }
264 static int re_probe(device_t);
265 static int re_attach(device_t);
266 static int re_detach(device_t);
267 static int re_suspend(device_t);
268 static int re_resume(device_t);
269 static void re_shutdown(device_t);
271 static void re_dma_map_desc(void *, bus_dma_segment_t *, int,
273 static int re_allocmem(device_t);
274 static void re_freemem(device_t);
275 static void re_freebufmem(struct re_softc *, int, int);
276 static int re_encap(struct re_softc *, struct mbuf **, int *);
277 static int re_newbuf_std(struct re_softc *, int, int);
278 static int re_newbuf_jumbo(struct re_softc *, int, int);
279 static void re_setup_rxdesc(struct re_softc *, int);
280 static int re_rx_list_init(struct re_softc *);
281 static int re_tx_list_init(struct re_softc *);
282 static int re_rxeof(struct re_softc *);
283 static int re_txeof(struct re_softc *);
284 static int re_tx_collect(struct re_softc *);
285 static void re_intr(void *);
286 static void re_tick(void *);
287 static void re_tick_serialized(void *);
289 static void re_start(struct ifnet *);
290 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
291 static void re_init(void *);
292 static void re_stop(struct re_softc *);
293 static void re_watchdog(struct ifnet *);
294 static int re_ifmedia_upd(struct ifnet *);
295 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
297 static void re_eeprom_putbyte(struct re_softc *, int);
298 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *);
299 static void re_read_eeprom(struct re_softc *, caddr_t, int, int);
300 static void re_get_eewidth(struct re_softc *);
302 static int re_gmii_readreg(device_t, int, int);
303 static int re_gmii_writereg(device_t, int, int, int);
305 static int re_miibus_readreg(device_t, int, int);
306 static int re_miibus_writereg(device_t, int, int, int);
307 static void re_miibus_statchg(device_t);
309 static void re_setmulti(struct re_softc *);
310 static void re_reset(struct re_softc *, int);
311 static void re_get_eaddr(struct re_softc *, uint8_t *);
313 static void re_setup_hw_im(struct re_softc *);
314 static void re_setup_sim_im(struct re_softc *);
315 static void re_disable_hw_im(struct re_softc *);
316 static void re_disable_sim_im(struct re_softc *);
317 static void re_config_imtype(struct re_softc *, int);
318 static void re_setup_intr(struct re_softc *, int, int);
320 static int re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *);
321 static int re_sysctl_rxtime(SYSCTL_HANDLER_ARGS);
322 static int re_sysctl_txtime(SYSCTL_HANDLER_ARGS);
323 static int re_sysctl_simtime(SYSCTL_HANDLER_ARGS);
324 static int re_sysctl_imtype(SYSCTL_HANDLER_ARGS);
326 static int re_jpool_alloc(struct re_softc *);
327 static void re_jpool_free(struct re_softc *);
328 static struct re_jbuf *re_jbuf_alloc(struct re_softc *);
329 static void re_jbuf_free(void *);
330 static void re_jbuf_ref(void *);
333 static int re_diag(struct re_softc *);
336 #ifdef DEVICE_POLLING
337 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
340 static device_method_t re_methods[] = {
341 /* Device interface */
342 DEVMETHOD(device_probe, re_probe),
343 DEVMETHOD(device_attach, re_attach),
344 DEVMETHOD(device_detach, re_detach),
345 DEVMETHOD(device_suspend, re_suspend),
346 DEVMETHOD(device_resume, re_resume),
347 DEVMETHOD(device_shutdown, re_shutdown),
350 DEVMETHOD(bus_print_child, bus_generic_print_child),
351 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
354 DEVMETHOD(miibus_readreg, re_miibus_readreg),
355 DEVMETHOD(miibus_writereg, re_miibus_writereg),
356 DEVMETHOD(miibus_statchg, re_miibus_statchg),
361 static driver_t re_driver = {
364 sizeof(struct re_softc)
367 static devclass_t re_devclass;
369 DECLARE_DUMMY_MODULE(if_re);
370 MODULE_DEPEND(if_re, miibus, 1, 1, 1);
371 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0);
372 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0);
373 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
375 static int re_rx_desc_count = RE_RX_DESC_CNT_DEF;
376 static int re_tx_desc_count = RE_TX_DESC_CNT_DEF;
378 TUNABLE_INT("hw.re.rx_desc_count", &re_rx_desc_count);
379 TUNABLE_INT("hw.re.tx_desc_count", &re_tx_desc_count);
382 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
385 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
388 re_free_rxchain(struct re_softc *sc)
390 if (sc->re_head != NULL) {
391 m_freem(sc->re_head);
392 sc->re_head = sc->re_tail = NULL;
397 * Send a read command and address to the EEPROM, check for ACK.
400 re_eeprom_putbyte(struct re_softc *sc, int addr)
404 d = addr | (RE_9346_READ << sc->re_eewidth);
407 * Feed in each bit and strobe the clock.
409 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) {
411 EE_SET(RE_EE_DATAIN);
413 EE_CLR(RE_EE_DATAIN);
423 * Read a word of data stored in the EEPROM at address 'addr.'
426 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
432 * Send address of word we want to read.
434 re_eeprom_putbyte(sc, addr);
437 * Start reading bits from EEPROM.
439 for (i = 0x8000; i != 0; i >>= 1) {
442 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
452 * Read a sequence of words from the EEPROM.
455 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt)
458 uint16_t word = 0, *ptr;
460 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
463 for (i = 0; i < cnt; i++) {
464 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL);
465 re_eeprom_getword(sc, off + i, &word);
466 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL);
467 ptr = (uint16_t *)(dest + (i * 2));
471 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
475 re_get_eewidth(struct re_softc *sc)
480 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
481 if (re_did != 0x8129)
486 re_gmii_readreg(device_t dev, int phy, int reg)
488 struct re_softc *sc = device_get_softc(dev);
495 /* Let the rgephy driver read the GMEDIASTAT register */
497 if (reg == RE_GMEDIASTAT)
498 return(CSR_READ_1(sc, RE_GMEDIASTAT));
500 CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
503 for (i = 0; i < RE_TIMEOUT; i++) {
504 rval = CSR_READ_4(sc, RE_PHYAR);
505 if (rval & RE_PHYAR_BUSY)
510 if (i == RE_TIMEOUT) {
511 device_printf(dev, "PHY read failed\n");
515 return(rval & RE_PHYAR_PHYDATA);
519 re_gmii_writereg(device_t dev, int phy, int reg, int data)
521 struct re_softc *sc = device_get_softc(dev);
525 CSR_WRITE_4(sc, RE_PHYAR,
526 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
529 for (i = 0; i < RE_TIMEOUT; i++) {
530 rval = CSR_READ_4(sc, RE_PHYAR);
531 if ((rval & RE_PHYAR_BUSY) == 0)
537 device_printf(dev, "PHY write failed\n");
543 re_miibus_readreg(device_t dev, int phy, int reg)
545 struct re_softc *sc = device_get_softc(dev);
547 uint16_t re8139_reg = 0;
549 if (!RE_IS_8139CP(sc)) {
550 rval = re_gmii_readreg(dev, phy, reg);
554 /* Pretend the internal PHY is only at address 0 */
560 re8139_reg = RE_BMCR;
563 re8139_reg = RE_BMSR;
566 re8139_reg = RE_ANAR;
569 re8139_reg = RE_ANER;
572 re8139_reg = RE_LPAR;
578 * Allow the rlphy driver to read the media status
579 * register. If we have a link partner which does not
580 * support NWAY, this is the register which will tell
581 * us the results of parallel detection.
584 return(CSR_READ_1(sc, RE_MEDIASTAT));
586 device_printf(dev, "bad phy register\n");
589 rval = CSR_READ_2(sc, re8139_reg);
590 if (re8139_reg == RE_BMCR) {
591 /* 8139C+ has different bit layout. */
592 rval &= ~(BMCR_LOOP | BMCR_ISO);
598 re_miibus_writereg(device_t dev, int phy, int reg, int data)
600 struct re_softc *sc= device_get_softc(dev);
601 u_int16_t re8139_reg = 0;
603 if (!RE_IS_8139CP(sc))
604 return(re_gmii_writereg(dev, phy, reg, data));
606 /* Pretend the internal PHY is only at address 0 */
612 re8139_reg = RE_BMCR;
613 /* 8139C+ has different bit layout. */
614 data &= ~(BMCR_LOOP | BMCR_ISO);
617 re8139_reg = RE_BMSR;
620 re8139_reg = RE_ANAR;
623 re8139_reg = RE_ANER;
626 re8139_reg = RE_LPAR;
632 device_printf(dev, "bad phy register\n");
635 CSR_WRITE_2(sc, re8139_reg, data);
640 re_miibus_statchg(device_t dev)
645 * Program the 64-bit multicast hash filter.
648 re_setmulti(struct re_softc *sc)
650 struct ifnet *ifp = &sc->arpcom.ac_if;
652 uint32_t hashes[2] = { 0, 0 };
653 struct ifmultiaddr *ifma;
657 rxfilt = CSR_READ_4(sc, RE_RXCFG);
659 /* Set the individual bit to receive frames for this host only. */
660 rxfilt |= RE_RXCFG_RX_INDIV;
661 /* Set capture broadcast bit to capture broadcast frames. */
662 rxfilt |= RE_RXCFG_RX_BROAD;
664 rxfilt &= ~(RE_RXCFG_RX_ALLPHYS | RE_RXCFG_RX_MULTI);
665 if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) {
666 rxfilt |= RE_RXCFG_RX_MULTI;
668 /* If we want promiscuous mode, set the allframes bit. */
669 if (ifp->if_flags & IFF_PROMISC)
670 rxfilt |= RE_RXCFG_RX_ALLPHYS;
672 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
673 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
674 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
678 /* first, zot all the existing hash bits */
679 CSR_WRITE_4(sc, RE_MAR0, 0);
680 CSR_WRITE_4(sc, RE_MAR4, 0);
682 /* now program new ones */
683 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
684 if (ifma->ifma_addr->sa_family != AF_LINK)
686 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
687 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
689 hashes[0] |= (1 << h);
691 hashes[1] |= (1 << (h - 32));
696 rxfilt |= RE_RXCFG_RX_MULTI;
698 rxfilt &= ~RE_RXCFG_RX_MULTI;
700 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
703 * For some unfathomable reason, RealTek decided to reverse
704 * the order of the multicast hash registers in the PCI Express
705 * parts. This means we have to write the hash pattern in reverse
706 * order for those devices.
708 if (sc->re_caps & RE_C_PCIE) {
709 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[0]));
710 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[1]));
712 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
713 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
718 re_reset(struct re_softc *sc, int running)
722 if ((sc->re_caps & RE_C_STOP_RXTX) && running) {
723 CSR_WRITE_1(sc, RE_COMMAND,
724 RE_CMD_STOPREQ | RE_CMD_TX_ENB | RE_CMD_RX_ENB);
728 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
730 for (i = 0; i < RE_TIMEOUT; i++) {
732 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
736 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
741 * The following routine is designed to test for a defect on some
742 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
743 * lines connected to the bus, however for a 32-bit only card, they
744 * should be pulled high. The result of this defect is that the
745 * NIC will not work right if you plug it into a 64-bit slot: DMA
746 * operations will be done with 64-bit transfers, which will fail
747 * because the 64-bit data lines aren't connected.
749 * There's no way to work around this (short of talking a soldering
750 * iron to the board), however we can detect it. The method we use
751 * here is to put the NIC into digital loopback mode, set the receiver
752 * to promiscuous mode, and then try to send a frame. We then compare
753 * the frame data we sent to what was received. If the data matches,
754 * then the NIC is working correctly, otherwise we know the user has
755 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
756 * slot. In the latter case, there's no way the NIC can work correctly,
757 * so we print out a message on the console and abort the device attach.
761 re_diag(struct re_softc *sc)
763 struct ifnet *ifp = &sc->arpcom.ac_if;
765 struct ether_header *eh;
766 struct re_desc *cur_rx;
769 int total_len, i, error = 0, phyaddr;
770 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
771 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
773 /* Allocate a single mbuf */
775 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
780 * Initialize the NIC in test mode. This sets the chip up
781 * so that it can send and receive frames, but performs the
782 * following special functions:
783 * - Puts receiver in promiscuous mode
784 * - Enables digital loopback mode
785 * - Leaves interrupts turned off
788 ifp->if_flags |= IFF_PROMISC;
789 sc->re_flags |= RE_F_TESTMODE;
791 sc->re_flags |= RE_F_LINKED;
792 if (!RE_IS_8139CP(sc))
797 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET);
798 for (i = 0; i < RE_TIMEOUT; i++) {
799 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR);
800 if (!(status & BMCR_RESET))
804 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP);
805 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG);
809 /* Put some data in the mbuf */
811 eh = mtod(m0, struct ether_header *);
812 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
813 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
814 eh->ether_type = htons(ETHERTYPE_IP);
815 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
818 * Queue the packet, start transmission.
819 * Note: ifq_handoff() ultimately calls re_start() for us.
822 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
823 error = ifq_handoff(ifp, m0, NULL);
830 /* Wait for it to propagate through the chip */
833 for (i = 0; i < RE_TIMEOUT; i++) {
834 status = CSR_READ_2(sc, RE_ISR);
835 CSR_WRITE_2(sc, RE_ISR, status);
836 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
837 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
842 if (i == RE_TIMEOUT) {
843 if_printf(ifp, "diagnostic failed to receive packet "
844 "in loopback mode\n");
850 * The packet should have been dumped into the first
851 * entry in the RX DMA ring. Grab it from there.
854 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
855 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
856 bus_dmamap_sync(sc->re_ldata.re_rx_mtag, sc->re_ldata.re_rx_dmamap[0],
857 BUS_DMASYNC_POSTREAD);
858 bus_dmamap_unload(sc->re_ldata.re_rx_mtag,
859 sc->re_ldata.re_rx_dmamap[0]);
861 m0 = sc->re_ldata.re_rx_mbuf[0];
862 sc->re_ldata.re_rx_mbuf[0] = NULL;
863 eh = mtod(m0, struct ether_header *);
865 cur_rx = &sc->re_ldata.re_rx_list[0];
866 total_len = RE_RXBYTES(cur_rx);
867 rxstat = le32toh(cur_rx->re_cmdstat);
869 if (total_len != ETHER_MIN_LEN) {
870 if_printf(ifp, "diagnostic failed, received short packet\n");
875 /* Test that the received packet data matches what we sent. */
877 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
878 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
879 be16toh(eh->ether_type) != ETHERTYPE_IP) {
880 if_printf(ifp, "WARNING, DMA FAILURE!\n");
881 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
882 dst, ":", src, ":", ETHERTYPE_IP);
883 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
884 eh->ether_dhost, ":", eh->ether_shost, ":",
885 ntohs(eh->ether_type));
886 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
887 "into a 64-bit PCI slot.\n");
888 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
889 "for proper operation.\n");
890 if_printf(ifp, "Read the re(4) man page for more details.\n");
895 /* Turn interface off, release resources */
897 sc->re_flags &= ~(RE_F_LINKED | RE_F_TESTMODE);
898 ifp->if_flags &= ~IFF_PROMISC;
908 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
909 * IDs against our list and return a device name if we find a match.
912 re_probe(device_t dev)
914 const struct re_type *t;
915 const struct re_hwrev *hw_rev;
918 uint32_t hwrev, macmode, txcfg;
919 uint16_t vendor, product;
921 vendor = pci_get_vendor(dev);
922 product = pci_get_device(dev);
925 * Only attach to rev.3 of the Linksys EG1032 adapter.
926 * Rev.2 is supported by sk(4).
928 if (vendor == PCI_VENDOR_LINKSYS &&
929 product == PCI_PRODUCT_LINKSYS_EG1032 &&
930 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3)
933 if (vendor == PCI_VENDOR_REALTEK &&
934 product == PCI_PRODUCT_REALTEK_RT8139 &&
935 pci_get_revid(dev) != PCI_REVID_REALTEK_RT8139CP) {
940 for (t = re_devs; t->re_name != NULL; t++) {
941 if (product == t->re_did && vendor == t->re_vid)
946 * Check if we found a RealTek device.
948 if (t->re_name == NULL)
952 * Temporarily map the I/O space so we can read the chip ID register.
954 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
956 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
958 if (sc->re_res == NULL) {
959 device_printf(dev, "couldn't map ports/memory\n");
964 sc->re_btag = rman_get_bustag(sc->re_res);
965 sc->re_bhandle = rman_get_bushandle(sc->re_res);
967 txcfg = CSR_READ_4(sc, RE_TXCFG);
968 hwrev = txcfg & RE_TXCFG_HWREV;
969 macmode = txcfg & RE_TXCFG_MACMODE;
970 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
974 * and continue matching for the specific chip...
976 for (hw_rev = re_hwrevs; hw_rev->re_hwrev != RE_HWREV_NULL; hw_rev++) {
977 if (hw_rev->re_hwrev == hwrev) {
978 sc = device_get_softc(dev);
980 sc->re_hwrev = hw_rev->re_hwrev;
981 sc->re_macver = hw_rev->re_macver;
982 sc->re_caps = hw_rev->re_caps;
983 sc->re_maxmtu = hw_rev->re_maxmtu;
986 * Apply chip property fixup
988 switch (sc->re_hwrev) {
989 case RE_HWREV_8101E1:
990 case RE_HWREV_8101E2:
992 sc->re_macver = RE_MACVER_11;
993 else if (macmode == 0x200000)
994 sc->re_macver = RE_MACVER_12;
997 case RE_HWREV_8102EL:
999 sc->re_macver = RE_MACVER_13;
1000 else if (macmode == 0x100000)
1001 sc->re_macver = RE_MACVER_14;
1003 case RE_HWREV_8168B2:
1004 case RE_HWREV_8168B3:
1006 sc->re_macver = RE_MACVER_22;
1008 case RE_HWREV_8168C:
1010 sc->re_macver = RE_MACVER_24;
1011 else if (macmode == 0x200000)
1012 sc->re_macver = RE_MACVER_25;
1013 else if (macmode == 0x300000)
1014 sc->re_macver = RE_MACVER_27;
1016 case RE_HWREV_8168CP:
1018 sc->re_macver = RE_MACVER_26;
1019 else if (macmode == 0x100000)
1020 sc->re_macver = RE_MACVER_28;
1023 if (pci_is_pcie(dev))
1024 sc->re_caps |= RE_C_PCIE;
1026 device_set_desc(dev, t->re_name);
1032 device_printf(dev, "unknown hwrev 0x%08x, macmode 0x%08x\n",
1039 re_dma_map_desc(void *xarg, bus_dma_segment_t *segs, int nsegs,
1040 bus_size_t mapsize, int error)
1042 struct re_dmaload_arg *arg = xarg;
1048 if (nsegs > arg->re_nsegs) {
1053 arg->re_nsegs = nsegs;
1054 for (i = 0; i < nsegs; ++i)
1055 arg->re_segs[i] = segs[i];
1059 re_allocmem(device_t dev)
1061 struct re_softc *sc = device_get_softc(dev);
1066 * Allocate list data
1068 sc->re_ldata.re_tx_mbuf =
1069 kmalloc(sc->re_tx_desc_cnt * sizeof(struct mbuf *),
1070 M_DEVBUF, M_ZERO | M_WAITOK);
1072 sc->re_ldata.re_rx_mbuf =
1073 kmalloc(sc->re_rx_desc_cnt * sizeof(struct mbuf *),
1074 M_DEVBUF, M_ZERO | M_WAITOK);
1076 sc->re_ldata.re_rx_paddr =
1077 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_addr_t),
1078 M_DEVBUF, M_ZERO | M_WAITOK);
1080 sc->re_ldata.re_tx_dmamap =
1081 kmalloc(sc->re_tx_desc_cnt * sizeof(bus_dmamap_t),
1082 M_DEVBUF, M_ZERO | M_WAITOK);
1084 sc->re_ldata.re_rx_dmamap =
1085 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_dmamap_t),
1086 M_DEVBUF, M_ZERO | M_WAITOK);
1089 * Allocate the parent bus DMA tag appropriate for PCI.
1091 error = bus_dma_tag_create(NULL, /* parent */
1092 1, 0, /* alignment, boundary */
1093 BUS_SPACE_MAXADDR, /* lowaddr */
1094 BUS_SPACE_MAXADDR, /* highaddr */
1095 NULL, NULL, /* filter, filterarg */
1096 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
1098 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1100 &sc->re_parent_tag);
1102 device_printf(dev, "could not allocate parent dma tag\n");
1106 /* Allocate TX descriptor list. */
1107 error = bus_dmamem_coherent(sc->re_parent_tag,
1109 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1110 RE_TX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO,
1113 device_printf(dev, "could not allocate TX ring\n");
1116 sc->re_ldata.re_tx_list_tag = dmem.dmem_tag;
1117 sc->re_ldata.re_tx_list_map = dmem.dmem_map;
1118 sc->re_ldata.re_tx_list = dmem.dmem_addr;
1119 sc->re_ldata.re_tx_list_addr = dmem.dmem_busaddr;
1121 /* Allocate RX descriptor list. */
1122 error = bus_dmamem_coherent(sc->re_parent_tag,
1124 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1125 RE_RX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO,
1128 device_printf(dev, "could not allocate RX ring\n");
1131 sc->re_ldata.re_rx_list_tag = dmem.dmem_tag;
1132 sc->re_ldata.re_rx_list_map = dmem.dmem_map;
1133 sc->re_ldata.re_rx_list = dmem.dmem_addr;
1134 sc->re_ldata.re_rx_list_addr = dmem.dmem_busaddr;
1136 /* Allocate maps for TX mbufs. */
1137 error = bus_dma_tag_create(sc->re_parent_tag,
1139 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1141 RE_FRAMELEN_MAX, RE_MAXSEGS, MCLBYTES,
1142 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEPAGE,
1143 &sc->re_ldata.re_tx_mtag);
1145 device_printf(dev, "could not allocate TX buf dma tag\n");
1149 /* Create DMA maps for TX buffers */
1150 for (i = 0; i < sc->re_tx_desc_cnt; i++) {
1151 error = bus_dmamap_create(sc->re_ldata.re_tx_mtag,
1152 BUS_DMA_WAITOK | BUS_DMA_ONEPAGE,
1153 &sc->re_ldata.re_tx_dmamap[i]);
1155 device_printf(dev, "can't create DMA map for TX buf\n");
1156 re_freebufmem(sc, i, 0);
1161 /* Allocate maps for RX mbufs. */
1162 error = bus_dma_tag_create(sc->re_parent_tag,
1164 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1166 MCLBYTES, 1, MCLBYTES,
1167 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
1168 &sc->re_ldata.re_rx_mtag);
1170 device_printf(dev, "could not allocate RX buf dma tag\n");
1174 /* Create spare DMA map for RX */
1175 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, BUS_DMA_WAITOK,
1176 &sc->re_ldata.re_rx_spare);
1178 device_printf(dev, "can't create spare DMA map for RX\n");
1179 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag);
1180 sc->re_ldata.re_rx_mtag = NULL;
1184 /* Create DMA maps for RX buffers */
1185 for (i = 0; i < sc->re_rx_desc_cnt; i++) {
1186 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag,
1187 BUS_DMA_WAITOK, &sc->re_ldata.re_rx_dmamap[i]);
1189 device_printf(dev, "can't create DMA map for RX buf\n");
1190 re_freebufmem(sc, sc->re_tx_desc_cnt, i);
1195 /* Create jumbo buffer pool for RX if required */
1196 if (sc->re_caps & RE_C_CONTIGRX) {
1197 error = re_jpool_alloc(sc);
1200 /* Disable jumbo frame support */
1201 sc->re_maxmtu = ETHERMTU;
1208 re_freebufmem(struct re_softc *sc, int tx_cnt, int rx_cnt)
1212 /* Destroy all the RX and TX buffer maps */
1213 if (sc->re_ldata.re_tx_mtag) {
1214 for (i = 0; i < tx_cnt; i++) {
1215 bus_dmamap_destroy(sc->re_ldata.re_tx_mtag,
1216 sc->re_ldata.re_tx_dmamap[i]);
1218 bus_dma_tag_destroy(sc->re_ldata.re_tx_mtag);
1219 sc->re_ldata.re_tx_mtag = NULL;
1222 if (sc->re_ldata.re_rx_mtag) {
1223 for (i = 0; i < rx_cnt; i++) {
1224 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag,
1225 sc->re_ldata.re_rx_dmamap[i]);
1227 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag,
1228 sc->re_ldata.re_rx_spare);
1229 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag);
1230 sc->re_ldata.re_rx_mtag = NULL;
1235 re_freemem(device_t dev)
1237 struct re_softc *sc = device_get_softc(dev);
1239 /* Unload and free the RX DMA ring memory and map */
1240 if (sc->re_ldata.re_rx_list_tag) {
1241 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1242 sc->re_ldata.re_rx_list_map);
1243 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1244 sc->re_ldata.re_rx_list,
1245 sc->re_ldata.re_rx_list_map);
1246 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1249 /* Unload and free the TX DMA ring memory and map */
1250 if (sc->re_ldata.re_tx_list_tag) {
1251 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1252 sc->re_ldata.re_tx_list_map);
1253 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1254 sc->re_ldata.re_tx_list,
1255 sc->re_ldata.re_tx_list_map);
1256 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1259 /* Free RX/TX buf DMA stuffs */
1260 re_freebufmem(sc, sc->re_tx_desc_cnt, sc->re_rx_desc_cnt);
1262 /* Unload and free the stats buffer and map */
1263 if (sc->re_ldata.re_stag) {
1264 bus_dmamap_unload(sc->re_ldata.re_stag,
1265 sc->re_ldata.re_rx_list_map);
1266 bus_dmamem_free(sc->re_ldata.re_stag,
1267 sc->re_ldata.re_stats,
1268 sc->re_ldata.re_smap);
1269 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1272 if (sc->re_caps & RE_C_CONTIGRX)
1275 if (sc->re_parent_tag)
1276 bus_dma_tag_destroy(sc->re_parent_tag);
1278 if (sc->re_ldata.re_tx_mbuf != NULL)
1279 kfree(sc->re_ldata.re_tx_mbuf, M_DEVBUF);
1280 if (sc->re_ldata.re_rx_mbuf != NULL)
1281 kfree(sc->re_ldata.re_rx_mbuf, M_DEVBUF);
1282 if (sc->re_ldata.re_rx_paddr != NULL)
1283 kfree(sc->re_ldata.re_rx_paddr, M_DEVBUF);
1284 if (sc->re_ldata.re_tx_dmamap != NULL)
1285 kfree(sc->re_ldata.re_tx_dmamap, M_DEVBUF);
1286 if (sc->re_ldata.re_rx_dmamap != NULL)
1287 kfree(sc->re_ldata.re_rx_dmamap, M_DEVBUF);
1291 * Attach the interface. Allocate softc structures, do ifmedia
1292 * setup and ethernet/BPF attach.
1295 re_attach(device_t dev)
1297 struct re_softc *sc = device_get_softc(dev);
1299 uint8_t eaddr[ETHER_ADDR_LEN];
1300 int error = 0, rid, qlen;
1302 callout_init(&sc->re_timer);
1305 if (RE_IS_8139CP(sc)) {
1306 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_8139CP;
1307 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_8139CP;
1309 sc->re_rx_desc_cnt = re_rx_desc_count;
1310 if (sc->re_rx_desc_cnt > RE_RX_DESC_CNT_MAX)
1311 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_MAX;
1313 sc->re_tx_desc_cnt = re_tx_desc_count;
1314 if (sc->re_tx_desc_cnt > RE_TX_DESC_CNT_MAX)
1315 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_MAX;
1318 qlen = RE_IFQ_MAXLEN;
1319 if (sc->re_tx_desc_cnt > qlen)
1320 qlen = sc->re_tx_desc_cnt;
1322 sc->re_rxbuf_size = MCLBYTES;
1323 sc->re_newbuf = re_newbuf_std;
1325 sc->re_tx_time = 5; /* 125us */
1326 sc->re_rx_time = 2; /* 50us */
1327 if (sc->re_caps & RE_C_PCIE)
1328 sc->re_sim_time = 75; /* 75us */
1330 sc->re_sim_time = 125; /* 125us */
1331 if (!RE_IS_8139CP(sc)) {
1332 /* simulated interrupt moderation */
1333 sc->re_imtype = RE_IMTYPE_SIM;
1335 sc->re_imtype = RE_IMTYPE_NONE;
1337 re_config_imtype(sc, sc->re_imtype);
1339 sysctl_ctx_init(&sc->re_sysctl_ctx);
1340 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx,
1341 SYSCTL_STATIC_CHILDREN(_hw),
1343 device_get_nameunit(dev),
1345 if (sc->re_sysctl_tree == NULL) {
1346 device_printf(dev, "can't add sysctl node\n");
1350 SYSCTL_ADD_INT(&sc->re_sysctl_ctx,
1351 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO,
1352 "rx_desc_count", CTLFLAG_RD, &sc->re_rx_desc_cnt,
1353 0, "RX desc count");
1354 SYSCTL_ADD_INT(&sc->re_sysctl_ctx,
1355 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO,
1356 "tx_desc_count", CTLFLAG_RD, &sc->re_tx_desc_cnt,
1357 0, "TX desc count");
1358 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1359 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1360 OID_AUTO, "sim_time",
1361 CTLTYPE_INT | CTLFLAG_RW,
1362 sc, 0, re_sysctl_simtime, "I",
1363 "Simulated interrupt moderation time (usec).");
1364 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1365 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1367 CTLTYPE_INT | CTLFLAG_RW,
1368 sc, 0, re_sysctl_imtype, "I",
1369 "Interrupt moderation type -- "
1370 "0:disable, 1:simulated, "
1371 "2:hardware(if supported)");
1372 if (sc->re_caps & RE_C_HWIM) {
1373 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1374 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1375 OID_AUTO, "hw_rxtime",
1376 CTLTYPE_INT | CTLFLAG_RW,
1377 sc, 0, re_sysctl_rxtime, "I",
1378 "Hardware interrupt moderation time "
1380 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1381 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1382 OID_AUTO, "hw_txtime",
1383 CTLTYPE_INT | CTLFLAG_RW,
1384 sc, 0, re_sysctl_txtime, "I",
1385 "Hardware interrupt moderation time "
1389 #ifndef BURN_BRIDGES
1391 * Handle power management nonsense.
1394 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1395 uint32_t membase, irq;
1397 /* Save important PCI config data. */
1398 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1399 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1401 /* Reset the power state. */
1402 device_printf(dev, "chip is in D%d power mode "
1403 "-- setting to D0\n", pci_get_powerstate(dev));
1405 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1407 /* Restore PCI config data. */
1408 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1409 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1413 * Map control/status registers.
1415 pci_enable_busmaster(dev);
1418 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1421 if (sc->re_res == NULL) {
1422 device_printf(dev, "couldn't map ports\n");
1427 sc->re_btag = rman_get_bustag(sc->re_res);
1428 sc->re_bhandle = rman_get_bushandle(sc->re_res);
1430 /* Allocate interrupt */
1432 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1433 RF_SHAREABLE | RF_ACTIVE);
1435 if (sc->re_irq == NULL) {
1436 device_printf(dev, "couldn't map interrupt\n");
1441 /* Reset the adapter. */
1444 if (RE_IS_8139CP(sc)) {
1445 sc->re_bus_speed = 33; /* XXX */
1446 } else if (sc->re_caps & RE_C_PCIE) {
1447 sc->re_bus_speed = 125;
1451 cfg2 = CSR_READ_1(sc, RE_CFG2);
1452 switch (cfg2 & RE_CFG2_PCICLK_MASK) {
1453 case RE_CFG2_PCICLK_33MHZ:
1454 sc->re_bus_speed = 33;
1456 case RE_CFG2_PCICLK_66MHZ:
1457 sc->re_bus_speed = 66;
1460 device_printf(dev, "unknown bus speed, assume 33MHz\n");
1461 sc->re_bus_speed = 33;
1464 if (cfg2 & RE_CFG2_PCI64)
1465 sc->re_caps |= RE_C_PCI64;
1467 device_printf(dev, "Hardware rev. 0x%08x; MAC ver. 0x%02x; "
1469 sc->re_hwrev, sc->re_macver,
1470 (sc->re_caps & RE_C_PCIE) ?
1471 "-E" : ((sc->re_caps & RE_C_PCI64) ? "64" : "32"),
1476 * DO NOT try to adjust config1 and config5 which was spotted in
1477 * Realtek's Linux drivers. It will _permanently_ damage certain
1478 * cards EEPROM, e.g. one of my 8168B (0x38000000) card ...
1481 re_get_eaddr(sc, eaddr);
1483 if (!RE_IS_8139CP(sc)) {
1484 /* Set RX length mask */
1485 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1486 sc->re_txstart = RE_GTXSTART;
1488 /* Set RX length mask */
1489 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1490 sc->re_txstart = RE_TXSTART;
1493 /* Allocate DMA stuffs */
1494 error = re_allocmem(dev);
1499 * Apply some magic PCI settings from Realtek ...
1501 if (RE_IS_8169(sc)) {
1502 CSR_WRITE_1(sc, 0x82, 1);
1503 pci_write_config(dev, PCIR_CACHELNSZ, 0x8, 1);
1505 pci_write_config(dev, PCIR_LATTIMER, 0x40, 1);
1507 if (sc->re_caps & RE_C_MAC2) {
1509 * Following part is extracted from Realtek BSD driver v176.
1510 * However, this does _not_ make much/any sense:
1511 * 8168C's PCI Express device control is located at 0x78,
1512 * so the reading from 0x79 (higher part of 0x78) and setting
1513 * the 4~6bits intend to enlarge the "max read request size"
1514 * (we will do it). The content of the rest part of this
1515 * register is not meaningful to other PCI registers, so
1516 * writing the value to 0x54 could be completely wrong.
1517 * 0x80 is the lower part of PCI Express device status, non-
1518 * reserved bits are RW1C, writing 0 to them will not have
1519 * any effect at all.
1524 val = pci_read_config(dev, 0x79, 1);
1525 val = (val & ~0x70) | 0x50;
1526 pci_write_config(dev, 0x54, val, 1);
1527 pci_write_config(dev, 0x80, 0, 1);
1532 * Apply some PHY fixup from Realtek ...
1534 if (sc->re_hwrev == RE_HWREV_8110S) {
1535 CSR_WRITE_1(sc, 0x82, 1);
1536 re_miibus_writereg(dev, 1, 0xb, 0);
1538 if (sc->re_caps & RE_C_PHYPMGT) {
1540 re_miibus_writereg(dev, 1, 0x1f, 0);
1541 re_miibus_writereg(dev, 1, 0xe, 0);
1545 if (mii_phy_probe(dev, &sc->re_miibus,
1546 re_ifmedia_upd, re_ifmedia_sts)) {
1547 device_printf(dev, "MII without any phy!\n");
1552 ifp = &sc->arpcom.ac_if;
1554 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1555 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1556 ifp->if_ioctl = re_ioctl;
1557 ifp->if_start = re_start;
1558 #ifdef DEVICE_POLLING
1559 ifp->if_poll = re_poll;
1561 ifp->if_watchdog = re_watchdog;
1562 ifp->if_init = re_init;
1563 if (!RE_IS_8139CP(sc)) /* XXX */
1564 ifp->if_baudrate = 1000000000;
1566 ifp->if_baudrate = 100000000;
1567 ifq_set_maxlen(&ifp->if_snd, qlen);
1568 ifq_set_ready(&ifp->if_snd);
1570 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1571 if (sc->re_caps & RE_C_HWCSUM)
1572 ifp->if_capabilities |= IFCAP_HWCSUM;
1574 ifp->if_capenable = ifp->if_capabilities;
1575 if (ifp->if_capabilities & IFCAP_HWCSUM)
1576 ifp->if_hwassist = RE_CSUM_FEATURES;
1578 ifp->if_hwassist = 0;
1581 * Call MI attach routine.
1583 ether_ifattach(ifp, eaddr, NULL);
1587 * Perform hardware diagnostic on the original RTL8169.
1588 * Some 32-bit cards were incorrectly wired and would
1589 * malfunction if plugged into a 64-bit slot.
1591 if (sc->re_hwrev == RE_HWREV_8169) {
1592 lwkt_serialize_enter(ifp->if_serializer);
1593 error = re_diag(sc);
1594 lwkt_serialize_exit(ifp->if_serializer);
1597 device_printf(dev, "hardware diagnostic failure\n");
1598 ether_ifdetach(ifp);
1602 #endif /* RE_DIAG */
1604 /* Hook interrupt last to avoid having to lock softc */
1605 error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc,
1606 &sc->re_intrhand, ifp->if_serializer);
1609 device_printf(dev, "couldn't set up irq\n");
1610 ether_ifdetach(ifp);
1614 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->re_irq));
1615 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1625 * Shutdown hardware and free up resources. This can be called any
1626 * time after the mutex has been initialized. It is called in both
1627 * the error case in attach and the normal detach case so it needs
1628 * to be careful about only freeing resources that have actually been
1632 re_detach(device_t dev)
1634 struct re_softc *sc = device_get_softc(dev);
1635 struct ifnet *ifp = &sc->arpcom.ac_if;
1637 /* These should only be active if attach succeeded */
1638 if (device_is_attached(dev)) {
1639 lwkt_serialize_enter(ifp->if_serializer);
1641 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1642 lwkt_serialize_exit(ifp->if_serializer);
1644 ether_ifdetach(ifp);
1647 device_delete_child(dev, sc->re_miibus);
1648 bus_generic_detach(dev);
1650 if (sc->re_sysctl_tree != NULL)
1651 sysctl_ctx_free(&sc->re_sysctl_ctx);
1654 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1656 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1660 /* Free DMA stuffs */
1667 re_setup_rxdesc(struct re_softc *sc, int idx)
1673 paddr = sc->re_ldata.re_rx_paddr[idx];
1674 d = &sc->re_ldata.re_rx_list[idx];
1676 d->re_bufaddr_lo = htole32(RE_ADDR_LO(paddr));
1677 d->re_bufaddr_hi = htole32(RE_ADDR_HI(paddr));
1679 cmdstat = sc->re_rxbuf_size | RE_RDESC_CMD_OWN;
1680 if (idx == (sc->re_rx_desc_cnt - 1))
1681 cmdstat |= RE_RDESC_CMD_EOR;
1682 d->re_cmdstat = htole32(cmdstat);
1686 re_newbuf_std(struct re_softc *sc, int idx, int init)
1688 struct re_dmaload_arg arg;
1689 bus_dma_segment_t seg;
1694 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1699 if_printf(&sc->arpcom.ac_if, "m_getcl failed\n");
1705 m->m_len = m->m_pkthdr.len = MCLBYTES;
1709 * re(4) chips need address of the receive buffer to be 8-byte
1710 * aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1715 error = bus_dmamap_load_mbuf(sc->re_ldata.re_rx_mtag,
1716 sc->re_ldata.re_rx_spare, m,
1717 re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1718 if (error || arg.re_nsegs == 0) {
1720 if_printf(&sc->arpcom.ac_if, "too many segments?!\n");
1721 bus_dmamap_unload(sc->re_ldata.re_rx_mtag,
1722 sc->re_ldata.re_rx_spare);
1728 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
1736 bus_dmamap_sync(sc->re_ldata.re_rx_mtag,
1737 sc->re_ldata.re_rx_dmamap[idx],
1738 BUS_DMASYNC_POSTREAD);
1739 bus_dmamap_unload(sc->re_ldata.re_rx_mtag,
1740 sc->re_ldata.re_rx_dmamap[idx]);
1742 sc->re_ldata.re_rx_mbuf[idx] = m;
1743 sc->re_ldata.re_rx_paddr[idx] = seg.ds_addr;
1745 map = sc->re_ldata.re_rx_dmamap[idx];
1746 sc->re_ldata.re_rx_dmamap[idx] = sc->re_ldata.re_rx_spare;
1747 sc->re_ldata.re_rx_spare = map;
1749 re_setup_rxdesc(sc, idx);
1754 re_newbuf_jumbo(struct re_softc *sc, int idx, int init)
1757 struct re_jbuf *jbuf;
1760 MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1764 if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n");
1771 jbuf = re_jbuf_alloc(sc);
1777 if_printf(&sc->arpcom.ac_if, "jpool is empty\n");
1784 m->m_ext.ext_arg = jbuf;
1785 m->m_ext.ext_buf = jbuf->re_buf;
1786 m->m_ext.ext_free = re_jbuf_free;
1787 m->m_ext.ext_ref = re_jbuf_ref;
1788 m->m_ext.ext_size = sc->re_rxbuf_size;
1790 m->m_data = m->m_ext.ext_buf;
1791 m->m_flags |= M_EXT;
1792 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
1796 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer
1797 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1800 sc->re_ldata.re_rx_mbuf[idx] = m;
1801 sc->re_ldata.re_rx_paddr[idx] = jbuf->re_paddr;
1803 re_setup_rxdesc(sc, idx);
1808 re_tx_list_init(struct re_softc *sc)
1810 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc));
1812 /* Flush the TX descriptors */
1813 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1814 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
1816 sc->re_ldata.re_tx_prodidx = 0;
1817 sc->re_ldata.re_tx_considx = 0;
1818 sc->re_ldata.re_tx_free = sc->re_tx_desc_cnt;
1824 re_rx_list_init(struct re_softc *sc)
1828 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc));
1830 for (i = 0; i < sc->re_rx_desc_cnt; i++) {
1831 error = sc->re_newbuf(sc, i, 1);
1836 /* Flush the RX descriptors */
1837 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1838 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
1840 sc->re_ldata.re_rx_prodidx = 0;
1841 sc->re_head = sc->re_tail = NULL;
1846 #define RE_IP4_PACKET 0x1
1847 #define RE_TCP_PACKET 0x2
1848 #define RE_UDP_PACKET 0x4
1850 static __inline uint8_t
1851 re_packet_type(struct re_softc *sc, uint32_t rxstat, uint32_t rxctrl)
1853 uint8_t packet_type = 0;
1855 if (sc->re_caps & RE_C_MAC2) {
1856 if (rxctrl & RE_RDESC_CTL_PROTOIP4)
1857 packet_type |= RE_IP4_PACKET;
1859 if (rxstat & RE_RDESC_STAT_PROTOID)
1860 packet_type |= RE_IP4_PACKET;
1862 if (RE_TCPPKT(rxstat))
1863 packet_type |= RE_TCP_PACKET;
1864 else if (RE_UDPPKT(rxstat))
1865 packet_type |= RE_UDP_PACKET;
1870 * RX handler for C+ and 8169. For the gigE chips, we support
1871 * the reception of jumbo frames that have been fragmented
1872 * across multiple 2K mbuf cluster buffers.
1875 re_rxeof(struct re_softc *sc)
1877 struct ifnet *ifp = &sc->arpcom.ac_if;
1879 struct re_desc *cur_rx;
1880 uint32_t rxstat, rxctrl;
1881 int i, total_len, rx = 0;
1882 struct mbuf_chain chain[MAXCPU];
1884 /* Invalidate the descriptor memory */
1886 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1887 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
1889 ether_input_chain_init(chain);
1891 for (i = sc->re_ldata.re_rx_prodidx;
1892 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0; RE_RXDESC_INC(sc, i)) {
1893 cur_rx = &sc->re_ldata.re_rx_list[i];
1894 m = sc->re_ldata.re_rx_mbuf[i];
1895 total_len = RE_RXBYTES(cur_rx);
1896 rxstat = le32toh(cur_rx->re_cmdstat);
1897 rxctrl = le32toh(cur_rx->re_control);
1902 if (sc->re_flags & RE_F_USE_JPOOL)
1903 KKASSERT(rxstat & RE_RDESC_STAT_EOF);
1906 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1907 if (sc->re_flags & RE_F_DROP_RXFRAG) {
1908 re_setup_rxdesc(sc, i);
1912 if (sc->re_newbuf(sc, i, 0)) {
1913 /* Drop upcoming fragments */
1914 sc->re_flags |= RE_F_DROP_RXFRAG;
1918 m->m_len = MCLBYTES;
1919 if (sc->re_head == NULL) {
1920 sc->re_head = sc->re_tail = m;
1922 sc->re_tail->m_next = m;
1926 } else if (sc->re_flags & RE_F_DROP_RXFRAG) {
1928 * Last fragment of a multi-fragment packet.
1930 * Since error already happened, this fragment
1931 * must be dropped as well as the fragment chain.
1933 re_setup_rxdesc(sc, i);
1934 re_free_rxchain(sc);
1935 sc->re_flags &= ~RE_F_DROP_RXFRAG;
1940 * NOTE: for the 8139C+, the frame length field
1941 * is always 12 bits in size, but for the gigE chips,
1942 * it is 13 bits (since the max RX frame length is 16K).
1943 * Unfortunately, all 32 bits in the status word
1944 * were already used, so to make room for the extra
1945 * length bit, RealTek took out the 'frame alignment
1946 * error' bit and shifted the other status bits
1947 * over one slot. The OWN, EOR, FS and LS bits are
1948 * still in the same places. We have already extracted
1949 * the frame length and checked the OWN bit, so rather
1950 * than using an alternate bit mapping, we shift the
1951 * status bits one space to the right so we can evaluate
1952 * them using the 8169 status as though it was in the
1953 * same format as that of the 8139C+.
1955 if (!RE_IS_8139CP(sc))
1958 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1961 * If this is part of a multi-fragment packet,
1962 * discard all the pieces.
1964 re_free_rxchain(sc);
1965 re_setup_rxdesc(sc, i);
1970 * If allocating a replacement mbuf fails,
1971 * reload the current one.
1974 if (sc->re_newbuf(sc, i, 0)) {
1979 if (sc->re_head != NULL) {
1980 m->m_len = total_len % MCLBYTES;
1982 * Special case: if there's 4 bytes or less
1983 * in this buffer, the mbuf can be discarded:
1984 * the last 4 bytes is the CRC, which we don't
1985 * care about anyway.
1987 if (m->m_len <= ETHER_CRC_LEN) {
1988 sc->re_tail->m_len -=
1989 (ETHER_CRC_LEN - m->m_len);
1992 m->m_len -= ETHER_CRC_LEN;
1993 sc->re_tail->m_next = m;
1996 sc->re_head = sc->re_tail = NULL;
1997 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1999 m->m_pkthdr.len = m->m_len =
2000 (total_len - ETHER_CRC_LEN);
2004 m->m_pkthdr.rcvif = ifp;
2006 /* Do RX checksumming if enabled */
2008 if (ifp->if_capenable & IFCAP_RXCSUM) {
2009 uint8_t packet_type;
2011 packet_type = re_packet_type(sc, rxstat, rxctrl);
2013 /* Check IP header checksum */
2014 if (packet_type & RE_IP4_PACKET) {
2015 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2016 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
2017 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2020 /* Check TCP/UDP checksum */
2021 if (((packet_type & RE_TCP_PACKET) &&
2022 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
2023 ((packet_type & RE_UDP_PACKET) &&
2024 (rxstat & RE_RDESC_STAT_UDPSUMBAD) == 0)) {
2025 m->m_pkthdr.csum_flags |=
2026 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
2027 CSUM_FRAG_NOT_CHECKED;
2028 m->m_pkthdr.csum_data = 0xffff;
2032 if (rxctrl & RE_RDESC_CTL_HASTAG) {
2033 m->m_flags |= M_VLANTAG;
2034 m->m_pkthdr.ether_vlantag =
2035 be16toh((rxctrl & RE_RDESC_CTL_TAGDATA));
2037 ether_input_chain(ifp, m, chain);
2040 ether_input_dispatch(chain);
2042 /* Flush the RX DMA ring */
2044 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
2045 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
2047 sc->re_ldata.re_rx_prodidx = i;
2052 #undef RE_IP4_PACKET
2053 #undef RE_TCP_PACKET
2054 #undef RE_UDP_PACKET
2057 re_tx_collect(struct re_softc *sc)
2059 struct ifnet *ifp = &sc->arpcom.ac_if;
2063 /* Invalidate the TX descriptor list */
2064 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
2065 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_POSTREAD);
2067 for (idx = sc->re_ldata.re_tx_considx;
2068 sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt;
2069 RE_TXDESC_INC(sc, idx)) {
2070 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
2071 if (txstat & RE_TDESC_CMD_OWN)
2076 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0;
2079 * We only stash mbufs in the last descriptor
2080 * in a fragment chain, which also happens to
2081 * be the only place where the TX status bits
2084 if (txstat & RE_TDESC_CMD_EOF) {
2085 bus_dmamap_unload(sc->re_ldata.re_tx_mtag,
2086 sc->re_ldata.re_tx_dmamap[idx]);
2087 m_freem(sc->re_ldata.re_tx_mbuf[idx]);
2088 sc->re_ldata.re_tx_mbuf[idx] = NULL;
2089 if (txstat & (RE_TDESC_STAT_EXCESSCOL|
2090 RE_TDESC_STAT_COLCNT))
2091 ifp->if_collisions++;
2092 if (txstat & RE_TDESC_STAT_TXERRSUM)
2097 sc->re_ldata.re_tx_free++;
2099 sc->re_ldata.re_tx_considx = idx;
2105 re_txeof(struct re_softc *sc)
2107 struct ifnet *ifp = &sc->arpcom.ac_if;
2110 tx = re_tx_collect(sc);
2112 /* There is enough free TX descs */
2113 if (sc->re_ldata.re_tx_free > RE_TXDESC_SPARE)
2114 ifp->if_flags &= ~IFF_OACTIVE;
2117 * Some chips will ignore a second TX request issued while an
2118 * existing transmission is in progress. If the transmitter goes
2119 * idle but there are still packets waiting to be sent, we need
2120 * to restart the channel here to flush them out. This only seems
2121 * to be required with the PCIe devices.
2123 if (sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt)
2124 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2134 struct re_softc *sc = xsc;
2136 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
2137 re_tick_serialized(xsc);
2138 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
2142 re_tick_serialized(void *xsc)
2144 struct re_softc *sc = xsc;
2145 struct ifnet *ifp = &sc->arpcom.ac_if;
2146 struct mii_data *mii;
2148 ASSERT_SERIALIZED(ifp->if_serializer);
2150 mii = device_get_softc(sc->re_miibus);
2152 if (sc->re_flags & RE_F_LINKED) {
2153 if (!(mii->mii_media_status & IFM_ACTIVE))
2154 sc->re_flags &= ~RE_F_LINKED;
2156 if (mii->mii_media_status & IFM_ACTIVE &&
2157 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2158 sc->re_flags |= RE_F_LINKED;
2159 if (!ifq_is_empty(&ifp->if_snd))
2164 callout_reset(&sc->re_timer, hz, re_tick, sc);
2167 #ifdef DEVICE_POLLING
2170 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2172 struct re_softc *sc = ifp->if_softc;
2174 ASSERT_SERIALIZED(ifp->if_serializer);
2178 /* disable interrupts */
2179 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
2182 case POLL_DEREGISTER:
2183 /* enable interrupts */
2184 re_setup_intr(sc, 1, sc->re_imtype);
2188 sc->rxcycles = count;
2192 if (!ifq_is_empty(&ifp->if_snd))
2195 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2198 status = CSR_READ_2(sc, RE_ISR);
2199 if (status == 0xffff)
2202 CSR_WRITE_2(sc, RE_ISR, status);
2205 * XXX check behaviour on receiver stalls.
2208 if (status & RE_ISR_SYSTEM_ERR)
2214 #endif /* DEVICE_POLLING */
2219 struct re_softc *sc = arg;
2220 struct ifnet *ifp = &sc->arpcom.ac_if;
2224 ASSERT_SERIALIZED(ifp->if_serializer);
2226 if ((sc->re_flags & RE_F_SUSPENDED) ||
2227 (ifp->if_flags & IFF_RUNNING) == 0)
2232 status = CSR_READ_2(sc, RE_ISR);
2233 /* If the card has gone away the read returns 0xffff. */
2234 if (status == 0xffff)
2237 CSR_WRITE_2(sc, RE_ISR, status);
2239 if ((status & sc->re_intrs) == 0)
2242 if (status & (sc->re_rx_ack | RE_ISR_RX_ERR))
2245 if (status & (sc->re_tx_ack | RE_ISR_TX_ERR))
2248 if (status & RE_ISR_SYSTEM_ERR)
2251 if (status & RE_ISR_LINKCHG) {
2252 callout_stop(&sc->re_timer);
2253 re_tick_serialized(sc);
2257 if (sc->re_imtype == RE_IMTYPE_SIM) {
2258 if ((sc->re_flags & RE_F_TIMER_INTR)) {
2259 if ((tx | rx) == 0) {
2261 * Nothing needs to be processed, fallback
2262 * to use TX/RX interrupts.
2264 re_setup_intr(sc, 1, RE_IMTYPE_NONE);
2267 * Recollect, mainly to avoid the possible
2268 * race introduced by changing interrupt
2274 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */
2276 } else if (tx | rx) {
2278 * Assume that using simulated interrupt moderation
2279 * (hardware timer based) could reduce the interript
2282 re_setup_intr(sc, 1, RE_IMTYPE_SIM);
2286 if (tx && !ifq_is_empty(&ifp->if_snd))
2291 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx0)
2293 struct ifnet *ifp = &sc->arpcom.ac_if;
2295 struct re_dmaload_arg arg;
2296 bus_dma_segment_t segs[RE_MAXSEGS];
2298 int error, maxsegs, idx, i;
2299 struct re_desc *d, *tx_ring;
2300 uint32_t cmd_csum, ctl_csum, vlantag;
2302 KASSERT(sc->re_ldata.re_tx_free > RE_TXDESC_SPARE,
2303 ("not enough free TX desc\n"));
2306 map = sc->re_ldata.re_tx_dmamap[*idx0];
2309 * Set up checksum offload. Note: checksum offload bits must
2310 * appear in all descriptors of a multi-descriptor transmit
2311 * attempt. (This is according to testing done with an 8169
2312 * chip. I'm not sure if this is a requirement or a bug.)
2314 cmd_csum = ctl_csum = 0;
2315 if (m->m_pkthdr.csum_flags & CSUM_IP) {
2316 cmd_csum |= RE_TDESC_CMD_IPCSUM;
2317 ctl_csum |= RE_TDESC_CTL_IPCSUM;
2319 if (m->m_pkthdr.csum_flags & CSUM_TCP) {
2320 cmd_csum |= RE_TDESC_CMD_TCPCSUM;
2321 ctl_csum |= RE_TDESC_CTL_TCPCSUM;
2323 if (m->m_pkthdr.csum_flags & CSUM_UDP) {
2324 cmd_csum |= RE_TDESC_CMD_UDPCSUM;
2325 ctl_csum |= RE_TDESC_CTL_UDPCSUM;
2328 /* For MAC2 chips, csum flags are set on re_control */
2329 if (sc->re_caps & RE_C_MAC2)
2334 if ((sc->re_caps & RE_C_AUTOPAD) == 0) {
2336 * With some of the RealTek chips, using the checksum offload
2337 * support in conjunction with the autopadding feature results
2338 * in the transmission of corrupt frames. For example, if we
2339 * need to send a really small IP fragment that's less than 60
2340 * bytes in size, and IP header checksumming is enabled, the
2341 * resulting ethernet frame that appears on the wire will
2342 * have garbled payload. To work around this, if TX checksum
2343 * offload is enabled, we always manually pad short frames out
2344 * to the minimum ethernet frame size.
2346 * Note: this appears unnecessary for TCP, and doing it for TCP
2347 * with PCIe adapters seems to result in bad checksums.
2349 if ((m->m_pkthdr.csum_flags &
2350 (CSUM_DELAY_IP | CSUM_DELAY_DATA)) &&
2351 (m->m_pkthdr.csum_flags & CSUM_TCP) == 0 &&
2352 m->m_pkthdr.len < RE_MIN_FRAMELEN) {
2353 error = m_devpad(m, RE_MIN_FRAMELEN);
2360 if (m->m_flags & M_VLANTAG) {
2361 vlantag = htobe16(m->m_pkthdr.ether_vlantag) |
2362 RE_TDESC_CTL_INSTAG;
2365 maxsegs = sc->re_ldata.re_tx_free;
2366 if (maxsegs > RE_MAXSEGS)
2367 maxsegs = RE_MAXSEGS;
2369 arg.re_nsegs = maxsegs;
2371 error = bus_dmamap_load_mbuf(sc->re_ldata.re_tx_mtag, map, m,
2372 re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
2373 if (error && error != EFBIG) {
2374 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2379 * Too many segments to map, coalesce into a single mbuf
2381 if (!error && arg.re_nsegs == 0) {
2382 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, map);
2388 m_new = m_defrag(m, MB_DONTWAIT);
2389 if (m_new == NULL) {
2390 if_printf(ifp, "can't defrag TX mbuf\n");
2394 *m_head = m = m_new;
2397 arg.re_nsegs = maxsegs;
2399 error = bus_dmamap_load_mbuf(sc->re_ldata.re_tx_mtag, map, m,
2400 re_dma_map_desc, &arg,
2402 if (error || arg.re_nsegs == 0) {
2404 bus_dmamap_unload(sc->re_ldata.re_tx_mtag, map);
2407 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2411 bus_dmamap_sync(sc->re_ldata.re_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2414 * Map the segment array into descriptors. We also keep track
2415 * of the end of the ring and set the end-of-ring bits as needed,
2416 * and we set the ownership bits in all except the very first
2417 * descriptor, whose ownership bits will be turned on later.
2419 tx_ring = sc->re_ldata.re_tx_list;
2427 cmdstat = segs[i].ds_len;
2428 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
2429 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
2431 cmdstat |= RE_TDESC_CMD_SOF;
2433 cmdstat |= RE_TDESC_CMD_OWN;
2434 if (idx == (sc->re_tx_desc_cnt - 1))
2435 cmdstat |= RE_TDESC_CMD_EOR;
2436 d->re_cmdstat = htole32(cmdstat | cmd_csum);
2437 d->re_control = htole32(ctl_csum | vlantag);
2440 if (i == arg.re_nsegs)
2442 RE_TXDESC_INC(sc, idx);
2444 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
2446 /* Transfer ownership of packet to the chip. */
2447 d->re_cmdstat |= htole32(RE_TDESC_CMD_OWN);
2449 tx_ring[*idx0].re_cmdstat |= htole32(RE_TDESC_CMD_OWN);
2452 * Insure that the map for this transmission
2453 * is placed at the array index of the last descriptor
2456 sc->re_ldata.re_tx_dmamap[*idx0] = sc->re_ldata.re_tx_dmamap[idx];
2457 sc->re_ldata.re_tx_dmamap[idx] = map;
2459 sc->re_ldata.re_tx_mbuf[idx] = m;
2460 sc->re_ldata.re_tx_free -= arg.re_nsegs;
2462 RE_TXDESC_INC(sc, idx);
2473 * Main transmit routine for C+ and gigE NICs.
2477 re_start(struct ifnet *ifp)
2479 struct re_softc *sc = ifp->if_softc;
2480 struct mbuf *m_head;
2481 int idx, need_trans, oactive, error;
2483 ASSERT_SERIALIZED(ifp->if_serializer);
2485 if ((sc->re_flags & RE_F_LINKED) == 0) {
2486 ifq_purge(&ifp->if_snd);
2490 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
2493 idx = sc->re_ldata.re_tx_prodidx;
2497 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
2498 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) {
2500 if (re_tx_collect(sc)) {
2505 ifp->if_flags |= IFF_OACTIVE;
2509 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2513 error = re_encap(sc, &m_head, &idx);
2515 /* m_head is freed by re_encap(), if we reach here */
2518 if (error == EFBIG && !oactive) {
2519 if (re_tx_collect(sc)) {
2524 ifp->if_flags |= IFF_OACTIVE;
2532 * If there's a BPF listener, bounce a copy of this frame
2535 ETHER_BPF_MTAP(ifp, m_head);
2541 /* Flush the TX descriptors */
2542 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
2543 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
2545 sc->re_ldata.re_tx_prodidx = idx;
2548 * RealTek put the TX poll request register in a different
2549 * location on the 8169 gigE chip. I don't know why.
2551 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2554 * Set a timeout in case the chip goes out to lunch.
2562 struct re_softc *sc = xsc;
2563 struct ifnet *ifp = &sc->arpcom.ac_if;
2564 struct mii_data *mii;
2565 int error, framelen;
2567 ASSERT_SERIALIZED(ifp->if_serializer);
2569 mii = device_get_softc(sc->re_miibus);
2572 * Cancel pending I/O and free all RX/TX buffers.
2576 if (sc->re_caps & RE_C_CONTIGRX) {
2577 if (ifp->if_mtu > ETHERMTU) {
2578 KKASSERT(sc->re_ldata.re_jbuf != NULL);
2579 sc->re_flags |= RE_F_USE_JPOOL;
2580 sc->re_rxbuf_size = RE_FRAMELEN_MAX;
2581 sc->re_newbuf = re_newbuf_jumbo;
2583 sc->re_flags &= ~RE_F_USE_JPOOL;
2584 sc->re_rxbuf_size = MCLBYTES;
2585 sc->re_newbuf = re_newbuf_std;
2590 * Adjust max read request size according to MTU; mainly to
2591 * improve TX performance for common case (ETHERMTU) on GigE
2592 * NICs. However, this could _not_ be done on 10/100 only
2593 * NICs; their DMA engines will malfunction using non-default
2594 * max read request size.
2596 if ((sc->re_caps & (RE_C_PCIE | RE_C_FASTE)) == RE_C_PCIE) {
2597 if (ifp->if_mtu > ETHERMTU) {
2599 * 512 seems to be the only value that works
2600 * reliably with jumbo frame
2602 pcie_set_max_readrq(sc->re_dev,
2603 PCIEM_DEVCTL_MAX_READRQ_512);
2605 pcie_set_max_readrq(sc->re_dev,
2606 PCIEM_DEVCTL_MAX_READRQ_4096);
2611 * Enable C+ RX and TX mode, as well as VLAN stripping and
2612 * RX checksum offload. We must configure the C+ register
2613 * before all others.
2615 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
2616 RE_CPLUSCMD_PCI_MRW |
2617 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING ?
2618 RE_CPLUSCMD_VLANSTRIP : 0) |
2619 (ifp->if_capenable & IFCAP_RXCSUM ?
2620 RE_CPLUSCMD_RXCSUM_ENB : 0));
2623 * Init our MAC address. Even though the chipset
2624 * documentation doesn't mention it, we need to enter "Config
2625 * register write enable" mode to modify the ID registers.
2627 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
2628 CSR_WRITE_4(sc, RE_IDR0,
2629 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0])));
2630 CSR_WRITE_2(sc, RE_IDR4,
2631 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4])));
2632 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
2635 * For C+ mode, initialize the RX descriptors and mbufs.
2637 error = re_rx_list_init(sc);
2642 error = re_tx_list_init(sc);
2649 * Load the addresses of the RX and TX lists into the chip.
2651 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
2652 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2653 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2654 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2656 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2657 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2658 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2659 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2662 * Enable transmit and receive.
2664 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2667 * Set the initial TX and RX configuration.
2669 if (sc->re_flags & RE_F_TESTMODE) {
2670 if (!RE_IS_8139CP(sc))
2671 CSR_WRITE_4(sc, RE_TXCFG,
2672 RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
2674 CSR_WRITE_4(sc, RE_TXCFG,
2675 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
2677 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
2679 framelen = RE_FRAMELEN(ifp->if_mtu);
2680 if (framelen < MCLBYTES)
2681 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(MCLBYTES, 128));
2683 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(framelen, 128));
2685 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
2688 * Program the multicast filter, if necessary.
2692 #ifdef DEVICE_POLLING
2694 * Disable interrupts if we are polling.
2696 if (ifp->if_flags & IFF_POLLING)
2697 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
2698 else /* otherwise ... */
2699 #endif /* DEVICE_POLLING */
2701 * Enable interrupts.
2703 if (sc->re_flags & RE_F_TESTMODE)
2704 CSR_WRITE_2(sc, RE_IMR, 0);
2706 re_setup_intr(sc, 1, sc->re_imtype);
2707 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs);
2709 /* Start RX/TX process. */
2710 CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
2713 /* Enable receiver and transmitter. */
2714 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2718 * For 8169 gigE NICs, set the max allowed RX packet
2719 * size so we can receive jumbo frames.
2721 if (!RE_IS_8139CP(sc)) {
2722 if (sc->re_caps & RE_C_CONTIGRX)
2723 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, sc->re_rxbuf_size);
2725 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2728 if (sc->re_flags & RE_F_TESTMODE)
2733 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2735 ifp->if_flags |= IFF_RUNNING;
2736 ifp->if_flags &= ~IFF_OACTIVE;
2738 callout_reset(&sc->re_timer, hz, re_tick, sc);
2742 * Set media options.
2745 re_ifmedia_upd(struct ifnet *ifp)
2747 struct re_softc *sc = ifp->if_softc;
2748 struct mii_data *mii;
2750 ASSERT_SERIALIZED(ifp->if_serializer);
2752 mii = device_get_softc(sc->re_miibus);
2759 * Report current media status.
2762 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2764 struct re_softc *sc = ifp->if_softc;
2765 struct mii_data *mii;
2767 ASSERT_SERIALIZED(ifp->if_serializer);
2769 mii = device_get_softc(sc->re_miibus);
2772 ifmr->ifm_active = mii->mii_media_active;
2773 ifmr->ifm_status = mii->mii_media_status;
2777 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2779 struct re_softc *sc = ifp->if_softc;
2780 struct ifreq *ifr = (struct ifreq *) data;
2781 struct mii_data *mii;
2782 int error = 0, mask;
2784 ASSERT_SERIALIZED(ifp->if_serializer);
2788 if (ifr->ifr_mtu > sc->re_maxmtu) {
2790 } else if (ifp->if_mtu != ifr->ifr_mtu) {
2791 ifp->if_mtu = ifr->ifr_mtu;
2792 if (ifp->if_flags & IFF_RUNNING)
2798 if (ifp->if_flags & IFF_UP) {
2799 if (ifp->if_flags & IFF_RUNNING) {
2800 if ((ifp->if_flags ^ sc->re_if_flags) &
2801 (IFF_PROMISC | IFF_ALLMULTI))
2806 } else if (ifp->if_flags & IFF_RUNNING) {
2809 sc->re_if_flags = ifp->if_flags;
2819 mii = device_get_softc(sc->re_miibus);
2820 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2824 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) &
2825 ifp->if_capabilities;
2826 ifp->if_capenable ^= mask;
2828 if (mask & IFCAP_HWCSUM) {
2829 if (ifp->if_capenable & IFCAP_TXCSUM)
2830 ifp->if_hwassist = RE_CSUM_FEATURES;
2832 ifp->if_hwassist = 0;
2834 if (mask && (ifp->if_flags & IFF_RUNNING))
2839 error = ether_ioctl(ifp, command, data);
2846 re_watchdog(struct ifnet *ifp)
2848 struct re_softc *sc = ifp->if_softc;
2850 ASSERT_SERIALIZED(ifp->if_serializer);
2852 if_printf(ifp, "watchdog timeout\n");
2861 if (!ifq_is_empty(&ifp->if_snd))
2866 * Stop the adapter and free any mbufs allocated to the
2870 re_stop(struct re_softc *sc)
2872 struct ifnet *ifp = &sc->arpcom.ac_if;
2875 ASSERT_SERIALIZED(ifp->if_serializer);
2877 /* Reset the adapter. */
2878 re_reset(sc, ifp->if_flags & IFF_RUNNING);
2881 callout_stop(&sc->re_timer);
2883 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2884 sc->re_flags &= ~(RE_F_TIMER_INTR | RE_F_DROP_RXFRAG | RE_F_LINKED);
2886 CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2887 CSR_WRITE_2(sc, RE_IMR, 0x0000);
2888 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
2890 re_free_rxchain(sc);
2892 /* Free the TX list buffers. */
2893 for (i = 0; i < sc->re_tx_desc_cnt; i++) {
2894 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2895 bus_dmamap_unload(sc->re_ldata.re_tx_mtag,
2896 sc->re_ldata.re_tx_dmamap[i]);
2897 m_freem(sc->re_ldata.re_tx_mbuf[i]);
2898 sc->re_ldata.re_tx_mbuf[i] = NULL;
2902 /* Free the RX list buffers. */
2903 for (i = 0; i < sc->re_rx_desc_cnt; i++) {
2904 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2905 if ((sc->re_flags & RE_F_USE_JPOOL) == 0) {
2906 bus_dmamap_unload(sc->re_ldata.re_rx_mtag,
2907 sc->re_ldata.re_rx_dmamap[i]);
2909 m_freem(sc->re_ldata.re_rx_mbuf[i]);
2910 sc->re_ldata.re_rx_mbuf[i] = NULL;
2916 * Device suspend routine. Stop the interface and save some PCI
2917 * settings in case the BIOS doesn't restore them properly on
2921 re_suspend(device_t dev)
2923 #ifndef BURN_BRIDGES
2926 struct re_softc *sc = device_get_softc(dev);
2927 struct ifnet *ifp = &sc->arpcom.ac_if;
2929 lwkt_serialize_enter(ifp->if_serializer);
2933 #ifndef BURN_BRIDGES
2934 for (i = 0; i < 5; i++)
2935 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2936 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2937 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2938 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2939 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2942 sc->re_flags |= RE_F_SUSPENDED;
2944 lwkt_serialize_exit(ifp->if_serializer);
2950 * Device resume routine. Restore some PCI settings in case the BIOS
2951 * doesn't, re-enable busmastering, and restart the interface if
2955 re_resume(device_t dev)
2957 struct re_softc *sc = device_get_softc(dev);
2958 struct ifnet *ifp = &sc->arpcom.ac_if;
2959 #ifndef BURN_BRIDGES
2963 lwkt_serialize_enter(ifp->if_serializer);
2965 #ifndef BURN_BRIDGES
2966 /* better way to do this? */
2967 for (i = 0; i < 5; i++)
2968 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2969 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2970 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2971 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2972 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2974 /* reenable busmastering */
2975 pci_enable_busmaster(dev);
2976 pci_enable_io(dev, SYS_RES_IOPORT);
2979 /* reinitialize interface if necessary */
2980 if (ifp->if_flags & IFF_UP)
2983 sc->re_flags &= ~RE_F_SUSPENDED;
2985 lwkt_serialize_exit(ifp->if_serializer);
2991 * Stop all chip I/O so that the kernel's probe routines don't
2992 * get confused by errant DMAs when rebooting.
2995 re_shutdown(device_t dev)
2997 struct re_softc *sc = device_get_softc(dev);
2998 struct ifnet *ifp = &sc->arpcom.ac_if;
3000 lwkt_serialize_enter(ifp->if_serializer);
3002 lwkt_serialize_exit(ifp->if_serializer);
3006 re_sysctl_rxtime(SYSCTL_HANDLER_ARGS)
3008 struct re_softc *sc = arg1;
3010 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_rx_time);
3014 re_sysctl_txtime(SYSCTL_HANDLER_ARGS)
3016 struct re_softc *sc = arg1;
3018 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_tx_time);
3022 re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *hwtime)
3024 struct re_softc *sc = arg1;
3025 struct ifnet *ifp = &sc->arpcom.ac_if;
3028 lwkt_serialize_enter(ifp->if_serializer);
3031 error = sysctl_handle_int(oidp, &v, 0, req);
3032 if (error || req->newptr == NULL)
3043 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) ==
3044 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_HW)
3048 lwkt_serialize_exit(ifp->if_serializer);
3053 re_sysctl_simtime(SYSCTL_HANDLER_ARGS)
3055 struct re_softc *sc = arg1;
3056 struct ifnet *ifp = &sc->arpcom.ac_if;
3059 lwkt_serialize_enter(ifp->if_serializer);
3061 v = sc->re_sim_time;
3062 error = sysctl_handle_int(oidp, &v, 0, req);
3063 if (error || req->newptr == NULL)
3071 if (v != sc->re_sim_time) {
3072 sc->re_sim_time = v;
3074 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) ==
3075 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_SIM) {
3080 * Following code causes various strange
3081 * performance problems. Hmm ...
3083 CSR_WRITE_2(sc, RE_IMR, 0);
3084 if (!RE_IS_8139CP(sc))
3085 reg = RE_TIMERINT_8169;
3088 CSR_WRITE_4(sc, reg, 0);
3089 CSR_READ_4(sc, reg); /* flush */
3091 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
3092 re_setup_sim_im(sc);
3094 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
3096 re_setup_intr(sc, 1, RE_IMTYPE_SIM);
3101 lwkt_serialize_exit(ifp->if_serializer);
3106 re_sysctl_imtype(SYSCTL_HANDLER_ARGS)
3108 struct re_softc *sc = arg1;
3109 struct ifnet *ifp = &sc->arpcom.ac_if;
3112 lwkt_serialize_enter(ifp->if_serializer);
3115 error = sysctl_handle_int(oidp, &v, 0, req);
3116 if (error || req->newptr == NULL)
3119 if (v != RE_IMTYPE_HW && v != RE_IMTYPE_SIM && v != RE_IMTYPE_NONE) {
3123 if (v == RE_IMTYPE_HW && (sc->re_caps & RE_C_HWIM) == 0) {
3124 /* Can't do hardware interrupt moderation */
3129 if (v != sc->re_imtype) {
3131 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) ==
3133 re_setup_intr(sc, 1, sc->re_imtype);
3136 lwkt_serialize_exit(ifp->if_serializer);
3141 re_setup_hw_im(struct re_softc *sc)
3143 KKASSERT(sc->re_caps & RE_C_HWIM);
3146 * Interrupt moderation
3149 * A - unknown (maybe TX related)
3150 * B - TX timer (unit: 25us)
3151 * C - unknown (maybe RX related)
3152 * D - RX timer (unit: 25us)
3155 * re(4)'s interrupt moderation is actually controlled by
3156 * two variables, like most other NICs (bge, bce etc.)
3158 * o number of packets [P]
3160 * The logic relationship between these two variables is
3161 * similar to other NICs too:
3162 * if (timer expire || packets > [P])
3163 * Interrupt is delivered
3165 * Currently we only know how to set 'timer', but not
3166 * 'number of packets', which should be ~30, as far as I
3167 * tested (sink ~900Kpps, interrupt rate is 30KHz)
3169 CSR_WRITE_2(sc, RE_IM,
3170 RE_IM_RXTIME(sc->re_rx_time) |
3171 RE_IM_TXTIME(sc->re_tx_time) |
3176 re_disable_hw_im(struct re_softc *sc)
3178 if (sc->re_caps & RE_C_HWIM)
3179 CSR_WRITE_2(sc, RE_IM, 0);
3183 re_setup_sim_im(struct re_softc *sc)
3185 if (!RE_IS_8139CP(sc)) {
3189 * Datasheet says tick decreases at bus speed,
3190 * but it seems the clock runs a little bit
3191 * faster, so we do some compensation here.
3193 ticks = (sc->re_sim_time * sc->re_bus_speed * 8) / 5;
3194 CSR_WRITE_4(sc, RE_TIMERINT_8169, ticks);
3196 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); /* XXX */
3198 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */
3199 sc->re_flags |= RE_F_TIMER_INTR;
3203 re_disable_sim_im(struct re_softc *sc)
3205 if (!RE_IS_8139CP(sc))
3206 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0);
3208 CSR_WRITE_4(sc, RE_TIMERINT, 0);
3209 sc->re_flags &= ~RE_F_TIMER_INTR;
3213 re_config_imtype(struct re_softc *sc, int imtype)
3217 KKASSERT(sc->re_caps & RE_C_HWIM);
3219 case RE_IMTYPE_NONE:
3220 sc->re_intrs = RE_INTRS;
3221 sc->re_rx_ack = RE_ISR_RX_OK | RE_ISR_FIFO_OFLOW |
3223 sc->re_tx_ack = RE_ISR_TX_OK;
3227 sc->re_intrs = RE_INTRS_TIMER;
3228 sc->re_rx_ack = RE_ISR_TIMEOUT_EXPIRED;
3229 sc->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED;
3233 panic("%s: unknown imtype %d\n",
3234 sc->arpcom.ac_if.if_xname, imtype);
3239 re_setup_intr(struct re_softc *sc, int enable_intrs, int imtype)
3241 re_config_imtype(sc, imtype);
3244 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
3246 CSR_WRITE_2(sc, RE_IMR, 0);
3249 case RE_IMTYPE_NONE:
3250 re_disable_sim_im(sc);
3251 re_disable_hw_im(sc);
3255 KKASSERT(sc->re_caps & RE_C_HWIM);
3256 re_disable_sim_im(sc);
3261 re_disable_hw_im(sc);
3262 re_setup_sim_im(sc);
3266 panic("%s: unknown imtype %d\n",
3267 sc->arpcom.ac_if.if_xname, imtype);
3272 re_get_eaddr(struct re_softc *sc, uint8_t *eaddr)
3276 if (sc->re_macver == RE_MACVER_11 || sc->re_macver == RE_MACVER_12) {
3280 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
3281 if (re_did == 0x8128) {
3282 uint16_t as[ETHER_ADDR_LEN / 2];
3285 * Get station address from the EEPROM.
3287 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3);
3288 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
3289 as[i] = le16toh(as[i]);
3290 bcopy(as, eaddr, sizeof(eaddr));
3296 * Get station address from IDRx.
3298 for (i = 0; i < ETHER_ADDR_LEN; ++i)
3299 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i);
3303 re_jpool_alloc(struct re_softc *sc)
3305 struct re_list_data *ldata = &sc->re_ldata;
3306 struct re_jbuf *jbuf;
3308 bus_size_t jpool_size;
3313 lwkt_serialize_init(&ldata->re_jbuf_serializer);
3315 ldata->re_jbuf = kmalloc(sizeof(struct re_jbuf) * RE_JBUF_COUNT(sc),
3316 M_DEVBUF, M_WAITOK | M_ZERO);
3318 jpool_size = RE_JBUF_COUNT(sc) * RE_JBUF_SIZE;
3320 error = bus_dmamem_coherent(sc->re_parent_tag,
3322 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3323 jpool_size, BUS_DMA_WAITOK, &dmem);
3325 device_printf(sc->re_dev, "could not allocate jumbo memory\n");
3328 ldata->re_jpool_tag = dmem.dmem_tag;
3329 ldata->re_jpool_map = dmem.dmem_map;
3330 ldata->re_jpool = dmem.dmem_addr;
3331 paddr = dmem.dmem_busaddr;
3333 /* ..and split it into 9KB chunks */
3334 SLIST_INIT(&ldata->re_jbuf_free);
3336 buf = ldata->re_jpool;
3337 for (i = 0; i < RE_JBUF_COUNT(sc); i++) {
3338 jbuf = &ldata->re_jbuf[i];
3344 jbuf->re_paddr = paddr;
3346 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link);
3348 buf += RE_JBUF_SIZE;
3349 paddr += RE_JBUF_SIZE;
3355 re_jpool_free(struct re_softc *sc)
3357 struct re_list_data *ldata = &sc->re_ldata;
3359 if (ldata->re_jpool_tag != NULL) {
3360 bus_dmamap_unload(ldata->re_jpool_tag, ldata->re_jpool_map);
3361 bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool,
3362 ldata->re_jpool_map);
3363 bus_dma_tag_destroy(ldata->re_jpool_tag);
3364 ldata->re_jpool_tag = NULL;
3367 if (ldata->re_jbuf != NULL) {
3368 kfree(ldata->re_jbuf, M_DEVBUF);
3369 ldata->re_jbuf = NULL;
3373 static struct re_jbuf *
3374 re_jbuf_alloc(struct re_softc *sc)
3376 struct re_list_data *ldata = &sc->re_ldata;
3377 struct re_jbuf *jbuf;
3379 lwkt_serialize_enter(&ldata->re_jbuf_serializer);
3381 jbuf = SLIST_FIRST(&ldata->re_jbuf_free);
3383 SLIST_REMOVE_HEAD(&ldata->re_jbuf_free, re_link);
3387 lwkt_serialize_exit(&ldata->re_jbuf_serializer);
3393 re_jbuf_free(void *arg)
3395 struct re_jbuf *jbuf = arg;
3396 struct re_softc *sc = jbuf->re_sc;
3397 struct re_list_data *ldata = &sc->re_ldata;
3399 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) {
3400 panic("%s: free wrong jumbo buffer\n",
3401 sc->arpcom.ac_if.if_xname);
3402 } else if (jbuf->re_inuse == 0) {
3403 panic("%s: jumbo buffer already freed\n",
3404 sc->arpcom.ac_if.if_xname);
3407 lwkt_serialize_enter(&ldata->re_jbuf_serializer);
3408 atomic_subtract_int(&jbuf->re_inuse, 1);
3409 if (jbuf->re_inuse == 0)
3410 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link);
3411 lwkt_serialize_exit(&ldata->re_jbuf_serializer);
3415 re_jbuf_ref(void *arg)
3417 struct re_jbuf *jbuf = arg;
3418 struct re_softc *sc = jbuf->re_sc;
3419 struct re_list_data *ldata = &sc->re_ldata;
3421 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) {
3422 panic("%s: ref wrong jumbo buffer\n",
3423 sc->arpcom.ac_if.if_xname);
3424 } else if (jbuf->re_inuse == 0) {
3425 panic("%s: jumbo buffer already freed\n",
3426 sc->arpcom.ac_if.if_xname);
3428 atomic_add_int(&jbuf->re_inuse, 1);