sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.111 2008/10/22 14:24:24 sephe Exp $
  35  *
  36  */
  37
  38 /*
  39  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  40  *
  41  * Written by Bill Paul <wpaul@windriver.com>
  42  * Senior Engineer, Wind River Systems
  43  */
  44
  45 /*
  46  * The Broadcom BCM5700 is based on technology originally developed by
  47  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  48  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  49  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  50  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  51  * frames, highly configurable RX filtering, and 16 RX and TX queues
  52  * (which, along with RX filter rules, can be used for QOS applications).
  53  * Other features, such as TCP segmentation, may be available as part
  54  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  55  * firmware images can be stored in hardware and need not be compiled
  56  * into the driver.
  57  *
  58  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  59  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  60  *
  61  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  62  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  63  * does not support external SSRAM.
  64  *
  65  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  66  * brand name, which is functionally similar but lacks PCI-X support.
  67  *
  68  * Without external SSRAM, you can only have at most 4 TX rings,
  69  * and the use of the mini RX ring is disabled. This seems to imply
  70  * that these features are simply not available on the BCM5701. As a
  71  * result, this driver does not implement any support for the mini RX
  72  * ring.
  73  */
  74
  75 #include "opt_polling.h"
  76
  77 #include <sys/param.h>
  78 #include <sys/bus.h>
  79 #include <sys/endian.h>
  80 #include <sys/kernel.h>
  81 #include <sys/ktr.h>
  82 #include <sys/interrupt.h>
  83 #include <sys/mbuf.h>
  84 #include <sys/malloc.h>
  85 #include <sys/queue.h>
  86 #include <sys/rman.h>
  87 #include <sys/serialize.h>
  88 #include <sys/socket.h>
  89 #include <sys/sockio.h>
  90 #include <sys/sysctl.h>
  91
  92 #include <net/bpf.h>
  93 #include <net/ethernet.h>
  94 #include <net/if.h>
  95 #include <net/if_arp.h>
  96 #include <net/if_dl.h>
  97 #include <net/if_media.h>
  98 #include <net/if_types.h>
  99 #include <net/ifq_var.h>
 100 #include <net/vlan/if_vlan_var.h>
 101 #include <net/vlan/if_vlan_ether.h>
 102
 103 #include <dev/netif/mii_layer/mii.h>
 104 #include <dev/netif/mii_layer/miivar.h>
 105 #include <dev/netif/mii_layer/brgphyreg.h>
 106
 107 #include <bus/pci/pcidevs.h>
 108 #include <bus/pci/pcireg.h>
 109 #include <bus/pci/pcivar.h>
 110
 111 #include <dev/netif/bge/if_bgereg.h>
 112
 113 /* "device miibus" required.  See GENERIC if you get errors here. */
 114 #include "miibus_if.h"
 115
 116 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 117 #define BGE_MIN_FRAME           60
 118
 119 static const struct bge_type bge_devs[] = {
 120         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
 121                 "3COM 3C996 Gigabit Ethernet" },
 122
 123         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 124                 "Alteon BCM5700 Gigabit Ethernet" },
 125         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
 126                 "Alteon BCM5701 Gigabit Ethernet" },
 127
 128         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 129                 "Altima AC1000 Gigabit Ethernet" },
 130         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 131                 "Altima AC1002 Gigabit Ethernet" },
 132         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 133                 "Altima AC9100 Gigabit Ethernet" },
 134
 135         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
 136                 "Apple BCM5701 Gigabit Ethernet" },
 137
 138         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 139                 "Broadcom BCM5700 Gigabit Ethernet" },
 140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 141                 "Broadcom BCM5701 Gigabit Ethernet" },
 142         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
 143                 "Broadcom BCM5702 Gigabit Ethernet" },
 144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 145                 "Broadcom BCM5702X Gigabit Ethernet" },
 146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
 147                 "Broadcom BCM5702 Gigabit Ethernet" },
 148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
 149                 "Broadcom BCM5703 Gigabit Ethernet" },
 150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 151                 "Broadcom BCM5703X Gigabit Ethernet" },
 152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
 153                 "Broadcom BCM5703 Gigabit Ethernet" },
 154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 155                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 157                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
 159                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 161                 "Broadcom BCM5705 Gigabit Ethernet" },
 162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
 163                 "Broadcom BCM5705F Gigabit Ethernet" },
 164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
 165                 "Broadcom BCM5705K Gigabit Ethernet" },
 166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 167                 "Broadcom BCM5705M Gigabit Ethernet" },
 168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
 169                 "Broadcom BCM5705M Gigabit Ethernet" },
 170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
 171                 "Broadcom BCM5714C Gigabit Ethernet" },
 172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
 173                 "Broadcom BCM5714S Gigabit Ethernet" },
 174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
 175                 "Broadcom BCM5715 Gigabit Ethernet" },
 176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
 177                 "Broadcom BCM5715S Gigabit Ethernet" },
 178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
 179                 "Broadcom BCM5720 Gigabit Ethernet" },
 180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
 181                 "Broadcom BCM5721 Gigabit Ethernet" },
 182         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
 183                 "Broadcom BCM5722 Gigabit Ethernet" },
 184         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
 185                 "Broadcom BCM5750 Gigabit Ethernet" },
 186         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
 187                 "Broadcom BCM5750M Gigabit Ethernet" },
 188         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
 189                 "Broadcom BCM5751 Gigabit Ethernet" },
 190         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
 191                 "Broadcom BCM5751F Gigabit Ethernet" },
 192         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
 193                 "Broadcom BCM5751M Gigabit Ethernet" },
 194         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
 195                 "Broadcom BCM5752 Gigabit Ethernet" },
 196         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
 197                 "Broadcom BCM5752M Gigabit Ethernet" },
 198         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
 199                 "Broadcom BCM5753 Gigabit Ethernet" },
 200         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
 201                 "Broadcom BCM5753F Gigabit Ethernet" },
 202         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
 203                 "Broadcom BCM5753M Gigabit Ethernet" },
 204         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
 205                 "Broadcom BCM5754 Gigabit Ethernet" },
 206         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
 207                 "Broadcom BCM5754M Gigabit Ethernet" },
 208         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
 209                 "Broadcom BCM5755 Gigabit Ethernet" },
 210         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
 211                 "Broadcom BCM5755M Gigabit Ethernet" },
 212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
 213                 "Broadcom BCM5756 Gigabit Ethernet" },
 214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
 215                 "Broadcom BCM5780 Gigabit Ethernet" },
 216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
 217                 "Broadcom BCM5780S Gigabit Ethernet" },
 218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
 219                 "Broadcom BCM5781 Gigabit Ethernet" },
 220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 221                 "Broadcom BCM5782 Gigabit Ethernet" },
 222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
 223                 "Broadcom BCM5786 Gigabit Ethernet" },
 224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
 225                 "Broadcom BCM5787 Gigabit Ethernet" },
 226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
 227                 "Broadcom BCM5787F Gigabit Ethernet" },
 228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
 229                 "Broadcom BCM5787M Gigabit Ethernet" },
 230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
 231                 "Broadcom BCM5788 Gigabit Ethernet" },
 232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
 233                 "Broadcom BCM5789 Gigabit Ethernet" },
 234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 235                 "Broadcom BCM5901 Fast Ethernet" },
 236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 237                 "Broadcom BCM5901A2 Fast Ethernet" },
 238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
 239                 "Broadcom BCM5903M Fast Ethernet" },
 240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
 241                 "Broadcom BCM5906 Fast Ethernet"},
 242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
 243                 "Broadcom BCM5906M Fast Ethernet"},
 244
 245         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 246                 "SysKonnect Gigabit Ethernet" },
 247
 248         { 0, 0, NULL }
 249 };
 250
 251 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 252 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 253 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 254 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 255 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 256
 257 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 258
 259 static int      bge_probe(device_t);
 260 static int      bge_attach(device_t);
 261 static int      bge_detach(device_t);
 262 static void     bge_txeof(struct bge_softc *);
 263 static void     bge_rxeof(struct bge_softc *);
 264
 265 static void     bge_tick(void *);
 266 static void     bge_stats_update(struct bge_softc *);
 267 static void     bge_stats_update_regs(struct bge_softc *);
 268 static int      bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 269
 270 #ifdef DEVICE_POLLING
 271 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 272 #endif
 273 static void     bge_intr(void *);
 274 static void     bge_enable_intr(struct bge_softc *);
 275 static void     bge_disable_intr(struct bge_softc *);
 276 static void     bge_start(struct ifnet *);
 277 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 278 static void     bge_init(void *);
 279 static void     bge_stop(struct bge_softc *);
 280 static void     bge_watchdog(struct ifnet *);
 281 static void     bge_shutdown(device_t);
 282 static int      bge_suspend(device_t);
 283 static int      bge_resume(device_t);
 284 static int      bge_ifmedia_upd(struct ifnet *);
 285 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 286
 287 static uint8_t  bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 288 static int      bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 289
 290 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 291 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 292
 293 static void     bge_setmulti(struct bge_softc *);
 294 static void     bge_setpromisc(struct bge_softc *);
 295
 296 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 297 static void     bge_free_jumbo_mem(struct bge_softc *);
 298 static struct bge_jslot
 299                 *bge_jalloc(struct bge_softc *);
 300 static void     bge_jfree(void *);
 301 static void     bge_jref(void *);
 302 static int      bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
 303 static int      bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
 304 static int      bge_init_rx_ring_std(struct bge_softc *);
 305 static void     bge_free_rx_ring_std(struct bge_softc *);
 306 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 307 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 308 static void     bge_free_tx_ring(struct bge_softc *);
 309 static int      bge_init_tx_ring(struct bge_softc *);
 310
 311 static int      bge_chipinit(struct bge_softc *);
 312 static int      bge_blockinit(struct bge_softc *);
 313
 314 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 315 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 316 #ifdef notdef
 317 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 318 #endif
 319 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 320 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
 321 static void     bge_writembx(struct bge_softc *, int, int);
 322
 323 static int      bge_miibus_readreg(device_t, int, int);
 324 static int      bge_miibus_writereg(device_t, int, int, int);
 325 static void     bge_miibus_statchg(device_t);
 326 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
 327 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
 328 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
 329
 330 static void     bge_reset(struct bge_softc *);
 331
 332 static void     bge_dma_map_mbuf(void *, bus_dma_segment_t *, int,
 333                                  bus_size_t, int);
 334 static int      bge_dma_alloc(struct bge_softc *);
 335 static void     bge_dma_free(struct bge_softc *);
 336 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
 337                                     bus_dma_tag_t *, bus_dmamap_t *,
 338                                     void **, bus_addr_t *);
 339 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 340
 341 static int      bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 342 static int      bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 343 static int      bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 344 static int      bge_get_eaddr(struct bge_softc *, uint8_t[]);
 345
 346 static void     bge_coal_change(struct bge_softc *);
 347 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 348 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 349 static int      bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 350 static int      bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 351 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
 352
 353 /*
 354  * Set following tunable to 1 for some IBM blade servers with the DNLK
 355  * switch module. Auto negotiation is broken for those configurations.
 356  */
 357 static int      bge_fake_autoneg = 0;
 358 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
 359
 360 /* Interrupt moderation control variables. */
 361 static int      bge_rx_coal_ticks = 100;        /* usec */
 362 static int      bge_tx_coal_ticks = 1023;       /* usec */
 363 static int      bge_rx_max_coal_bds = 80;
 364 static int      bge_tx_max_coal_bds = 128;
 365
 366 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
 367 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
 368 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
 369 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
 370
 371 #if !defined(KTR_IF_BGE)
 372 #define KTR_IF_BGE      KTR_ALL
 373 #endif
 374 KTR_INFO_MASTER(if_bge);
 375 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr", 0);
 376 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt", 0);
 377 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt", 0);
 378 #define logif(name)     KTR_LOG(if_bge_ ## name)
 379
 380 static device_method_t bge_methods[] = {
 381         /* Device interface */
 382         DEVMETHOD(device_probe,         bge_probe),
 383         DEVMETHOD(device_attach,        bge_attach),
 384         DEVMETHOD(device_detach,        bge_detach),
 385         DEVMETHOD(device_shutdown,      bge_shutdown),
 386         DEVMETHOD(device_suspend,       bge_suspend),
 387         DEVMETHOD(device_resume,        bge_resume),
 388
 389         /* bus interface */
 390         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 391         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 392
 393         /* MII interface */
 394         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 395         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 396         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 397
 398         { 0, 0 }
 399 };
 400
 401 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 402 static devclass_t bge_devclass;
 403
 404 DECLARE_DUMMY_MODULE(if_bge);
 405 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
 406 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 407
 408 static uint32_t
 409 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 410 {
 411         device_t dev = sc->bge_dev;
 412         uint32_t val;
 413
 414         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 415         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 416         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 417         return (val);
 418 }
 419
 420 static void
 421 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 422 {
 423         device_t dev = sc->bge_dev;
 424
 425         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 426         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 427         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 428 }
 429
 430 #ifdef notdef
 431 static uint32_t
 432 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 433 {
 434         device_t dev = sc->bge_dev;
 435
 436         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 437         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 438 }
 439 #endif
 440
 441 static void
 442 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 443 {
 444         device_t dev = sc->bge_dev;
 445
 446         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 447         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 448 }
 449
 450 static void
 451 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
 452 {
 453         CSR_WRITE_4(sc, off, val);
 454 }
 455
 456 static void
 457 bge_writembx(struct bge_softc *sc, int off, int val)
 458 {
 459         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 460                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 461
 462         CSR_WRITE_4(sc, off, val);
 463 }
 464
 465 static uint8_t
 466 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 467 {
 468         uint32_t access, byte = 0;
 469         int i;
 470
 471         /* Lock. */
 472         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 473         for (i = 0; i < 8000; i++) {
 474                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 475                         break;
 476                 DELAY(20);
 477         }
 478         if (i == 8000)
 479                 return (1);
 480
 481         /* Enable access. */
 482         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 483         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 484
 485         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 486         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 487         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 488                 DELAY(10);
 489                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 490                         DELAY(10);
 491                         break;
 492                 }
 493         }
 494
 495         if (i == BGE_TIMEOUT * 10) {
 496                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
 497                 return (1);
 498         }
 499
 500         /* Get result. */
 501         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 502
 503         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 504
 505         /* Disable access. */
 506         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 507
 508         /* Unlock. */
 509         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 510         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 511
 512         return (0);
 513 }
 514
 515 /*
 516  * Read a sequence of bytes from NVRAM.
 517  */
 518 static int
 519 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 520 {
 521         int err = 0, i;
 522         uint8_t byte = 0;
 523
 524         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 525                 return (1);
 526
 527         for (i = 0; i < cnt; i++) {
 528                 err = bge_nvram_getbyte(sc, off + i, &byte);
 529                 if (err)
 530                         break;
 531                 *(dest + i) = byte;
 532         }
 533
 534         return (err ? 1 : 0);
 535 }
 536
 537 /*
 538  * Read a byte of data stored in the EEPROM at address 'addr.' The
 539  * BCM570x supports both the traditional bitbang interface and an
 540  * auto access interface for reading the EEPROM. We use the auto
 541  * access method.
 542  */
 543 static uint8_t
 544 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 545 {
 546         int i;
 547         uint32_t byte = 0;
 548
 549         /*
 550          * Enable use of auto EEPROM access so we can avoid
 551          * having to use the bitbang method.
 552          */
 553         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 554
 555         /* Reset the EEPROM, load the clock period. */
 556         CSR_WRITE_4(sc, BGE_EE_ADDR,
 557             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 558         DELAY(20);
 559
 560         /* Issue the read EEPROM command. */
 561         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 562
 563         /* Wait for completion */
 564         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 565                 DELAY(10);
 566                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 567                         break;
 568         }
 569
 570         if (i == BGE_TIMEOUT) {
 571                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 572                 return(1);
 573         }
 574
 575         /* Get result. */
 576         byte = CSR_READ_4(sc, BGE_EE_DATA);
 577
 578         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 579
 580         return(0);
 581 }
 582
 583 /*
 584  * Read a sequence of bytes from the EEPROM.
 585  */
 586 static int
 587 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 588 {
 589         size_t i;
 590         int err;
 591         uint8_t byte;
 592
 593         for (byte = 0, err = 0, i = 0; i < len; i++) {
 594                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 595                 if (err)
 596                         break;
 597                 *(dest + i) = byte;
 598         }
 599
 600         return(err ? 1 : 0);
 601 }
 602
 603 static int
 604 bge_miibus_readreg(device_t dev, int phy, int reg)
 605 {
 606         struct bge_softc *sc = device_get_softc(dev);
 607         struct ifnet *ifp = &sc->arpcom.ac_if;
 608         uint32_t val, autopoll;
 609         int i;
 610
 611         /*
 612          * Broadcom's own driver always assumes the internal
 613          * PHY is at GMII address 1. On some chips, the PHY responds
 614          * to accesses at all addresses, which could cause us to
 615          * bogusly attach the PHY 32 times at probe type. Always
 616          * restricting the lookup to address 1 is simpler than
 617          * trying to figure out which chips revisions should be
 618          * special-cased.
 619          */
 620         if (phy != 1)
 621                 return(0);
 622
 623         /* Reading with autopolling on may trigger PCI errors */
 624         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 625         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 626                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 627                 DELAY(40);
 628         }
 629
 630         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
 631             BGE_MIPHY(phy)|BGE_MIREG(reg));
 632
 633         for (i = 0; i < BGE_TIMEOUT; i++) {
 634                 DELAY(10);
 635                 val = CSR_READ_4(sc, BGE_MI_COMM);
 636                 if (!(val & BGE_MICOMM_BUSY))
 637                         break;
 638         }
 639
 640         if (i == BGE_TIMEOUT) {
 641                 if_printf(ifp, "PHY read timed out "
 642                           "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 643                 val = 0;
 644                 goto done;
 645         }
 646
 647         DELAY(5);
 648         val = CSR_READ_4(sc, BGE_MI_COMM);
 649
 650 done:
 651         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 652                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 653                 DELAY(40);
 654         }
 655
 656         if (val & BGE_MICOMM_READFAIL)
 657                 return(0);
 658
 659         return(val & 0xFFFF);
 660 }
 661
 662 static int
 663 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 664 {
 665         struct bge_softc *sc = device_get_softc(dev);
 666         uint32_t autopoll;
 667         int i;
 668
 669         /*
 670          * See the related comment in bge_miibus_readreg()
 671          */
 672         if (phy != 1)
 673                 return(0);
 674
 675         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 676             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 677                return(0);
 678
 679         /* Reading with autopolling on may trigger PCI errors */
 680         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 681         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 682                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 683                 DELAY(40);
 684         }
 685
 686         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
 687             BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
 688
 689         for (i = 0; i < BGE_TIMEOUT; i++) {
 690                 DELAY(10);
 691                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 692                         DELAY(5);
 693                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 694                         break;
 695                 }
 696         }
 697
 698         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 699                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 700                 DELAY(40);
 701         }
 702
 703         if (i == BGE_TIMEOUT) {
 704                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 705                           "(phy %d, reg %d, val %d)\n", phy, reg, val);
 706                 return(0);
 707         }
 708
 709         return(0);
 710 }
 711
 712 static void
 713 bge_miibus_statchg(device_t dev)
 714 {
 715         struct bge_softc *sc;
 716         struct mii_data *mii;
 717
 718         sc = device_get_softc(dev);
 719         mii = device_get_softc(sc->bge_miibus);
 720
 721         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 722         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
 723                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 724         } else {
 725                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 726         }
 727
 728         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 729                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 730         } else {
 731                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 732         }
 733 }
 734
 735 /*
 736  * Memory management for jumbo frames.
 737  */
 738 static int
 739 bge_alloc_jumbo_mem(struct bge_softc *sc)
 740 {
 741         struct ifnet *ifp = &sc->arpcom.ac_if;
 742         struct bge_jslot *entry;
 743         uint8_t *ptr;
 744         bus_addr_t paddr;
 745         int i, error;
 746
 747         /*
 748          * Create tag for jumbo mbufs.
 749          * This is really a bit of a kludge. We allocate a special
 750          * jumbo buffer pool which (thanks to the way our DMA
 751          * memory allocation works) will consist of contiguous
 752          * pages. This means that even though a jumbo buffer might
 753          * be larger than a page size, we don't really need to
 754          * map it into more than one DMA segment. However, the
 755          * default mbuf tag will result in multi-segment mappings,
 756          * so we have to create a special jumbo mbuf tag that
 757          * lets us get away with mapping the jumbo buffers as
 758          * a single segment. I think eventually the driver should
 759          * be changed so that it uses ordinary mbufs and cluster
 760          * buffers, i.e. jumbo frames can span multiple DMA
 761          * descriptors. But that's a project for another day.
 762          */
 763
 764         /*
 765          * Create DMA stuffs for jumbo RX ring.
 766          */
 767         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 768                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
 769                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
 770                                     (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
 771                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
 772         if (error) {
 773                 if_printf(ifp, "could not create jumbo RX ring\n");
 774                 return error;
 775         }
 776
 777         /*
 778          * Create DMA stuffs for jumbo buffer block.
 779          */
 780         error = bge_dma_block_alloc(sc, BGE_JMEM,
 781                                     &sc->bge_cdata.bge_jumbo_tag,
 782                                     &sc->bge_cdata.bge_jumbo_map,
 783                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
 784                                     &paddr);
 785         if (error) {
 786                 if_printf(ifp, "could not create jumbo buffer\n");
 787                 return error;
 788         }
 789
 790         SLIST_INIT(&sc->bge_jfree_listhead);
 791
 792         /*
 793          * Now divide it up into 9K pieces and save the addresses
 794          * in an array. Note that we play an evil trick here by using
 795          * the first few bytes in the buffer to hold the the address
 796          * of the softc structure for this interface. This is because
 797          * bge_jfree() needs it, but it is called by the mbuf management
 798          * code which will not pass it to us explicitly.
 799          */
 800         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
 801                 entry = &sc->bge_cdata.bge_jslots[i];
 802                 entry->bge_sc = sc;
 803                 entry->bge_buf = ptr;
 804                 entry->bge_paddr = paddr;
 805                 entry->bge_inuse = 0;
 806                 entry->bge_slot = i;
 807                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 808
 809                 ptr += BGE_JLEN;
 810                 paddr += BGE_JLEN;
 811         }
 812         return 0;
 813 }
 814
 815 static void
 816 bge_free_jumbo_mem(struct bge_softc *sc)
 817 {
 818         /* Destroy jumbo RX ring. */
 819         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 820                            sc->bge_cdata.bge_rx_jumbo_ring_map,
 821                            sc->bge_ldata.bge_rx_jumbo_ring);
 822
 823         /* Destroy jumbo buffer block. */
 824         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
 825                            sc->bge_cdata.bge_jumbo_map,
 826                            sc->bge_ldata.bge_jumbo_buf);
 827 }
 828
 829 /*
 830  * Allocate a jumbo buffer.
 831  */
 832 static struct bge_jslot *
 833 bge_jalloc(struct bge_softc *sc)
 834 {
 835         struct bge_jslot *entry;
 836
 837         lwkt_serialize_enter(&sc->bge_jslot_serializer);
 838         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 839         if (entry) {
 840                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 841                 entry->bge_inuse = 1;
 842         } else {
 843                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 844         }
 845         lwkt_serialize_exit(&sc->bge_jslot_serializer);
 846         return(entry);
 847 }
 848
 849 /*
 850  * Adjust usage count on a jumbo buffer.
 851  */
 852 static void
 853 bge_jref(void *arg)
 854 {
 855         struct bge_jslot *entry = (struct bge_jslot *)arg;
 856         struct bge_softc *sc = entry->bge_sc;
 857
 858         if (sc == NULL)
 859                 panic("bge_jref: can't find softc pointer!");
 860
 861         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 862                 panic("bge_jref: asked to reference buffer "
 863                     "that we don't manage!");
 864         } else if (entry->bge_inuse == 0) {
 865                 panic("bge_jref: buffer already free!");
 866         } else {
 867                 atomic_add_int(&entry->bge_inuse, 1);
 868         }
 869 }
 870
 871 /*
 872  * Release a jumbo buffer.
 873  */
 874 static void
 875 bge_jfree(void *arg)
 876 {
 877         struct bge_jslot *entry = (struct bge_jslot *)arg;
 878         struct bge_softc *sc = entry->bge_sc;
 879
 880         if (sc == NULL)
 881                 panic("bge_jfree: can't find softc pointer!");
 882
 883         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 884                 panic("bge_jfree: asked to free buffer that we don't manage!");
 885         } else if (entry->bge_inuse == 0) {
 886                 panic("bge_jfree: buffer already free!");
 887         } else {
 888                 /*
 889                  * Possible MP race to 0, use the serializer.  The atomic insn
 890                  * is still needed for races against bge_jref().
 891                  */
 892                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
 893                 atomic_subtract_int(&entry->bge_inuse, 1);
 894                 if (entry->bge_inuse == 0) {
 895                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
 896                                           entry, jslot_link);
 897                 }
 898                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
 899         }
 900 }
 901
 902
 903 /*
 904  * Intialize a standard receive ring descriptor.
 905  */
 906 static int
 907 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
 908 {
 909         struct mbuf *m_new = NULL;
 910         struct bge_dmamap_arg ctx;
 911         bus_dma_segment_t seg;
 912         struct bge_rx_bd *r;
 913         int error;
 914
 915         if (m == NULL) {
 916                 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
 917                 if (m_new == NULL)
 918                         return ENOBUFS;
 919         } else {
 920                 m_new = m;
 921                 m_new->m_data = m_new->m_ext.ext_buf;
 922         }
 923         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 924
 925         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 926                 m_adj(m_new, ETHER_ALIGN);
 927
 928         ctx.bge_maxsegs = 1;
 929         ctx.bge_segs = &seg;
 930         error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag,
 931                                      sc->bge_cdata.bge_rx_std_dmamap[i],
 932                                      m_new, bge_dma_map_mbuf, &ctx,
 933                                      BUS_DMA_NOWAIT);
 934         if (error || ctx.bge_maxsegs == 0) {
 935                 if (!error) {
 936                         if_printf(&sc->arpcom.ac_if, "too many segments?!\n");
 937                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
 938                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
 939                 }
 940                 if (m == NULL)
 941                         m_freem(m_new);
 942                 return ENOMEM;
 943         }
 944
 945         sc->bge_cdata.bge_rx_std_chain[i] = m_new;
 946
 947         r = &sc->bge_ldata.bge_rx_std_ring[i];
 948         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[0].ds_addr);
 949         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[0].ds_addr);
 950         r->bge_flags = BGE_RXBDFLAG_END;
 951         r->bge_len = m_new->m_len;
 952         r->bge_idx = i;
 953
 954         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
 955                         sc->bge_cdata.bge_rx_std_dmamap[i],
 956                         BUS_DMASYNC_PREREAD);
 957         return 0;
 958 }
 959
 960 /*
 961  * Initialize a jumbo receive ring descriptor. This allocates
 962  * a jumbo buffer from the pool managed internally by the driver.
 963  */
 964 static int
 965 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
 966 {
 967         struct mbuf *m_new = NULL;
 968         struct bge_jslot *buf;
 969         struct bge_rx_bd *r;
 970         bus_addr_t paddr;
 971
 972         if (m == NULL) {
 973                 /* Allocate the mbuf. */
 974                 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
 975                 if (m_new == NULL)
 976                         return(ENOBUFS);
 977
 978                 /* Allocate the jumbo buffer */
 979                 buf = bge_jalloc(sc);
 980                 if (buf == NULL) {
 981                         m_freem(m_new);
 982                         if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
 983                             "-- packet dropped!\n");
 984                         return ENOBUFS;
 985                 }
 986
 987                 /* Attach the buffer to the mbuf. */
 988                 m_new->m_ext.ext_arg = buf;
 989                 m_new->m_ext.ext_buf = buf->bge_buf;
 990                 m_new->m_ext.ext_free = bge_jfree;
 991                 m_new->m_ext.ext_ref = bge_jref;
 992                 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 993
 994                 m_new->m_flags |= M_EXT;
 995         } else {
 996                 KKASSERT(m->m_flags & M_EXT);
 997                 m_new = m;
 998                 buf = m_new->m_ext.ext_arg;
 999         }
1000         m_new->m_data = m_new->m_ext.ext_buf;
1001         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1002
1003         paddr = buf->bge_paddr;
1004         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1005                 m_adj(m_new, ETHER_ALIGN);
1006                 paddr += ETHER_ALIGN;
1007         }
1008
1009         /* Set up the descriptor. */
1010         sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
1011
1012         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1013         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(paddr);
1014         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(paddr);
1015         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1016         r->bge_len = m_new->m_len;
1017         r->bge_idx = i;
1018
1019         return 0;
1020 }
1021
1022 /*
1023  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1024  * that's 1MB or memory, which is a lot. For now, we fill only the first
1025  * 256 ring entries and hope that our CPU is fast enough to keep up with
1026  * the NIC.
1027  */
1028 static int
1029 bge_init_rx_ring_std(struct bge_softc *sc)
1030 {
1031         int i;
1032
1033         for (i = 0; i < BGE_SSLOTS; i++) {
1034                 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
1035                         return(ENOBUFS);
1036         };
1037
1038         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1039                         sc->bge_cdata.bge_rx_std_ring_map,
1040                         BUS_DMASYNC_PREWRITE);
1041
1042         sc->bge_std = i - 1;
1043         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1044
1045         return(0);
1046 }
1047
1048 static void
1049 bge_free_rx_ring_std(struct bge_softc *sc)
1050 {
1051         int i;
1052
1053         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1054                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1055                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1056                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
1057                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1058                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1059                 }
1060                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1061                     sizeof(struct bge_rx_bd));
1062         }
1063 }
1064
1065 static int
1066 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1067 {
1068         int i;
1069         struct bge_rcb *rcb;
1070
1071         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1072                 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1073                         return(ENOBUFS);
1074         };
1075
1076         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1077                         sc->bge_cdata.bge_rx_jumbo_ring_map,
1078                         BUS_DMASYNC_PREWRITE);
1079
1080         sc->bge_jumbo = i - 1;
1081
1082         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1083         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1084         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1085
1086         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1087
1088         return(0);
1089 }
1090
1091 static void
1092 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1093 {
1094         int i;
1095
1096         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1097                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1098                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1099                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1100                 }
1101                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1102                     sizeof(struct bge_rx_bd));
1103         }
1104 }
1105
1106 static void
1107 bge_free_tx_ring(struct bge_softc *sc)
1108 {
1109         int i;
1110
1111         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1112                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1113                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1114                                           sc->bge_cdata.bge_tx_dmamap[i]);
1115                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1116                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1117                 }
1118                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1119                     sizeof(struct bge_tx_bd));
1120         }
1121 }
1122
1123 static int
1124 bge_init_tx_ring(struct bge_softc *sc)
1125 {
1126         sc->bge_txcnt = 0;
1127         sc->bge_tx_saved_considx = 0;
1128         sc->bge_tx_prodidx = 0;
1129
1130         /* Initialize transmit producer index for host-memory send ring. */
1131         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1132
1133         /* 5700 b2 errata */
1134         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1135                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1136
1137         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1138         /* 5700 b2 errata */
1139         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1140                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1141
1142         return(0);
1143 }
1144
1145 static void
1146 bge_setmulti(struct bge_softc *sc)
1147 {
1148         struct ifnet *ifp;
1149         struct ifmultiaddr *ifma;
1150         uint32_t hashes[4] = { 0, 0, 0, 0 };
1151         int h, i;
1152
1153         ifp = &sc->arpcom.ac_if;
1154
1155         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1156                 for (i = 0; i < 4; i++)
1157                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1158                 return;
1159         }
1160
1161         /* First, zot all the existing filters. */
1162         for (i = 0; i < 4; i++)
1163                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1164
1165         /* Now program new ones. */
1166         LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1167                 if (ifma->ifma_addr->sa_family != AF_LINK)
1168                         continue;
1169                 h = ether_crc32_le(
1170                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1171                     ETHER_ADDR_LEN) & 0x7f;
1172                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1173         }
1174
1175         for (i = 0; i < 4; i++)
1176                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1177 }
1178
1179 /*
1180  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1181  * self-test results.
1182  */
1183 static int
1184 bge_chipinit(struct bge_softc *sc)
1185 {
1186         int i;
1187         uint32_t dma_rw_ctl;
1188
1189         /* Set endian type before we access any non-PCI registers. */
1190         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1191
1192         /* Clear the MAC control register */
1193         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1194
1195         /*
1196          * Clear the MAC statistics block in the NIC's
1197          * internal memory.
1198          */
1199         for (i = BGE_STATS_BLOCK;
1200             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1201                 BGE_MEMWIN_WRITE(sc, i, 0);
1202
1203         for (i = BGE_STATUS_BLOCK;
1204             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1205                 BGE_MEMWIN_WRITE(sc, i, 0);
1206
1207         /* Set up the PCI DMA control register. */
1208         if (sc->bge_flags & BGE_FLAG_PCIE) {
1209                 /* PCI Express */
1210                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1211                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1212                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1213         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1214                 /* PCI-X bus */
1215                 if (BGE_IS_5714_FAMILY(sc)) {
1216                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1217                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1218                         /* XXX magic values, Broadcom-supplied Linux driver */
1219                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1220                                 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1221                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1222                         } else {
1223                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1224                         }
1225                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1226                         /*
1227                          * The 5704 uses a different encoding of read/write
1228                          * watermarks.
1229                          */
1230                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1231                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1232                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1233                 } else {
1234                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1235                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1236                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1237                             (0x0F);
1238                 }
1239
1240                 /*
1241                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1242                  * for hardware bugs.
1243                  */
1244                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1245                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1246                         uint32_t tmp;
1247
1248                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1249                         if (tmp == 0x6 || tmp == 0x7)
1250                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1251                 }
1252         } else {
1253                 /* Conventional PCI bus */
1254                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1255                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1256                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1257                     (0x0F);
1258         }
1259
1260         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1261             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1262             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1263                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1264         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1265
1266         /*
1267          * Set up general mode register.
1268          */
1269         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1270             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1271             BGE_MODECTL_TX_NO_PHDR_CSUM);
1272
1273         /*
1274          * Disable memory write invalidate.  Apparently it is not supported
1275          * properly by these devices.
1276          */
1277         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1278
1279         /* Set the timer prescaler (always 66Mhz) */
1280         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1281
1282         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1283                 DELAY(40);      /* XXX */
1284
1285                 /* Put PHY into ready state */
1286                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1287                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1288                 DELAY(40);
1289         }
1290
1291         return(0);
1292 }
1293
1294 static int
1295 bge_blockinit(struct bge_softc *sc)
1296 {
1297         struct bge_rcb *rcb;
1298         bus_size_t vrcb;
1299         bge_hostaddr taddr;
1300         uint32_t val;
1301         int i;
1302
1303         /*
1304          * Initialize the memory window pointer register so that
1305          * we can access the first 32K of internal NIC RAM. This will
1306          * allow us to set up the TX send ring RCBs and the RX return
1307          * ring RCBs, plus other things which live in NIC memory.
1308          */
1309         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1310
1311         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1312
1313         if (!BGE_IS_5705_PLUS(sc)) {
1314                 /* Configure mbuf memory pool */
1315                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1316                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1317                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1318                 else
1319                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1320
1321                 /* Configure DMA resource pool */
1322                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1323                     BGE_DMA_DESCRIPTORS);
1324                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1325         }
1326
1327         /* Configure mbuf pool watermarks */
1328         if (!BGE_IS_5705_PLUS(sc)) {
1329                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1330                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1331                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1332         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1333                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1334                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1335                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1336         } else {
1337                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1338                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1339                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1340         }
1341
1342         /* Configure DMA resource watermarks */
1343         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1344         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1345
1346         /* Enable buffer manager */
1347         if (!BGE_IS_5705_PLUS(sc)) {
1348                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1349                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1350
1351                 /* Poll for buffer manager start indication */
1352                 for (i = 0; i < BGE_TIMEOUT; i++) {
1353                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1354                                 break;
1355                         DELAY(10);
1356                 }
1357
1358                 if (i == BGE_TIMEOUT) {
1359                         if_printf(&sc->arpcom.ac_if,
1360                                   "buffer manager failed to start\n");
1361                         return(ENXIO);
1362                 }
1363         }
1364
1365         /* Enable flow-through queues */
1366         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1367         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1368
1369         /* Wait until queue initialization is complete */
1370         for (i = 0; i < BGE_TIMEOUT; i++) {
1371                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1372                         break;
1373                 DELAY(10);
1374         }
1375
1376         if (i == BGE_TIMEOUT) {
1377                 if_printf(&sc->arpcom.ac_if,
1378                           "flow-through queue init failed\n");
1379                 return(ENXIO);
1380         }
1381
1382         /* Initialize the standard RX ring control block */
1383         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1384         rcb->bge_hostaddr.bge_addr_lo =
1385             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1386         rcb->bge_hostaddr.bge_addr_hi =
1387             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1388         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1389             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1390         if (BGE_IS_5705_PLUS(sc))
1391                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1392         else
1393                 rcb->bge_maxlen_flags =
1394                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1395         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1396         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1397         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1398         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1399         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1400
1401         /*
1402          * Initialize the jumbo RX ring control block
1403          * We set the 'ring disabled' bit in the flags
1404          * field until we're actually ready to start
1405          * using this ring (i.e. once we set the MTU
1406          * high enough to require it).
1407          */
1408         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1409                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1410
1411                 rcb->bge_hostaddr.bge_addr_lo =
1412                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1413                 rcb->bge_hostaddr.bge_addr_hi =
1414                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1415                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1416                     sc->bge_cdata.bge_rx_jumbo_ring_map,
1417                     BUS_DMASYNC_PREREAD);
1418                 rcb->bge_maxlen_flags =
1419                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1420                     BGE_RCB_FLAG_RING_DISABLED);
1421                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1422                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1423                     rcb->bge_hostaddr.bge_addr_hi);
1424                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1425                     rcb->bge_hostaddr.bge_addr_lo);
1426                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1427                     rcb->bge_maxlen_flags);
1428                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1429
1430                 /* Set up dummy disabled mini ring RCB */
1431                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1432                 rcb->bge_maxlen_flags =
1433                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1434                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1435                     rcb->bge_maxlen_flags);
1436         }
1437
1438         /*
1439          * Set the BD ring replentish thresholds. The recommended
1440          * values are 1/8th the number of descriptors allocated to
1441          * each ring.
1442          */
1443         if (BGE_IS_5705_PLUS(sc))
1444                 val = 8;
1445         else
1446                 val = BGE_STD_RX_RING_CNT / 8;
1447         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1448         CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1449
1450         /*
1451          * Disable all unused send rings by setting the 'ring disabled'
1452          * bit in the flags field of all the TX send ring control blocks.
1453          * These are located in NIC memory.
1454          */
1455         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1456         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1457                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1458                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1459                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1460                 vrcb += sizeof(struct bge_rcb);
1461         }
1462
1463         /* Configure TX RCB 0 (we use only the first ring) */
1464         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1465         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1466         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1467         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1468         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1469             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1470         if (!BGE_IS_5705_PLUS(sc)) {
1471                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1472                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1473         }
1474
1475         /* Disable all unused RX return rings */
1476         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1477         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1478                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1479                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1480                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1481                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1482                     BGE_RCB_FLAG_RING_DISABLED));
1483                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1484                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1485                     (i * (sizeof(uint64_t))), 0);
1486                 vrcb += sizeof(struct bge_rcb);
1487         }
1488
1489         /* Initialize RX ring indexes */
1490         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1491         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1492         bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1493
1494         /*
1495          * Set up RX return ring 0
1496          * Note that the NIC address for RX return rings is 0x00000000.
1497          * The return rings live entirely within the host, so the
1498          * nicaddr field in the RCB isn't used.
1499          */
1500         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1501         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1502         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1503         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1504         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1505         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1506             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1507
1508         /* Set random backoff seed for TX */
1509         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1510             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1511             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1512             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1513             BGE_TX_BACKOFF_SEED_MASK);
1514
1515         /* Set inter-packet gap */
1516         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1517
1518         /*
1519          * Specify which ring to use for packets that don't match
1520          * any RX rules.
1521          */
1522         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1523
1524         /*
1525          * Configure number of RX lists. One interrupt distribution
1526          * list, sixteen active lists, one bad frames class.
1527          */
1528         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1529
1530         /* Inialize RX list placement stats mask. */
1531         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1532         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1533
1534         /* Disable host coalescing until we get it set up */
1535         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1536
1537         /* Poll to make sure it's shut down. */
1538         for (i = 0; i < BGE_TIMEOUT; i++) {
1539                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1540                         break;
1541                 DELAY(10);
1542         }
1543
1544         if (i == BGE_TIMEOUT) {
1545                 if_printf(&sc->arpcom.ac_if,
1546                           "host coalescing engine failed to idle\n");
1547                 return(ENXIO);
1548         }
1549
1550         /* Set up host coalescing defaults */
1551         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1552         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1553         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1554         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1555         if (!BGE_IS_5705_PLUS(sc)) {
1556                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1557                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1558         }
1559         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1560         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1561
1562         /* Set up address of statistics block */
1563         if (!BGE_IS_5705_PLUS(sc)) {
1564                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1565                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1566                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1567                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1568
1569                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1570                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1571                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1572         }
1573
1574         /* Set up address of status block */
1575         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1576             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1577         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1578             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1579         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1580         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1581
1582         /* Turn on host coalescing state machine */
1583         CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1584
1585         /* Turn on RX BD completion state machine and enable attentions */
1586         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1587             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1588
1589         /* Turn on RX list placement state machine */
1590         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1591
1592         /* Turn on RX list selector state machine. */
1593         if (!BGE_IS_5705_PLUS(sc))
1594                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1595
1596         /* Turn on DMA, clear stats */
1597         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1598             BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1599             BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1600             BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1601             ((sc->bge_flags & BGE_FLAG_TBI) ?
1602              BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1603
1604         /* Set misc. local control, enable interrupts on attentions */
1605         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1606
1607 #ifdef notdef
1608         /* Assert GPIO pins for PHY reset */
1609         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1610             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1611         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1612             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1613 #endif
1614
1615         /* Turn on DMA completion state machine */
1616         if (!BGE_IS_5705_PLUS(sc))
1617                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1618
1619         /* Turn on write DMA state machine */
1620         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1621         if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1622             sc->bge_asicrev == BGE_ASICREV_BCM5787)
1623                 val |= (1 << 29);       /* Enable host coalescing bug fix. */
1624         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1625         DELAY(40);
1626
1627         /* Turn on read DMA state machine */
1628         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1629         if (sc->bge_flags & BGE_FLAG_PCIE)
1630                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1631         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1632         DELAY(40);
1633
1634         /* Turn on RX data completion state machine */
1635         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1636
1637         /* Turn on RX BD initiator state machine */
1638         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1639
1640         /* Turn on RX data and RX BD initiator state machine */
1641         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1642
1643         /* Turn on Mbuf cluster free state machine */
1644         if (!BGE_IS_5705_PLUS(sc))
1645                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1646
1647         /* Turn on send BD completion state machine */
1648         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1649
1650         /* Turn on send data completion state machine */
1651         CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1652
1653         /* Turn on send data initiator state machine */
1654         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1655
1656         /* Turn on send BD initiator state machine */
1657         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1658
1659         /* Turn on send BD selector state machine */
1660         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1661
1662         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1663         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1664             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1665
1666         /* ack/clear link change events */
1667         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1668             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1669             BGE_MACSTAT_LINK_CHANGED);
1670         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1671
1672         /* Enable PHY auto polling (for MII/GMII only) */
1673         if (sc->bge_flags & BGE_FLAG_TBI) {
1674                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1675         } else {
1676                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1677                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1678                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1679                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1680                             BGE_EVTENB_MI_INTERRUPT);
1681                 }
1682         }
1683
1684         /*
1685          * Clear any pending link state attention.
1686          * Otherwise some link state change events may be lost until attention
1687          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1688          * It's not necessary on newer BCM chips - perhaps enabling link
1689          * state change attentions implies clearing pending attention.
1690          */
1691         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1692             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1693             BGE_MACSTAT_LINK_CHANGED);
1694
1695         /* Enable link state change attentions. */
1696         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1697
1698         return(0);
1699 }
1700
1701 /*
1702  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1703  * against our list and return its name if we find a match. Note
1704  * that since the Broadcom controller contains VPD support, we
1705  * can get the device name string from the controller itself instead
1706  * of the compiled-in string. This is a little slow, but it guarantees
1707  * we'll always announce the right product name.
1708  */
1709 static int
1710 bge_probe(device_t dev)
1711 {
1712         const struct bge_type *t;
1713         uint16_t product, vendor;
1714
1715         product = pci_get_device(dev);
1716         vendor = pci_get_vendor(dev);
1717
1718         for (t = bge_devs; t->bge_name != NULL; t++) {
1719                 if (vendor == t->bge_vid && product == t->bge_did)
1720                         break;
1721         }
1722         if (t->bge_name == NULL)
1723                 return(ENXIO);
1724
1725         device_set_desc(dev, t->bge_name);
1726         if (pci_get_subvendor(dev) == PCI_VENDOR_DELL) {
1727                 struct bge_softc *sc = device_get_softc(dev);
1728                 sc->bge_flags |= BGE_FLAG_NO_3LED;
1729         }
1730         return(0);
1731 }
1732
1733 static int
1734 bge_attach(device_t dev)
1735 {
1736         struct ifnet *ifp;
1737         struct bge_softc *sc;
1738         uint32_t hwcfg = 0;
1739         int error = 0, rid;
1740         uint8_t ether_addr[ETHER_ADDR_LEN];
1741
1742         sc = device_get_softc(dev);
1743         sc->bge_dev = dev;
1744         callout_init(&sc->bge_stat_timer);
1745         lwkt_serialize_init(&sc->bge_jslot_serializer);
1746
1747 #ifndef BURN_BRIDGES
1748         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1749                 uint32_t irq, mem;
1750
1751                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1752                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1753
1754                 device_printf(dev, "chip is in D%d power mode "
1755                     "-- setting to D0\n", pci_get_powerstate(dev));
1756
1757                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1758
1759                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1760                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1761         }
1762 #endif  /* !BURN_BRIDGE */
1763
1764         /*
1765          * Map control/status registers.
1766          */
1767         pci_enable_busmaster(dev);
1768
1769         rid = BGE_PCI_BAR0;
1770         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1771             RF_ACTIVE);
1772
1773         if (sc->bge_res == NULL) {
1774                 device_printf(dev, "couldn't map memory\n");
1775                 return ENXIO;
1776         }
1777
1778         sc->bge_btag = rman_get_bustag(sc->bge_res);
1779         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1780
1781         /* Save various chip information */
1782         sc->bge_chipid =
1783             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1784             BGE_PCIMISCCTL_ASICREV;
1785         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1786         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1787
1788         /* Save chipset family. */
1789         switch (sc->bge_asicrev) {
1790         case BGE_ASICREV_BCM5700:
1791         case BGE_ASICREV_BCM5701:
1792         case BGE_ASICREV_BCM5703:
1793         case BGE_ASICREV_BCM5704:
1794                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1795                 break;
1796
1797         case BGE_ASICREV_BCM5714_A0:
1798         case BGE_ASICREV_BCM5780:
1799         case BGE_ASICREV_BCM5714:
1800                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1801                 /* Fall through */
1802
1803         case BGE_ASICREV_BCM5750:
1804         case BGE_ASICREV_BCM5752:
1805         case BGE_ASICREV_BCM5755:
1806         case BGE_ASICREV_BCM5787:
1807         case BGE_ASICREV_BCM5906:
1808                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1809                 /* Fall through */
1810
1811         case BGE_ASICREV_BCM5705:
1812                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1813                 break;
1814         }
1815
1816         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
1817                 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
1818
1819         /*
1820          * Set various quirk flags.
1821          */
1822
1823         sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1824         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1825             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1826              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1827               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1828             sc->bge_asicrev == BGE_ASICREV_BCM5906)
1829                 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1830
1831         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1832             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1833                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1834
1835         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1836             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1837                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1838
1839         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1840                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1841
1842         if (BGE_IS_5705_PLUS(sc)) {
1843                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1844                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1845                         uint32_t product = pci_get_device(dev);
1846
1847                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
1848                             product != PCI_PRODUCT_BROADCOM_BCM5756)
1849                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1850                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1851                                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1852                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1853                         sc->bge_flags |= BGE_FLAG_BER_BUG;
1854                 }
1855         }
1856
1857         /* Allocate interrupt */
1858         rid = 0;
1859
1860         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1861             RF_SHAREABLE | RF_ACTIVE);
1862
1863         if (sc->bge_irq == NULL) {
1864                 device_printf(dev, "couldn't map interrupt\n");
1865                 error = ENXIO;
1866                 goto fail;
1867         }
1868
1869         /*
1870          * Check if this is a PCI-X or PCI Express device.
1871          */
1872         if (BGE_IS_5705_PLUS(sc)) {
1873                 if (pci_is_pcie(dev)) {
1874                         sc->bge_flags |= BGE_FLAG_PCIE;
1875                         pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1876                 }
1877         } else {
1878                 /*
1879                  * Check if the device is in PCI-X Mode.
1880                  * (This bit is not valid on PCI Express controllers.)
1881                  */
1882                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1883                     BGE_PCISTATE_PCI_BUSMODE) == 0)
1884                         sc->bge_flags |= BGE_FLAG_PCIX;
1885         }
1886
1887         device_printf(dev, "CHIP ID 0x%08x; "
1888                       "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
1889                       sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
1890                       (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
1891                       : ((sc->bge_flags & BGE_FLAG_PCIE) ?
1892                         "PCI-E" : "PCI"));
1893
1894         ifp = &sc->arpcom.ac_if;
1895         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1896
1897         /* Try to reset the chip. */
1898         bge_reset(sc);
1899
1900         if (bge_chipinit(sc)) {
1901                 device_printf(dev, "chip initialization failed\n");
1902                 error = ENXIO;
1903                 goto fail;
1904         }
1905
1906         /*
1907          * Get station address
1908          */
1909         error = bge_get_eaddr(sc, ether_addr);
1910         if (error) {
1911                 device_printf(dev, "failed to read station address\n");
1912                 goto fail;
1913         }
1914
1915         /* 5705/5750 limits RX return ring to 512 entries. */
1916         if (BGE_IS_5705_PLUS(sc))
1917                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1918         else
1919                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1920
1921         error = bge_dma_alloc(sc);
1922         if (error)
1923                 goto fail;
1924
1925         /* Set default tuneable values. */
1926         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1927         sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
1928         sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
1929         sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
1930         sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
1931
1932         /* Set up ifnet structure */
1933         ifp->if_softc = sc;
1934         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1935         ifp->if_ioctl = bge_ioctl;
1936         ifp->if_start = bge_start;
1937 #ifdef DEVICE_POLLING
1938         ifp->if_poll = bge_poll;
1939 #endif
1940         ifp->if_watchdog = bge_watchdog;
1941         ifp->if_init = bge_init;
1942         ifp->if_mtu = ETHERMTU;
1943         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1944         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1945         ifq_set_ready(&ifp->if_snd);
1946
1947         /*
1948          * 5700 B0 chips do not support checksumming correctly due
1949          * to hardware bugs.
1950          */
1951         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
1952                 ifp->if_capabilities |= IFCAP_HWCSUM;
1953                 ifp->if_hwassist = BGE_CSUM_FEATURES;
1954         }
1955         ifp->if_capenable = ifp->if_capabilities;
1956
1957         /*
1958          * Figure out what sort of media we have by checking the
1959          * hardware config word in the first 32k of NIC internal memory,
1960          * or fall back to examining the EEPROM if necessary.
1961          * Note: on some BCM5700 cards, this value appears to be unset.
1962          * If that's the case, we have to rely on identifying the NIC
1963          * by its PCI subsystem ID, as we do below for the SysKonnect
1964          * SK-9D41.
1965          */
1966         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1967                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1968         else {
1969                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1970                                     sizeof(hwcfg))) {
1971                         device_printf(dev, "failed to read EEPROM\n");
1972                         error = ENXIO;
1973                         goto fail;
1974                 }
1975                 hwcfg = ntohl(hwcfg);
1976         }
1977
1978         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1979                 sc->bge_flags |= BGE_FLAG_TBI;
1980
1981         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1982         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1983                 sc->bge_flags |= BGE_FLAG_TBI;
1984
1985         if (sc->bge_flags & BGE_FLAG_TBI) {
1986                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1987                     bge_ifmedia_upd, bge_ifmedia_sts);
1988                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1989                 ifmedia_add(&sc->bge_ifmedia,
1990                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1991                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1992                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1993                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
1994         } else {
1995                 /*
1996                  * Do transceiver setup.
1997                  */
1998                 if (mii_phy_probe(dev, &sc->bge_miibus,
1999                     bge_ifmedia_upd, bge_ifmedia_sts)) {
2000                         device_printf(dev, "MII without any PHY!\n");
2001                         error = ENXIO;
2002                         goto fail;
2003                 }
2004         }
2005
2006         /*
2007          * When using the BCM5701 in PCI-X mode, data corruption has
2008          * been observed in the first few bytes of some received packets.
2009          * Aligning the packet buffer in memory eliminates the corruption.
2010          * Unfortunately, this misaligns the packet payloads.  On platforms
2011          * which do not support unaligned accesses, we will realign the
2012          * payloads by copying the received packets.
2013          */
2014         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2015             (sc->bge_flags & BGE_FLAG_PCIX))
2016                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2017
2018         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2019             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2020                 sc->bge_link_upd = bge_bcm5700_link_upd;
2021                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2022         } else if (sc->bge_flags & BGE_FLAG_TBI) {
2023                 sc->bge_link_upd = bge_tbi_link_upd;
2024                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2025         } else {
2026                 sc->bge_link_upd = bge_copper_link_upd;
2027                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2028         }
2029
2030         /*
2031          * Create sysctl nodes.
2032          */
2033         sysctl_ctx_init(&sc->bge_sysctl_ctx);
2034         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2035                                               SYSCTL_STATIC_CHILDREN(_hw),
2036                                               OID_AUTO,
2037                                               device_get_nameunit(dev),
2038                                               CTLFLAG_RD, 0, "");
2039         if (sc->bge_sysctl_tree == NULL) {
2040                 device_printf(dev, "can't add sysctl node\n");
2041                 error = ENXIO;
2042                 goto fail;
2043         }
2044
2045         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2046                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2047                         OID_AUTO, "rx_coal_ticks",
2048                         CTLTYPE_INT | CTLFLAG_RW,
2049                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
2050                         "Receive coalescing ticks (usec).");
2051         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2052                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2053                         OID_AUTO, "tx_coal_ticks",
2054                         CTLTYPE_INT | CTLFLAG_RW,
2055                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
2056                         "Transmit coalescing ticks (usec).");
2057         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2058                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2059                         OID_AUTO, "rx_max_coal_bds",
2060                         CTLTYPE_INT | CTLFLAG_RW,
2061                         sc, 0, bge_sysctl_rx_max_coal_bds, "I",
2062                         "Receive max coalesced BD count.");
2063         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2064                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2065                         OID_AUTO, "tx_max_coal_bds",
2066                         CTLTYPE_INT | CTLFLAG_RW,
2067                         sc, 0, bge_sysctl_tx_max_coal_bds, "I",
2068                         "Transmit max coalesced BD count.");
2069
2070         /*
2071          * Call MI attach routine.
2072          */
2073         ether_ifattach(ifp, ether_addr, NULL);
2074
2075         error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE,
2076                                bge_intr, sc, &sc->bge_intrhand,
2077                                ifp->if_serializer);
2078         if (error) {
2079                 ether_ifdetach(ifp);
2080                 device_printf(dev, "couldn't set up irq\n");
2081                 goto fail;
2082         }
2083
2084         ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bge_irq));
2085         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2086
2087         return(0);
2088 fail:
2089         bge_detach(dev);
2090         return(error);
2091 }
2092
2093 static int
2094 bge_detach(device_t dev)
2095 {
2096         struct bge_softc *sc = device_get_softc(dev);
2097
2098         if (device_is_attached(dev)) {
2099                 struct ifnet *ifp = &sc->arpcom.ac_if;
2100
2101                 lwkt_serialize_enter(ifp->if_serializer);
2102                 bge_stop(sc);
2103                 bge_reset(sc);
2104                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2105                 lwkt_serialize_exit(ifp->if_serializer);
2106
2107                 ether_ifdetach(ifp);
2108         }
2109
2110         if (sc->bge_flags & BGE_FLAG_TBI)
2111                 ifmedia_removeall(&sc->bge_ifmedia);
2112         if (sc->bge_miibus)
2113                 device_delete_child(dev, sc->bge_miibus);
2114         bus_generic_detach(dev);
2115
2116         if (sc->bge_irq != NULL)
2117                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2118
2119         if (sc->bge_res != NULL)
2120                 bus_release_resource(dev, SYS_RES_MEMORY,
2121                     BGE_PCI_BAR0, sc->bge_res);
2122
2123         if (sc->bge_sysctl_tree != NULL)
2124                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2125
2126         bge_dma_free(sc);
2127
2128         return 0;
2129 }
2130
2131 static void
2132 bge_reset(struct bge_softc *sc)
2133 {
2134         device_t dev;
2135         uint32_t cachesize, command, pcistate, reset;
2136         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2137         int i, val = 0;
2138
2139         dev = sc->bge_dev;
2140
2141         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2142             sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2143                 if (sc->bge_flags & BGE_FLAG_PCIE)
2144                         write_op = bge_writemem_direct;
2145                 else
2146                         write_op = bge_writemem_ind;
2147         } else {
2148                 write_op = bge_writereg_ind;
2149         }
2150
2151         /* Save some important PCI state. */
2152         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2153         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2154         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2155
2156         pci_write_config(dev, BGE_PCI_MISC_CTL,
2157             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2158             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2159
2160         /* Disable fastboot on controllers that support it. */
2161         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2162             sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2163             sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2164                 if (bootverbose)
2165                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2166                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2167         }
2168
2169         /*
2170          * Write the magic number to SRAM at offset 0xB50.
2171          * When firmware finishes its initialization it will
2172          * write ~BGE_MAGIC_NUMBER to the same location.
2173          */
2174         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2175
2176         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2177
2178         /* XXX: Broadcom Linux driver. */
2179         if (sc->bge_flags & BGE_FLAG_PCIE) {
2180                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
2181                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
2182                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2183                         /* Prevent PCIE link training during global reset */
2184                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2185                         reset |= (1<<29);
2186                 }
2187         }
2188
2189         /*
2190          * Set GPHY Power Down Override to leave GPHY
2191          * powered up in D0 uninitialized.
2192          */
2193         if (BGE_IS_5705_PLUS(sc))
2194                 reset |= 0x04000000;
2195
2196         /* Issue global reset */
2197         write_op(sc, BGE_MISC_CFG, reset);
2198
2199         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2200                 uint32_t status, ctrl;
2201
2202                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2203                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2204                     status | BGE_VCPU_STATUS_DRV_RESET);
2205                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2206                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2207                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2208         }
2209
2210         DELAY(1000);
2211
2212         /* XXX: Broadcom Linux driver. */
2213         if (sc->bge_flags & BGE_FLAG_PCIE) {
2214                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2215                         uint32_t v;
2216
2217                         DELAY(500000); /* wait for link training to complete */
2218                         v = pci_read_config(dev, 0xc4, 4);
2219                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2220                 }
2221                 /*
2222                  * Set PCIE max payload size to 128 bytes and
2223                  * clear error status.
2224                  */
2225                 pci_write_config(dev, 0xd8, 0xf5000, 4);
2226         }
2227
2228         /* Reset some of the PCI state that got zapped by reset */
2229         pci_write_config(dev, BGE_PCI_MISC_CTL,
2230             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2231             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2232         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2233         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2234         write_op(sc, BGE_MISC_CFG, (65 << 1));
2235
2236         /* Enable memory arbiter. */
2237         if (BGE_IS_5714_FAMILY(sc)) {
2238                 uint32_t val;
2239
2240                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2241                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2242         } else {
2243                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2244         }
2245
2246         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2247                 for (i = 0; i < BGE_TIMEOUT; i++) {
2248                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2249                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2250                                 break;
2251                         DELAY(100);
2252                 }
2253                 if (i == BGE_TIMEOUT) {
2254                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2255                         return;
2256                 }
2257         } else {
2258                 /*
2259                  * Poll until we see the 1's complement of the magic number.
2260                  * This indicates that the firmware initialization
2261                  * is complete.
2262                  */
2263                 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2264                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2265                         if (val == ~BGE_MAGIC_NUMBER)
2266                                 break;
2267                         DELAY(10);
2268                 }
2269                 if (i == BGE_FIRMWARE_TIMEOUT) {
2270                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2271                                   "timed out, found 0x%08x\n", val);
2272                         return;
2273                 }
2274         }
2275
2276         /*
2277          * XXX Wait for the value of the PCISTATE register to
2278          * return to its original pre-reset state. This is a
2279          * fairly good indicator of reset completion. If we don't
2280          * wait for the reset to fully complete, trying to read
2281          * from the device's non-PCI registers may yield garbage
2282          * results.
2283          */
2284         for (i = 0; i < BGE_TIMEOUT; i++) {
2285                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2286                         break;
2287                 DELAY(10);
2288         }
2289
2290         if (sc->bge_flags & BGE_FLAG_PCIE) {
2291                 reset = bge_readmem_ind(sc, 0x7c00);
2292                 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2293         }
2294
2295         /* Fix up byte swapping */
2296         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2297             BGE_MODECTL_BYTESWAP_DATA);
2298
2299         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2300
2301         /*
2302          * The 5704 in TBI mode apparently needs some special
2303          * adjustment to insure the SERDES drive level is set
2304          * to 1.2V.
2305          */
2306         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2307             (sc->bge_flags & BGE_FLAG_TBI)) {
2308                 uint32_t serdescfg;
2309
2310                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2311                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2312                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2313         }
2314
2315         /* XXX: Broadcom Linux driver. */
2316         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2317             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2318                 uint32_t v;
2319
2320                 v = CSR_READ_4(sc, 0x7c00);
2321                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2322         }
2323
2324         DELAY(10000);
2325 }
2326
2327 /*
2328  * Frame reception handling. This is called if there's a frame
2329  * on the receive return list.
2330  *
2331  * Note: we have to be able to handle two possibilities here:
2332  * 1) the frame is from the jumbo recieve ring
2333  * 2) the frame is from the standard receive ring
2334  */
2335
2336 static void
2337 bge_rxeof(struct bge_softc *sc)
2338 {
2339         struct ifnet *ifp;
2340         int stdcnt = 0, jumbocnt = 0;
2341         struct mbuf_chain chain[MAXCPU];
2342
2343         if (sc->bge_rx_saved_considx ==
2344             sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2345                 return;
2346
2347         ether_input_chain_init(chain);
2348
2349         ifp = &sc->arpcom.ac_if;
2350
2351         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2352                         sc->bge_cdata.bge_rx_return_ring_map,
2353                         BUS_DMASYNC_POSTREAD);
2354         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2355                         sc->bge_cdata.bge_rx_std_ring_map,
2356                         BUS_DMASYNC_POSTREAD);
2357         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2358                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2359                                 sc->bge_cdata.bge_rx_jumbo_ring_map,
2360                                 BUS_DMASYNC_POSTREAD);
2361         }
2362
2363         while (sc->bge_rx_saved_considx !=
2364                sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2365                 struct bge_rx_bd        *cur_rx;
2366                 uint32_t                rxidx;
2367                 struct mbuf             *m = NULL;
2368                 uint16_t                vlan_tag = 0;
2369                 int                     have_tag = 0;
2370
2371                 cur_rx =
2372             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2373
2374                 rxidx = cur_rx->bge_idx;
2375                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2376                 logif(rx_pkt);
2377
2378                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2379                         have_tag = 1;
2380                         vlan_tag = cur_rx->bge_vlan_tag;
2381                 }
2382
2383                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2384                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2385                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2386                         sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2387                         jumbocnt++;
2388                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2389                                 ifp->if_ierrors++;
2390                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2391                                 continue;
2392                         }
2393                         if (bge_newbuf_jumbo(sc,
2394                             sc->bge_jumbo, NULL) == ENOBUFS) {
2395                                 ifp->if_ierrors++;
2396                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2397                                 continue;
2398                         }
2399                 } else {
2400                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2401                         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2402                                         sc->bge_cdata.bge_rx_std_dmamap[rxidx],
2403                                         BUS_DMASYNC_POSTREAD);
2404                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2405                                 sc->bge_cdata.bge_rx_std_dmamap[rxidx]);
2406                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2407                         sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2408                         stdcnt++;
2409                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2410                                 ifp->if_ierrors++;
2411                                 bge_newbuf_std(sc, sc->bge_std, m);
2412                                 continue;
2413                         }
2414                         if (bge_newbuf_std(sc, sc->bge_std,
2415                             NULL) == ENOBUFS) {
2416                                 ifp->if_ierrors++;
2417                                 bge_newbuf_std(sc, sc->bge_std, m);
2418                                 continue;
2419                         }
2420                 }
2421
2422                 ifp->if_ipackets++;
2423 #ifndef __i386__
2424                 /*
2425                  * The i386 allows unaligned accesses, but for other
2426                  * platforms we must make sure the payload is aligned.
2427                  */
2428                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2429                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2430                             cur_rx->bge_len);
2431                         m->m_data += ETHER_ALIGN;
2432                 }
2433 #endif
2434                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2435                 m->m_pkthdr.rcvif = ifp;
2436
2437                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2438                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2439                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2440                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2441                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2442                         }
2443                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2444                             m->m_pkthdr.len >= BGE_MIN_FRAME) {
2445                                 m->m_pkthdr.csum_data =
2446                                         cur_rx->bge_tcp_udp_csum;
2447                                 m->m_pkthdr.csum_flags |=
2448                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2449                         }
2450                 }
2451
2452                 /*
2453                  * If we received a packet with a vlan tag, pass it
2454                  * to vlan_input() instead of ether_input().
2455                  */
2456                 if (have_tag) {
2457                         m->m_flags |= M_VLANTAG;
2458                         m->m_pkthdr.ether_vlantag = vlan_tag;
2459                         have_tag = vlan_tag = 0;
2460                 }
2461                 ether_input_chain(ifp, m, chain);
2462         }
2463
2464         ether_input_dispatch(chain);
2465
2466         if (stdcnt > 0) {
2467                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2468                                 sc->bge_cdata.bge_rx_std_ring_map,
2469                                 BUS_DMASYNC_PREWRITE);
2470         }
2471
2472         if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) {
2473                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2474                                 sc->bge_cdata.bge_rx_jumbo_ring_map,
2475                                 BUS_DMASYNC_PREWRITE);
2476         }
2477
2478         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2479         if (stdcnt)
2480                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2481         if (jumbocnt)
2482                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2483 }
2484
2485 static void
2486 bge_txeof(struct bge_softc *sc)
2487 {
2488         struct bge_tx_bd *cur_tx = NULL;
2489         struct ifnet *ifp;
2490
2491         if (sc->bge_tx_saved_considx ==
2492             sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2493                 return;
2494
2495         ifp = &sc->arpcom.ac_if;
2496
2497         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
2498                         sc->bge_cdata.bge_tx_ring_map,
2499                         BUS_DMASYNC_POSTREAD);
2500
2501         /*
2502          * Go through our tx ring and free mbufs for those
2503          * frames that have been sent.
2504          */
2505         while (sc->bge_tx_saved_considx !=
2506                sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2507                 uint32_t idx = 0;
2508
2509                 idx = sc->bge_tx_saved_considx;
2510                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2511                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2512                         ifp->if_opackets++;
2513                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2514                         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2515                                         sc->bge_cdata.bge_tx_dmamap[idx],
2516                                         BUS_DMASYNC_POSTWRITE);
2517                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2518                             sc->bge_cdata.bge_tx_dmamap[idx]);
2519                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2520                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2521                 }
2522                 sc->bge_txcnt--;
2523                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2524                 logif(tx_pkt);
2525         }
2526
2527         if (cur_tx != NULL &&
2528             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2529             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2530                 ifp->if_flags &= ~IFF_OACTIVE;
2531
2532         if (sc->bge_txcnt == 0)
2533                 ifp->if_timer = 0;
2534
2535         if (!ifq_is_empty(&ifp->if_snd))
2536                 if_devstart(ifp);
2537 }
2538
2539 #ifdef DEVICE_POLLING
2540
2541 static void
2542 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2543 {
2544         struct bge_softc *sc = ifp->if_softc;
2545         uint32_t status;
2546
2547         switch(cmd) {
2548         case POLL_REGISTER:
2549                 bge_disable_intr(sc);
2550                 break;
2551         case POLL_DEREGISTER:
2552                 bge_enable_intr(sc);
2553                 break;
2554         case POLL_AND_CHECK_STATUS:
2555                 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2556                                 sc->bge_cdata.bge_status_map,
2557                                 BUS_DMASYNC_POSTREAD);
2558
2559                 /*
2560                  * Process link state changes.
2561                  */
2562                 status = CSR_READ_4(sc, BGE_MAC_STS);
2563                 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2564                         sc->bge_link_evt = 0;
2565                         sc->bge_link_upd(sc, status);
2566                 }
2567                 /* fall through */
2568         case POLL_ONLY:
2569                 if (ifp->if_flags & IFF_RUNNING) {
2570                         bge_rxeof(sc);
2571                         bge_txeof(sc);
2572                 }
2573                 break;
2574         }
2575 }
2576
2577 #endif
2578
2579 static void
2580 bge_intr(void *xsc)
2581 {
2582         struct bge_softc *sc = xsc;
2583         struct ifnet *ifp = &sc->arpcom.ac_if;
2584         uint32_t status;
2585
2586         logif(intr);
2587
2588         /*
2589          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2590          * disable interrupts by writing nonzero like we used to, since with
2591          * our current organization this just gives complications and
2592          * pessimizations for re-enabling interrupts.  We used to have races
2593          * instead of the necessary complications.  Disabling interrupts
2594          * would just reduce the chance of a status update while we are
2595          * running (by switching to the interrupt-mode coalescence
2596          * parameters), but this chance is already very low so it is more
2597          * efficient to get another interrupt than prevent it.
2598          *
2599          * We do the ack first to ensure another interrupt if there is a
2600          * status update after the ack.  We don't check for the status
2601          * changing later because it is more efficient to get another
2602          * interrupt than prevent it, not quite as above (not checking is
2603          * a smaller optimization than not toggling the interrupt enable,
2604          * since checking doesn't involve PCI accesses and toggling require
2605          * the status check).  So toggling would probably be a pessimization
2606          * even with MSI.  It would only be needed for using a task queue.
2607          */
2608         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
2609
2610         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2611                         sc->bge_cdata.bge_status_map,
2612                         BUS_DMASYNC_POSTREAD);
2613
2614         /*
2615          * Process link state changes.
2616          */
2617         status = CSR_READ_4(sc, BGE_MAC_STS);
2618         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2619                 sc->bge_link_evt = 0;
2620                 sc->bge_link_upd(sc, status);
2621         }
2622
2623         if (ifp->if_flags & IFF_RUNNING) {
2624                 /* Check RX return ring producer/consumer */
2625                 bge_rxeof(sc);
2626
2627                 /* Check TX ring producer/consumer */
2628                 bge_txeof(sc);
2629         }
2630
2631         if (sc->bge_coal_chg)
2632                 bge_coal_change(sc);
2633 }
2634
2635 static void
2636 bge_tick(void *xsc)
2637 {
2638         struct bge_softc *sc = xsc;
2639         struct ifnet *ifp = &sc->arpcom.ac_if;
2640
2641         lwkt_serialize_enter(ifp->if_serializer);
2642
2643         if (BGE_IS_5705_PLUS(sc))
2644                 bge_stats_update_regs(sc);
2645         else
2646                 bge_stats_update(sc);
2647
2648         if (sc->bge_flags & BGE_FLAG_TBI) {
2649                 /*
2650                  * Since in TBI mode auto-polling can't be used we should poll
2651                  * link status manually. Here we register pending link event
2652                  * and trigger interrupt.
2653                  */
2654                 sc->bge_link_evt++;
2655                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2656         } else if (!sc->bge_link) {
2657                 mii_tick(device_get_softc(sc->bge_miibus));
2658         }
2659
2660         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2661
2662         lwkt_serialize_exit(ifp->if_serializer);
2663 }
2664
2665 static void
2666 bge_stats_update_regs(struct bge_softc *sc)
2667 {
2668         struct ifnet *ifp = &sc->arpcom.ac_if;
2669         struct bge_mac_stats_regs stats;
2670         uint32_t *s;
2671         int i;
2672
2673         s = (uint32_t *)&stats;
2674         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2675                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2676                 s++;
2677         }
2678
2679         ifp->if_collisions +=
2680            (stats.dot3StatsSingleCollisionFrames +
2681            stats.dot3StatsMultipleCollisionFrames +
2682            stats.dot3StatsExcessiveCollisions +
2683            stats.dot3StatsLateCollisions) -
2684            ifp->if_collisions;
2685 }
2686
2687 static void
2688 bge_stats_update(struct bge_softc *sc)
2689 {
2690         struct ifnet *ifp = &sc->arpcom.ac_if;
2691         bus_size_t stats;
2692
2693         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2694
2695 #define READ_STAT(sc, stats, stat)      \
2696         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2697
2698         ifp->if_collisions +=
2699            (READ_STAT(sc, stats,
2700                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2701             READ_STAT(sc, stats,
2702                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2703             READ_STAT(sc, stats,
2704                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2705             READ_STAT(sc, stats,
2706                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
2707            ifp->if_collisions;
2708
2709 #undef READ_STAT
2710
2711 #ifdef notdef
2712         ifp->if_collisions +=
2713            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2714            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2715            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2716            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2717            ifp->if_collisions;
2718 #endif
2719 }
2720
2721 /*
2722  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2723  * pointers to descriptors.
2724  */
2725 static int
2726 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
2727 {
2728         struct bge_tx_bd *d = NULL;
2729         uint16_t csum_flags = 0;
2730         struct bge_dmamap_arg ctx;
2731         bus_dma_segment_t segs[BGE_NSEG_NEW];
2732         bus_dmamap_t map;
2733         int error, maxsegs, idx, i;
2734         struct mbuf *m_head = *m_head0;
2735
2736         if (m_head->m_pkthdr.csum_flags) {
2737                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2738                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2739                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2740                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2741                 if (m_head->m_flags & M_LASTFRAG)
2742                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2743                 else if (m_head->m_flags & M_FRAG)
2744                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2745         }
2746
2747         idx = *txidx;
2748         map = sc->bge_cdata.bge_tx_dmamap[idx];
2749
2750         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2751         KASSERT(maxsegs >= BGE_NSEG_SPARE,
2752                 ("not enough segments %d\n", maxsegs));
2753
2754         if (maxsegs > BGE_NSEG_NEW)
2755                 maxsegs = BGE_NSEG_NEW;
2756
2757         /*
2758          * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2759          * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2760          * but when such padded frames employ the bge IP/TCP checksum
2761          * offload, the hardware checksum assist gives incorrect results
2762          * (possibly from incorporating its own padding into the UDP/TCP
2763          * checksum; who knows).  If we pad such runts with zeros, the
2764          * onboard checksum comes out correct.
2765          */
2766         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2767             m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2768                 error = m_devpad(m_head, BGE_MIN_FRAME);
2769                 if (error)
2770                         goto back;
2771         }
2772
2773         ctx.bge_segs = segs;
2774         ctx.bge_maxsegs = maxsegs;
2775         error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map, m_head,
2776                                      bge_dma_map_mbuf, &ctx, BUS_DMA_NOWAIT);
2777         if (error == EFBIG || ctx.bge_maxsegs == 0) {
2778                 struct mbuf *m_new;
2779
2780                 if (!error)
2781                         bus_dmamap_unload(sc->bge_cdata.bge_mtag, map);
2782
2783                 m_new = m_defrag(m_head, MB_DONTWAIT);
2784                 if (m_new == NULL) {
2785                         if_printf(&sc->arpcom.ac_if,
2786                                   "could not defrag TX mbuf\n");
2787                         error = ENOBUFS;
2788                         goto back;
2789                 } else {
2790                         m_head = m_new;
2791                         *m_head0 = m_head;
2792                 }
2793
2794                 ctx.bge_segs = segs;
2795                 ctx.bge_maxsegs = maxsegs;
2796                 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2797                                              m_head, bge_dma_map_mbuf, &ctx,
2798                                              BUS_DMA_NOWAIT);
2799                 if (error || ctx.bge_maxsegs == 0) {
2800                         if_printf(&sc->arpcom.ac_if,
2801                                   "could not defrag TX mbuf\n");
2802                         if (!error) {
2803                                 bus_dmamap_unload(sc->bge_cdata.bge_mtag, map);
2804                                 error = EFBIG;
2805                         }
2806                         goto back;
2807                 }
2808         } else if (error) {
2809                 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
2810                 goto back;
2811         }
2812
2813         bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE);
2814
2815         for (i = 0; ; i++) {
2816                 d = &sc->bge_ldata.bge_tx_ring[idx];
2817
2818                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[i].ds_addr);
2819                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[i].ds_addr);
2820                 d->bge_len = segs[i].ds_len;
2821                 d->bge_flags = csum_flags;
2822
2823                 if (i == ctx.bge_maxsegs - 1)
2824                         break;
2825                 BGE_INC(idx, BGE_TX_RING_CNT);
2826         }
2827         /* Mark the last segment as end of packet... */
2828         d->bge_flags |= BGE_TXBDFLAG_END;
2829
2830         /* Set vlan tag to the first segment of the packet. */
2831         d = &sc->bge_ldata.bge_tx_ring[*txidx];
2832         if (m_head->m_flags & M_VLANTAG) {
2833                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2834                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
2835         } else {
2836                 d->bge_vlan_tag = 0;
2837         }
2838
2839         /*
2840          * Insure that the map for this transmission is placed at
2841          * the array index of the last descriptor in this chain.
2842          */
2843         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2844         sc->bge_cdata.bge_tx_dmamap[idx] = map;
2845         sc->bge_cdata.bge_tx_chain[idx] = m_head;
2846         sc->bge_txcnt += ctx.bge_maxsegs;
2847
2848         BGE_INC(idx, BGE_TX_RING_CNT);
2849         *txidx = idx;
2850 back:
2851         if (error) {
2852                 m_freem(m_head);
2853                 *m_head0 = NULL;
2854         }
2855         return error;
2856 }
2857
2858 /*
2859  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2860  * to the mbuf data regions directly in the transmit descriptors.
2861  */
2862 static void
2863 bge_start(struct ifnet *ifp)
2864 {
2865         struct bge_softc *sc = ifp->if_softc;
2866         struct mbuf *m_head = NULL;
2867         uint32_t prodidx;
2868         int need_trans;
2869
2870         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2871                 return;
2872
2873         prodidx = sc->bge_tx_prodidx;
2874
2875         need_trans = 0;
2876         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2877                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2878                 if (m_head == NULL)
2879                         break;
2880
2881                 /*
2882                  * XXX
2883                  * The code inside the if() block is never reached since we
2884                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2885                  * requests to checksum TCP/UDP in a fragmented packet.
2886                  *
2887                  * XXX
2888                  * safety overkill.  If this is a fragmented packet chain
2889                  * with delayed TCP/UDP checksums, then only encapsulate
2890                  * it if we have enough descriptors to handle the entire
2891                  * chain at once.
2892                  * (paranoia -- may not actually be needed)
2893                  */
2894                 if ((m_head->m_flags & M_FIRSTFRAG) &&
2895                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
2896                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2897                             m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
2898                                 ifp->if_flags |= IFF_OACTIVE;
2899                                 ifq_prepend(&ifp->if_snd, m_head);
2900                                 break;
2901                         }
2902                 }
2903
2904                 /*
2905                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2906                  * descriptors of the end of the ring.  Also make
2907                  * sure there are BGE_NSEG_SPARE descriptors for
2908                  * jumbo buffers' defragmentation.
2909                  */
2910                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2911                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
2912                         ifp->if_flags |= IFF_OACTIVE;
2913                         ifq_prepend(&ifp->if_snd, m_head);
2914                         break;
2915                 }
2916
2917                 /*
2918                  * Pack the data into the transmit ring. If we
2919                  * don't have room, set the OACTIVE flag and wait
2920                  * for the NIC to drain the ring.
2921                  */
2922                 if (bge_encap(sc, &m_head, &prodidx)) {
2923                         ifp->if_flags |= IFF_OACTIVE;
2924                         ifp->if_oerrors++;
2925                         break;
2926                 }
2927                 need_trans = 1;
2928
2929                 ETHER_BPF_MTAP(ifp, m_head);
2930         }
2931
2932         if (!need_trans)
2933                 return;
2934
2935         /* Transmit */
2936         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2937         /* 5700 b2 errata */
2938         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2939                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2940
2941         sc->bge_tx_prodidx = prodidx;
2942
2943         /*
2944          * Set a timeout in case the chip goes out to lunch.
2945          */
2946         ifp->if_timer = 5;
2947 }
2948
2949 static void
2950 bge_init(void *xsc)
2951 {
2952         struct bge_softc *sc = xsc;
2953         struct ifnet *ifp = &sc->arpcom.ac_if;
2954         uint16_t *m;
2955
2956         ASSERT_SERIALIZED(ifp->if_serializer);
2957
2958         if (ifp->if_flags & IFF_RUNNING)
2959                 return;
2960
2961         /* Cancel pending I/O and flush buffers. */
2962         bge_stop(sc);
2963         bge_reset(sc);
2964         bge_chipinit(sc);
2965
2966         /*
2967          * Init the various state machines, ring
2968          * control blocks and firmware.
2969          */
2970         if (bge_blockinit(sc)) {
2971                 if_printf(ifp, "initialization failure\n");
2972                 return;
2973         }
2974
2975         /* Specify MTU. */
2976         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2977             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2978
2979         /* Load our MAC address. */
2980         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2981         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2982         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2983
2984         /* Enable or disable promiscuous mode as needed. */
2985         bge_setpromisc(sc);
2986
2987         /* Program multicast filter. */
2988         bge_setmulti(sc);
2989
2990         /* Init RX ring. */
2991         bge_init_rx_ring_std(sc);
2992
2993         /*
2994          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2995          * memory to insure that the chip has in fact read the first
2996          * entry of the ring.
2997          */
2998         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2999                 uint32_t                v, i;
3000                 for (i = 0; i < 10; i++) {
3001                         DELAY(20);
3002                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3003                         if (v == (MCLBYTES - ETHER_ALIGN))
3004                                 break;
3005                 }
3006                 if (i == 10)
3007                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3008         }
3009
3010         /* Init jumbo RX ring. */
3011         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
3012                 bge_init_rx_ring_jumbo(sc);
3013
3014         /* Init our RX return ring index */
3015         sc->bge_rx_saved_considx = 0;
3016
3017         /* Init TX ring. */
3018         bge_init_tx_ring(sc);
3019
3020         /* Turn on transmitter */
3021         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
3022
3023         /* Turn on receiver */
3024         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3025
3026         /* Tell firmware we're alive. */
3027         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3028
3029         /* Enable host interrupts if polling(4) is not enabled. */
3030         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3031 #ifdef DEVICE_POLLING
3032         if (ifp->if_flags & IFF_POLLING)
3033                 bge_disable_intr(sc);
3034         else
3035 #endif
3036         bge_enable_intr(sc);
3037
3038         bge_ifmedia_upd(ifp);
3039
3040         ifp->if_flags |= IFF_RUNNING;
3041         ifp->if_flags &= ~IFF_OACTIVE;
3042
3043         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3044 }
3045
3046 /*
3047  * Set media options.
3048  */
3049 static int
3050 bge_ifmedia_upd(struct ifnet *ifp)
3051 {
3052         struct bge_softc *sc = ifp->if_softc;
3053
3054         /* If this is a 1000baseX NIC, enable the TBI port. */
3055         if (sc->bge_flags & BGE_FLAG_TBI) {
3056                 struct ifmedia *ifm = &sc->bge_ifmedia;
3057
3058                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3059                         return(EINVAL);
3060
3061                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3062                 case IFM_AUTO:
3063                         /*
3064                          * The BCM5704 ASIC appears to have a special
3065                          * mechanism for programming the autoneg
3066                          * advertisement registers in TBI mode.
3067                          */
3068                         if (!bge_fake_autoneg &&
3069                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3070                                 uint32_t sgdig;
3071
3072                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3073                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3074                                 sgdig |= BGE_SGDIGCFG_AUTO |
3075                                          BGE_SGDIGCFG_PAUSE_CAP |
3076                                          BGE_SGDIGCFG_ASYM_PAUSE;
3077                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3078                                             sgdig | BGE_SGDIGCFG_SEND);
3079                                 DELAY(5);
3080                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3081                         }
3082                         break;
3083                 case IFM_1000_SX:
3084                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3085                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3086                                     BGE_MACMODE_HALF_DUPLEX);
3087                         } else {
3088                                 BGE_SETBIT(sc, BGE_MAC_MODE,
3089                                     BGE_MACMODE_HALF_DUPLEX);
3090                         }
3091                         break;
3092                 default:
3093                         return(EINVAL);
3094                 }
3095         } else {
3096                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3097
3098                 sc->bge_link_evt++;
3099                 sc->bge_link = 0;
3100                 if (mii->mii_instance) {
3101                         struct mii_softc *miisc;
3102
3103                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3104                                 mii_phy_reset(miisc);
3105                 }
3106                 mii_mediachg(mii);
3107         }
3108         return(0);
3109 }
3110
3111 /*
3112  * Report current media status.
3113  */
3114 static void
3115 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3116 {
3117         struct bge_softc *sc = ifp->if_softc;
3118
3119         if (sc->bge_flags & BGE_FLAG_TBI) {
3120                 ifmr->ifm_status = IFM_AVALID;
3121                 ifmr->ifm_active = IFM_ETHER;
3122                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3123                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3124                         ifmr->ifm_status |= IFM_ACTIVE;
3125                 } else {
3126                         ifmr->ifm_active |= IFM_NONE;
3127                         return;
3128                 }
3129
3130                 ifmr->ifm_active |= IFM_1000_SX;
3131                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3132                         ifmr->ifm_active |= IFM_HDX;
3133                 else
3134                         ifmr->ifm_active |= IFM_FDX;
3135         } else {
3136                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3137
3138                 mii_pollstat(mii);
3139                 ifmr->ifm_active = mii->mii_media_active;
3140                 ifmr->ifm_status = mii->mii_media_status;
3141         }
3142 }
3143
3144 static int
3145 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3146 {
3147         struct bge_softc *sc = ifp->if_softc;
3148         struct ifreq *ifr = (struct ifreq *)data;
3149         int mask, error = 0;
3150
3151         ASSERT_SERIALIZED(ifp->if_serializer);
3152
3153         switch (command) {
3154         case SIOCSIFMTU:
3155                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3156                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3157                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3158                         error = EINVAL;
3159                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3160                         ifp->if_mtu = ifr->ifr_mtu;
3161                         ifp->if_flags &= ~IFF_RUNNING;
3162                         bge_init(sc);
3163                 }
3164                 break;
3165         case SIOCSIFFLAGS:
3166                 if (ifp->if_flags & IFF_UP) {
3167                         if (ifp->if_flags & IFF_RUNNING) {
3168                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3169
3170                                 /*
3171                                  * If only the state of the PROMISC flag
3172                                  * changed, then just use the 'set promisc
3173                                  * mode' command instead of reinitializing
3174                                  * the entire NIC. Doing a full re-init
3175                                  * means reloading the firmware and waiting
3176                                  * for it to start up, which may take a
3177                                  * second or two.  Similarly for ALLMULTI.
3178                                  */
3179                                 if (mask & IFF_PROMISC)
3180                                         bge_setpromisc(sc);
3181                                 if (mask & IFF_ALLMULTI)
3182                                         bge_setmulti(sc);
3183                         } else {
3184                                 bge_init(sc);
3185                         }
3186                 } else {
3187                         if (ifp->if_flags & IFF_RUNNING)
3188                                 bge_stop(sc);
3189                 }
3190                 sc->bge_if_flags = ifp->if_flags;
3191                 break;
3192         case SIOCADDMULTI:
3193         case SIOCDELMULTI:
3194                 if (ifp->if_flags & IFF_RUNNING)
3195                         bge_setmulti(sc);
3196                 break;
3197         case SIOCSIFMEDIA:
3198         case SIOCGIFMEDIA:
3199                 if (sc->bge_flags & BGE_FLAG_TBI) {
3200                         error = ifmedia_ioctl(ifp, ifr,
3201                             &sc->bge_ifmedia, command);
3202                 } else {
3203                         struct mii_data *mii;
3204
3205                         mii = device_get_softc(sc->bge_miibus);
3206                         error = ifmedia_ioctl(ifp, ifr,
3207                                               &mii->mii_media, command);
3208                 }
3209                 break;
3210         case SIOCSIFCAP:
3211                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3212                 if (mask & IFCAP_HWCSUM) {
3213                         ifp->if_capenable ^= IFCAP_HWCSUM;
3214                         if (IFCAP_HWCSUM & ifp->if_capenable)
3215                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3216                         else
3217                                 ifp->if_hwassist = 0;
3218                 }
3219                 break;
3220         default:
3221                 error = ether_ioctl(ifp, command, data);
3222                 break;
3223         }
3224         return error;
3225 }
3226
3227 static void
3228 bge_watchdog(struct ifnet *ifp)
3229 {
3230         struct bge_softc *sc = ifp->if_softc;
3231
3232         if_printf(ifp, "watchdog timeout -- resetting\n");
3233
3234         ifp->if_flags &= ~IFF_RUNNING;
3235         bge_init(sc);
3236
3237         ifp->if_oerrors++;
3238
3239         if (!ifq_is_empty(&ifp->if_snd))
3240                 if_devstart(ifp);
3241 }
3242
3243 /*
3244  * Stop the adapter and free any mbufs allocated to the
3245  * RX and TX lists.
3246  */
3247 static void
3248 bge_stop(struct bge_softc *sc)
3249 {
3250         struct ifnet *ifp = &sc->arpcom.ac_if;
3251         struct ifmedia_entry *ifm;
3252         struct mii_data *mii = NULL;
3253         int mtmp, itmp;
3254
3255         ASSERT_SERIALIZED(ifp->if_serializer);
3256
3257         if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
3258                 mii = device_get_softc(sc->bge_miibus);
3259
3260         callout_stop(&sc->bge_stat_timer);
3261
3262         /*
3263          * Disable all of the receiver blocks
3264          */
3265         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3266         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3267         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3268         if (!BGE_IS_5705_PLUS(sc))
3269                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3270         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3271         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3272         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3273
3274         /*
3275          * Disable all of the transmit blocks
3276          */
3277         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3278         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3279         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3280         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3281         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3282         if (!BGE_IS_5705_PLUS(sc))
3283                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3284         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3285
3286         /*
3287          * Shut down all of the memory managers and related
3288          * state machines.
3289          */
3290         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3291         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3292         if (!BGE_IS_5705_PLUS(sc))
3293                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3294         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3295         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3296         if (!BGE_IS_5705_PLUS(sc)) {
3297                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3298                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3299         }
3300
3301         /* Disable host interrupts. */
3302         bge_disable_intr(sc);
3303
3304         /*
3305          * Tell firmware we're shutting down.
3306          */
3307         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3308
3309         /* Free the RX lists. */
3310         bge_free_rx_ring_std(sc);
3311
3312         /* Free jumbo RX list. */
3313         if (BGE_IS_JUMBO_CAPABLE(sc))
3314                 bge_free_rx_ring_jumbo(sc);
3315
3316         /* Free TX buffers. */
3317         bge_free_tx_ring(sc);
3318
3319         /*
3320          * Isolate/power down the PHY, but leave the media selection
3321          * unchanged so that things will be put back to normal when
3322          * we bring the interface back up.
3323          *
3324          * 'mii' may be NULL in the following cases:
3325          * - The device uses TBI.
3326          * - bge_stop() is called by bge_detach().
3327          */
3328         if (mii != NULL) {
3329                 itmp = ifp->if_flags;
3330                 ifp->if_flags |= IFF_UP;
3331                 ifm = mii->mii_media.ifm_cur;
3332                 mtmp = ifm->ifm_media;
3333                 ifm->ifm_media = IFM_ETHER|IFM_NONE;
3334                 mii_mediachg(mii);
3335                 ifm->ifm_media = mtmp;
3336                 ifp->if_flags = itmp;
3337         }
3338
3339         sc->bge_link = 0;
3340         sc->bge_coal_chg = 0;
3341
3342         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3343
3344         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3345         ifp->if_timer = 0;
3346 }
3347
3348 /*
3349  * Stop all chip I/O so that the kernel's probe routines don't
3350  * get confused by errant DMAs when rebooting.
3351  */
3352 static void
3353 bge_shutdown(device_t dev)
3354 {
3355         struct bge_softc *sc = device_get_softc(dev);
3356         struct ifnet *ifp = &sc->arpcom.ac_if;
3357
3358         lwkt_serialize_enter(ifp->if_serializer);
3359         bge_stop(sc);
3360         bge_reset(sc);
3361         lwkt_serialize_exit(ifp->if_serializer);
3362 }
3363
3364 static int
3365 bge_suspend(device_t dev)
3366 {
3367         struct bge_softc *sc = device_get_softc(dev);
3368         struct ifnet *ifp = &sc->arpcom.ac_if;
3369
3370         lwkt_serialize_enter(ifp->if_serializer);
3371         bge_stop(sc);
3372         lwkt_serialize_exit(ifp->if_serializer);
3373
3374         return 0;
3375 }
3376
3377 static int
3378 bge_resume(device_t dev)
3379 {
3380         struct bge_softc *sc = device_get_softc(dev);
3381         struct ifnet *ifp = &sc->arpcom.ac_if;
3382
3383         lwkt_serialize_enter(ifp->if_serializer);
3384
3385         if (ifp->if_flags & IFF_UP) {
3386                 bge_init(sc);
3387
3388                 if (!ifq_is_empty(&ifp->if_snd))
3389                         if_devstart(ifp);
3390         }
3391
3392         lwkt_serialize_exit(ifp->if_serializer);
3393
3394         return 0;
3395 }
3396
3397 static void
3398 bge_setpromisc(struct bge_softc *sc)
3399 {
3400         struct ifnet *ifp = &sc->arpcom.ac_if;
3401
3402         if (ifp->if_flags & IFF_PROMISC)
3403                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3404         else
3405                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3406 }
3407
3408 static void
3409 bge_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nsegs,
3410                  bus_size_t mapsz __unused, int error)
3411 {
3412         struct bge_dmamap_arg *ctx = arg;
3413         int i;
3414
3415         if (error)
3416                 return;
3417
3418         if (nsegs > ctx->bge_maxsegs) {
3419                 ctx->bge_maxsegs = 0;
3420                 return;
3421         }
3422
3423         ctx->bge_maxsegs = nsegs;
3424         for (i = 0; i < nsegs; ++i)
3425                 ctx->bge_segs[i] = segs[i];
3426 }
3427
3428 static void
3429 bge_dma_free(struct bge_softc *sc)
3430 {
3431         int i;
3432
3433         /* Destroy RX/TX mbuf DMA stuffs. */
3434         if (sc->bge_cdata.bge_mtag != NULL) {
3435                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3436                         if (sc->bge_cdata.bge_rx_std_dmamap[i]) {
3437                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3438                                     sc->bge_cdata.bge_rx_std_dmamap[i]);
3439                         }
3440                 }
3441
3442                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3443                         if (sc->bge_cdata.bge_tx_dmamap[i]) {
3444                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3445                                     sc->bge_cdata.bge_tx_dmamap[i]);
3446                         }
3447                 }
3448                 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3449         }
3450
3451         /* Destroy standard RX ring */
3452         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3453                            sc->bge_cdata.bge_rx_std_ring_map,
3454                            sc->bge_ldata.bge_rx_std_ring);
3455
3456         if (BGE_IS_JUMBO_CAPABLE(sc))
3457                 bge_free_jumbo_mem(sc);
3458
3459         /* Destroy RX return ring */
3460         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3461                            sc->bge_cdata.bge_rx_return_ring_map,
3462                            sc->bge_ldata.bge_rx_return_ring);
3463
3464         /* Destroy TX ring */
3465         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3466                            sc->bge_cdata.bge_tx_ring_map,
3467                            sc->bge_ldata.bge_tx_ring);
3468
3469         /* Destroy status block */
3470         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3471                            sc->bge_cdata.bge_status_map,
3472                            sc->bge_ldata.bge_status_block);
3473
3474         /* Destroy statistics block */
3475         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3476                            sc->bge_cdata.bge_stats_map,
3477                            sc->bge_ldata.bge_stats);
3478
3479         /* Destroy the parent tag */
3480         if (sc->bge_cdata.bge_parent_tag != NULL)
3481                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3482 }
3483
3484 static int
3485 bge_dma_alloc(struct bge_softc *sc)
3486 {
3487         struct ifnet *ifp = &sc->arpcom.ac_if;
3488         int i, error;
3489
3490         /*
3491          * Allocate the parent bus DMA tag appropriate for PCI.
3492          */
3493         error = bus_dma_tag_create(NULL, 1, 0,
3494                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3495                                    NULL, NULL,
3496                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3497                                    BUS_SPACE_MAXSIZE_32BIT,
3498                                    0, &sc->bge_cdata.bge_parent_tag);
3499         if (error) {
3500                 if_printf(ifp, "could not allocate parent dma tag\n");
3501                 return error;
3502         }
3503
3504         /*
3505          * Create DMA tag for mbufs.
3506          */
3507         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3508                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3509                                    NULL, NULL,
3510                                    BGE_JUMBO_FRAMELEN, BGE_NSEG_NEW, MCLBYTES,
3511                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3512                                    &sc->bge_cdata.bge_mtag);
3513         if (error) {
3514                 if_printf(ifp, "could not allocate mbuf dma tag\n");
3515                 return error;
3516         }
3517
3518         /*
3519          * Create DMA maps for TX/RX mbufs.
3520          */
3521         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3522                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag,
3523                                           BUS_DMA_WAITOK,
3524                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
3525                 if (error) {
3526                         int j;
3527
3528                         for (j = 0; j < i; ++j) {
3529                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3530                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3531                         }
3532                         bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3533                         sc->bge_cdata.bge_mtag = NULL;
3534
3535                         if_printf(ifp, "could not create DMA map for RX\n");
3536                         return error;
3537                 }
3538         }
3539
3540         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3541                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag,
3542                                           BUS_DMA_WAITOK,
3543                                           &sc->bge_cdata.bge_tx_dmamap[i]);
3544                 if (error) {
3545                         int j;
3546
3547                         for (j = 0; j < BGE_STD_RX_RING_CNT; ++j) {
3548                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3549                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3550                         }
3551                         for (j = 0; j < i; ++j) {
3552                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3553                                         sc->bge_cdata.bge_tx_dmamap[j]);
3554                         }
3555                         bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3556                         sc->bge_cdata.bge_mtag = NULL;
3557
3558                         if_printf(ifp, "could not create DMA map for TX\n");
3559                         return error;
3560                 }
3561         }
3562
3563         /*
3564          * Create DMA stuffs for standard RX ring.
3565          */
3566         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3567                                     &sc->bge_cdata.bge_rx_std_ring_tag,
3568                                     &sc->bge_cdata.bge_rx_std_ring_map,
3569                                     (void **)&sc->bge_ldata.bge_rx_std_ring,
3570                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
3571         if (error) {
3572                 if_printf(ifp, "could not create std RX ring\n");
3573                 return error;
3574         }
3575
3576         /*
3577          * Create jumbo buffer pool.
3578          */
3579         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3580                 error = bge_alloc_jumbo_mem(sc);
3581                 if (error) {
3582                         if_printf(ifp, "could not create jumbo buffer pool\n");
3583                         return error;
3584                 }
3585         }
3586
3587         /*
3588          * Create DMA stuffs for RX return ring.
3589          */
3590         error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3591                                     &sc->bge_cdata.bge_rx_return_ring_tag,
3592                                     &sc->bge_cdata.bge_rx_return_ring_map,
3593                                     (void **)&sc->bge_ldata.bge_rx_return_ring,
3594                                     &sc->bge_ldata.bge_rx_return_ring_paddr);
3595         if (error) {
3596                 if_printf(ifp, "could not create RX ret ring\n");
3597                 return error;
3598         }
3599
3600         /*
3601          * Create DMA stuffs for TX ring.
3602          */
3603         error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3604                                     &sc->bge_cdata.bge_tx_ring_tag,
3605                                     &sc->bge_cdata.bge_tx_ring_map,
3606                                     (void **)&sc->bge_ldata.bge_tx_ring,
3607                                     &sc->bge_ldata.bge_tx_ring_paddr);
3608         if (error) {
3609                 if_printf(ifp, "could not create TX ring\n");
3610                 return error;
3611         }
3612
3613         /*
3614          * Create DMA stuffs for status block.
3615          */
3616         error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3617                                     &sc->bge_cdata.bge_status_tag,
3618                                     &sc->bge_cdata.bge_status_map,
3619                                     (void **)&sc->bge_ldata.bge_status_block,
3620                                     &sc->bge_ldata.bge_status_block_paddr);
3621         if (error) {
3622                 if_printf(ifp, "could not create status block\n");
3623                 return error;
3624         }
3625
3626         /*
3627          * Create DMA stuffs for statistics block.
3628          */
3629         error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3630                                     &sc->bge_cdata.bge_stats_tag,
3631                                     &sc->bge_cdata.bge_stats_map,
3632                                     (void **)&sc->bge_ldata.bge_stats,
3633                                     &sc->bge_ldata.bge_stats_paddr);
3634         if (error) {
3635                 if_printf(ifp, "could not create stats block\n");
3636                 return error;
3637         }
3638         return 0;
3639 }
3640
3641 static int
3642 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3643                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3644 {
3645         bus_dmamem_t dmem;
3646         int error;
3647
3648         error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3649                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3650                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3651         if (error)
3652                 return error;
3653
3654         *tag = dmem.dmem_tag;
3655         *map = dmem.dmem_map;
3656         *addr = dmem.dmem_addr;
3657         *paddr = dmem.dmem_busaddr;
3658
3659         return 0;
3660 }
3661
3662 static void
3663 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3664 {
3665         if (tag != NULL) {
3666                 bus_dmamap_unload(tag, map);
3667                 bus_dmamem_free(tag, addr, map);
3668                 bus_dma_tag_destroy(tag);
3669         }
3670 }
3671
3672 /*
3673  * Grrr. The link status word in the status block does
3674  * not work correctly on the BCM5700 rev AX and BX chips,
3675  * according to all available information. Hence, we have
3676  * to enable MII interrupts in order to properly obtain
3677  * async link changes. Unfortunately, this also means that
3678  * we have to read the MAC status register to detect link
3679  * changes, thereby adding an additional register access to
3680  * the interrupt handler.
3681  *
3682  * XXX: perhaps link state detection procedure used for
3683  * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3684  */
3685 static void
3686 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3687 {
3688         struct ifnet *ifp = &sc->arpcom.ac_if;
3689         struct mii_data *mii = device_get_softc(sc->bge_miibus);
3690
3691         mii_pollstat(mii);
3692
3693         if (!sc->bge_link &&
3694             (mii->mii_media_status & IFM_ACTIVE) &&
3695             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3696                 sc->bge_link++;
3697                 if (bootverbose)
3698                         if_printf(ifp, "link UP\n");
3699         } else if (sc->bge_link &&
3700             (!(mii->mii_media_status & IFM_ACTIVE) ||
3701             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3702                 sc->bge_link = 0;
3703                 if (bootverbose)
3704                         if_printf(ifp, "link DOWN\n");
3705         }
3706
3707         /* Clear the interrupt. */
3708         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
3709         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
3710         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
3711 }
3712
3713 static void
3714 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
3715 {
3716         struct ifnet *ifp = &sc->arpcom.ac_if;
3717
3718 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3719
3720         /*
3721          * Sometimes PCS encoding errors are detected in
3722          * TBI mode (on fiber NICs), and for some reason
3723          * the chip will signal them as link changes.
3724          * If we get a link change event, but the 'PCS
3725          * encoding error' bit in the MAC status register
3726          * is set, don't bother doing a link check.
3727          * This avoids spurious "gigabit link up" messages
3728          * that sometimes appear on fiber NICs during
3729          * periods of heavy traffic.
3730          */
3731         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3732                 if (!sc->bge_link) {
3733                         sc->bge_link++;
3734                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3735                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3736                                     BGE_MACMODE_TBI_SEND_CFGS);
3737                         }
3738                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3739
3740                         if (bootverbose)
3741                                 if_printf(ifp, "link UP\n");
3742
3743                         ifp->if_link_state = LINK_STATE_UP;
3744                         if_link_state_change(ifp);
3745                 }
3746         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3747                 if (sc->bge_link) {
3748                         sc->bge_link = 0;
3749
3750                         if (bootverbose)
3751                                 if_printf(ifp, "link DOWN\n");
3752
3753                         ifp->if_link_state = LINK_STATE_DOWN;
3754                         if_link_state_change(ifp);
3755                 }
3756         }
3757
3758 #undef PCS_ENCODE_ERR
3759
3760         /* Clear the attention. */
3761         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3762             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3763             BGE_MACSTAT_LINK_CHANGED);
3764 }
3765
3766 static void
3767 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
3768 {
3769         /*
3770          * Check that the AUTOPOLL bit is set before
3771          * processing the event as a real link change.
3772          * Turning AUTOPOLL on and off in the MII read/write
3773          * functions will often trigger a link status
3774          * interrupt for no reason.
3775          */
3776         if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
3777                 struct ifnet *ifp = &sc->arpcom.ac_if;
3778                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3779
3780                 mii_pollstat(mii);
3781
3782                 if (!sc->bge_link &&
3783                     (mii->mii_media_status & IFM_ACTIVE) &&
3784                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3785                         sc->bge_link++;
3786                         if (bootverbose)
3787                                 if_printf(ifp, "link UP\n");
3788                 } else if (sc->bge_link &&
3789                     (!(mii->mii_media_status & IFM_ACTIVE) ||
3790                     IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3791                         sc->bge_link = 0;
3792                         if (bootverbose)
3793                                 if_printf(ifp, "link DOWN\n");
3794                 }
3795         }
3796
3797         /* Clear the attention. */
3798         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3799             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3800             BGE_MACSTAT_LINK_CHANGED);
3801 }
3802
3803 static int
3804 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3805 {
3806         struct bge_softc *sc = arg1;
3807
3808         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3809                                    &sc->bge_rx_coal_ticks,
3810                                    BGE_RX_COAL_TICKS_CHG);
3811 }
3812
3813 static int
3814 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3815 {
3816         struct bge_softc *sc = arg1;
3817
3818         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3819                                    &sc->bge_tx_coal_ticks,
3820                                    BGE_TX_COAL_TICKS_CHG);
3821 }
3822
3823 static int
3824 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3825 {
3826         struct bge_softc *sc = arg1;
3827
3828         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3829                                    &sc->bge_rx_max_coal_bds,
3830                                    BGE_RX_MAX_COAL_BDS_CHG);
3831 }
3832
3833 static int
3834 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3835 {
3836         struct bge_softc *sc = arg1;
3837
3838         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3839                                    &sc->bge_tx_max_coal_bds,
3840                                    BGE_TX_MAX_COAL_BDS_CHG);
3841 }
3842
3843 static int
3844 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3845                     uint32_t coal_chg_mask)
3846 {
3847         struct bge_softc *sc = arg1;
3848         struct ifnet *ifp = &sc->arpcom.ac_if;
3849         int error = 0, v;
3850
3851         lwkt_serialize_enter(ifp->if_serializer);
3852
3853         v = *coal;
3854         error = sysctl_handle_int(oidp, &v, 0, req);
3855         if (!error && req->newptr != NULL) {
3856                 if (v < 0) {
3857                         error = EINVAL;
3858                 } else {
3859                         *coal = v;
3860                         sc->bge_coal_chg |= coal_chg_mask;
3861                 }
3862         }
3863
3864         lwkt_serialize_exit(ifp->if_serializer);
3865         return error;
3866 }
3867
3868 static void
3869 bge_coal_change(struct bge_softc *sc)
3870 {
3871         struct ifnet *ifp = &sc->arpcom.ac_if;
3872         uint32_t val;
3873
3874         ASSERT_SERIALIZED(ifp->if_serializer);
3875
3876         if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
3877                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3878                             sc->bge_rx_coal_ticks);
3879                 DELAY(10);
3880                 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3881
3882                 if (bootverbose) {
3883                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3884                                   sc->bge_rx_coal_ticks);
3885                 }
3886         }
3887
3888         if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
3889                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3890                             sc->bge_tx_coal_ticks);
3891                 DELAY(10);
3892                 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3893
3894                 if (bootverbose) {
3895                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3896                                   sc->bge_tx_coal_ticks);
3897                 }
3898         }
3899
3900         if (sc->bge_coal_chg & BGE_RX_MAX_COAL_BDS_CHG) {
3901                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3902                             sc->bge_rx_max_coal_bds);
3903                 DELAY(10);
3904                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3905
3906                 if (bootverbose) {
3907                         if_printf(ifp, "rx_max_coal_bds -> %u\n",
3908                                   sc->bge_rx_max_coal_bds);
3909                 }
3910         }
3911
3912         if (sc->bge_coal_chg & BGE_TX_MAX_COAL_BDS_CHG) {
3913                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3914                             sc->bge_tx_max_coal_bds);
3915                 DELAY(10);
3916                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3917
3918                 if (bootverbose) {
3919                         if_printf(ifp, "tx_max_coal_bds -> %u\n",
3920                                   sc->bge_tx_max_coal_bds);
3921                 }
3922         }
3923
3924         sc->bge_coal_chg = 0;
3925 }
3926
3927 static void
3928 bge_enable_intr(struct bge_softc *sc)
3929 {
3930         struct ifnet *ifp = &sc->arpcom.ac_if;
3931
3932         lwkt_serialize_handler_enable(ifp->if_serializer);
3933
3934         /*
3935          * Enable interrupt.
3936          */
3937         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3938
3939         /*
3940          * Unmask the interrupt when we stop polling.
3941          */
3942         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3943
3944         /*
3945          * Trigger another interrupt, since above writing
3946          * to interrupt mailbox0 may acknowledge pending
3947          * interrupt.
3948          */
3949         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3950 }
3951
3952 static void
3953 bge_disable_intr(struct bge_softc *sc)
3954 {
3955         struct ifnet *ifp = &sc->arpcom.ac_if;
3956
3957         /*
3958          * Mask the interrupt when we start polling.
3959          */
3960         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3961
3962         /*
3963          * Acknowledge possible asserted interrupt.
3964          */
3965         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3966
3967         lwkt_serialize_handler_disable(ifp->if_serializer);
3968 }
3969
3970 static int
3971 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
3972 {
3973         uint32_t mac_addr;
3974         int ret = 1;
3975
3976         mac_addr = bge_readmem_ind(sc, 0x0c14);
3977         if ((mac_addr >> 16) == 0x484b) {
3978                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
3979                 ether_addr[1] = (uint8_t)mac_addr;
3980                 mac_addr = bge_readmem_ind(sc, 0x0c18);
3981                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
3982                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
3983                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
3984                 ether_addr[5] = (uint8_t)mac_addr;
3985                 ret = 0;
3986         }
3987         return ret;
3988 }
3989
3990 static int
3991 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
3992 {
3993         int mac_offset = BGE_EE_MAC_OFFSET;
3994
3995         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
3996                 mac_offset = BGE_EE_MAC_OFFSET_5906;
3997
3998         return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
3999 }
4000
4001 static int
4002 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
4003 {
4004         if (sc->bge_flags & BGE_FLAG_NO_EEPROM)
4005                 return 1;
4006
4007         return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4008                                ETHER_ADDR_LEN);
4009 }
4010
4011 static int
4012 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
4013 {
4014         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
4015                 /* NOTE: Order is critical */
4016                 bge_get_eaddr_mem,
4017                 bge_get_eaddr_nvram,
4018                 bge_get_eaddr_eeprom,
4019                 NULL
4020         };
4021         const bge_eaddr_fcn_t *func;
4022
4023         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
4024                 if ((*func)(sc, eaddr) == 0)
4025                         break;
4026         }
4027         return (*func == NULL ? ENXIO : 0);
4028 }