2 * Copyright (c) 1999 Seigo Tanimura
5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in
6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor.
7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * $FreeBSD: src/sys/dev/sound/pci/csa.c,v 1.33.2.1 2005/12/30 19:55:53 netchild Exp $
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
40 #include <sys/soundcard.h>
42 #include <dev/sound/pcm/sound.h>
43 #include <dev/sound/chip.h>
44 #include <dev/sound/pci/csareg.h>
45 #include <dev/sound/pci/csavar.h>
47 #include <bus/pci/pcireg.h>
48 #include <bus/pci/pcivar.h>
50 #include <gnu/dev/sound/pci/csaimg.h>
52 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/csa.c,v 1.8 2007/01/04 21:47:02 corecode Exp $");
54 /* This is the pci device id. */
55 #define CS4610_PCI_ID 0x60011013
56 #define CS4614_PCI_ID 0x60031013
57 #define CS4615_PCI_ID 0x60041013
59 /* Here is the parameter structure per a device. */
61 device_t dev; /* device */
62 csa_res res; /* resources */
64 device_t pcm; /* pcm device */
65 driver_intr_t* pcmintr; /* pcm intr */
66 void *pcmintr_arg; /* pcm intr arg */
67 device_t midi; /* midi device */
68 driver_intr_t* midiintr; /* midi intr */
69 void *midiintr_arg; /* midi intr arg */
70 void *ih; /* cookie */
72 struct csa_card *card;
73 struct csa_bridgeinfo binfo; /* The state of this bridge. */
76 typedef struct csa_softc *sc_p;
78 static int csa_probe(device_t dev);
79 static int csa_attach(device_t dev);
80 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
81 u_long start, u_long end, u_long count, u_int flags, int cpuid);
82 static int csa_release_resource(device_t bus, device_t child, int type, int rid,
84 static int csa_setup_intr(device_t bus, device_t child,
85 struct resource *irq, int flags,
86 driver_intr_t *intr, void *arg, void **cookiep);
87 static int csa_teardown_intr(device_t bus, device_t child,
88 struct resource *irq, void *cookie);
89 static driver_intr_t csa_intr;
90 static int csa_initialize(sc_p scp);
91 static int csa_downloadimage(csa_res *resp);
93 static devclass_t csa_devclass;
109 devclass_t pci_devclass;
110 device_t *pci_devices, *pci_children, *busp, *childp;
111 int pci_count = 0, pci_childcount = 0;
114 bus_space_tag_t btag;
116 if ((pci_devclass = devclass_find("pci")) == NULL) {
120 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
122 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
124 device_get_children(*busp, &pci_children, &pci_childcount);
125 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) {
126 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) {
127 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10;
129 btag = I386_BUS_SPACE_IO;
131 control = bus_space_read_2(btag, 0x0, port);
133 control |= run? 0 : 0x2000;
134 bus_space_write_2(btag, 0x0, port, control);
135 kfree(pci_devices, M_TEMP);
136 kfree(pci_children, M_TEMP);
140 kfree(pci_children, M_TEMP);
143 kfree(pci_devices, M_TEMP);
150 static struct csa_card cards_4610[] = {
151 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0},
154 static struct csa_card cards_4614[] = {
155 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0},
156 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1},
157 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0},
158 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
159 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
160 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0},
161 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0},
162 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0},
163 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0},
166 static struct csa_card cards_4615[] = {
167 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0},
170 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0};
175 struct csa_card *cards;
178 static struct card_type cards[] = {
179 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610},
180 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614},
181 {CS4615_PCI_ID, "CS4615", cards_4615},
185 static struct card_type *
186 csa_findcard(device_t dev)
191 while (cards[i].devid != 0) {
192 if (pci_get_devid(dev) == cards[i].devid)
200 csa_findsubcard(device_t dev)
203 struct card_type *card;
204 struct csa_card *subcard;
206 card = csa_findcard(dev);
209 subcard = card->cards;
211 while (subcard[i].subvendor != 0) {
212 if (pci_get_subvendor(dev) == subcard[i].subvendor
213 && pci_get_subdevice(dev) == subcard[i].subdevice) {
222 csa_probe(device_t dev)
224 struct card_type *card;
226 card = csa_findcard(dev);
228 device_set_desc(dev, card->name);
229 return BUS_PROBE_DEFAULT;
235 csa_attach(device_t dev)
240 struct sndcard_func *func;
243 scp = device_get_softc(dev);
245 /* Fill in the softc. */
246 bzero(scp, sizeof(*scp));
249 /* Wake up the device. */
250 stcmd = pci_read_config(dev, PCIR_COMMAND, 2);
251 if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) {
252 stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
253 pci_write_config(dev, PCIR_COMMAND, stcmd, 2);
256 /* Allocate the resources. */
258 scp->card = csa_findsubcard(dev);
259 scp->binfo.card = scp->card;
260 kprintf("csa: card is %s\n", scp->card->name);
261 resp->io_rid = PCIR_BAR(0);
262 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
263 &resp->io_rid, RF_ACTIVE);
264 if (resp->io == NULL)
266 resp->mem_rid = PCIR_BAR(1);
267 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
268 &resp->mem_rid, RF_ACTIVE);
269 if (resp->mem == NULL)
272 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
273 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE);
274 if (resp->irq == NULL)
277 /* Enable interrupt. */
278 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih))
281 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
282 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
285 /* Initialize the chip. */
286 if (csa_initialize(scp))
289 /* Reset the Processor. */
292 /* Download the Processor Image to the processor. */
293 if (csa_downloadimage(resp))
296 /* Attach the children. */
299 func = kmalloc(sizeof(struct sndcard_func), M_DEVBUF,
301 func->varinfo = &scp->binfo;
302 func->func = SCF_PCM;
303 scp->pcm = device_add_child(dev, "pcm", -1);
304 device_set_ivars(scp->pcm, func);
307 func = kmalloc(sizeof(struct sndcard_func), M_DEVBUF,
309 func->varinfo = &scp->binfo;
310 func->func = SCF_MIDI;
311 scp->midi = device_add_child(dev, "midi", -1);
312 device_set_ivars(scp->midi, func);
314 bus_generic_attach(dev);
319 bus_teardown_intr(dev, resp->irq, scp->ih);
321 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
323 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
325 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
330 csa_detach(device_t dev)
336 scp = device_get_softc(dev);
340 if (scp->midi != NULL)
341 err = device_delete_child(dev, scp->midi);
346 if (scp->pcm != NULL)
347 err = device_delete_child(dev, scp->pcm);
352 bus_teardown_intr(dev, resp->irq, scp->ih);
353 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
354 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
355 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
357 return bus_generic_detach(dev);
361 csa_resume(device_t dev)
366 scp = device_get_softc(dev);
369 /* Initialize the chip. */
370 if (csa_initialize(scp))
373 /* Reset the Processor. */
376 /* Download the Processor Image to the processor. */
377 if (csa_downloadimage(resp))
380 return (bus_generic_resume(dev));
383 static struct resource *
384 csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
385 u_long start, u_long end, u_long count, u_int flags, int cpuid __unused)
389 struct resource *res;
391 scp = device_get_softc(bus);
419 csa_release_resource(device_t bus, device_t child, int type, int rid,
426 * The following three functions deal with interrupt handling.
427 * An interrupt is primarily handled by the bridge driver.
428 * The bridge driver then determines the child devices to pass
429 * the interrupt. Certain information of the device can be read
430 * only once(eg the value of HISR). The bridge driver is responsible
431 * to pass such the information to the children.
435 csa_setup_intr(device_t bus, device_t child,
436 struct resource *irq, int flags,
437 driver_intr_t *intr, void *arg, void **cookiep)
441 struct sndcard_func *func;
443 scp = device_get_softc(bus);
447 * Look at the function code of the child to determine
448 * the appropriate hander for it.
450 func = device_get_ivars(child);
451 if (func == NULL || irq != resp->irq)
454 switch (func->func) {
457 scp->pcmintr_arg = arg;
461 scp->midiintr = intr;
462 scp->midiintr_arg = arg;
469 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
470 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
476 csa_teardown_intr(device_t bus, device_t child,
477 struct resource *irq, void *cookie)
481 struct sndcard_func *func;
483 scp = device_get_softc(bus);
487 * Look at the function code of the child to determine
488 * the appropriate hander for it.
490 func = device_get_ivars(child);
491 if (func == NULL || irq != resp->irq || cookie != scp)
494 switch (func->func) {
497 scp->pcmintr_arg = NULL;
501 scp->midiintr = NULL;
502 scp->midiintr_arg = NULL;
512 /* The interrupt handler */
522 /* Is this interrupt for us? */
523 hisr = csa_readio(resp, BA0_HISR);
524 if ((hisr & 0x7fffffff) == 0) {
526 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
531 * Pass the value of HISR via struct csa_bridgeinfo.
532 * The children get access through their ivars.
534 scp->binfo.hisr = hisr;
536 /* Invoke the handlers of the children. */
537 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) {
538 scp->pcmintr(scp->pcmintr_arg);
539 hisr &= ~(HISR_VC0 | HISR_VC1);
541 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) {
542 scp->midiintr(scp->midiintr_arg);
547 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
551 csa_initialize(sc_p scp)
554 u_int32_t acsts, acisv;
560 * First, blast the clock control register to zero so that the PLL starts
561 * out in a known state, and blast the master serial port control register
562 * to zero so that the serial ports also start out in a known state.
564 csa_writeio(resp, BA0_CLKCR1, 0);
565 csa_writeio(resp, BA0_SERMC1, 0);
568 * If we are in AC97 mode, then we must set the part to a host controlled
569 * AC-link. Otherwise, we won't be able to bring up the link.
572 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */
574 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */
578 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
579 * spec) and then drive it high. This is done for non AC97 modes since
580 * there might be logic external to the CS461x that uses the ARST# line
583 csa_writeio(resp, BA0_ACCTL, 1);
585 csa_writeio(resp, BA0_ACCTL, 0);
587 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN);
590 * The first thing we do here is to enable sync generation. As soon
591 * as we start receiving bit clock, we'll start producing the SYNC
594 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
597 * Now wait for a short while to allow the AC97 part to start
598 * generating bit clock (so we don't try to start the PLL without an
604 * Set the serial port timing configuration, so that
605 * the clock control circuit gets its clock from the correct place.
607 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97);
611 * Write the selected clock control setup to the hardware. Do not turn on
612 * SWCE yet (if requested), so that the devices clocked by the output of
613 * PLL are not clocked until the PLL is stable.
615 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
616 csa_writeio(resp, BA0_PLLM, 0x3a);
617 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8);
622 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP);
625 * Wait until the PLL has stabilized.
630 * Turn on clocking of the core so that we can setup the serial ports.
632 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE);
635 * Fill the serial port FIFOs with silence.
637 csa_clearserialfifos(resp);
640 * Set the serial port FIFO pointer to the first sample in the FIFO.
643 csa_writeio(resp, BA0_SERBSP, 0);
647 * Write the serial port configuration to the part. The master
648 * enable bit is not set until all other values have been written.
650 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
651 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
652 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
655 * Wait for the codec ready signal from the AC97 codec.
658 for (i = 0 ; i < 1000 ; i++) {
660 * First, lets wait a short while to let things settle out a bit,
661 * and to prevent retrying the read too quickly.
666 * Read the AC97 status register to see if we've seen a CODEC READY
667 * signal from the AC97 codec.
669 acsts = csa_readio(resp, BA0_ACSTS);
670 if ((acsts & ACSTS_CRDY) != 0)
675 * Make sure we sampled CODEC READY.
677 if ((acsts & ACSTS_CRDY) == 0)
681 * Assert the vaid frame signal so that we can start sending commands
684 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
687 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
688 * the codec is pumping ADC data across the AC-link.
691 for (i = 0 ; i < 1000 ; i++) {
693 * First, lets wait a short while to let things settle out a bit,
694 * and to prevent retrying the read too quickly.
697 DELAY(10000000L); /* clw */
702 * Read the input slot valid register and see if input slots 3 and
705 acisv = csa_readio(resp, BA0_ACISV);
706 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
710 * Make sure we sampled valid input slots 3 and 4. If not, then return
713 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4))
717 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
718 * commense the transfer of digital audio data to the AC97 codec.
720 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
723 * Power down the DAC and ADC. We will power them up (if) when we need
727 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300);
731 * Turn off the Processor by turning off the software clock enable flag in
732 * the clock control register.
735 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE;
736 csa_writeio(resp, BA0_CLKCR1, clkcr1);
740 * Enable interrupts on the part.
743 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
750 csa_clearserialfifos(csa_res *resp)
753 u_int8_t clkcr1, serbst;
756 * See if the devices are powered down. If so, we must power them up first
757 * or they will not respond.
760 clkcr1 = csa_readio(resp, BA0_CLKCR1);
761 if ((clkcr1 & CLKCR1_SWCE) == 0) {
762 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE);
767 * We want to clear out the serial port FIFOs so we don't end up playing
768 * whatever random garbage happens to be in them. We fill the sample FIFOs
769 * with zero (silence).
771 csa_writeio(resp, BA0_SERBWP, 0);
773 /* Fill all 256 sample FIFO locations. */
775 for (i = 0 ; i < 256 ; i++) {
776 /* Make sure the previous FIFO write operation has completed. */
777 for (j = 0 ; j < 5 ; j++) {
779 serbst = csa_readio(resp, BA0_SERBST);
780 if ((serbst & SERBST_WBSY) == 0)
783 if ((serbst & SERBST_WBSY) != 0) {
785 csa_writeio(resp, BA0_CLKCR1, clkcr1);
787 /* Write the serial port FIFO index. */
788 csa_writeio(resp, BA0_SERBAD, i);
789 /* Tell the serial port to load the new value into the FIFO location. */
790 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC);
793 * Now, if we powered up the devices, then power them back down again.
794 * This is kinda ugly, but should never happen.
797 csa_writeio(resp, BA0_CLKCR1, clkcr1);
801 csa_resetdsp(csa_res *resp)
806 * Write the reset bit of the SP control register.
808 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP);
811 * Write the control register.
813 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN);
816 * Clear the trap registers.
818 for (i = 0 ; i < 8 ; i++) {
819 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i);
820 csa_writemem(resp, BA1_TWPR, 0xffff);
822 csa_writemem(resp, BA1_DREG, 0);
825 * Set the frame timer to reflect the number of cycles per frame.
827 csa_writemem(resp, BA1_FRMT, 0xadf);
831 csa_downloadimage(csa_res *resp)
834 u_int32_t tmp, src, dst, count, data;
836 for (i = 0; i < CLEAR__COUNT; i++) {
837 dst = ClrStat[i].BA1__DestByteOffset;
838 count = ClrStat[i].BA1__SourceSize;
839 for (tmp = 0; tmp < count; tmp += 4)
840 csa_writemem(resp, dst + tmp, 0x00000000);
843 for (i = 0; i < FILL__COUNT; i++) {
845 dst = FillStat[i].Offset;
846 count = FillStat[i].Size;
847 for (tmp = 0; tmp < count; tmp += 4) {
848 data = FillStat[i].pFill[src];
849 csa_writemem(resp, dst + tmp, data);
858 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data)
861 u_int32_t acsda, acctl, acsts;
864 * Make sure that there is not data sitting around from a previous
865 * uncompleted access. ACSDA = Status Data Register = 47Ch
867 acsda = csa_readio(resp, BA0_ACSDA);
870 * Setup the AC97 control registers on the CS461x to send the
871 * appropriate command to the AC97 to perform the read.
872 * ACCAD = Command Address Register = 46Ch
873 * ACCDA = Command Data Register = 470h
874 * ACCTL = Control Register = 460h
875 * set DCV - will clear when process completed
876 * set CRW - Read command
877 * set VFRM - valid frame enabled
878 * set ESYN - ASYNC generation enabled
879 * set RSTN - ARST# inactive, AC97 codec not reset
883 * Get the actual AC97 register from the offset
885 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
886 csa_writeio(resp, BA0_ACCDA, 0);
887 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
890 * Wait for the read to occur.
893 for (i = 0 ; i < 10 ; i++) {
895 * First, we want to wait for a short time.
900 * Now, check to see if the read has completed.
901 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
903 acctl = csa_readio(resp, BA0_ACCTL);
904 if ((acctl & ACCTL_DCV) == 0)
909 * Make sure the read completed.
911 if ((acctl & ACCTL_DCV) != 0)
915 * Wait for the valid status bit to go active.
918 for (i = 0 ; i < 10 ; i++) {
920 * Read the AC97 status register.
921 * ACSTS = Status Register = 464h
923 acsts = csa_readio(resp, BA0_ACSTS);
925 * See if we have valid status.
926 * VSTS - Valid Status
928 if ((acsts & ACSTS_VSTS) != 0)
931 * Wait for a short while.
937 * Make sure we got valid status.
939 if ((acsts & ACSTS_VSTS) == 0)
943 * Read the data returned from the AC97 register.
944 * ACSDA = Status Data Register = 474h
946 *data = csa_readio(resp, BA0_ACSDA);
952 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data)
958 * Setup the AC97 control registers on the CS461x to send the
959 * appropriate command to the AC97 to perform the write.
960 * ACCAD = Command Address Register = 46Ch
961 * ACCDA = Command Data Register = 470h
962 * ACCTL = Control Register = 460h
963 * set DCV - will clear when process completed
964 * set VFRM - valid frame enabled
965 * set ESYN - ASYNC generation enabled
966 * set RSTN - ARST# inactive, AC97 codec not reset
970 * Get the actual AC97 register from the offset
972 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
973 csa_writeio(resp, BA0_ACCDA, data);
974 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
977 * Wait for the write to occur.
980 for (i = 0 ; i < 10 ; i++) {
982 * First, we want to wait for a short time.
987 * Now, check to see if the read has completed.
988 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
990 acctl = csa_readio(resp, BA0_ACCTL);
991 if ((acctl & ACCTL_DCV) == 0)
996 * Make sure the write completed.
998 if ((acctl & ACCTL_DCV) != 0)
1005 csa_readio(csa_res *resp, u_long offset)
1009 if (offset < BA0_AC97_RESET)
1010 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff;
1012 if (csa_readcodec(resp, offset, &ul))
1019 csa_writeio(csa_res *resp, u_long offset, u_int32_t data)
1021 if (offset < BA0_AC97_RESET)
1022 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data);
1024 csa_writecodec(resp, offset, data);
1028 csa_readmem(csa_res *resp, u_long offset)
1030 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset);
1034 csa_writemem(csa_res *resp, u_long offset, u_int32_t data)
1036 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data);
1039 static device_method_t csa_methods[] = {
1040 /* Device interface */
1041 DEVMETHOD(device_probe, csa_probe),
1042 DEVMETHOD(device_attach, csa_attach),
1043 DEVMETHOD(device_detach, csa_detach),
1044 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1045 DEVMETHOD(device_suspend, bus_generic_suspend),
1046 DEVMETHOD(device_resume, csa_resume),
1049 DEVMETHOD(bus_print_child, bus_generic_print_child),
1050 DEVMETHOD(bus_alloc_resource, csa_alloc_resource),
1051 DEVMETHOD(bus_release_resource, csa_release_resource),
1052 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1053 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1054 DEVMETHOD(bus_setup_intr, csa_setup_intr),
1055 DEVMETHOD(bus_teardown_intr, csa_teardown_intr),
1060 static driver_t csa_driver = {
1063 sizeof(struct csa_softc),
1067 * csa can be attached to a pci bus.
1069 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, NULL, NULL);
1070 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1071 MODULE_VERSION(snd_csa, 1);