2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $
29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.9 2004/03/23 22:19:00 hsu Exp $
33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/malloc.h>
40 /* #include <sys/mutex.h> */
41 #include <sys/kernel.h>
42 #include <sys/socket.h>
43 #include <sys/sysctl.h>
46 #include <net/if_dl.h>
47 #include <net/if_media.h>
51 #include <netns/ns_if.h>
55 #include <sys/sockio.h>
57 #include <machine/bus.h>
59 #include <machine/resource.h>
61 #include <net/ethernet.h>
62 #include <net/if_arp.h>
64 #include <vm/vm.h> /* for vtophys */
65 #include <vm/pmap.h> /* for vtophys */
66 #include <machine/clock.h> /* for DELAY */
68 #include <net/if_types.h>
69 #include <net/vlan/if_vlan_var.h>
71 #include <bus/pci/pcivar.h>
72 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */
74 #include "../mii_layer/mii.h"
75 #include "../mii_layer/miivar.h"
77 #include "if_fxpreg.h"
78 #include "if_fxpvar.h"
81 #include "miibus_if.h"
84 * NOTE! On the Alpha, we have an alignment constraint. The
85 * card DMAs the packet immediately following the RFA. However,
86 * the first thing in the packet is a 14-byte Ethernet header.
87 * This means that the packet is misaligned. To compensate,
88 * we actually offset the RFA 2 bytes into the cluster. This
89 * alignes the packet after the Ethernet header at a 32-bit
90 * boundary. HOWEVER! This means that the RFA is misaligned!
92 #define RFA_ALIGNMENT_FUDGE 2
95 * Set initial transmit threshold at 64 (512 bytes). This is
96 * increased by 64 (512 bytes) at a time, to maximum of 192
97 * (1536 bytes), if an underrun occurs.
99 static int tx_threshold = 64;
102 * The configuration byte map has several undefined fields which
103 * must be one or must be zero. Set up a template for these bits
104 * only, (assuming a 82557 chip) leaving the actual configuration
107 * See struct fxp_cb_config for the bit definitions.
109 static u_char fxp_cb_config_template[] = {
110 0x0, 0x0, /* cb_status */
111 0x0, 0x0, /* cb_command */
112 0x0, 0x0, 0x0, 0x0, /* link_addr */
139 int16_t revid; /* -1 matches anything */
144 * Claim various Intel PCI device identifiers for this driver. The
145 * sub-vendor and sub-device field are extensively used to identify
146 * particular variants, but we don't currently differentiate between
149 static struct fxp_ident fxp_ident_table[] = {
150 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" },
151 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" },
152 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
153 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
154 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
155 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
156 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
157 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
158 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
159 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
160 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
161 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
162 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
163 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
164 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
165 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
166 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
167 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" },
168 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" },
169 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" },
170 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" },
171 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" },
172 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" },
173 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" },
174 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" },
175 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" },
176 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" },
177 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" },
178 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" },
179 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" },
180 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" },
181 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" },
182 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" },
183 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" },
184 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
188 static int fxp_probe(device_t dev);
189 static int fxp_attach(device_t dev);
190 static int fxp_detach(device_t dev);
191 static int fxp_shutdown(device_t dev);
192 static int fxp_suspend(device_t dev);
193 static int fxp_resume(device_t dev);
195 static void fxp_intr(void *xsc);
196 static void fxp_intr_body(struct fxp_softc *sc,
197 u_int8_t statack, int count);
199 static void fxp_init(void *xsc);
200 static void fxp_tick(void *xsc);
201 static void fxp_powerstate_d0(device_t dev);
202 static void fxp_start(struct ifnet *ifp);
203 static void fxp_stop(struct fxp_softc *sc);
204 static void fxp_release(struct fxp_softc *sc);
205 static int fxp_ioctl(struct ifnet *ifp, u_long command,
206 caddr_t data, struct ucred *);
207 static void fxp_watchdog(struct ifnet *ifp);
208 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm);
209 static int fxp_mc_addrs(struct fxp_softc *sc);
210 static void fxp_mc_setup(struct fxp_softc *sc);
211 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
213 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
215 static void fxp_autosize_eeprom(struct fxp_softc *sc);
216 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
217 int offset, int words);
218 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
219 int offset, int words);
220 static int fxp_ifmedia_upd(struct ifnet *ifp);
221 static void fxp_ifmedia_sts(struct ifnet *ifp,
222 struct ifmediareq *ifmr);
223 static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
224 static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
225 struct ifmediareq *ifmr);
226 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg);
227 static void fxp_miibus_writereg(device_t dev, int phy, int reg,
229 static void fxp_load_ucode(struct fxp_softc *sc);
230 static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
232 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
233 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
234 static __inline void fxp_lwcopy(volatile u_int32_t *src,
235 volatile u_int32_t *dst);
236 static __inline void fxp_scb_wait(struct fxp_softc *sc);
237 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
238 static __inline void fxp_dma_wait(volatile u_int16_t *status,
239 struct fxp_softc *sc);
241 static device_method_t fxp_methods[] = {
242 /* Device interface */
243 DEVMETHOD(device_probe, fxp_probe),
244 DEVMETHOD(device_attach, fxp_attach),
245 DEVMETHOD(device_detach, fxp_detach),
246 DEVMETHOD(device_shutdown, fxp_shutdown),
247 DEVMETHOD(device_suspend, fxp_suspend),
248 DEVMETHOD(device_resume, fxp_resume),
251 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
252 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
257 static driver_t fxp_driver = {
260 sizeof(struct fxp_softc),
263 static devclass_t fxp_devclass;
265 DECLARE_DUMMY_MODULE(if_fxp);
266 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1);
267 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0);
268 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0);
269 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
272 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events");
275 * Inline function to copy a 16-bit aligned 32-bit quantity.
278 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst)
283 volatile u_int16_t *a = (volatile u_int16_t *)src;
284 volatile u_int16_t *b = (volatile u_int16_t *)dst;
292 * Wait for the previous command to be accepted (but not necessarily
296 fxp_scb_wait(struct fxp_softc *sc)
300 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
303 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
304 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
305 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
306 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
307 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
311 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
314 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
315 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
318 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
322 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc)
326 while (!(*status & FXP_CB_STATUS_C) && --i)
329 device_printf(sc->dev, "DMA timeout\n");
333 * Return identification string if this is device is ours.
336 fxp_probe(device_t dev)
340 struct fxp_ident *ident;
342 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
343 devid = pci_get_device(dev);
344 revid = pci_get_revid(dev);
345 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
346 if (ident->devid == devid &&
347 (ident->revid == revid || ident->revid == -1)) {
348 device_set_desc(dev, ident->name);
357 fxp_powerstate_d0(device_t dev)
359 #if defined(__DragonFly__) || __FreeBSD_version >= 430002
360 u_int32_t iobase, membase, irq;
362 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
363 /* Save important PCI config data. */
364 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4);
365 membase = pci_read_config(dev, FXP_PCI_MMBA, 4);
366 irq = pci_read_config(dev, PCIR_INTLINE, 4);
368 /* Reset the power state. */
369 device_printf(dev, "chip is in D%d power mode "
370 "-- setting to D0\n", pci_get_powerstate(dev));
372 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
374 /* Restore PCI config data. */
375 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4);
376 pci_write_config(dev, FXP_PCI_MMBA, membase, 4);
377 pci_write_config(dev, PCIR_INTLINE, irq, 4);
383 fxp_attach(device_t dev)
386 struct fxp_softc *sc = device_get_softc(dev);
390 int i, rid, m1, m2, prefer_iomap;
393 bzero(sc, sizeof(*sc));
395 callout_handle_init(&sc->stat_ch);
396 sysctl_ctx_init(&sc->sysctl_ctx);
397 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
402 * Enable bus mastering. Enable memory space too, in case
403 * BIOS/Prom forgot about it.
405 val = pci_read_config(dev, PCIR_COMMAND, 2);
406 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
407 pci_write_config(dev, PCIR_COMMAND, val, 2);
408 val = pci_read_config(dev, PCIR_COMMAND, 2);
410 fxp_powerstate_d0(dev);
413 * Figure out which we should try first - memory mapping or i/o mapping?
414 * We default to memory mapping. Then we accept an override from the
415 * command line. Then we check to see which one is enabled.
418 m2 = PCIM_CMD_PORTEN;
420 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
421 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
422 m1 = PCIM_CMD_PORTEN;
428 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
429 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
430 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
431 0, ~0, 1, RF_ACTIVE);
433 if (sc->mem == NULL && (val & m2)) {
435 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
436 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
437 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
438 0, ~0, 1, RF_ACTIVE);
442 device_printf(dev, "could not map device registers\n");
447 device_printf(dev, "using %s space register mapping\n",
448 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
451 sc->sc_st = rman_get_bustag(sc->mem);
452 sc->sc_sh = rman_get_bushandle(sc->mem);
455 * Allocate our interrupt.
458 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
459 RF_SHAREABLE | RF_ACTIVE);
460 if (sc->irq == NULL) {
461 device_printf(dev, "could not map interrupt\n");
466 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
467 fxp_intr, sc, &sc->ih);
469 device_printf(dev, "could not setup irq\n");
474 * Reset to a stable state.
476 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
479 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
480 M_DEVBUF, M_NOWAIT | M_ZERO);
481 if (sc->cbl_base == NULL)
484 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF,
486 if (sc->fxp_stats == NULL)
489 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT);
490 if (sc->mcsp == NULL)
494 * Pre-allocate our receive buffers.
496 for (i = 0; i < FXP_NRFABUFS; i++) {
497 if (fxp_add_rfabuf(sc, NULL) != 0) {
503 * Find out how large of an SEEPROM we have.
505 fxp_autosize_eeprom(sc);
508 * Determine whether we must use the 503 serial interface.
510 fxp_read_eeprom(sc, &data, 6, 1);
511 if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
512 (data & FXP_PHY_SERIAL_ONLY))
513 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
516 * Create the sysctl tree
518 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
519 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
520 device_get_nameunit(dev), CTLFLAG_RD, 0, "");
521 if (sc->sysctl_tree == NULL)
523 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
524 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
525 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I",
526 "FXP driver receive interrupt microcode bundling delay");
527 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
528 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
529 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I",
530 "FXP driver receive interrupt microcode bundle size limit");
533 * Pull in device tunables.
535 sc->tunable_int_delay = TUNABLE_INT_DELAY;
536 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
537 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
538 "int_delay", &sc->tunable_int_delay);
539 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
540 "bundle_max", &sc->tunable_bundle_max);
543 * Find out the chip revision; lump all 82557 revs together.
545 fxp_read_eeprom(sc, &data, 5, 1);
546 if ((data >> 8) == 1)
547 sc->revision = FXP_REV_82557;
549 sc->revision = pci_get_revid(dev);
552 * Enable workarounds for certain chip revision deficiencies.
554 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
555 * some systems based a normal 82559 design, have a defect where
556 * the chip can cause a PCI protocol violation if it receives
557 * a CU_RESUME command when it is entering the IDLE state. The
558 * workaround is to disable Dynamic Standby Mode, so the chip never
559 * deasserts CLKRUN#, and always remains in an active state.
561 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
563 i = pci_get_device(dev);
564 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) ||
565 sc->revision >= FXP_REV_82559_A0) {
566 fxp_read_eeprom(sc, &data, 10, 1);
567 if (data & 0x02) { /* STB enable */
572 "Disabling dynamic standby mode in EEPROM\n");
574 fxp_write_eeprom(sc, &data, 10, 1);
575 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
577 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
578 fxp_read_eeprom(sc, &data, i, 1);
581 i = (1 << sc->eeprom_size) - 1;
582 cksum = 0xBABA - cksum;
583 fxp_read_eeprom(sc, &data, i, 1);
584 fxp_write_eeprom(sc, &cksum, i, 1);
586 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
590 * If the user elects to continue, try the software
591 * workaround, as it is better than nothing.
593 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
599 * If we are not a 82557 chip, we can enable extended features.
601 if (sc->revision != FXP_REV_82557) {
603 * If MWI is enabled in the PCI configuration, and there
604 * is a valid cacheline size (8 or 16 dwords), then tell
605 * the board to turn on MWI.
607 if (val & PCIM_CMD_MWRICEN &&
608 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
609 sc->flags |= FXP_FLAG_MWI_ENABLE;
611 /* turn on the extended TxCB feature */
612 sc->flags |= FXP_FLAG_EXT_TXCB;
614 /* enable reception of long frames for VLAN */
615 sc->flags |= FXP_FLAG_LONG_PKT_EN;
621 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3);
622 device_printf(dev, "Ethernet address %6D%s\n",
623 sc->arpcom.ac_enaddr, ":",
624 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : "");
626 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
627 pci_get_vendor(dev), pci_get_device(dev),
628 pci_get_subvendor(dev), pci_get_subdevice(dev),
630 fxp_read_eeprom(sc, &data, 10, 1);
631 device_printf(dev, "Dynamic Standby mode is %s\n",
632 data & 0x02 ? "enabled" : "disabled");
636 * If this is only a 10Mbps device, then there is no MII, and
637 * the PHY will use a serial interface instead.
639 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
640 * doesn't have a programming interface of any sort. The
641 * media is sensed automatically based on how the link partner
642 * is configured. This is, in essence, manual configuration.
644 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
645 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
646 fxp_serial_ifmedia_sts);
647 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
648 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
650 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
652 device_printf(dev, "MII without any PHY!\n");
658 ifp = &sc->arpcom.ac_if;
659 if_initname(ifp, "fxp", device_get_unit(dev));
660 ifp->if_output = ether_output;
661 ifp->if_baudrate = 100000000;
662 ifp->if_init = fxp_init;
664 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
665 ifp->if_ioctl = fxp_ioctl;
666 ifp->if_start = fxp_start;
667 ifp->if_watchdog = fxp_watchdog;
670 * Attach the interface.
672 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
675 * Tell the upper layer(s) we support long frames.
677 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
680 * Let the system queue as many packets as we have available
683 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
689 device_printf(dev, "Failed to malloc memory\n");
698 * release all resources
701 fxp_release(struct fxp_softc *sc)
704 bus_generic_detach(sc->dev);
706 device_delete_child(sc->dev, sc->miibus);
709 free(sc->cbl_base, M_DEVBUF);
711 free(sc->fxp_stats, M_DEVBUF);
713 free(sc->mcsp, M_DEVBUF);
715 m_freem(sc->rfa_headm);
718 bus_teardown_intr(sc->dev, sc->irq, sc->ih);
720 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
722 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem);
724 sysctl_ctx_free(&sc->sysctl_ctx);
726 mtx_destroy(&sc->sc_mtx);
733 fxp_detach(device_t dev)
735 struct fxp_softc *sc = device_get_softc(dev);
738 /* disable interrupts */
739 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
744 * Stop DMA and drop transmit queue.
749 * Close down routes etc.
751 ether_ifdetach(&sc->arpcom.ac_if);
754 * Free all media structures.
756 ifmedia_removeall(&sc->sc_media);
760 /* Release our allocated resources. */
767 * Device shutdown routine. Called at system shutdown after sync. The
768 * main purpose of this routine is to shut off receiver DMA so that
769 * kernel memory doesn't get clobbered during warmboot.
772 fxp_shutdown(device_t dev)
775 * Make sure that DMA is disabled prior to reboot. Not doing
776 * do could allow DMA to corrupt kernel memory during the
777 * reboot before the driver initializes.
779 fxp_stop((struct fxp_softc *) device_get_softc(dev));
784 * Device suspend routine. Stop the interface and save some PCI
785 * settings in case the BIOS doesn't restore them properly on
789 fxp_suspend(device_t dev)
791 struct fxp_softc *sc = device_get_softc(dev);
798 for (i = 0; i < 5; i++)
799 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
800 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
801 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
802 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
803 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
812 * Device resume routine. Restore some PCI settings in case the BIOS
813 * doesn't, re-enable busmastering, and restart the interface if
817 fxp_resume(device_t dev)
819 struct fxp_softc *sc = device_get_softc(dev);
820 struct ifnet *ifp = &sc->sc_if;
821 u_int16_t pci_command;
826 fxp_powerstate_d0(dev);
828 /* better way to do this? */
829 for (i = 0; i < 5; i++)
830 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
831 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
832 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
833 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
834 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
836 /* reenable busmastering */
837 pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
838 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
839 pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
841 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
844 /* reinitialize interface if necessary */
845 if (ifp->if_flags & IFF_UP)
855 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
863 for (x = 1 << (length - 1); x; x >>= 1) {
865 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
867 reg = FXP_EEPROM_EECS;
868 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
870 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
872 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
878 * Read from the serial EEPROM. Basically, you manually shift in
879 * the read opcode (one bit at a time) and then shift in the address,
880 * and then you shift out the data (all of this one bit at a time).
881 * The word size is 16 bits, so you have to provide the address for
882 * every 16 bits of data.
885 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
890 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
892 * Shift in read opcode.
894 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
899 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
901 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
903 reg = FXP_EEPROM_EECS;
904 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
906 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
908 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
910 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
912 if (autosize && reg == 0) {
913 sc->eeprom_size = data;
921 reg = FXP_EEPROM_EECS;
922 for (x = 1 << 15; x; x >>= 1) {
923 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
925 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
927 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
930 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
937 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
942 * Erase/write enable.
944 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
945 fxp_eeprom_shiftin(sc, 0x4, 3);
946 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
947 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
950 * Shift in write opcode, address, data.
952 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
953 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
954 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
955 fxp_eeprom_shiftin(sc, data, 16);
956 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
959 * Wait for EEPROM to finish up.
961 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
963 for (i = 0; i < 1000; i++) {
964 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
968 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
971 * Erase/write disable.
973 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
974 fxp_eeprom_shiftin(sc, 0x4, 3);
975 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
976 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
983 * Figure out EEPROM size.
985 * 559's can have either 64-word or 256-word EEPROMs, the 558
986 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
987 * talks about the existance of 16 to 256 word EEPROMs.
989 * The only known sizes are 64 and 256, where the 256 version is used
990 * by CardBus cards to store CIS information.
992 * The address is shifted in msb-to-lsb, and after the last
993 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
994 * after which follows the actual data. We try to detect this zero, by
995 * probing the data-out bit in the EEPROM control register just after
996 * having shifted in a bit. If the bit is zero, we assume we've
997 * shifted enough address bits. The data-out should be tri-state,
998 * before this, which should translate to a logical one.
1001 fxp_autosize_eeprom(struct fxp_softc *sc)
1004 /* guess maximum size of 256 words */
1005 sc->eeprom_size = 8;
1008 (void) fxp_eeprom_getword(sc, 0, 1);
1012 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1016 for (i = 0; i < words; i++)
1017 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1021 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1025 for (i = 0; i < words; i++)
1026 fxp_eeprom_putword(sc, offset + i, data[i]);
1030 * Start packet transmission on the interface.
1033 fxp_start(struct ifnet *ifp)
1035 struct fxp_softc *sc = ifp->if_softc;
1036 struct fxp_cb_tx *txp;
1039 * See if we need to suspend xmit until the multicast filter
1040 * has been reprogrammed (which can only be done at the head
1041 * of the command chain).
1043 if (sc->need_mcsetup) {
1050 * We're finished if there is nothing more to add to the list or if
1051 * we're all filled up with buffers to transmit.
1052 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1053 * a NOP command when needed.
1055 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) {
1056 struct mbuf *m, *mb_head;
1060 * Grab a packet to transmit.
1062 IF_DEQUEUE(&ifp->if_snd, mb_head);
1065 * Get pointer to next available tx desc.
1067 txp = sc->cbl_last->next;
1070 * Go through each of the mbufs in the chain and initialize
1071 * the transmit buffer descriptors with the physical address
1072 * and size of the mbuf.
1075 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
1076 if (m->m_len != 0) {
1077 if (segment == FXP_NTXSEG)
1079 txp->tbd[segment].tb_addr =
1080 vtophys(mtod(m, vm_offset_t));
1081 txp->tbd[segment].tb_size = m->m_len;
1089 * We ran out of segments. We have to recopy this
1090 * mbuf chain first. Bail out if we can't get the
1093 MGETHDR(mn, M_DONTWAIT, MT_DATA);
1098 if (mb_head->m_pkthdr.len > MHLEN) {
1099 MCLGET(mn, M_DONTWAIT);
1100 if ((mn->m_flags & M_EXT) == 0) {
1106 m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
1108 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
1114 txp->tbd_number = segment;
1115 txp->mb_head = mb_head;
1117 if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1119 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1123 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1124 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
1126 * Set a 5 second timer just in case we don't hear
1127 * from the card again.
1131 txp->tx_threshold = tx_threshold;
1134 * Advance the end of list forward.
1139 * On platforms which can't access memory in 16-bit
1140 * granularities, we must prevent the card from DMA'ing
1141 * up the status while we update the command field.
1142 * This could cause us to overwrite the completion status.
1144 atomic_clear_short(&sc->cbl_last->cb_command,
1147 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
1148 #endif /*__alpha__*/
1152 * Advance the beginning of the list forward if there are
1153 * no other packets queued (when nothing is queued, cbl_first
1154 * sits on the last TxCB that was sent out).
1156 if (sc->tx_queued == 0)
1157 sc->cbl_first = txp;
1162 * Pass packet to bpf if there is a listener.
1165 bpf_mtap(ifp, mb_head);
1169 * We're finished. If we added to the list, issue a RESUME to get DMA
1170 * going again if suspended.
1174 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1178 #ifdef DEVICE_POLLING
1179 static poll_handler_t fxp_poll;
1182 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1184 struct fxp_softc *sc = ifp->if_softc;
1187 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1188 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1191 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1193 if (cmd == POLL_AND_CHECK_STATUS) {
1196 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1197 if (tmp == 0xff || tmp == 0)
1198 return; /* nothing to do */
1200 /* ack what we can */
1202 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1205 fxp_intr_body(sc, statack, count);
1207 #endif /* DEVICE_POLLING */
1210 * Process interface interrupts.
1215 struct fxp_softc *sc = xsc;
1218 #ifdef DEVICE_POLLING
1219 struct ifnet *ifp = &sc->sc_if;
1221 if (ifp->if_ipending & IFF_POLLING)
1223 if (ether_poll_register(fxp_poll, ifp)) {
1224 /* disable interrupts */
1225 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1226 fxp_poll(ifp, 0, 1);
1231 if (sc->suspended) {
1235 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1237 * It should not be possible to have all bits set; the
1238 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1239 * all bits are set, this may indicate that the card has
1240 * been physically ejected, so ignore it.
1242 if (statack == 0xff)
1246 * First ACK all the interrupts in this pass.
1248 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1249 fxp_intr_body(sc, statack, -1);
1254 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count)
1256 struct ifnet *ifp = &sc->sc_if;
1258 struct fxp_rfa *rfa;
1259 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1263 #ifdef DEVICE_POLLING
1264 /* Pick up a deferred RNR condition if `count' ran out last time. */
1265 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1266 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1272 * Free any finished transmit mbuf chains.
1274 * Handle the CNA event likt a CXTNO event. It used to
1275 * be that this event (control unit not ready) was not
1276 * encountered, but it is now with the SMPng modifications.
1277 * The exact sequence of events that occur when the interface
1278 * is brought up are different now, and if this event
1279 * goes unhandled, the configuration/rxfilter setup sequence
1280 * can stall for several seconds. The result is that no
1281 * packets go out onto the wire for about 5 to 10 seconds
1282 * after the interface is ifconfig'ed for the first time.
1284 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1285 struct fxp_cb_tx *txp;
1287 for (txp = sc->cbl_first; sc->tx_queued &&
1288 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1290 if (txp->mb_head != NULL) {
1291 m_freem(txp->mb_head);
1292 txp->mb_head = NULL;
1296 sc->cbl_first = txp;
1298 if (sc->tx_queued == 0) {
1299 if (sc->need_mcsetup)
1303 * Try to start more packets transmitting.
1305 if (ifp->if_snd.ifq_head != NULL)
1310 * Just return if nothing happened on the receive side.
1312 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1316 * Process receiver interrupts. If a no-resource (RNR)
1317 * condition exists, get whatever packets we can and
1318 * re-start the receiver.
1320 * When using polling, we do not process the list to completion,
1321 * so when we get an RNR interrupt we must defer the restart
1322 * until we hit the last buffer with the C bit set.
1323 * If we run out of cycles and rfa_headm has the C bit set,
1324 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1325 * that the info will be used in the subsequent polling cycle.
1329 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1330 RFA_ALIGNMENT_FUDGE);
1332 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1333 if (count >= 0 && count-- == 0) {
1335 /* Defer RNR processing until the next time. */
1336 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1341 #endif /* DEVICE_POLLING */
1343 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0)
1347 * Remove first packet from the chain.
1349 sc->rfa_headm = m->m_next;
1353 * Add a new buffer to the receive chain.
1354 * If this fails, the old buffer is recycled
1357 if (fxp_add_rfabuf(sc, m) == 0) {
1361 * Fetch packet length (the top 2 bits of
1362 * actual_size are flags set by the controller
1363 * upon completion), and drop the packet in case
1364 * of bogus length or CRC errors.
1366 total_len = rfa->actual_size & 0x3fff;
1367 if (total_len < sizeof(struct ether_header) ||
1368 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE -
1369 sizeof(struct fxp_rfa) ||
1370 rfa->rfa_status & FXP_RFA_STATUS_CRC) {
1374 m->m_pkthdr.len = m->m_len = total_len;
1375 ether_input(ifp, NULL, m);
1380 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1381 vtophys(sc->rfa_headm->m_ext.ext_buf) +
1382 RFA_ALIGNMENT_FUDGE);
1383 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1388 * Update packet in/out/collision statistics. The i82557 doesn't
1389 * allow you to access these counters without doing a fairly
1390 * expensive DMA to get _all_ of the statistics it maintains, so
1391 * we do this operation here only once per second. The statistics
1392 * counters in the kernel are updated from the previous dump-stats
1393 * DMA and then a new dump-stats DMA is started. The on-chip
1394 * counters are zeroed when the DMA completes. If we can't start
1395 * the DMA immediately, we don't wait - we just prepare to read
1396 * them again next time.
1401 struct fxp_softc *sc = xsc;
1402 struct ifnet *ifp = &sc->sc_if;
1403 struct fxp_stats *sp = sc->fxp_stats;
1404 struct fxp_cb_tx *txp;
1407 ifp->if_opackets += sp->tx_good;
1408 ifp->if_collisions += sp->tx_total_collisions;
1410 ifp->if_ipackets += sp->rx_good;
1411 sc->rx_idle_secs = 0;
1414 * Receiver's been idle for another second.
1420 sp->rx_alignment_errors +
1422 sp->rx_overrun_errors;
1424 * If any transmit underruns occured, bump up the transmit
1425 * threshold by another 512 bytes (64 * 8).
1427 if (sp->tx_underruns) {
1428 ifp->if_oerrors += sp->tx_underruns;
1429 if (tx_threshold < 192)
1434 * Release any xmit buffers that have completed DMA. This isn't
1435 * strictly necessary to do here, but it's advantagous for mbufs
1436 * with external storage to be released in a timely manner rather
1437 * than being defered for a potentially long time. This limits
1438 * the delay to a maximum of one second.
1440 for (txp = sc->cbl_first; sc->tx_queued &&
1441 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1443 if (txp->mb_head != NULL) {
1444 m_freem(txp->mb_head);
1445 txp->mb_head = NULL;
1449 sc->cbl_first = txp;
1451 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1452 * then assume the receiver has locked up and attempt to clear
1453 * the condition by reprogramming the multicast filter. This is
1454 * a work-around for a bug in the 82557 where the receiver locks
1455 * up if it gets certain types of garbage in the syncronization
1456 * bits prior to the packet header. This bug is supposed to only
1457 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1458 * mode as well (perhaps due to a 10/100 speed transition).
1460 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1461 sc->rx_idle_secs = 0;
1465 * If there is no pending command, start another stats
1466 * dump. Otherwise punt for now.
1468 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1470 * Start another stats dump.
1472 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1475 * A previous command is still waiting to be accepted.
1476 * Just zero our copy of the stats and wait for the
1477 * next timer event to update them.
1480 sp->tx_underruns = 0;
1481 sp->tx_total_collisions = 0;
1484 sp->rx_crc_errors = 0;
1485 sp->rx_alignment_errors = 0;
1486 sp->rx_rnr_errors = 0;
1487 sp->rx_overrun_errors = 0;
1489 if (sc->miibus != NULL)
1490 mii_tick(device_get_softc(sc->miibus));
1493 * Schedule another timeout one second from now.
1495 sc->stat_ch = timeout(fxp_tick, sc, hz);
1499 * Stop the interface. Cancels the statistics updater and resets
1503 fxp_stop(struct fxp_softc *sc)
1505 struct ifnet *ifp = &sc->sc_if;
1506 struct fxp_cb_tx *txp;
1509 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1512 #ifdef DEVICE_POLLING
1513 ether_poll_deregister(ifp);
1516 * Cancel stats updater.
1518 untimeout(fxp_tick, sc, sc->stat_ch);
1521 * Issue software reset, which also unloads the microcode.
1523 sc->flags &= ~FXP_FLAG_UCODE;
1524 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
1528 * Release any xmit buffers.
1532 for (i = 0; i < FXP_NTXCB; i++) {
1533 if (txp[i].mb_head != NULL) {
1534 m_freem(txp[i].mb_head);
1535 txp[i].mb_head = NULL;
1542 * Free all the receive buffers then reallocate/reinitialize
1544 if (sc->rfa_headm != NULL)
1545 m_freem(sc->rfa_headm);
1546 sc->rfa_headm = NULL;
1547 sc->rfa_tailm = NULL;
1548 for (i = 0; i < FXP_NRFABUFS; i++) {
1549 if (fxp_add_rfabuf(sc, NULL) != 0) {
1551 * This "can't happen" - we're at splimp()
1552 * and we just freed all the buffers we need
1555 panic("fxp_stop: no buffers!");
1561 * Watchdog/transmission transmit timeout handler. Called when a
1562 * transmission is started on the interface, but no interrupt is
1563 * received before the timeout. This usually indicates that the
1564 * card has wedged for some reason.
1567 fxp_watchdog(struct ifnet *ifp)
1569 struct fxp_softc *sc = ifp->if_softc;
1571 device_printf(sc->dev, "device timeout\n");
1580 struct fxp_softc *sc = xsc;
1581 struct ifnet *ifp = &sc->sc_if;
1582 struct fxp_cb_config *cbp;
1583 struct fxp_cb_ias *cb_ias;
1584 struct fxp_cb_tx *txp;
1585 struct fxp_cb_mcs *mcsp;
1590 * Cancel any pending I/O
1594 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1597 * Initialize base of CBL and RFA memory. Loading with zero
1598 * sets it up for regular linear addressing.
1600 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1601 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1604 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1607 * Initialize base of dump-stats buffer.
1610 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1611 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1614 * Attempt to load microcode if requested.
1616 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0)
1620 * Initialize the multicast address list.
1622 if (fxp_mc_addrs(sc)) {
1624 mcsp->cb_status = 0;
1625 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL;
1626 mcsp->link_addr = -1;
1628 * Start the multicast setup command.
1631 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
1632 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1633 /* ...and wait for it to complete. */
1634 fxp_dma_wait(&mcsp->cb_status, sc);
1638 * We temporarily use memory that contains the TxCB list to
1639 * construct the config CB. The TxCB list memory is rebuilt
1642 cbp = (struct fxp_cb_config *) sc->cbl_base;
1645 * This bcopy is kind of disgusting, but there are a bunch of must be
1646 * zero and must be one bits in this structure and this is the easiest
1647 * way to initialize them all to proper values.
1649 bcopy(fxp_cb_config_template,
1650 (void *)(uintptr_t)(volatile void *)&cbp->cb_status,
1651 sizeof(fxp_cb_config_template));
1654 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
1655 cbp->link_addr = -1; /* (no) next command */
1656 cbp->byte_count = 22; /* (22) bytes to config */
1657 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1658 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
1659 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
1660 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
1661 cbp->type_enable = 0; /* actually reserved */
1662 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
1663 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
1664 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
1665 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
1666 cbp->dma_mbce = 0; /* (disable) dma max counters */
1667 cbp->late_scb = 0; /* (don't) defer SCB update */
1668 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
1669 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
1670 cbp->ci_int = 1; /* interrupt on CU idle */
1671 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
1672 cbp->ext_stats_dis = 1; /* disable extended counters */
1673 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
1674 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm;
1675 cbp->disc_short_rx = !prm; /* discard short packets */
1676 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
1677 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
1678 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */
1679 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
1680 cbp->csma_dis = 0; /* (don't) disable link */
1681 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */
1682 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
1683 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
1684 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
1685 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
1686 cbp->nsai = 1; /* (don't) disable source addr insert */
1687 cbp->preamble_length = 2; /* (7 byte) preamble */
1688 cbp->loopback = 0; /* (don't) loopback */
1689 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
1690 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
1691 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
1692 cbp->promiscuous = prm; /* promiscuous mode */
1693 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
1694 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
1695 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
1696 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
1697 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
1699 cbp->stripping = !prm; /* truncate rx packet to byte count */
1700 cbp->padding = 1; /* (do) pad short tx packets */
1701 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
1702 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
1703 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
1704 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */
1705 /* must set wake_en in PMCSR also */
1706 cbp->force_fdx = 0; /* (don't) force full duplex */
1707 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
1708 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
1709 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
1711 if (sc->revision == FXP_REV_82557) {
1713 * The 82557 has no hardware flow control, the values
1714 * below are the defaults for the chip.
1716 cbp->fc_delay_lsb = 0;
1717 cbp->fc_delay_msb = 0x40;
1718 cbp->pri_fc_thresh = 3;
1720 cbp->rx_fc_restop = 0;
1721 cbp->rx_fc_restart = 0;
1723 cbp->pri_fc_loc = 1;
1725 cbp->fc_delay_lsb = 0x1f;
1726 cbp->fc_delay_msb = 0x01;
1727 cbp->pri_fc_thresh = 3;
1728 cbp->tx_fc_dis = 0; /* enable transmit FC */
1729 cbp->rx_fc_restop = 1; /* enable FC restop frames */
1730 cbp->rx_fc_restart = 1; /* enable FC restart frames */
1731 cbp->fc_filter = !prm; /* drop FC frames to host */
1732 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
1736 * Start the config command/DMA.
1739 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1740 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1741 /* ...and wait for it to complete. */
1742 fxp_dma_wait(&cbp->cb_status, sc);
1745 * Now initialize the station address. Temporarily use the TxCB
1746 * memory area like we did above for the config CB.
1748 cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1749 cb_ias->cb_status = 0;
1750 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
1751 cb_ias->link_addr = -1;
1752 bcopy(sc->arpcom.ac_enaddr,
1753 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr,
1754 sizeof(sc->arpcom.ac_enaddr));
1757 * Start the IAS (Individual Address Setup) command/DMA.
1760 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1761 /* ...and wait for it to complete. */
1762 fxp_dma_wait(&cb_ias->cb_status, sc);
1765 * Initialize transmit control block (TxCB) list.
1769 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1770 for (i = 0; i < FXP_NTXCB; i++) {
1771 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK;
1772 txp[i].cb_command = FXP_CB_COMMAND_NOP;
1774 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1775 if (sc->flags & FXP_FLAG_EXT_TXCB)
1776 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]);
1778 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1779 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1782 * Set the suspend flag on the first TxCB and start the control
1783 * unit. It will execute the NOP and then suspend.
1785 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S;
1786 sc->cbl_first = sc->cbl_last = txp;
1790 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1793 * Initialize receiver buffer area - RFA.
1796 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1797 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1798 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1801 * Set current media.
1803 if (sc->miibus != NULL)
1804 mii_mediachg(device_get_softc(sc->miibus));
1806 ifp->if_flags |= IFF_RUNNING;
1807 ifp->if_flags &= ~IFF_OACTIVE;
1810 * Enable interrupts.
1812 #ifdef DEVICE_POLLING
1814 * ... but only do that if we are not polling. And because (presumably)
1815 * the default is interrupts on, we need to disable them explicitly!
1817 if ( ifp->if_ipending & IFF_POLLING )
1818 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1820 #endif /* DEVICE_POLLING */
1821 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1825 * Start stats updater.
1827 sc->stat_ch = timeout(fxp_tick, sc, hz);
1831 fxp_serial_ifmedia_upd(struct ifnet *ifp)
1838 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1841 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
1845 * Change media according to request.
1848 fxp_ifmedia_upd(struct ifnet *ifp)
1850 struct fxp_softc *sc = ifp->if_softc;
1851 struct mii_data *mii;
1853 mii = device_get_softc(sc->miibus);
1859 * Notify the world which media we're using.
1862 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1864 struct fxp_softc *sc = ifp->if_softc;
1865 struct mii_data *mii;
1867 mii = device_get_softc(sc->miibus);
1869 ifmr->ifm_active = mii->mii_media_active;
1870 ifmr->ifm_status = mii->mii_media_status;
1872 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
1873 sc->cu_resume_bug = 1;
1875 sc->cu_resume_bug = 0;
1879 * Add a buffer to the end of the RFA buffer list.
1880 * Return 0 if successful, 1 for failure. A failure results in
1881 * adding the 'oldm' (if non-NULL) on to the end of the list -
1882 * tossing out its old contents and recycling it.
1883 * The RFA struct is stuck at the beginning of mbuf cluster and the
1884 * data pointer is fixed up to point just past it.
1887 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm)
1891 struct fxp_rfa *rfa, *p_rfa;
1893 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1894 if (m == NULL) { /* try to recycle the old mbuf instead */
1898 m->m_data = m->m_ext.ext_buf;
1902 * Move the data pointer up so that the incoming data packet
1903 * will be 32-bit aligned.
1905 m->m_data += RFA_ALIGNMENT_FUDGE;
1908 * Get a pointer to the base of the mbuf cluster and move
1909 * data start past it.
1911 rfa = mtod(m, struct fxp_rfa *);
1912 m->m_data += sizeof(struct fxp_rfa);
1913 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE);
1916 * Initialize the rest of the RFA. Note that since the RFA
1917 * is misaligned, we cannot store values directly. Instead,
1918 * we use an optimized, inline copy.
1921 rfa->rfa_status = 0;
1922 rfa->rfa_control = FXP_RFA_CONTROL_EL;
1923 rfa->actual_size = 0;
1926 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr);
1927 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr);
1930 * If there are other buffers already on the list, attach this
1931 * one to the end by fixing up the tail to point to this one.
1933 if (sc->rfa_headm != NULL) {
1934 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf +
1935 RFA_ALIGNMENT_FUDGE);
1936 sc->rfa_tailm->m_next = m;
1938 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr);
1939 p_rfa->rfa_control = 0;
1949 fxp_miibus_readreg(device_t dev, int phy, int reg)
1951 struct fxp_softc *sc = device_get_softc(dev);
1955 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1956 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
1958 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
1963 device_printf(dev, "fxp_miibus_readreg: timed out\n");
1965 return (value & 0xffff);
1969 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
1971 struct fxp_softc *sc = device_get_softc(dev);
1974 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1975 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
1978 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
1983 device_printf(dev, "fxp_miibus_writereg: timed out\n");
1987 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1989 struct fxp_softc *sc = ifp->if_softc;
1990 struct ifreq *ifr = (struct ifreq *)data;
1991 struct mii_data *mii;
2000 error = ether_ioctl(ifp, command, data);
2004 if (ifp->if_flags & IFF_ALLMULTI)
2005 sc->flags |= FXP_FLAG_ALL_MCAST;
2007 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2010 * If interface is marked up and not running, then start it.
2011 * If it is marked down and running, stop it.
2012 * XXX If it's up then re-initialize it. This is so flags
2013 * such as IFF_PROMISC are handled.
2015 if (ifp->if_flags & IFF_UP) {
2018 if (ifp->if_flags & IFF_RUNNING)
2025 if (ifp->if_flags & IFF_ALLMULTI)
2026 sc->flags |= FXP_FLAG_ALL_MCAST;
2028 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2030 * Multicast list has changed; set the hardware filter
2033 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2036 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2037 * again rather than else {}.
2039 if (sc->flags & FXP_FLAG_ALL_MCAST)
2046 if (sc->miibus != NULL) {
2047 mii = device_get_softc(sc->miibus);
2048 error = ifmedia_ioctl(ifp, ifr,
2049 &mii->mii_media, command);
2051 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2063 * Fill in the multicast address list and return number of entries.
2066 fxp_mc_addrs(struct fxp_softc *sc)
2068 struct fxp_cb_mcs *mcsp = sc->mcsp;
2069 struct ifnet *ifp = &sc->sc_if;
2070 struct ifmultiaddr *ifma;
2074 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2075 #if defined(__DragonFly__) || __FreeBSD_version < 500000
2076 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2078 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2080 if (ifma->ifma_addr->sa_family != AF_LINK)
2082 if (nmcasts >= MAXMCADDR) {
2083 sc->flags |= FXP_FLAG_ALL_MCAST;
2087 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2088 (void *)(uintptr_t)(volatile void *)
2089 &sc->mcsp->mc_addr[nmcasts][0], 6);
2093 mcsp->mc_cnt = nmcasts * 6;
2098 * Program the multicast filter.
2100 * We have an artificial restriction that the multicast setup command
2101 * must be the first command in the chain, so we take steps to ensure
2102 * this. By requiring this, it allows us to keep up the performance of
2103 * the pre-initialized command ring (esp. link pointers) by not actually
2104 * inserting the mcsetup command in the ring - i.e. its link pointer
2105 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2106 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2107 * lead into the regular TxCB ring when it completes.
2109 * This function must be called at splimp.
2112 fxp_mc_setup(struct fxp_softc *sc)
2114 struct fxp_cb_mcs *mcsp = sc->mcsp;
2115 struct ifnet *ifp = &sc->sc_if;
2119 * If there are queued commands, we must wait until they are all
2120 * completed. If we are already waiting, then add a NOP command
2121 * with interrupt option so that we're notified when all commands
2122 * have been completed - fxp_start() ensures that no additional
2123 * TX commands will be added when need_mcsetup is true.
2125 if (sc->tx_queued) {
2126 struct fxp_cb_tx *txp;
2129 * need_mcsetup will be true if we are already waiting for the
2130 * NOP command to be completed (see below). In this case, bail.
2132 if (sc->need_mcsetup)
2134 sc->need_mcsetup = 1;
2137 * Add a NOP command with interrupt so that we are notified
2138 * when all TX commands have been processed.
2140 txp = sc->cbl_last->next;
2141 txp->mb_head = NULL;
2143 txp->cb_command = FXP_CB_COMMAND_NOP |
2144 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2146 * Advance the end of list forward.
2148 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
2152 * Issue a resume in case the CU has just suspended.
2155 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2157 * Set a 5 second timer just in case we don't hear from the
2164 sc->need_mcsetup = 0;
2167 * Initialize multicast setup descriptor.
2169 mcsp->next = sc->cbl_base;
2170 mcsp->mb_head = NULL;
2171 mcsp->cb_status = 0;
2172 mcsp->cb_command = FXP_CB_COMMAND_MCAS |
2173 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2174 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
2175 (void) fxp_mc_addrs(sc);
2176 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
2180 * Wait until command unit is not active. This should never
2181 * be the case when nothing is queued, but make sure anyway.
2184 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2185 FXP_SCB_CUS_ACTIVE && --count)
2188 device_printf(sc->dev, "command queue timeout\n");
2193 * Start the multicast setup command.
2196 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
2197 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2203 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2204 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2205 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2206 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2207 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2208 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2210 #define UCODE(x) x, sizeof(x)
2216 u_short int_delay_offset;
2217 u_short bundle_max_offset;
2219 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2220 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2221 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2222 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2223 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2224 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2225 { FXP_REV_82550, UCODE(fxp_ucode_d102),
2226 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2227 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2228 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2229 { 0, NULL, 0, 0, 0 }
2233 fxp_load_ucode(struct fxp_softc *sc)
2236 struct fxp_cb_ucode *cbp;
2238 for (uc = ucode_table; uc->ucode != NULL; uc++)
2239 if (sc->revision == uc->revision)
2241 if (uc->ucode == NULL)
2243 cbp = (struct fxp_cb_ucode *)sc->cbl_base;
2245 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL;
2246 cbp->link_addr = -1; /* (no) next command */
2247 memcpy(cbp->ucode, uc->ucode, uc->length);
2248 if (uc->int_delay_offset)
2249 *(u_short *)&cbp->ucode[uc->int_delay_offset] =
2250 sc->tunable_int_delay + sc->tunable_int_delay / 2;
2251 if (uc->bundle_max_offset)
2252 *(u_short *)&cbp->ucode[uc->bundle_max_offset] =
2253 sc->tunable_bundle_max;
2255 * Download the ucode to the chip.
2258 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
2259 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2260 /* ...and wait for it to complete. */
2261 fxp_dma_wait(&cbp->cb_status, sc);
2262 device_printf(sc->dev,
2263 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
2264 sc->tunable_int_delay,
2265 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
2266 sc->flags |= FXP_FLAG_UCODE;
2270 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2274 value = *(int *)arg1;
2275 error = sysctl_handle_int(oidp, &value, 0, req);
2276 if (error || !req->newptr)
2278 if (value < low || value > high)
2280 *(int *)arg1 = value;
2285 * Interrupt delay is expressed in microseconds, a multiplier is used
2286 * to convert this to the appropriate clock ticks before using.
2289 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
2291 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
2295 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
2297 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));