2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMATES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/alc/if_alcreg.h,v 1.1 2009/06/10 02:07:58 yongari Exp $
35 * Atheros Communucations, Inc. PCI vendor ID
37 #define VENDORID_ATHEROS 0x1969
40 * Atheros AR813x/AR815x device ID
42 #define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */
43 #define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */
44 #define DEVICEID_ATHEROS_AR8151 0x1073 /* L1D V1.0 */
45 #define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */
46 #define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */
47 #define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */
49 #define ATHEROS_AR8152_B_V10 0xC0
50 #define ATHEROS_AR8152_B_V11 0xC1
53 * From FreeBSD dev/pci/pcireg.h
55 * PCIM_xxx: mask to locate subfield in register
56 * PCIR_xxx: config register offset
58 #define PCIR_EXPRESS_DEVICE_CTL 0x8
59 #define PCIR_EXPRESS_LINK_CAP 0xc
60 #define PCIR_EXPRESS_LINK_CTL 0x10
61 #define PCIM_EXP_CTL_MAX_READ_REQUEST 0x7000
62 #define PCIM_EXP_CTL_MAX_PAYLOAD 0x00e0
63 #define PCIM_LINK_CAP_ASPM 0x00000c00
65 /* 0x0000 - 0x02FF : PCIe configuration space */
67 #define ALC_PEX_UNC_ERR_SEV 0x10C
68 #define PEX_UNC_ERR_SEV_TRN 0x00000001
69 #define PEX_UNC_ERR_SEV_DLP 0x00000010
70 #define PEX_UNC_ERR_SEV_PSN_TLP 0x00001000
71 #define PEX_UNC_ERR_SEV_FCP 0x00002000
72 #define PEX_UNC_ERR_SEV_CPL_TO 0x00004000
73 #define PEX_UNC_ERR_SEV_CA 0x00008000
74 #define PEX_UNC_ERR_SEV_UC 0x00010000
75 #define PEX_UNC_ERR_SEV_ROV 0x00020000
76 #define PEX_UNC_ERR_SEV_MLFP 0x00040000
77 #define PEX_UNC_ERR_SEV_ECRC 0x00080000
78 #define PEX_UNC_ERR_SEV_UR 0x00100000
80 #define ALC_TWSI_CFG 0x218
81 #define TWSI_CFG_SW_LD_START 0x00000800
82 #define TWSI_CFG_HW_LD_START 0x00001000
83 #define TWSI_CFG_LD_EXIST 0x00400000
85 #define ALC_PCIE_PHYMISC 0x1000
86 #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004
88 #define ALC_PCIE_PHYMISC2 0x1004
89 #define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000
90 #define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000
91 #define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16
92 #define PCIE_PHYMISC2_SERDES_TH_SHIFT 18
94 #define ALC_TWSI_DEBUG 0x1108
95 #define TWSI_DEBUG_DEV_EXIST 0x20000000
97 #define ALC_EEPROM_CFG 0x12C0
98 #define EEPROM_CFG_DATA_HI_MASK 0x0000FFFF
99 #define EEPROM_CFG_ADDR_MASK 0x03FF0000
100 #define EEPROM_CFG_ACK 0x40000000
101 #define EEPROM_CFG_RW 0x80000000
102 #define EEPROM_CFG_DATA_HI_SHIFT 0
103 #define EEPROM_CFG_ADDR_SHIFT 16
105 #define ALC_EEPROM_DATA_LO 0x12C4
107 #define ALC_OPT_CFG 0x12F0
108 #define OPT_CFG_CLK_ENB 0x00000002
110 #define ALC_PM_CFG 0x12F8
111 #define PM_CFG_SERDES_ENB 0x00000001
112 #define PM_CFG_RBER_ENB 0x00000002
113 #define PM_CFG_CLK_REQ_ENB 0x00000004
114 #define PM_CFG_ASPM_L1_ENB 0x00000008
115 #define PM_CFG_SERDES_L1_ENB 0x00000010
116 #define PM_CFG_SERDES_PLL_L1_ENB 0x00000020
117 #define PM_CFG_SERDES_PD_EX_L1 0x00000040
118 #define PM_CFG_SERDES_BUDS_RX_L1_ENB 0x00000080
119 #define PM_CFG_L0S_ENTRY_TIMER_MASK 0x00000F00
120 #define PM_CFG_ASPM_L0S_ENB 0x00001000
121 #define PM_CFG_CLK_SWH_L1 0x00002000
122 #define PM_CFG_CLK_PWM_VER1_1 0x00004000
123 #define PM_CFG_PCIE_RECV 0x00008000
124 #define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000
125 #define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000
126 #define PM_CFG_LCKDET_TIMER_MASK 0x3F000000
127 #define PM_CFG_EN_BUFS_RX_L0S 0x10000000
128 #define PM_CFG_SA_DLY_ENB 0x20000000
129 #define PM_CFG_MAC_ASPM_CHK 0x40000000
130 #define PM_CFG_HOTRST 0x80000000
131 #define PM_CFG_L0S_ENTRY_TIMER_SHIFT 8
132 #define PM_CFG_L1_ENTRY_TIMER_SHIFT 16
133 #define PM_CFG_PM_REQ_TIMER_SHIFT 20
134 #define PM_CFG_LCKDET_TIMER_SHIFT 24
136 #define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6
137 #define PM_CFG_L1_ENTRY_TIMER_DEFAULT 12
138 #define PM_CFG_PM_REQ_TIMER_DEFAULT 1
140 #define ALC_LTSSM_ID_CFG 0x12FC
141 #define LTSSM_ID_WRO_ENB 0x00001000
143 #define ALC_MASTER_CFG 0x1400
144 #define MASTER_RESET 0x00000001
145 #define MASTER_TEST_MODE_MASK 0x0000000C
146 #define MASTER_BERT_START 0x00000010
147 #define MASTER_OOB_DIS_OFF 0x00000040
148 #define MASTER_SA_TIMER_ENB 0x00000080
149 #define MASTER_MTIMER_ENB 0x00000100
150 #define MASTER_MANUAL_INTR_ENB 0x00000200
151 #define MASTER_IM_TX_TIMER_ENB 0x00000400
152 #define MASTER_IM_RX_TIMER_ENB 0x00000800
153 #define MASTER_CLK_SEL_DIS 0x00001000
154 #define MASTER_CLK_SWH_MODE 0x00002000
155 #define MASTER_INTR_RD_CLR 0x00004000
156 #define MASTER_CHIP_REV_MASK 0x00FF0000
157 #define MASTER_CHIP_ID_MASK 0x7F000000
158 #define MASTER_OTP_SEL 0x80000000
159 #define MASTER_TEST_MODE_SHIFT 2
160 #define MASTER_CHIP_REV_SHIFT 16
161 #define MASTER_CHIP_ID_SHIFT 24
163 /* Number of ticks per usec for AR813x/AR815x. */
164 #define ALC_TICK_USECS 2
165 #define ALC_USECS(x) ((x) / ALC_TICK_USECS)
167 #define ALC_MANUAL_TIMER 0x1404
169 #define ALC_IM_TIMER 0x1408
170 #define IM_TIMER_TX_MASK 0x0000FFFF
171 #define IM_TIMER_RX_MASK 0xFFFF0000
172 #define IM_TIMER_TX_SHIFT 0
173 #define IM_TIMER_RX_SHIFT 16
174 #define ALC_IM_TIMER_MIN 0
175 #define ALC_IM_TIMER_MAX 130000 /* 130ms */
177 * 100us will ensure alc(4) wouldn't generate more than 10000 Rx
178 * interrupts in a second.
180 #define ALC_IM_RX_TIMER_DEFAULT 100 /* 100us */
182 * alc(4) does not rely on Tx completion interrupts, so set it
183 * somewhat large value to reduce Tx completion interrupts.
185 #define ALC_IM_TX_TIMER_DEFAULT 1000 /* 1ms */
187 #define ALC_GPHY_CFG 0x140C /* 16bits */
188 #define GPHY_CFG_EXT_RESET 0x0001
189 #define GPHY_CFG_RTL_MODE 0x0002
190 #define GPHY_CFG_LED_MODE 0x0004
191 #define GPHY_CFG_ANEG_NOW 0x0008
192 #define GPHY_CFG_RECV_ANEG 0x0010
193 #define GPHY_CFG_GATE_25M_ENB 0x0020
194 #define GPHY_CFG_LPW_EXIT 0x0040
195 #define GPHY_CFG_PHY_IDDQ 0x0080
196 #define GPHY_CFG_PHY_IDDQ_DIS 0x0100
197 #define GPHY_CFG_PCLK_SEL_DIS 0x0200
198 #define GPHY_CFG_HIB_EN 0x0400
199 #define GPHY_CFG_HIB_PULSE 0x0800
200 #define GPHY_CFG_SEL_ANA_RESET 0x1000
201 #define GPHY_CFG_PHY_PLL_ON 0x2000
202 #define GPHY_CFG_PWDOWN_HW 0x4000
203 #define GPHY_CFG_PHY_PLL_BYPASS 0x8000
205 #define ALC_IDLE_STATUS 0x1410
206 #define IDLE_STATUS_RXMAC 0x00000001
207 #define IDLE_STATUS_TXMAC 0x00000002
208 #define IDLE_STATUS_RXQ 0x00000004
209 #define IDLE_STATUS_TXQ 0x00000008
210 #define IDLE_STATUS_DMARD 0x00000010
211 #define IDLE_STATUS_DMAWR 0x00000020
212 #define IDLE_STATUS_SMB 0x00000040
213 #define IDLE_STATUS_CMB 0x00000080
215 #define ALC_MDIO 0x1414
216 #define MDIO_DATA_MASK 0x0000FFFF
217 #define MDIO_REG_ADDR_MASK 0x001F0000
218 #define MDIO_OP_READ 0x00200000
219 #define MDIO_OP_WRITE 0x00000000
220 #define MDIO_SUP_PREAMBLE 0x00400000
221 #define MDIO_OP_EXECUTE 0x00800000
222 #define MDIO_CLK_25_4 0x00000000
223 #define MDIO_CLK_25_6 0x02000000
224 #define MDIO_CLK_25_8 0x03000000
225 #define MDIO_CLK_25_10 0x04000000
226 #define MDIO_CLK_25_14 0x05000000
227 #define MDIO_CLK_25_20 0x06000000
228 #define MDIO_CLK_25_28 0x07000000
229 #define MDIO_OP_BUSY 0x08000000
230 #define MDIO_AP_ENB 0x10000000
231 #define MDIO_DATA_SHIFT 0
232 #define MDIO_REG_ADDR_SHIFT 16
234 #define MDIO_REG_ADDR(x) \
235 (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK)
236 /* Default PHY address. */
237 #define ALC_PHY_ADDR 0
239 #define ALC_PHY_STATUS 0x1418
240 #define PHY_STATUS_RECV_ENB 0x00000001
241 #define PHY_STATUS_GENERAL_MASK 0x0000FFFF
242 #define PHY_STATUS_OE_PWSP_MASK 0x07FF0000
243 #define PHY_STATUS_LPW_STATE 0x80000000
244 #define PHY_STATIS_OE_PWSP_SHIFT 16
246 /* Packet memory BIST. */
247 #define ALC_BIST0 0x141C
248 #define BIST0_ENB 0x00000001
249 #define BIST0_SRAM_FAIL 0x00000002
250 #define BIST0_FUSE_FLAG 0x00000004
252 /* PCIe retry buffer BIST. */
253 #define ALC_BIST1 0x1420
254 #define BIST1_ENB 0x00000001
255 #define BIST1_SRAM_FAIL 0x00000002
256 #define BIST1_FUSE_FLAG 0x00000004
258 #define ALC_SERDES_LOCK 0x1424
259 #define SERDES_LOCK_DET 0x00000001
260 #define SERDES_LOCK_DET_ENB 0x00000002
261 #define SERDES_MAC_CLK_SLOWDOWN 0x00020000
262 #define SERDES_PHY_CLK_SLOWDOWN 0x00040000
264 #define ALC_MAC_CFG 0x1480
265 #define MAC_CFG_TX_ENB 0x00000001
266 #define MAC_CFG_RX_ENB 0x00000002
267 #define MAC_CFG_TX_FC 0x00000004
268 #define MAC_CFG_RX_FC 0x00000008
269 #define MAC_CFG_LOOP 0x00000010
270 #define MAC_CFG_FULL_DUPLEX 0x00000020
271 #define MAC_CFG_TX_CRC_ENB 0x00000040
272 #define MAC_CFG_TX_AUTO_PAD 0x00000080
273 #define MAC_CFG_TX_LENCHK 0x00000100
274 #define MAC_CFG_RX_JUMBO_ENB 0x00000200
275 #define MAC_CFG_PREAMBLE_MASK 0x00003C00
276 #define MAC_CFG_VLAN_TAG_STRIP 0x00004000
277 #define MAC_CFG_PROMISC 0x00008000
278 #define MAC_CFG_TX_PAUSE 0x00010000
279 #define MAC_CFG_SCNT 0x00020000
280 #define MAC_CFG_SYNC_RST_TX 0x00040000
281 #define MAC_CFG_SIM_RST_TX 0x00080000
282 #define MAC_CFG_SPEED_MASK 0x00300000
283 #define MAC_CFG_SPEED_10_100 0x00100000
284 #define MAC_CFG_SPEED_1000 0x00200000
285 #define MAC_CFG_DBG_TX_BACKOFF 0x00400000
286 #define MAC_CFG_TX_JUMBO_ENB 0x00800000
287 #define MAC_CFG_RXCSUM_ENB 0x01000000
288 #define MAC_CFG_ALLMULTI 0x02000000
289 #define MAC_CFG_BCAST 0x04000000
290 #define MAC_CFG_DBG 0x08000000
291 #define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000
292 #define MAC_CFG_HASH_ALG_CRC32 0x20000000
293 #define MAC_CFG_SPEED_MODE_SW 0x40000000
294 #define MAC_CFG_PREAMBLE_SHIFT 10
295 #define MAC_CFG_PREAMBLE_DEFAULT 7
297 #define ALC_IPG_IFG_CFG 0x1484
298 #define IPG_IFG_IPGT_MASK 0x0000007F
299 #define IPG_IFG_MIFG_MASK 0x0000FF00
300 #define IPG_IFG_IPG1_MASK 0x007F0000
301 #define IPG_IFG_IPG2_MASK 0x7F000000
302 #define IPG_IFG_IPGT_SHIFT 0
303 #define IPG_IFG_IPGT_DEFAULT 0x60
304 #define IPG_IFG_MIFG_SHIFT 8
305 #define IPG_IFG_MIFG_DEFAULT 0x50
306 #define IPG_IFG_IPG1_SHIFT 16
307 #define IPG_IFG_IPG1_DEFAULT 0x40
308 #define IPG_IFG_IPG2_SHIFT 24
309 #define IPG_IFG_IPG2_DEFAULT 0x60
311 /* Station address. */
312 #define ALC_PAR0 0x1488
313 #define ALC_PAR1 0x148C
315 /* 64bit multicast hash register. */
316 #define ALC_MAR0 0x1490
317 #define ALC_MAR1 0x1494
319 /* half-duplex parameter configuration. */
320 #define ALC_HDPX_CFG 0x1498
321 #define HDPX_CFG_LCOL_MASK 0x000003FF
322 #define HDPX_CFG_RETRY_MASK 0x0000F000
323 #define HDPX_CFG_EXC_DEF_EN 0x00010000
324 #define HDPX_CFG_NO_BACK_C 0x00020000
325 #define HDPX_CFG_NO_BACK_P 0x00040000
326 #define HDPX_CFG_ABEBE 0x00080000
327 #define HDPX_CFG_ABEBT_MASK 0x00F00000
328 #define HDPX_CFG_JAMIPG_MASK 0x0F000000
329 #define HDPX_CFG_LCOL_SHIFT 0
330 #define HDPX_CFG_LCOL_DEFAULT 0x37
331 #define HDPX_CFG_RETRY_SHIFT 12
332 #define HDPX_CFG_RETRY_DEFAULT 0x0F
333 #define HDPX_CFG_ABEBT_SHIFT 20
334 #define HDPX_CFG_ABEBT_DEFAULT 0x0A
335 #define HDPX_CFG_JAMIPG_SHIFT 24
336 #define HDPX_CFG_JAMIPG_DEFAULT 0x07
338 #define ALC_FRAME_SIZE 0x149C
340 #define ALC_WOL_CFG 0x14A0
341 #define WOL_CFG_PATTERN 0x00000001
342 #define WOL_CFG_PATTERN_ENB 0x00000002
343 #define WOL_CFG_MAGIC 0x00000004
344 #define WOL_CFG_MAGIC_ENB 0x00000008
345 #define WOL_CFG_LINK_CHG 0x00000010
346 #define WOL_CFG_LINK_CHG_ENB 0x00000020
347 #define WOL_CFG_PATTERN_DET 0x00000100
348 #define WOL_CFG_MAGIC_DET 0x00000200
349 #define WOL_CFG_LINK_CHG_DET 0x00000400
350 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000
351 #define WOL_CFG_PATTERN0 0x00010000
352 #define WOL_CFG_PATTERN1 0x00020000
353 #define WOL_CFG_PATTERN2 0x00040000
354 #define WOL_CFG_PATTERN3 0x00080000
355 #define WOL_CFG_PATTERN4 0x00100000
356 #define WOL_CFG_PATTERN5 0x00200000
357 #define WOL_CFG_PATTERN6 0x00400000
359 /* WOL pattern length. */
360 #define ALC_PATTERN_CFG0 0x14A4
361 #define PATTERN_CFG_0_LEN_MASK 0x0000007F
362 #define PATTERN_CFG_1_LEN_MASK 0x00007F00
363 #define PATTERN_CFG_2_LEN_MASK 0x007F0000
364 #define PATTERN_CFG_3_LEN_MASK 0x7F000000
366 #define ALC_PATTERN_CFG1 0x14A8
367 #define PATTERN_CFG_4_LEN_MASK 0x0000007F
368 #define PATTERN_CFG_5_LEN_MASK 0x00007F00
369 #define PATTERN_CFG_6_LEN_MASK 0x007F0000
372 #define ALC_RSS_KEY0 0x14B0
374 #define ALC_RSS_KEY1 0x14B4
376 #define ALC_RSS_KEY2 0x14B8
378 #define ALC_RSS_KEY3 0x14BC
380 #define ALC_RSS_KEY4 0x14C0
382 #define ALC_RSS_KEY5 0x14C4
384 #define ALC_RSS_KEY6 0x14C8
386 #define ALC_RSS_KEY7 0x14CC
388 #define ALC_RSS_KEY8 0x14D0
390 #define ALC_RSS_KEY9 0x14D4
392 #define ALC_RSS_IDT_TABLE0 0x14E0
394 #define ALC_RSS_IDT_TABLE1 0x14E4
396 #define ALC_RSS_IDT_TABLE2 0x14E8
398 #define ALC_RSS_IDT_TABLE3 0x14EC
400 #define ALC_RSS_IDT_TABLE4 0x14F0
402 #define ALC_RSS_IDT_TABLE5 0x14F4
404 #define ALC_RSS_IDT_TABLE6 0x14F8
406 #define ALC_RSS_IDT_TABLE7 0x14FC
408 #define ALC_SRAM_RD0_ADDR 0x1500
410 #define ALC_SRAM_RD1_ADDR 0x1504
412 #define ALC_SRAM_RD2_ADDR 0x1508
414 #define ALC_SRAM_RD3_ADDR 0x150C
416 #define RD_HEAD_ADDR_MASK 0x000003FF
417 #define RD_TAIL_ADDR_MASK 0x03FF0000
418 #define RD_HEAD_ADDR_SHIFT 0
419 #define RD_TAIL_ADDR_SHIFT 16
421 #define ALC_RD_NIC_LEN0 0x1510 /* 8 bytes unit */
422 #define RD_NIC_LEN_MASK 0x000003FF
424 #define ALC_RD_NIC_LEN1 0x1514
426 #define ALC_SRAM_TD_ADDR 0x1518
427 #define TD_HEAD_ADDR_MASK 0x000003FF
428 #define TD_TAIL_ADDR_MASK 0x03FF0000
429 #define TD_HEAD_ADDR_SHIFT 0
430 #define TD_TAIL_ADDR_SHIFT 16
432 #define ALC_SRAM_TD_LEN 0x151C /* 8 bytes unit */
433 #define SRAM_TD_LEN_MASK 0x000003FF
435 #define ALC_SRAM_RX_FIFO_ADDR 0x1520
437 #define ALC_SRAM_RX_FIFO_LEN 0x1524
439 #define ALC_SRAM_TX_FIFO_ADDR 0x1528
441 #define ALC_SRAM_TX_FIFO_LEN 0x152C
443 #define ALC_SRAM_TCPH_ADDR 0x1530
444 #define SRAM_TCPH_ADDR_MASK 0x00000FFF
445 #define SRAM_PATH_ADDR_MASK 0x0FFF0000
446 #define SRAM_TCPH_ADDR_SHIFT 0
447 #define SRAM_PKTH_ADDR_SHIFT 16
449 #define ALC_DMA_BLOCK 0x1534
450 #define DMA_BLOCK_LOAD 0x00000001
452 #define ALC_RX_BASE_ADDR_HI 0x1540
454 #define ALC_TX_BASE_ADDR_HI 0x1544
456 #define ALC_SMB_BASE_ADDR_HI 0x1548
458 #define ALC_SMB_BASE_ADDR_LO 0x154C
460 #define ALC_RD0_HEAD_ADDR_LO 0x1550
462 #define ALC_RD1_HEAD_ADDR_LO 0x1554
464 #define ALC_RD2_HEAD_ADDR_LO 0x1558
466 #define ALC_RD3_HEAD_ADDR_LO 0x155C
468 #define ALC_RD_RING_CNT 0x1560
469 #define RD_RING_CNT_MASK 0x00000FFF
470 #define RD_RING_CNT_SHIFT 0
472 #define ALC_RX_BUF_SIZE 0x1564
473 #define RX_BUF_SIZE_MASK 0x0000FFFF
475 * If larger buffer size than 1536 is specified the controller
476 * will be locked up. This is hardware limitation.
478 #define RX_BUF_SIZE_MAX 1536
480 #define ALC_RRD0_HEAD_ADDR_LO 0x1568
482 #define ALC_RRD1_HEAD_ADDR_LO 0x156C
484 #define ALC_RRD2_HEAD_ADDR_LO 0x1570
486 #define ALC_RRD3_HEAD_ADDR_LO 0x1574
488 #define ALC_RRD_RING_CNT 0x1578
489 #define RRD_RING_CNT_MASK 0x00000FFF
490 #define RRD_RING_CNT_SHIFT 0
492 #define ALC_TDH_HEAD_ADDR_LO 0x157C
494 #define ALC_TDL_HEAD_ADDR_LO 0x1580
496 #define ALC_TD_RING_CNT 0x1584
497 #define TD_RING_CNT_MASK 0x0000FFFF
498 #define TD_RING_CNT_SHIFT 0
500 #define ALC_CMB_BASE_ADDR_LO 0x1588
502 #define ALC_TXQ_CFG 0x1590
503 #define TXQ_CFG_TD_BURST_MASK 0x0000000F
504 #define TXQ_CFG_IP_OPTION_ENB 0x00000010
505 #define TXQ_CFG_ENB 0x00000020
506 #define TXQ_CFG_ENHANCED_MODE 0x00000040
507 #define TXQ_CFG_8023_ENB 0x00000080
508 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000
509 #define TXQ_CFG_TD_BURST_SHIFT 0
510 #define TXQ_CFG_TD_BURST_DEFAULT 5
511 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16
513 #define ALC_TSO_OFFLOAD_THRESH 0x1594 /* 8 bytes unit */
514 #define TSO_OFFLOAD_THRESH_MASK 0x000007FF
515 #define TSO_OFFLOAD_THRESH_SHIFT 0
516 #define TSO_OFFLOAD_THRESH_UNIT 8
517 #define TSO_OFFLOAD_THRESH_UNIT_SHIFT 3
519 #define ALC_TXF_WATER_MARK 0x1598 /* 8 bytes unit */
520 #define TXF_WATER_MARK_HI_MASK 0x00000FFF
521 #define TXF_WATER_MARK_LO_MASK 0x0FFF0000
522 #define TXF_WATER_MARK_BURST_ENB 0x80000000
523 #define TXF_WATER_MARK_LO_SHIFT 0
524 #define TXF_WATER_MARK_HI_SHIFT 16
526 #define ALC_THROUGHPUT_MON 0x159C
527 #define THROUGHPUT_MON_RATE_MASK 0x00000003
528 #define THROUGHPUT_MON_ENB 0x00000080
529 #define THROUGHPUT_MON_RATE_SHIFT 0
531 #define ALC_RXQ_CFG 0x15A0
532 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK 0x00000003
533 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE 0x00000000
534 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M 0x00000001
535 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M 0x00000002
536 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M 0x00000003
537 #define RXQ_CFG_QUEUE1_ENB 0x00000010
538 #define RXQ_CFG_QUEUE2_ENB 0x00000020
539 #define RXQ_CFG_QUEUE3_ENB 0x00000040
540 #define RXQ_CFG_IPV6_CSUM_ENB 0x00000080
541 #define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00
542 #define RXQ_CFG_RSS_HASH_IPV4 0x00010000
543 #define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000
544 #define RXQ_CFG_RSS_HASH_IPV6 0x00040000
545 #define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000
546 #define RXQ_CFG_RD_BURST_MASK 0x03F00000
547 #define RXQ_CFG_RSS_MODE_DIS 0x00000000
548 #define RXQ_CFG_RSS_MODE_SQSINT 0x04000000
549 #define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000
550 #define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000
551 #define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000
552 #define RXQ_CFG_RSS_HASH_ENB 0x20000000
553 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000
554 #define RXQ_CFG_QUEUE0_ENB 0x80000000
555 #define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8
556 #define RXQ_CFG_RD_BURST_DEFAULT 8
557 #define RXQ_CFG_RD_BURST_SHIFT 20
558 #define RXQ_CFG_ENB \
559 (RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | \
560 RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB)
562 #define ALC_RX_RD_FREE_THRESH 0x15A4 /* 8 bytes unit. */
563 #define RX_RD_FREE_THRESH_HI_MASK 0x0000003F
564 #define RX_RD_FREE_THRESH_LO_MASK 0x00000FC0
565 #define RX_RD_FREE_THRESH_HI_SHIFT 0
566 #define RX_RD_FREE_THRESH_LO_SHIFT 6
567 #define RX_RD_FREE_THRESH_HI_DEFAULT 16
568 #define RX_RD_FREE_THRESH_LO_DEFAULT 8
570 #define ALC_RX_FIFO_PAUSE_THRESH 0x15A8
571 #define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF
572 #define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000
573 #define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0
574 #define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16
576 #define ALC_RD_DMA_CFG 0x15AC
577 #define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */
578 #define RD_DMA_CFG_TIMER_MASK 0xFFFF0000
579 #define RD_DMA_CFG_THRESH_SHIFT 0
580 #define RD_DMA_CFG_TIMER_SHIFT 16
581 #define RD_DMA_CFG_THRESH_DEFAULT 0x100
582 #define RD_DMA_CFG_TIMER_DEFAULT 0
583 #define RD_DMA_CFG_TICK_USECS 8
584 #define ALC_RD_DMA_CFG_USECS(x) ((x) / RD_DMA_CFG_TICK_USECS)
586 #define ALC_RSS_HASH_VALUE 0x15B0
588 #define ALC_RSS_HASH_FLAG 0x15B4
590 #define ALC_RSS_CPU 0x15B8
592 #define ALC_DMA_CFG 0x15C0
593 #define DMA_CFG_IN_ORDER 0x00000001
594 #define DMA_CFG_ENH_ORDER 0x00000002
595 #define DMA_CFG_OUT_ORDER 0x00000004
596 #define DMA_CFG_RCB_64 0x00000000
597 #define DMA_CFG_RCB_128 0x00000008
598 #define DMA_CFG_RD_BURST_128 0x00000000
599 #define DMA_CFG_RD_BURST_256 0x00000010
600 #define DMA_CFG_RD_BURST_512 0x00000020
601 #define DMA_CFG_RD_BURST_1024 0x00000030
602 #define DMA_CFG_RD_BURST_2048 0x00000040
603 #define DMA_CFG_RD_BURST_4096 0x00000050
604 #define DMA_CFG_WR_BURST_128 0x00000000
605 #define DMA_CFG_WR_BURST_256 0x00000080
606 #define DMA_CFG_WR_BURST_512 0x00000100
607 #define DMA_CFG_WR_BURST_1024 0x00000180
608 #define DMA_CFG_WR_BURST_2048 0x00000200
609 #define DMA_CFG_WR_BURST_4096 0x00000280
610 #define DMA_CFG_RD_REQ_PRI 0x00000400
611 #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800
612 #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000
613 #define DMA_CFG_CMB_ENB 0x00100000
614 #define DMA_CFG_SMB_ENB 0x00200000
615 #define DMA_CFG_CMB_NOW 0x00400000
616 #define DMA_CFG_SMB_DIS 0x01000000
617 #define DMA_CFG_SMB_NOW 0x80000000
618 #define DMA_CFG_RD_BURST_MASK 0x07
619 #define DMA_CFG_RD_BURST_SHIFT 4
620 #define DMA_CFG_WR_BURST_MASK 0x07
621 #define DMA_CFG_WR_BURST_SHIFT 7
622 #define DMA_CFG_RD_DELAY_CNT_SHIFT 11
623 #define DMA_CFG_WR_DELAY_CNT_SHIFT 16
624 #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15
625 #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4
627 #define ALC_SMB_STAT_TIMER 0x15C4
628 #define SMB_STAT_TIMER_MASK 0x00FFFFFF
629 #define SMB_STAT_TIMER_SHIFT 0
631 #define ALC_CMB_TD_THRESH 0x15C8
632 #define CMB_TD_THRESH_MASK 0x0000FFFF
633 #define CMB_TD_THRESH_SHIFT 0
635 #define ALC_CMB_TX_TIMER 0x15CC
636 #define CMB_TX_TIMER_MASK 0x0000FFFF
637 #define CMB_TX_TIMER_SHIFT 0
639 #define ALC_MBOX_RD0_PROD_IDX 0x15E0
641 #define ALC_MBOX_RD1_PROD_IDX 0x15E4
643 #define ALC_MBOX_RD2_PROD_IDX 0x15E8
645 #define ALC_MBOX_RD3_PROD_IDX 0x15EC
647 #define ALC_MBOX_RD_PROD_MASK 0x0000FFFF
648 #define MBOX_RD_PROD_SHIFT 0
650 #define ALC_MBOX_TD_PROD_IDX 0x15F0
651 #define MBOX_TD_PROD_HI_IDX_MASK 0x0000FFFF
652 #define MBOX_TD_PROD_LO_IDX_MASK 0xFFFF0000
653 #define MBOX_TD_PROD_HI_IDX_SHIFT 0
654 #define MBOX_TD_PROD_LO_IDX_SHIFT 16
656 #define ALC_MBOX_TD_CONS_IDX 0x15F4
657 #define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF
658 #define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000
659 #define MBOX_TD_CONS_HI_IDX_SHIFT 0
660 #define MBOX_TD_CONS_LO_IDX_SHIFT 16
662 #define ALC_MBOX_RD01_CONS_IDX 0x15F8
663 #define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF
664 #define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000
665 #define MBOX_RD0_CONS_IDX_SHIFT 0
666 #define MBOX_RD1_CONS_IDX_SHIFT 16
668 #define ALC_MBOX_RD23_CONS_IDX 0x15FC
669 #define MBOX_RD2_CONS_IDX_MASK 0x0000FFFF
670 #define MBOX_RD3_CONS_IDX_MASK 0xFFFF0000
671 #define MBOX_RD2_CONS_IDX_SHIFT 0
672 #define MBOX_RD3_CONS_IDX_SHIFT 16
674 #define ALC_INTR_STATUS 0x1600
675 #define INTR_SMB 0x00000001
676 #define INTR_TIMER 0x00000002
677 #define INTR_MANUAL_TIMER 0x00000004
678 #define INTR_RX_FIFO_OFLOW 0x00000008
679 #define INTR_RD0_UNDERRUN 0x00000010
680 #define INTR_RD1_UNDERRUN 0x00000020
681 #define INTR_RD2_UNDERRUN 0x00000040
682 #define INTR_RD3_UNDERRUN 0x00000080
683 #define INTR_TX_FIFO_UNDERRUN 0x00000100
684 #define INTR_DMA_RD_TO_RST 0x00000200
685 #define INTR_DMA_WR_TO_RST 0x00000400
686 #define INTR_TX_CREDIT 0x00000800
687 #define INTR_GPHY 0x00001000
688 #define INTR_GPHY_LOW_PW 0x00002000
689 #define INTR_TXQ_TO_RST 0x00004000
690 #define INTR_TX_PKT 0x00008000
691 #define INTR_RX_PKT0 0x00010000
692 #define INTR_RX_PKT1 0x00020000
693 #define INTR_RX_PKT2 0x00040000
694 #define INTR_RX_PKT3 0x00080000
695 #define INTR_MAC_RX 0x00100000
696 #define INTR_MAC_TX 0x00200000
697 #define INTR_UNDERRUN 0x00400000
698 #define INTR_FRAME_ERROR 0x00800000
699 #define INTR_FRAME_OK 0x01000000
700 #define INTR_CSUM_ERROR 0x02000000
701 #define INTR_PHY_LINK_DOWN 0x04000000
702 #define INTR_DIS_INT 0x80000000
704 /* Interrupt Mask Register */
705 #define ALC_INTR_MASK 0x1604
708 #define INTR_RX_PKT \
709 (INTR_RX_PKT0 | INTR_RX_PKT1 | INTR_RX_PKT2 | \
711 #define INTR_RD_UNDERRUN \
712 (INTR_RD0_UNDERRUN | INTR_RD1_UNDERRUN | \
713 INTR_RD2_UNDERRUN | INTR_RD3_UNDERRUN)
715 #define INTR_RX_PKT INTR_RX_PKT0
716 #define INTR_RD_UNDERRUN INTR_RD0_UNDERRUN
720 (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \
721 INTR_TXQ_TO_RST | INTR_RX_PKT | INTR_TX_PKT | \
722 INTR_RX_FIFO_OFLOW | INTR_RD_UNDERRUN | \
723 INTR_TX_FIFO_UNDERRUN)
725 #define ALC_INTR_RETRIG_TIMER 0x1608
726 #define INTR_RETRIG_TIMER_MASK 0x0000FFFF
727 #define INTR_RETRIG_TIMER_SHIFT 0
729 #define ALC_HDS_CFG 0x160C
730 #define HDS_CFG_ENB 0x00000001
731 #define HDS_CFG_BACKFILLSIZE_MASK 0x000FFF00
732 #define HDS_CFG_MAX_HDRSIZE_MASK 0xFFF00000
733 #define HDS_CFG_BACKFILLSIZE_SHIFT 8
734 #define HDS_CFG_MAX_HDRSIZE_SHIFT 20
736 /* AR813x/AR815x registers for MAC statistics */
737 #define ALC_RX_MIB_BASE 0x1700
739 #define ALC_TX_MIB_BASE 0x1760
741 #define ALC_DEBUG_DATA0 0x1900
743 #define ALC_DEBUG_DATA1 0x1904
745 #define ALC_MII_DBG_ADDR 0x1D
746 #define ALC_MII_DBG_DATA 0x1E
748 #define MII_ANA_CFG0 0x00
749 #define ANA_RESTART_CAL 0x0001
750 #define ANA_MANUL_SWICH_ON_MASK 0x001E
751 #define ANA_MAN_ENABLE 0x0020
752 #define ANA_SEL_HSP 0x0040
753 #define ANA_EN_HB 0x0080
754 #define ANA_EN_HBIAS 0x0100
755 #define ANA_OEN_125M 0x0200
756 #define ANA_EN_LCKDT 0x0400
757 #define ANA_LCKDT_PHY 0x0800
758 #define ANA_AFE_MODE 0x1000
759 #define ANA_VCO_SLOW 0x2000
760 #define ANA_VCO_FAST 0x4000
761 #define ANA_SEL_CLK125M_DSP 0x8000
762 #define ANA_MANUL_SWICH_ON_SHIFT 1
764 #define MII_ANA_CFG4 0x04
765 #define ANA_IECHO_ADJ_MASK 0x0F
766 #define ANA_IECHO_ADJ_3_MASK 0x000F
767 #define ANA_IECHO_ADJ_2_MASK 0x00F0
768 #define ANA_IECHO_ADJ_1_MASK 0x0F00
769 #define ANA_IECHO_ADJ_0_MASK 0xF000
770 #define ANA_IECHO_ADJ_3_SHIFT 0
771 #define ANA_IECHO_ADJ_2_SHIFT 4
772 #define ANA_IECHO_ADJ_1_SHIFT 8
773 #define ANA_IECHO_ADJ_0_SHIFT 12
775 #define MII_ANA_CFG5 0x05
776 #define ANA_SERDES_CDR_BW_MASK 0x0003
777 #define ANA_MS_PAD_DBG 0x0004
778 #define ANA_SPEEDUP_DBG 0x0008
779 #define ANA_SERDES_TH_LOS_MASK 0x0030
780 #define ANA_SERDES_EN_DEEM 0x0040
781 #define ANA_SERDES_TXELECIDLE 0x0080
782 #define ANA_SERDES_BEACON 0x0100
783 #define ANA_SERDES_HALFTXDR 0x0200
784 #define ANA_SERDES_SEL_HSP 0x0400
785 #define ANA_SERDES_EN_PLL 0x0800
786 #define ANA_SERDES_EN 0x1000
787 #define ANA_SERDES_EN_LCKDT 0x2000
788 #define ANA_SERDES_CDR_BW_SHIFT 0
789 #define ANA_SERDES_TH_LOS_SHIFT 4
791 #define MII_ANA_CFG11 0x0B
792 #define ANA_PS_HIB_EN 0x8000
794 #define MII_ANA_CFG18 0x12
795 #define ANA_TEST_MODE_10BT_01MASK 0x0003
796 #define ANA_LOOP_SEL_10BT 0x0004
797 #define ANA_RGMII_MODE_SW 0x0008
798 #define ANA_EN_LONGECABLE 0x0010
799 #define ANA_TEST_MODE_10BT_2 0x0020
800 #define ANA_EN_10BT_IDLE 0x0400
801 #define ANA_EN_MASK_TB 0x0800
802 #define ANA_TRIGGER_SEL_TIMER_MASK 0x3000
803 #define ANA_INTERVAL_SEL_TIMER_MASK 0xC000
804 #define ANA_TEST_MODE_10BT_01SHIFT 0
805 #define ANA_TRIGGER_SEL_TIMER_SHIFT 12
806 #define ANA_INTERVAL_SEL_TIMER_SHIFT 14
808 #define MII_ANA_CFG41 0x29
809 #define ANA_TOP_PS_EN 0x8000
811 #define MII_ANA_CFG54 0x36
812 #define ANA_LONG_CABLE_TH_100_MASK 0x003F
813 #define ANA_DESERVED 0x0040
814 #define ANA_EN_LIT_CH 0x0080
815 #define ANA_SHORT_CABLE_TH_100_MASK 0x3F00
816 #define ANA_BP_BAD_LINK_ACCUM 0x4000
817 #define ANA_BP_SMALL_BW 0x8000
818 #define ANA_LONG_CABLE_TH_100_SHIFT 0
819 #define ANA_SHORT_CABLE_TH_100_SHIFT 8
821 /* Statistics counters collected by the MAC. */
825 uint32_t rx_bcast_frames;
826 uint32_t rx_mcast_frames;
827 uint32_t rx_pause_frames;
828 uint32_t rx_control_frames;
833 uint32_t rx_fragments;
835 uint32_t rx_pkts_65_127;
836 uint32_t rx_pkts_128_255;
837 uint32_t rx_pkts_256_511;
838 uint32_t rx_pkts_512_1023;
839 uint32_t rx_pkts_1024_1518;
840 uint32_t rx_pkts_1519_max;
841 uint32_t rx_pkts_truncated;
842 uint32_t rx_fifo_oflows;
843 uint32_t rx_rrs_errs;
844 uint32_t rx_alignerrs;
845 uint32_t rx_bcast_bytes;
846 uint32_t rx_mcast_bytes;
847 uint32_t rx_pkts_filtered;
850 uint32_t tx_bcast_frames;
851 uint32_t tx_mcast_frames;
852 uint32_t tx_pause_frames;
853 uint32_t tx_excess_defer;
854 uint32_t tx_control_frames;
855 uint32_t tx_deferred;
858 uint32_t tx_pkts_65_127;
859 uint32_t tx_pkts_128_255;
860 uint32_t tx_pkts_256_511;
861 uint32_t tx_pkts_512_1023;
862 uint32_t tx_pkts_1024_1518;
863 uint32_t tx_pkts_1519_max;
864 uint32_t tx_single_colls;
865 uint32_t tx_multi_colls;
866 uint32_t tx_late_colls;
867 uint32_t tx_excess_colls;
869 uint32_t tx_underrun;
870 uint32_t tx_desc_underrun;
872 uint32_t tx_pkts_truncated;
873 uint32_t tx_bcast_bytes;
874 uint32_t tx_mcast_bytes;
878 /* CMB(Coalesing message block) */
883 /* Rx free descriptor */
888 /* Rx return descriptor */
891 #define RRD_CSUM_MASK 0x0000FFFF
892 #define RRD_RD_CNT_MASK 0x000F0000
893 #define RRD_RD_IDX_MASK 0xFFF00000
894 #define RRD_CSUM_SHIFT 0
895 #define RRD_RD_CNT_SHIFT 16
896 #define RRD_RD_IDX_SHIFT 20
897 #define RRD_CSUM(x) \
898 (((x) & RRD_CSUM_MASK) >> RRD_CSUM_SHIFT)
899 #define RRD_RD_CNT(x) \
900 (((x) & RRD_RD_CNT_MASK) >> RRD_RD_CNT_SHIFT)
901 #define RRD_RD_IDX(x) \
902 (((x) & RRD_RD_IDX_MASK) >> RRD_RD_IDX_SHIFT)
905 #define RRD_VLAN_MASK 0x0000FFFF
906 #define RRD_HEAD_LEN_MASK 0x00FF0000
907 #define RRD_HDS_MASK 0x03000000
908 #define RRD_HDS_NONE 0x00000000
909 #define RRD_HDS_HEAD 0x01000000
910 #define RRD_HDS_DATA 0x02000000
911 #define RRD_CPU_MASK 0x0C000000
912 #define RRD_HASH_FLAG_MASK 0xF0000000
913 #define RRD_VLAN_SHIFT 0
914 #define RRD_HEAD_LEN_SHIFT 16
915 #define RRD_HDS_SHIFT 24
916 #define RRD_CPU_SHIFT 26
917 #define RRD_HASH_FLAG_SHIFT 28
918 #define RRD_VLAN(x) \
919 (((x) & RRD_VLAN_MASK) >> RRD_VLAN_SHIFT)
920 #define RRD_HEAD_LEN(x) \
921 (((x) & RRD_HEAD_LEN_MASK) >> RRD_HEAD_LEN_SHIFT)
923 (((x) & RRD_CPU_MASK) >> RRD_CPU_SHIFT)
925 #define RRD_LEN_MASK 0x00003FFF
926 #define RRD_LEN_SHIFT 0
927 #define RRD_TCP_UDPCSUM_NOK 0x00004000
928 #define RRD_IPCSUM_NOK 0x00008000
929 #define RRD_VLAN_TAG 0x00010000
930 #define RRD_PROTO_MASK 0x000E0000
931 #define RRD_PROTO_IPV4 0x00020000
932 #define RRD_PROTO_IPV6 0x000C0000
933 #define RRD_ERR_SUM 0x00100000
934 #define RRD_ERR_CRC 0x00200000
935 #define RRD_ERR_ALIGN 0x00400000
936 #define RRD_ERR_TRUNC 0x00800000
937 #define RRD_ERR_RUNT 0x01000000
938 #define RRD_ERR_ICMP 0x02000000
939 #define RRD_BCAST 0x04000000
940 #define RRD_MCAST 0x08000000
941 #define RRD_SNAP_LLC 0x10000000
942 #define RRD_ETHER 0x00000000
943 #define RRD_FIFO_FULL 0x20000000
944 #define RRD_ERR_LENGTH 0x40000000
945 #define RRD_VALID 0x80000000
946 #define RRD_BYTES(x) \
947 (((x) & RRD_LEN_MASK) >> RRD_LEN_SHIFT)
948 #define RRD_IPV4(x) \
949 (((x) & RRD_PROTO_MASK) == RRD_PROTO_IPV4)
955 #define TD_BUFLEN_MASK 0x00003FFF
956 #define TD_VLAN_MASK 0xFFFF0000
957 #define TD_BUFLEN_SHIFT 0
958 #define TX_BYTES(x) \
959 (((x) << TD_BUFLEN_SHIFT) & TD_BUFLEN_MASK)
960 #define TD_VLAN_SHIFT 16
962 #define TD_L4HDR_OFFSET_MASK 0x000000FF /* byte unit */
963 #define TD_TCPHDR_OFFSET_MASK 0x000000FF /* byte unit */
964 #define TD_PLOAD_OFFSET_MASK 0x000000FF /* 2 bytes unit */
965 #define TD_CUSTOM_CSUM 0x00000100
966 #define TD_IPCSUM 0x00000200
967 #define TD_TCPCSUM 0x00000400
968 #define TD_UDPCSUM 0x00000800
969 #define TD_TSO 0x00001000
970 #define TD_TSO_DESCV1 0x00000000
971 #define TD_TSO_DESCV2 0x00002000
972 #define TD_CON_VLAN_TAG 0x00004000
973 #define TD_INS_VLAN_TAG 0x00008000
974 #define TD_IPV4_DESCV2 0x00010000
975 #define TD_LLC_SNAP 0x00020000
976 #define TD_ETHERNET 0x00000000
977 #define TD_CUSTOM_CSUM_OFFSET_MASK 0x03FC0000 /* 2 bytes unit */
978 #define TD_CUSTOM_CSUM_EVEN_PAD 0x40000000
979 #define TD_MSS_MASK 0x7FFC0000
980 #define TD_EOP 0x80000000
981 #define TD_L4HDR_OFFSET_SHIFT 0
982 #define TD_TCPHDR_OFFSET_SHIFT 0
983 #define TD_PLOAD_OFFSET_SHIFT 0
984 #define TD_CUSTOM_CSUM_OFFSET_SHIFT 18
985 #define TD_MSS_SHIFT 18
989 #endif /* _IF_ALCREG_H */