sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.111 2008/10/22 14:24:24 sephe Exp $
  35  *
  36  */
  37
  38 /*
  39  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  40  *
  41  * Written by Bill Paul <wpaul@windriver.com>
  42  * Senior Engineer, Wind River Systems
  43  */
  44
  45 /*
  46  * The Broadcom BCM5700 is based on technology originally developed by
  47  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  48  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  49  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  50  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  51  * frames, highly configurable RX filtering, and 16 RX and TX queues
  52  * (which, along with RX filter rules, can be used for QOS applications).
  53  * Other features, such as TCP segmentation, may be available as part
  54  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  55  * firmware images can be stored in hardware and need not be compiled
  56  * into the driver.
  57  *
  58  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  59  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  60  *
  61  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  62  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  63  * does not support external SSRAM.
  64  *
  65  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  66  * brand name, which is functionally similar but lacks PCI-X support.
  67  *
  68  * Without external SSRAM, you can only have at most 4 TX rings,
  69  * and the use of the mini RX ring is disabled. This seems to imply
  70  * that these features are simply not available on the BCM5701. As a
  71  * result, this driver does not implement any support for the mini RX
  72  * ring.
  73  */
  74
  75 #include "opt_polling.h"
  76
  77 #include <sys/param.h>
  78 #include <sys/bus.h>
  79 #include <sys/endian.h>
  80 #include <sys/kernel.h>
  81 #include <sys/ktr.h>
  82 #include <sys/interrupt.h>
  83 #include <sys/mbuf.h>
  84 #include <sys/malloc.h>
  85 #include <sys/queue.h>
  86 #include <sys/rman.h>
  87 #include <sys/serialize.h>
  88 #include <sys/socket.h>
  89 #include <sys/sockio.h>
  90 #include <sys/sysctl.h>
  91
  92 #include <net/bpf.h>
  93 #include <net/ethernet.h>
  94 #include <net/if.h>
  95 #include <net/if_arp.h>
  96 #include <net/if_dl.h>
  97 #include <net/if_media.h>
  98 #include <net/if_types.h>
  99 #include <net/ifq_var.h>
 100 #include <net/vlan/if_vlan_var.h>
 101 #include <net/vlan/if_vlan_ether.h>
 102
 103 #include <dev/netif/mii_layer/mii.h>
 104 #include <dev/netif/mii_layer/miivar.h>
 105 #include <dev/netif/mii_layer/brgphyreg.h>
 106
 107 #include <bus/pci/pcidevs.h>
 108 #include <bus/pci/pcireg.h>
 109 #include <bus/pci/pcivar.h>
 110
 111 #include <dev/netif/bge/if_bgereg.h>
 112
 113 /* "device miibus" required.  See GENERIC if you get errors here. */
 114 #include "miibus_if.h"
 115
 116 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 117 #define BGE_MIN_FRAME           60
 118
 119 static const struct bge_type bge_devs[] = {
 120         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
 121                 "3COM 3C996 Gigabit Ethernet" },
 122
 123         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 124                 "Alteon BCM5700 Gigabit Ethernet" },
 125         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
 126                 "Alteon BCM5701 Gigabit Ethernet" },
 127
 128         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 129                 "Altima AC1000 Gigabit Ethernet" },
 130         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 131                 "Altima AC1002 Gigabit Ethernet" },
 132         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 133                 "Altima AC9100 Gigabit Ethernet" },
 134
 135         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
 136                 "Apple BCM5701 Gigabit Ethernet" },
 137
 138         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 139                 "Broadcom BCM5700 Gigabit Ethernet" },
 140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 141                 "Broadcom BCM5701 Gigabit Ethernet" },
 142         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
 143                 "Broadcom BCM5702 Gigabit Ethernet" },
 144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 145                 "Broadcom BCM5702X Gigabit Ethernet" },
 146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
 147                 "Broadcom BCM5702 Gigabit Ethernet" },
 148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
 149                 "Broadcom BCM5703 Gigabit Ethernet" },
 150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 151                 "Broadcom BCM5703X Gigabit Ethernet" },
 152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
 153                 "Broadcom BCM5703 Gigabit Ethernet" },
 154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 155                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 157                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
 159                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 161                 "Broadcom BCM5705 Gigabit Ethernet" },
 162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
 163                 "Broadcom BCM5705F Gigabit Ethernet" },
 164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
 165                 "Broadcom BCM5705K Gigabit Ethernet" },
 166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 167                 "Broadcom BCM5705M Gigabit Ethernet" },
 168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
 169                 "Broadcom BCM5705M Gigabit Ethernet" },
 170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
 171                 "Broadcom BCM5714C Gigabit Ethernet" },
 172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
 173                 "Broadcom BCM5714S Gigabit Ethernet" },
 174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
 175                 "Broadcom BCM5715 Gigabit Ethernet" },
 176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
 177                 "Broadcom BCM5715S Gigabit Ethernet" },
 178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
 179                 "Broadcom BCM5720 Gigabit Ethernet" },
 180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
 181                 "Broadcom BCM5721 Gigabit Ethernet" },
 182         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
 183                 "Broadcom BCM5722 Gigabit Ethernet" },
 184         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
 185                 "Broadcom BCM5750 Gigabit Ethernet" },
 186         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
 187                 "Broadcom BCM5750M Gigabit Ethernet" },
 188         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
 189                 "Broadcom BCM5751 Gigabit Ethernet" },
 190         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
 191                 "Broadcom BCM5751F Gigabit Ethernet" },
 192         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
 193                 "Broadcom BCM5751M Gigabit Ethernet" },
 194         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
 195                 "Broadcom BCM5752 Gigabit Ethernet" },
 196         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
 197                 "Broadcom BCM5752M Gigabit Ethernet" },
 198         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
 199                 "Broadcom BCM5753 Gigabit Ethernet" },
 200         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
 201                 "Broadcom BCM5753F Gigabit Ethernet" },
 202         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
 203                 "Broadcom BCM5753M Gigabit Ethernet" },
 204         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
 205                 "Broadcom BCM5754 Gigabit Ethernet" },
 206         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
 207                 "Broadcom BCM5754M Gigabit Ethernet" },
 208         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
 209                 "Broadcom BCM5755 Gigabit Ethernet" },
 210         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
 211                 "Broadcom BCM5755M Gigabit Ethernet" },
 212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
 213                 "Broadcom BCM5756 Gigabit Ethernet" },
 214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
 215                 "Broadcom BCM5780 Gigabit Ethernet" },
 216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
 217                 "Broadcom BCM5780S Gigabit Ethernet" },
 218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
 219                 "Broadcom BCM5781 Gigabit Ethernet" },
 220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 221                 "Broadcom BCM5782 Gigabit Ethernet" },
 222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
 223                 "Broadcom BCM5786 Gigabit Ethernet" },
 224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
 225                 "Broadcom BCM5787 Gigabit Ethernet" },
 226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
 227                 "Broadcom BCM5787F Gigabit Ethernet" },
 228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
 229                 "Broadcom BCM5787M Gigabit Ethernet" },
 230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
 231                 "Broadcom BCM5788 Gigabit Ethernet" },
 232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
 233                 "Broadcom BCM5789 Gigabit Ethernet" },
 234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 235                 "Broadcom BCM5901 Fast Ethernet" },
 236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 237                 "Broadcom BCM5901A2 Fast Ethernet" },
 238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
 239                 "Broadcom BCM5903M Fast Ethernet" },
 240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
 241                 "Broadcom BCM5906 Fast Ethernet"},
 242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
 243                 "Broadcom BCM5906M Fast Ethernet"},
 244
 245         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 246                 "SysKonnect Gigabit Ethernet" },
 247
 248         { 0, 0, NULL }
 249 };
 250
 251 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 252 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 253 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 254 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 255 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 256
 257 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 258
 259 static int      bge_probe(device_t);
 260 static int      bge_attach(device_t);
 261 static int      bge_detach(device_t);
 262 static void     bge_txeof(struct bge_softc *);
 263 static void     bge_rxeof(struct bge_softc *);
 264
 265 static void     bge_tick(void *);
 266 static void     bge_stats_update(struct bge_softc *);
 267 static void     bge_stats_update_regs(struct bge_softc *);
 268 static int      bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 269
 270 #ifdef DEVICE_POLLING
 271 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 272 #endif
 273 static void     bge_intr(void *);
 274 static void     bge_enable_intr(struct bge_softc *);
 275 static void     bge_disable_intr(struct bge_softc *);
 276 static void     bge_start(struct ifnet *);
 277 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 278 static void     bge_init(void *);
 279 static void     bge_stop(struct bge_softc *);
 280 static void     bge_watchdog(struct ifnet *);
 281 static void     bge_shutdown(device_t);
 282 static int      bge_suspend(device_t);
 283 static int      bge_resume(device_t);
 284 static int      bge_ifmedia_upd(struct ifnet *);
 285 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 286
 287 static uint8_t  bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 288 static int      bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 289
 290 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 291 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 292
 293 static void     bge_setmulti(struct bge_softc *);
 294 static void     bge_setpromisc(struct bge_softc *);
 295
 296 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 297 static void     bge_free_jumbo_mem(struct bge_softc *);
 298 static struct bge_jslot
 299                 *bge_jalloc(struct bge_softc *);
 300 static void     bge_jfree(void *);
 301 static void     bge_jref(void *);
 302 static int      bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
 303 static int      bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
 304 static int      bge_init_rx_ring_std(struct bge_softc *);
 305 static void     bge_free_rx_ring_std(struct bge_softc *);
 306 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 307 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 308 static void     bge_free_tx_ring(struct bge_softc *);
 309 static int      bge_init_tx_ring(struct bge_softc *);
 310
 311 static int      bge_chipinit(struct bge_softc *);
 312 static int      bge_blockinit(struct bge_softc *);
 313
 314 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 315 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 316 #ifdef notdef
 317 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 318 #endif
 319 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 320 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
 321 static void     bge_writembx(struct bge_softc *, int, int);
 322
 323 static int      bge_miibus_readreg(device_t, int, int);
 324 static int      bge_miibus_writereg(device_t, int, int, int);
 325 static void     bge_miibus_statchg(device_t);
 326 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
 327 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
 328 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
 329
 330 static void     bge_reset(struct bge_softc *);
 331
 332 static void     bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 333 static void     bge_dma_map_mbuf(void *, bus_dma_segment_t *, int,
 334                                  bus_size_t, int);
 335 static int      bge_dma_alloc(struct bge_softc *);
 336 static void     bge_dma_free(struct bge_softc *);
 337 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
 338                                     bus_dma_tag_t *, bus_dmamap_t *,
 339                                     void **, bus_addr_t *);
 340 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 341
 342 static int      bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 343 static int      bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 344 static int      bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 345 static int      bge_get_eaddr(struct bge_softc *, uint8_t[]);
 346
 347 static void     bge_coal_change(struct bge_softc *);
 348 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 349 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 350 static int      bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 351 static int      bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 352 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
 353
 354 /*
 355  * Set following tunable to 1 for some IBM blade servers with the DNLK
 356  * switch module. Auto negotiation is broken for those configurations.
 357  */
 358 static int      bge_fake_autoneg = 0;
 359 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
 360
 361 /* Interrupt moderation control variables. */
 362 static int      bge_rx_coal_ticks = 100;        /* usec */
 363 static int      bge_tx_coal_ticks = 1023;       /* usec */
 364 static int      bge_rx_max_coal_bds = 80;
 365 static int      bge_tx_max_coal_bds = 128;
 366
 367 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
 368 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
 369 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
 370 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
 371
 372 #if !defined(KTR_IF_BGE)
 373 #define KTR_IF_BGE      KTR_ALL
 374 #endif
 375 KTR_INFO_MASTER(if_bge);
 376 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr", 0);
 377 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt", 0);
 378 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt", 0);
 379 #define logif(name)     KTR_LOG(if_bge_ ## name)
 380
 381 static device_method_t bge_methods[] = {
 382         /* Device interface */
 383         DEVMETHOD(device_probe,         bge_probe),
 384         DEVMETHOD(device_attach,        bge_attach),
 385         DEVMETHOD(device_detach,        bge_detach),
 386         DEVMETHOD(device_shutdown,      bge_shutdown),
 387         DEVMETHOD(device_suspend,       bge_suspend),
 388         DEVMETHOD(device_resume,        bge_resume),
 389
 390         /* bus interface */
 391         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 392         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 393
 394         /* MII interface */
 395         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 396         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 397         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 398
 399         { 0, 0 }
 400 };
 401
 402 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 403 static devclass_t bge_devclass;
 404
 405 DECLARE_DUMMY_MODULE(if_bge);
 406 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
 407 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 408
 409 static uint32_t
 410 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 411 {
 412         device_t dev = sc->bge_dev;
 413         uint32_t val;
 414
 415         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 416         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 417         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 418         return (val);
 419 }
 420
 421 static void
 422 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 423 {
 424         device_t dev = sc->bge_dev;
 425
 426         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 427         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 428         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 429 }
 430
 431 #ifdef notdef
 432 static uint32_t
 433 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 434 {
 435         device_t dev = sc->bge_dev;
 436
 437         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 438         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 439 }
 440 #endif
 441
 442 static void
 443 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 444 {
 445         device_t dev = sc->bge_dev;
 446
 447         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 448         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 449 }
 450
 451 static void
 452 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
 453 {
 454         CSR_WRITE_4(sc, off, val);
 455 }
 456
 457 static void
 458 bge_writembx(struct bge_softc *sc, int off, int val)
 459 {
 460         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 461                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 462
 463         CSR_WRITE_4(sc, off, val);
 464 }
 465
 466 static uint8_t
 467 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 468 {
 469         uint32_t access, byte = 0;
 470         int i;
 471
 472         /* Lock. */
 473         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 474         for (i = 0; i < 8000; i++) {
 475                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 476                         break;
 477                 DELAY(20);
 478         }
 479         if (i == 8000)
 480                 return (1);
 481
 482         /* Enable access. */
 483         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 484         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 485
 486         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 487         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 488         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 489                 DELAY(10);
 490                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 491                         DELAY(10);
 492                         break;
 493                 }
 494         }
 495
 496         if (i == BGE_TIMEOUT * 10) {
 497                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
 498                 return (1);
 499         }
 500
 501         /* Get result. */
 502         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 503
 504         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 505
 506         /* Disable access. */
 507         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 508
 509         /* Unlock. */
 510         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 511         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 512
 513         return (0);
 514 }
 515
 516 /*
 517  * Read a sequence of bytes from NVRAM.
 518  */
 519 static int
 520 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 521 {
 522         int err = 0, i;
 523         uint8_t byte = 0;
 524
 525         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 526                 return (1);
 527
 528         for (i = 0; i < cnt; i++) {
 529                 err = bge_nvram_getbyte(sc, off + i, &byte);
 530                 if (err)
 531                         break;
 532                 *(dest + i) = byte;
 533         }
 534
 535         return (err ? 1 : 0);
 536 }
 537
 538 /*
 539  * Read a byte of data stored in the EEPROM at address 'addr.' The
 540  * BCM570x supports both the traditional bitbang interface and an
 541  * auto access interface for reading the EEPROM. We use the auto
 542  * access method.
 543  */
 544 static uint8_t
 545 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 546 {
 547         int i;
 548         uint32_t byte = 0;
 549
 550         /*
 551          * Enable use of auto EEPROM access so we can avoid
 552          * having to use the bitbang method.
 553          */
 554         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 555
 556         /* Reset the EEPROM, load the clock period. */
 557         CSR_WRITE_4(sc, BGE_EE_ADDR,
 558             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 559         DELAY(20);
 560
 561         /* Issue the read EEPROM command. */
 562         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 563
 564         /* Wait for completion */
 565         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 566                 DELAY(10);
 567                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 568                         break;
 569         }
 570
 571         if (i == BGE_TIMEOUT) {
 572                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 573                 return(1);
 574         }
 575
 576         /* Get result. */
 577         byte = CSR_READ_4(sc, BGE_EE_DATA);
 578
 579         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 580
 581         return(0);
 582 }
 583
 584 /*
 585  * Read a sequence of bytes from the EEPROM.
 586  */
 587 static int
 588 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 589 {
 590         size_t i;
 591         int err;
 592         uint8_t byte;
 593
 594         for (byte = 0, err = 0, i = 0; i < len; i++) {
 595                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 596                 if (err)
 597                         break;
 598                 *(dest + i) = byte;
 599         }
 600
 601         return(err ? 1 : 0);
 602 }
 603
 604 static int
 605 bge_miibus_readreg(device_t dev, int phy, int reg)
 606 {
 607         struct bge_softc *sc = device_get_softc(dev);
 608         struct ifnet *ifp = &sc->arpcom.ac_if;
 609         uint32_t val, autopoll;
 610         int i;
 611
 612         /*
 613          * Broadcom's own driver always assumes the internal
 614          * PHY is at GMII address 1. On some chips, the PHY responds
 615          * to accesses at all addresses, which could cause us to
 616          * bogusly attach the PHY 32 times at probe type. Always
 617          * restricting the lookup to address 1 is simpler than
 618          * trying to figure out which chips revisions should be
 619          * special-cased.
 620          */
 621         if (phy != 1)
 622                 return(0);
 623
 624         /* Reading with autopolling on may trigger PCI errors */
 625         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 626         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 627                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 628                 DELAY(40);
 629         }
 630
 631         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
 632             BGE_MIPHY(phy)|BGE_MIREG(reg));
 633
 634         for (i = 0; i < BGE_TIMEOUT; i++) {
 635                 DELAY(10);
 636                 val = CSR_READ_4(sc, BGE_MI_COMM);
 637                 if (!(val & BGE_MICOMM_BUSY))
 638                         break;
 639         }
 640
 641         if (i == BGE_TIMEOUT) {
 642                 if_printf(ifp, "PHY read timed out "
 643                           "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 644                 val = 0;
 645                 goto done;
 646         }
 647
 648         DELAY(5);
 649         val = CSR_READ_4(sc, BGE_MI_COMM);
 650
 651 done:
 652         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 653                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 654                 DELAY(40);
 655         }
 656
 657         if (val & BGE_MICOMM_READFAIL)
 658                 return(0);
 659
 660         return(val & 0xFFFF);
 661 }
 662
 663 static int
 664 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 665 {
 666         struct bge_softc *sc = device_get_softc(dev);
 667         uint32_t autopoll;
 668         int i;
 669
 670         /*
 671          * See the related comment in bge_miibus_readreg()
 672          */
 673         if (phy != 1)
 674                 return(0);
 675
 676         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 677             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 678                return(0);
 679
 680         /* Reading with autopolling on may trigger PCI errors */
 681         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 682         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 683                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 684                 DELAY(40);
 685         }
 686
 687         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
 688             BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
 689
 690         for (i = 0; i < BGE_TIMEOUT; i++) {
 691                 DELAY(10);
 692                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 693                         DELAY(5);
 694                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 695                         break;
 696                 }
 697         }
 698
 699         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 700                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 701                 DELAY(40);
 702         }
 703
 704         if (i == BGE_TIMEOUT) {
 705                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 706                           "(phy %d, reg %d, val %d)\n", phy, reg, val);
 707                 return(0);
 708         }
 709
 710         return(0);
 711 }
 712
 713 static void
 714 bge_miibus_statchg(device_t dev)
 715 {
 716         struct bge_softc *sc;
 717         struct mii_data *mii;
 718
 719         sc = device_get_softc(dev);
 720         mii = device_get_softc(sc->bge_miibus);
 721
 722         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 723         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
 724                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 725         } else {
 726                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 727         }
 728
 729         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 730                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 731         } else {
 732                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 733         }
 734 }
 735
 736 /*
 737  * Memory management for jumbo frames.
 738  */
 739 static int
 740 bge_alloc_jumbo_mem(struct bge_softc *sc)
 741 {
 742         struct ifnet *ifp = &sc->arpcom.ac_if;
 743         struct bge_jslot *entry;
 744         uint8_t *ptr;
 745         bus_addr_t paddr;
 746         int i, error;
 747
 748         /*
 749          * Create tag for jumbo mbufs.
 750          * This is really a bit of a kludge. We allocate a special
 751          * jumbo buffer pool which (thanks to the way our DMA
 752          * memory allocation works) will consist of contiguous
 753          * pages. This means that even though a jumbo buffer might
 754          * be larger than a page size, we don't really need to
 755          * map it into more than one DMA segment. However, the
 756          * default mbuf tag will result in multi-segment mappings,
 757          * so we have to create a special jumbo mbuf tag that
 758          * lets us get away with mapping the jumbo buffers as
 759          * a single segment. I think eventually the driver should
 760          * be changed so that it uses ordinary mbufs and cluster
 761          * buffers, i.e. jumbo frames can span multiple DMA
 762          * descriptors. But that's a project for another day.
 763          */
 764
 765         /*
 766          * Create DMA stuffs for jumbo RX ring.
 767          */
 768         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 769                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
 770                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
 771                                     (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
 772                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
 773         if (error) {
 774                 if_printf(ifp, "could not create jumbo RX ring\n");
 775                 return error;
 776         }
 777
 778         /*
 779          * Create DMA stuffs for jumbo buffer block.
 780          */
 781         error = bge_dma_block_alloc(sc, BGE_JMEM,
 782                                     &sc->bge_cdata.bge_jumbo_tag,
 783                                     &sc->bge_cdata.bge_jumbo_map,
 784                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
 785                                     &paddr);
 786         if (error) {
 787                 if_printf(ifp, "could not create jumbo buffer\n");
 788                 return error;
 789         }
 790
 791         SLIST_INIT(&sc->bge_jfree_listhead);
 792
 793         /*
 794          * Now divide it up into 9K pieces and save the addresses
 795          * in an array. Note that we play an evil trick here by using
 796          * the first few bytes in the buffer to hold the the address
 797          * of the softc structure for this interface. This is because
 798          * bge_jfree() needs it, but it is called by the mbuf management
 799          * code which will not pass it to us explicitly.
 800          */
 801         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
 802                 entry = &sc->bge_cdata.bge_jslots[i];
 803                 entry->bge_sc = sc;
 804                 entry->bge_buf = ptr;
 805                 entry->bge_paddr = paddr;
 806                 entry->bge_inuse = 0;
 807                 entry->bge_slot = i;
 808                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 809
 810                 ptr += BGE_JLEN;
 811                 paddr += BGE_JLEN;
 812         }
 813         return 0;
 814 }
 815
 816 static void
 817 bge_free_jumbo_mem(struct bge_softc *sc)
 818 {
 819         /* Destroy jumbo RX ring. */
 820         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 821                            sc->bge_cdata.bge_rx_jumbo_ring_map,
 822                            sc->bge_ldata.bge_rx_jumbo_ring);
 823
 824         /* Destroy jumbo buffer block. */
 825         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
 826                            sc->bge_cdata.bge_jumbo_map,
 827                            sc->bge_ldata.bge_jumbo_buf);
 828 }
 829
 830 /*
 831  * Allocate a jumbo buffer.
 832  */
 833 static struct bge_jslot *
 834 bge_jalloc(struct bge_softc *sc)
 835 {
 836         struct bge_jslot *entry;
 837
 838         lwkt_serialize_enter(&sc->bge_jslot_serializer);
 839         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 840         if (entry) {
 841                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 842                 entry->bge_inuse = 1;
 843         } else {
 844                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 845         }
 846         lwkt_serialize_exit(&sc->bge_jslot_serializer);
 847         return(entry);
 848 }
 849
 850 /*
 851  * Adjust usage count on a jumbo buffer.
 852  */
 853 static void
 854 bge_jref(void *arg)
 855 {
 856         struct bge_jslot *entry = (struct bge_jslot *)arg;
 857         struct bge_softc *sc = entry->bge_sc;
 858
 859         if (sc == NULL)
 860                 panic("bge_jref: can't find softc pointer!");
 861
 862         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 863                 panic("bge_jref: asked to reference buffer "
 864                     "that we don't manage!");
 865         } else if (entry->bge_inuse == 0) {
 866                 panic("bge_jref: buffer already free!");
 867         } else {
 868                 atomic_add_int(&entry->bge_inuse, 1);
 869         }
 870 }
 871
 872 /*
 873  * Release a jumbo buffer.
 874  */
 875 static void
 876 bge_jfree(void *arg)
 877 {
 878         struct bge_jslot *entry = (struct bge_jslot *)arg;
 879         struct bge_softc *sc = entry->bge_sc;
 880
 881         if (sc == NULL)
 882                 panic("bge_jfree: can't find softc pointer!");
 883
 884         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 885                 panic("bge_jfree: asked to free buffer that we don't manage!");
 886         } else if (entry->bge_inuse == 0) {
 887                 panic("bge_jfree: buffer already free!");
 888         } else {
 889                 /*
 890                  * Possible MP race to 0, use the serializer.  The atomic insn
 891                  * is still needed for races against bge_jref().
 892                  */
 893                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
 894                 atomic_subtract_int(&entry->bge_inuse, 1);
 895                 if (entry->bge_inuse == 0) {
 896                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
 897                                           entry, jslot_link);
 898                 }
 899                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
 900         }
 901 }
 902
 903
 904 /*
 905  * Intialize a standard receive ring descriptor.
 906  */
 907 static int
 908 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
 909 {
 910         struct mbuf *m_new = NULL;
 911         struct bge_dmamap_arg ctx;
 912         bus_dma_segment_t seg;
 913         struct bge_rx_bd *r;
 914         int error;
 915
 916         if (m == NULL) {
 917                 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
 918                 if (m_new == NULL)
 919                         return ENOBUFS;
 920         } else {
 921                 m_new = m;
 922                 m_new->m_data = m_new->m_ext.ext_buf;
 923         }
 924         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 925
 926         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 927                 m_adj(m_new, ETHER_ALIGN);
 928
 929         ctx.bge_maxsegs = 1;
 930         ctx.bge_segs = &seg;
 931         error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag,
 932                                      sc->bge_cdata.bge_rx_std_dmamap[i],
 933                                      m_new, bge_dma_map_mbuf, &ctx,
 934                                      BUS_DMA_NOWAIT);
 935         if (error || ctx.bge_maxsegs == 0) {
 936                 if (!error) {
 937                         if_printf(&sc->arpcom.ac_if, "too many segments?!\n");
 938                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
 939                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
 940                 }
 941                 if (m == NULL)
 942                         m_freem(m_new);
 943                 return ENOMEM;
 944         }
 945
 946         sc->bge_cdata.bge_rx_std_chain[i] = m_new;
 947
 948         r = &sc->bge_ldata.bge_rx_std_ring[i];
 949         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[0].ds_addr);
 950         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[0].ds_addr);
 951         r->bge_flags = BGE_RXBDFLAG_END;
 952         r->bge_len = m_new->m_len;
 953         r->bge_idx = i;
 954
 955         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
 956                         sc->bge_cdata.bge_rx_std_dmamap[i],
 957                         BUS_DMASYNC_PREREAD);
 958         return 0;
 959 }
 960
 961 /*
 962  * Initialize a jumbo receive ring descriptor. This allocates
 963  * a jumbo buffer from the pool managed internally by the driver.
 964  */
 965 static int
 966 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
 967 {
 968         struct mbuf *m_new = NULL;
 969         struct bge_jslot *buf;
 970         struct bge_rx_bd *r;
 971         bus_addr_t paddr;
 972
 973         if (m == NULL) {
 974                 /* Allocate the mbuf. */
 975                 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
 976                 if (m_new == NULL)
 977                         return(ENOBUFS);
 978
 979                 /* Allocate the jumbo buffer */
 980                 buf = bge_jalloc(sc);
 981                 if (buf == NULL) {
 982                         m_freem(m_new);
 983                         if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
 984                             "-- packet dropped!\n");
 985                         return ENOBUFS;
 986                 }
 987
 988                 /* Attach the buffer to the mbuf. */
 989                 m_new->m_ext.ext_arg = buf;
 990                 m_new->m_ext.ext_buf = buf->bge_buf;
 991                 m_new->m_ext.ext_free = bge_jfree;
 992                 m_new->m_ext.ext_ref = bge_jref;
 993                 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 994
 995                 m_new->m_flags |= M_EXT;
 996         } else {
 997                 KKASSERT(m->m_flags & M_EXT);
 998                 m_new = m;
 999                 buf = m_new->m_ext.ext_arg;
1000         }
1001         m_new->m_data = m_new->m_ext.ext_buf;
1002         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1003
1004         paddr = buf->bge_paddr;
1005         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1006                 m_adj(m_new, ETHER_ALIGN);
1007                 paddr += ETHER_ALIGN;
1008         }
1009
1010         /* Set up the descriptor. */
1011         sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
1012
1013         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1014         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(paddr);
1015         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(paddr);
1016         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1017         r->bge_len = m_new->m_len;
1018         r->bge_idx = i;
1019
1020         return 0;
1021 }
1022
1023 /*
1024  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1025  * that's 1MB or memory, which is a lot. For now, we fill only the first
1026  * 256 ring entries and hope that our CPU is fast enough to keep up with
1027  * the NIC.
1028  */
1029 static int
1030 bge_init_rx_ring_std(struct bge_softc *sc)
1031 {
1032         int i;
1033
1034         for (i = 0; i < BGE_SSLOTS; i++) {
1035                 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
1036                         return(ENOBUFS);
1037         };
1038
1039         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1040                         sc->bge_cdata.bge_rx_std_ring_map,
1041                         BUS_DMASYNC_PREWRITE);
1042
1043         sc->bge_std = i - 1;
1044         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1045
1046         return(0);
1047 }
1048
1049 static void
1050 bge_free_rx_ring_std(struct bge_softc *sc)
1051 {
1052         int i;
1053
1054         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1055                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1056                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1057                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
1058                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1059                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1060                 }
1061                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1062                     sizeof(struct bge_rx_bd));
1063         }
1064 }
1065
1066 static int
1067 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1068 {
1069         int i;
1070         struct bge_rcb *rcb;
1071
1072         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1073                 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
1074                         return(ENOBUFS);
1075         };
1076
1077         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1078                         sc->bge_cdata.bge_rx_jumbo_ring_map,
1079                         BUS_DMASYNC_PREWRITE);
1080
1081         sc->bge_jumbo = i - 1;
1082
1083         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1084         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1085         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1086
1087         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1088
1089         return(0);
1090 }
1091
1092 static void
1093 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1094 {
1095         int i;
1096
1097         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1098                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1099                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1100                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1101                 }
1102                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1103                     sizeof(struct bge_rx_bd));
1104         }
1105 }
1106
1107 static void
1108 bge_free_tx_ring(struct bge_softc *sc)
1109 {
1110         int i;
1111
1112         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1113                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1114                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1115                                           sc->bge_cdata.bge_tx_dmamap[i]);
1116                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1117                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1118                 }
1119                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1120                     sizeof(struct bge_tx_bd));
1121         }
1122 }
1123
1124 static int
1125 bge_init_tx_ring(struct bge_softc *sc)
1126 {
1127         sc->bge_txcnt = 0;
1128         sc->bge_tx_saved_considx = 0;
1129         sc->bge_tx_prodidx = 0;
1130
1131         /* Initialize transmit producer index for host-memory send ring. */
1132         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1133
1134         /* 5700 b2 errata */
1135         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1136                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1137
1138         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1139         /* 5700 b2 errata */
1140         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1141                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1142
1143         return(0);
1144 }
1145
1146 static void
1147 bge_setmulti(struct bge_softc *sc)
1148 {
1149         struct ifnet *ifp;
1150         struct ifmultiaddr *ifma;
1151         uint32_t hashes[4] = { 0, 0, 0, 0 };
1152         int h, i;
1153
1154         ifp = &sc->arpcom.ac_if;
1155
1156         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1157                 for (i = 0; i < 4; i++)
1158                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1159                 return;
1160         }
1161
1162         /* First, zot all the existing filters. */
1163         for (i = 0; i < 4; i++)
1164                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1165
1166         /* Now program new ones. */
1167         LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1168                 if (ifma->ifma_addr->sa_family != AF_LINK)
1169                         continue;
1170                 h = ether_crc32_le(
1171                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1172                     ETHER_ADDR_LEN) & 0x7f;
1173                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1174         }
1175
1176         for (i = 0; i < 4; i++)
1177                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1178 }
1179
1180 /*
1181  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1182  * self-test results.
1183  */
1184 static int
1185 bge_chipinit(struct bge_softc *sc)
1186 {
1187         int i;
1188         uint32_t dma_rw_ctl;
1189
1190         /* Set endian type before we access any non-PCI registers. */
1191         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1192
1193         /* Clear the MAC control register */
1194         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1195
1196         /*
1197          * Clear the MAC statistics block in the NIC's
1198          * internal memory.
1199          */
1200         for (i = BGE_STATS_BLOCK;
1201             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1202                 BGE_MEMWIN_WRITE(sc, i, 0);
1203
1204         for (i = BGE_STATUS_BLOCK;
1205             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1206                 BGE_MEMWIN_WRITE(sc, i, 0);
1207
1208         /* Set up the PCI DMA control register. */
1209         if (sc->bge_flags & BGE_FLAG_PCIE) {
1210                 /* PCI Express */
1211                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1212                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1213                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1214         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1215                 /* PCI-X bus */
1216                 if (BGE_IS_5714_FAMILY(sc)) {
1217                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1218                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1219                         /* XXX magic values, Broadcom-supplied Linux driver */
1220                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1221                                 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1222                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1223                         } else {
1224                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1225                         }
1226                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1227                         /*
1228                          * The 5704 uses a different encoding of read/write
1229                          * watermarks.
1230                          */
1231                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1232                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1233                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1234                 } else {
1235                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1236                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1237                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1238                             (0x0F);
1239                 }
1240
1241                 /*
1242                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1243                  * for hardware bugs.
1244                  */
1245                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1246                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1247                         uint32_t tmp;
1248
1249                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1250                         if (tmp == 0x6 || tmp == 0x7)
1251                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1252                 }
1253         } else {
1254                 /* Conventional PCI bus */
1255                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1256                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1257                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1258                     (0x0F);
1259         }
1260
1261         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1262             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1263             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1264                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1265         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1266
1267         /*
1268          * Set up general mode register.
1269          */
1270         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1271             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1272             BGE_MODECTL_TX_NO_PHDR_CSUM);
1273
1274         /*
1275          * Disable memory write invalidate.  Apparently it is not supported
1276          * properly by these devices.
1277          */
1278         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1279
1280         /* Set the timer prescaler (always 66Mhz) */
1281         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1282
1283         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1284                 DELAY(40);      /* XXX */
1285
1286                 /* Put PHY into ready state */
1287                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1288                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1289                 DELAY(40);
1290         }
1291
1292         return(0);
1293 }
1294
1295 static int
1296 bge_blockinit(struct bge_softc *sc)
1297 {
1298         struct bge_rcb *rcb;
1299         bus_size_t vrcb;
1300         bge_hostaddr taddr;
1301         uint32_t val;
1302         int i;
1303
1304         /*
1305          * Initialize the memory window pointer register so that
1306          * we can access the first 32K of internal NIC RAM. This will
1307          * allow us to set up the TX send ring RCBs and the RX return
1308          * ring RCBs, plus other things which live in NIC memory.
1309          */
1310         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1311
1312         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1313
1314         if (!BGE_IS_5705_PLUS(sc)) {
1315                 /* Configure mbuf memory pool */
1316                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1317                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1318                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1319                 else
1320                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1321
1322                 /* Configure DMA resource pool */
1323                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1324                     BGE_DMA_DESCRIPTORS);
1325                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1326         }
1327
1328         /* Configure mbuf pool watermarks */
1329         if (!BGE_IS_5705_PLUS(sc)) {
1330                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1331                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1332                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1333         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1334                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1335                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1336                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1337         } else {
1338                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1339                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1340                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1341         }
1342
1343         /* Configure DMA resource watermarks */
1344         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1345         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1346
1347         /* Enable buffer manager */
1348         if (!BGE_IS_5705_PLUS(sc)) {
1349                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1350                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1351
1352                 /* Poll for buffer manager start indication */
1353                 for (i = 0; i < BGE_TIMEOUT; i++) {
1354                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1355                                 break;
1356                         DELAY(10);
1357                 }
1358
1359                 if (i == BGE_TIMEOUT) {
1360                         if_printf(&sc->arpcom.ac_if,
1361                                   "buffer manager failed to start\n");
1362                         return(ENXIO);
1363                 }
1364         }
1365
1366         /* Enable flow-through queues */
1367         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1368         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1369
1370         /* Wait until queue initialization is complete */
1371         for (i = 0; i < BGE_TIMEOUT; i++) {
1372                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1373                         break;
1374                 DELAY(10);
1375         }
1376
1377         if (i == BGE_TIMEOUT) {
1378                 if_printf(&sc->arpcom.ac_if,
1379                           "flow-through queue init failed\n");
1380                 return(ENXIO);
1381         }
1382
1383         /* Initialize the standard RX ring control block */
1384         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1385         rcb->bge_hostaddr.bge_addr_lo =
1386             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1387         rcb->bge_hostaddr.bge_addr_hi =
1388             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1389         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1390             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1391         if (BGE_IS_5705_PLUS(sc))
1392                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1393         else
1394                 rcb->bge_maxlen_flags =
1395                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1396         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1397         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1398         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1399         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1400         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1401
1402         /*
1403          * Initialize the jumbo RX ring control block
1404          * We set the 'ring disabled' bit in the flags
1405          * field until we're actually ready to start
1406          * using this ring (i.e. once we set the MTU
1407          * high enough to require it).
1408          */
1409         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1410                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1411
1412                 rcb->bge_hostaddr.bge_addr_lo =
1413                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1414                 rcb->bge_hostaddr.bge_addr_hi =
1415                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1416                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1417                     sc->bge_cdata.bge_rx_jumbo_ring_map,
1418                     BUS_DMASYNC_PREREAD);
1419                 rcb->bge_maxlen_flags =
1420                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1421                     BGE_RCB_FLAG_RING_DISABLED);
1422                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1423                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1424                     rcb->bge_hostaddr.bge_addr_hi);
1425                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1426                     rcb->bge_hostaddr.bge_addr_lo);
1427                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1428                     rcb->bge_maxlen_flags);
1429                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1430
1431                 /* Set up dummy disabled mini ring RCB */
1432                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1433                 rcb->bge_maxlen_flags =
1434                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1435                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1436                     rcb->bge_maxlen_flags);
1437         }
1438
1439         /*
1440          * Set the BD ring replentish thresholds. The recommended
1441          * values are 1/8th the number of descriptors allocated to
1442          * each ring.
1443          */
1444         if (BGE_IS_5705_PLUS(sc))
1445                 val = 8;
1446         else
1447                 val = BGE_STD_RX_RING_CNT / 8;
1448         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1449         CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1450
1451         /*
1452          * Disable all unused send rings by setting the 'ring disabled'
1453          * bit in the flags field of all the TX send ring control blocks.
1454          * These are located in NIC memory.
1455          */
1456         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1457         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1458                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1459                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1460                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1461                 vrcb += sizeof(struct bge_rcb);
1462         }
1463
1464         /* Configure TX RCB 0 (we use only the first ring) */
1465         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1466         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1467         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1468         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1469         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1470             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1471         if (!BGE_IS_5705_PLUS(sc)) {
1472                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1473                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1474         }
1475
1476         /* Disable all unused RX return rings */
1477         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1478         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1479                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1480                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1481                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1482                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1483                     BGE_RCB_FLAG_RING_DISABLED));
1484                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1485                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1486                     (i * (sizeof(uint64_t))), 0);
1487                 vrcb += sizeof(struct bge_rcb);
1488         }
1489
1490         /* Initialize RX ring indexes */
1491         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1492         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1493         bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1494
1495         /*
1496          * Set up RX return ring 0
1497          * Note that the NIC address for RX return rings is 0x00000000.
1498          * The return rings live entirely within the host, so the
1499          * nicaddr field in the RCB isn't used.
1500          */
1501         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1502         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1503         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1504         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1505         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1506         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1507             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1508
1509         /* Set random backoff seed for TX */
1510         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1511             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1512             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1513             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1514             BGE_TX_BACKOFF_SEED_MASK);
1515
1516         /* Set inter-packet gap */
1517         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1518
1519         /*
1520          * Specify which ring to use for packets that don't match
1521          * any RX rules.
1522          */
1523         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1524
1525         /*
1526          * Configure number of RX lists. One interrupt distribution
1527          * list, sixteen active lists, one bad frames class.
1528          */
1529         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1530
1531         /* Inialize RX list placement stats mask. */
1532         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1533         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1534
1535         /* Disable host coalescing until we get it set up */
1536         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1537
1538         /* Poll to make sure it's shut down. */
1539         for (i = 0; i < BGE_TIMEOUT; i++) {
1540                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1541                         break;
1542                 DELAY(10);
1543         }
1544
1545         if (i == BGE_TIMEOUT) {
1546                 if_printf(&sc->arpcom.ac_if,
1547                           "host coalescing engine failed to idle\n");
1548                 return(ENXIO);
1549         }
1550
1551         /* Set up host coalescing defaults */
1552         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1553         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1554         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1555         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1556         if (!BGE_IS_5705_PLUS(sc)) {
1557                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1558                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1559         }
1560         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1561         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1562
1563         /* Set up address of statistics block */
1564         if (!BGE_IS_5705_PLUS(sc)) {
1565                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1566                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1567                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1568                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1569
1570                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1571                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1572                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1573         }
1574
1575         /* Set up address of status block */
1576         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1577             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1578         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1579             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1580         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1581         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1582
1583         /* Turn on host coalescing state machine */
1584         CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1585
1586         /* Turn on RX BD completion state machine and enable attentions */
1587         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1588             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1589
1590         /* Turn on RX list placement state machine */
1591         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1592
1593         /* Turn on RX list selector state machine. */
1594         if (!BGE_IS_5705_PLUS(sc))
1595                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1596
1597         /* Turn on DMA, clear stats */
1598         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1599             BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1600             BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1601             BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1602             ((sc->bge_flags & BGE_FLAG_TBI) ?
1603              BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1604
1605         /* Set misc. local control, enable interrupts on attentions */
1606         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1607
1608 #ifdef notdef
1609         /* Assert GPIO pins for PHY reset */
1610         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1611             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1612         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1613             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1614 #endif
1615
1616         /* Turn on DMA completion state machine */
1617         if (!BGE_IS_5705_PLUS(sc))
1618                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1619
1620         /* Turn on write DMA state machine */
1621         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1622         if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1623             sc->bge_asicrev == BGE_ASICREV_BCM5787)
1624                 val |= (1 << 29);       /* Enable host coalescing bug fix. */
1625         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1626         DELAY(40);
1627
1628         /* Turn on read DMA state machine */
1629         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1630         if (sc->bge_flags & BGE_FLAG_PCIE)
1631                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1632         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1633         DELAY(40);
1634
1635         /* Turn on RX data completion state machine */
1636         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1637
1638         /* Turn on RX BD initiator state machine */
1639         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1640
1641         /* Turn on RX data and RX BD initiator state machine */
1642         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1643
1644         /* Turn on Mbuf cluster free state machine */
1645         if (!BGE_IS_5705_PLUS(sc))
1646                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1647
1648         /* Turn on send BD completion state machine */
1649         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1650
1651         /* Turn on send data completion state machine */
1652         CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1653
1654         /* Turn on send data initiator state machine */
1655         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1656
1657         /* Turn on send BD initiator state machine */
1658         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1659
1660         /* Turn on send BD selector state machine */
1661         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1662
1663         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1664         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1665             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1666
1667         /* ack/clear link change events */
1668         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1669             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1670             BGE_MACSTAT_LINK_CHANGED);
1671         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1672
1673         /* Enable PHY auto polling (for MII/GMII only) */
1674         if (sc->bge_flags & BGE_FLAG_TBI) {
1675                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1676         } else {
1677                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1678                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1679                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1680                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1681                             BGE_EVTENB_MI_INTERRUPT);
1682                 }
1683         }
1684
1685         /*
1686          * Clear any pending link state attention.
1687          * Otherwise some link state change events may be lost until attention
1688          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1689          * It's not necessary on newer BCM chips - perhaps enabling link
1690          * state change attentions implies clearing pending attention.
1691          */
1692         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1693             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1694             BGE_MACSTAT_LINK_CHANGED);
1695
1696         /* Enable link state change attentions. */
1697         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1698
1699         return(0);
1700 }
1701
1702 /*
1703  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1704  * against our list and return its name if we find a match. Note
1705  * that since the Broadcom controller contains VPD support, we
1706  * can get the device name string from the controller itself instead
1707  * of the compiled-in string. This is a little slow, but it guarantees
1708  * we'll always announce the right product name.
1709  */
1710 static int
1711 bge_probe(device_t dev)
1712 {
1713         const struct bge_type *t;
1714         uint16_t product, vendor;
1715
1716         product = pci_get_device(dev);
1717         vendor = pci_get_vendor(dev);
1718
1719         for (t = bge_devs; t->bge_name != NULL; t++) {
1720                 if (vendor == t->bge_vid && product == t->bge_did)
1721                         break;
1722         }
1723         if (t->bge_name == NULL)
1724                 return(ENXIO);
1725
1726         device_set_desc(dev, t->bge_name);
1727         if (pci_get_subvendor(dev) == PCI_VENDOR_DELL) {
1728                 struct bge_softc *sc = device_get_softc(dev);
1729                 sc->bge_flags |= BGE_FLAG_NO_3LED;
1730         }
1731         return(0);
1732 }
1733
1734 static int
1735 bge_attach(device_t dev)
1736 {
1737         struct ifnet *ifp;
1738         struct bge_softc *sc;
1739         uint32_t hwcfg = 0;
1740         int error = 0, rid;
1741         uint8_t ether_addr[ETHER_ADDR_LEN];
1742
1743         sc = device_get_softc(dev);
1744         sc->bge_dev = dev;
1745         callout_init(&sc->bge_stat_timer);
1746         lwkt_serialize_init(&sc->bge_jslot_serializer);
1747
1748 #ifndef BURN_BRIDGES
1749         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1750                 uint32_t irq, mem;
1751
1752                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1753                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1754
1755                 device_printf(dev, "chip is in D%d power mode "
1756                     "-- setting to D0\n", pci_get_powerstate(dev));
1757
1758                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1759
1760                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1761                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1762         }
1763 #endif  /* !BURN_BRIDGE */
1764
1765         /*
1766          * Map control/status registers.
1767          */
1768         pci_enable_busmaster(dev);
1769
1770         rid = BGE_PCI_BAR0;
1771         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1772             RF_ACTIVE);
1773
1774         if (sc->bge_res == NULL) {
1775                 device_printf(dev, "couldn't map memory\n");
1776                 return ENXIO;
1777         }
1778
1779         sc->bge_btag = rman_get_bustag(sc->bge_res);
1780         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1781
1782         /* Save various chip information */
1783         sc->bge_chipid =
1784             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1785             BGE_PCIMISCCTL_ASICREV;
1786         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1787         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1788
1789         /* Save chipset family. */
1790         switch (sc->bge_asicrev) {
1791         case BGE_ASICREV_BCM5700:
1792         case BGE_ASICREV_BCM5701:
1793         case BGE_ASICREV_BCM5703:
1794         case BGE_ASICREV_BCM5704:
1795                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1796                 break;
1797
1798         case BGE_ASICREV_BCM5714_A0:
1799         case BGE_ASICREV_BCM5780:
1800         case BGE_ASICREV_BCM5714:
1801                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1802                 /* Fall through */
1803
1804         case BGE_ASICREV_BCM5750:
1805         case BGE_ASICREV_BCM5752:
1806         case BGE_ASICREV_BCM5755:
1807         case BGE_ASICREV_BCM5787:
1808         case BGE_ASICREV_BCM5906:
1809                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1810                 /* Fall through */
1811
1812         case BGE_ASICREV_BCM5705:
1813                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1814                 break;
1815         }
1816
1817         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
1818                 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
1819
1820         /*
1821          * Set various quirk flags.
1822          */
1823
1824         sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1825         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1826             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1827              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1828               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1829             sc->bge_asicrev == BGE_ASICREV_BCM5906)
1830                 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1831
1832         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1833             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1834                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1835
1836         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1837             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1838                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1839
1840         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1841                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1842
1843         if (BGE_IS_5705_PLUS(sc)) {
1844                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1845                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1846                         uint32_t product = pci_get_device(dev);
1847
1848                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
1849                             product != PCI_PRODUCT_BROADCOM_BCM5756)
1850                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1851                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1852                                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1853                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1854                         sc->bge_flags |= BGE_FLAG_BER_BUG;
1855                 }
1856         }
1857
1858         /* Allocate interrupt */
1859         rid = 0;
1860
1861         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1862             RF_SHAREABLE | RF_ACTIVE);
1863
1864         if (sc->bge_irq == NULL) {
1865                 device_printf(dev, "couldn't map interrupt\n");
1866                 error = ENXIO;
1867                 goto fail;
1868         }
1869
1870         /*
1871          * Check if this is a PCI-X or PCI Express device.
1872          */
1873         if (BGE_IS_5705_PLUS(sc)) {
1874                 if (pci_get_pciecap_ptr(dev) != 0) {
1875                         sc->bge_flags |= BGE_FLAG_PCIE;
1876                         pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1877                 }
1878         } else {
1879                 /*
1880                  * Check if the device is in PCI-X Mode.
1881                  * (This bit is not valid on PCI Express controllers.)
1882                  */
1883                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1884                     BGE_PCISTATE_PCI_BUSMODE) == 0)
1885                         sc->bge_flags |= BGE_FLAG_PCIX;
1886         }
1887
1888         device_printf(dev, "CHIP ID 0x%08x; "
1889                       "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
1890                       sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
1891                       (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
1892                       : ((sc->bge_flags & BGE_FLAG_PCIE) ?
1893                         "PCI-E" : "PCI"));
1894
1895         ifp = &sc->arpcom.ac_if;
1896         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1897
1898         /* Try to reset the chip. */
1899         bge_reset(sc);
1900
1901         if (bge_chipinit(sc)) {
1902                 device_printf(dev, "chip initialization failed\n");
1903                 error = ENXIO;
1904                 goto fail;
1905         }
1906
1907         /*
1908          * Get station address
1909          */
1910         error = bge_get_eaddr(sc, ether_addr);
1911         if (error) {
1912                 device_printf(dev, "failed to read station address\n");
1913                 goto fail;
1914         }
1915
1916         /* 5705/5750 limits RX return ring to 512 entries. */
1917         if (BGE_IS_5705_PLUS(sc))
1918                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1919         else
1920                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1921
1922         error = bge_dma_alloc(sc);
1923         if (error)
1924                 goto fail;
1925
1926         /* Set default tuneable values. */
1927         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1928         sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
1929         sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
1930         sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
1931         sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
1932
1933         /* Set up ifnet structure */
1934         ifp->if_softc = sc;
1935         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1936         ifp->if_ioctl = bge_ioctl;
1937         ifp->if_start = bge_start;
1938 #ifdef DEVICE_POLLING
1939         ifp->if_poll = bge_poll;
1940 #endif
1941         ifp->if_watchdog = bge_watchdog;
1942         ifp->if_init = bge_init;
1943         ifp->if_mtu = ETHERMTU;
1944         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1945         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1946         ifq_set_ready(&ifp->if_snd);
1947
1948         /*
1949          * 5700 B0 chips do not support checksumming correctly due
1950          * to hardware bugs.
1951          */
1952         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
1953                 ifp->if_capabilities |= IFCAP_HWCSUM;
1954                 ifp->if_hwassist = BGE_CSUM_FEATURES;
1955         }
1956         ifp->if_capenable = ifp->if_capabilities;
1957
1958         /*
1959          * Figure out what sort of media we have by checking the
1960          * hardware config word in the first 32k of NIC internal memory,
1961          * or fall back to examining the EEPROM if necessary.
1962          * Note: on some BCM5700 cards, this value appears to be unset.
1963          * If that's the case, we have to rely on identifying the NIC
1964          * by its PCI subsystem ID, as we do below for the SysKonnect
1965          * SK-9D41.
1966          */
1967         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1968                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1969         else {
1970                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1971                                     sizeof(hwcfg))) {
1972                         device_printf(dev, "failed to read EEPROM\n");
1973                         error = ENXIO;
1974                         goto fail;
1975                 }
1976                 hwcfg = ntohl(hwcfg);
1977         }
1978
1979         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1980                 sc->bge_flags |= BGE_FLAG_TBI;
1981
1982         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1983         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1984                 sc->bge_flags |= BGE_FLAG_TBI;
1985
1986         if (sc->bge_flags & BGE_FLAG_TBI) {
1987                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1988                     bge_ifmedia_upd, bge_ifmedia_sts);
1989                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1990                 ifmedia_add(&sc->bge_ifmedia,
1991                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1992                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1993                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1994                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
1995         } else {
1996                 /*
1997                  * Do transceiver setup.
1998                  */
1999                 if (mii_phy_probe(dev, &sc->bge_miibus,
2000                     bge_ifmedia_upd, bge_ifmedia_sts)) {
2001                         device_printf(dev, "MII without any PHY!\n");
2002                         error = ENXIO;
2003                         goto fail;
2004                 }
2005         }
2006
2007         /*
2008          * When using the BCM5701 in PCI-X mode, data corruption has
2009          * been observed in the first few bytes of some received packets.
2010          * Aligning the packet buffer in memory eliminates the corruption.
2011          * Unfortunately, this misaligns the packet payloads.  On platforms
2012          * which do not support unaligned accesses, we will realign the
2013          * payloads by copying the received packets.
2014          */
2015         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2016             (sc->bge_flags & BGE_FLAG_PCIX))
2017                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2018
2019         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2020             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2021                 sc->bge_link_upd = bge_bcm5700_link_upd;
2022                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2023         } else if (sc->bge_flags & BGE_FLAG_TBI) {
2024                 sc->bge_link_upd = bge_tbi_link_upd;
2025                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2026         } else {
2027                 sc->bge_link_upd = bge_copper_link_upd;
2028                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2029         }
2030
2031         /*
2032          * Create sysctl nodes.
2033          */
2034         sysctl_ctx_init(&sc->bge_sysctl_ctx);
2035         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2036                                               SYSCTL_STATIC_CHILDREN(_hw),
2037                                               OID_AUTO,
2038                                               device_get_nameunit(dev),
2039                                               CTLFLAG_RD, 0, "");
2040         if (sc->bge_sysctl_tree == NULL) {
2041                 device_printf(dev, "can't add sysctl node\n");
2042                 error = ENXIO;
2043                 goto fail;
2044         }
2045
2046         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2047                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2048                         OID_AUTO, "rx_coal_ticks",
2049                         CTLTYPE_INT | CTLFLAG_RW,
2050                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
2051                         "Receive coalescing ticks (usec).");
2052         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2053                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2054                         OID_AUTO, "tx_coal_ticks",
2055                         CTLTYPE_INT | CTLFLAG_RW,
2056                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
2057                         "Transmit coalescing ticks (usec).");
2058         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2059                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2060                         OID_AUTO, "rx_max_coal_bds",
2061                         CTLTYPE_INT | CTLFLAG_RW,
2062                         sc, 0, bge_sysctl_rx_max_coal_bds, "I",
2063                         "Receive max coalesced BD count.");
2064         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2065                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2066                         OID_AUTO, "tx_max_coal_bds",
2067                         CTLTYPE_INT | CTLFLAG_RW,
2068                         sc, 0, bge_sysctl_tx_max_coal_bds, "I",
2069                         "Transmit max coalesced BD count.");
2070
2071         /*
2072          * Call MI attach routine.
2073          */
2074         ether_ifattach(ifp, ether_addr, NULL);
2075
2076         error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE,
2077                                bge_intr, sc, &sc->bge_intrhand,
2078                                ifp->if_serializer);
2079         if (error) {
2080                 ether_ifdetach(ifp);
2081                 device_printf(dev, "couldn't set up irq\n");
2082                 goto fail;
2083         }
2084
2085         ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bge_irq));
2086         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2087
2088         return(0);
2089 fail:
2090         bge_detach(dev);
2091         return(error);
2092 }
2093
2094 static int
2095 bge_detach(device_t dev)
2096 {
2097         struct bge_softc *sc = device_get_softc(dev);
2098
2099         if (device_is_attached(dev)) {
2100                 struct ifnet *ifp = &sc->arpcom.ac_if;
2101
2102                 lwkt_serialize_enter(ifp->if_serializer);
2103                 bge_stop(sc);
2104                 bge_reset(sc);
2105                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2106                 lwkt_serialize_exit(ifp->if_serializer);
2107
2108                 ether_ifdetach(ifp);
2109         }
2110
2111         if (sc->bge_flags & BGE_FLAG_TBI)
2112                 ifmedia_removeall(&sc->bge_ifmedia);
2113         if (sc->bge_miibus)
2114                 device_delete_child(dev, sc->bge_miibus);
2115         bus_generic_detach(dev);
2116
2117         if (sc->bge_irq != NULL)
2118                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2119
2120         if (sc->bge_res != NULL)
2121                 bus_release_resource(dev, SYS_RES_MEMORY,
2122                     BGE_PCI_BAR0, sc->bge_res);
2123
2124         if (sc->bge_sysctl_tree != NULL)
2125                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2126
2127         bge_dma_free(sc);
2128
2129         return 0;
2130 }
2131
2132 static void
2133 bge_reset(struct bge_softc *sc)
2134 {
2135         device_t dev;
2136         uint32_t cachesize, command, pcistate, reset;
2137         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2138         int i, val = 0;
2139
2140         dev = sc->bge_dev;
2141
2142         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2143             sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2144                 if (sc->bge_flags & BGE_FLAG_PCIE)
2145                         write_op = bge_writemem_direct;
2146                 else
2147                         write_op = bge_writemem_ind;
2148         } else {
2149                 write_op = bge_writereg_ind;
2150         }
2151
2152         /* Save some important PCI state. */
2153         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2154         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2155         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2156
2157         pci_write_config(dev, BGE_PCI_MISC_CTL,
2158             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2159             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2160
2161         /* Disable fastboot on controllers that support it. */
2162         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2163             sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2164             sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2165                 if (bootverbose)
2166                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2167                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2168         }
2169
2170         /*
2171          * Write the magic number to SRAM at offset 0xB50.
2172          * When firmware finishes its initialization it will
2173          * write ~BGE_MAGIC_NUMBER to the same location.
2174          */
2175         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2176
2177         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2178
2179         /* XXX: Broadcom Linux driver. */
2180         if (sc->bge_flags & BGE_FLAG_PCIE) {
2181                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
2182                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
2183                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2184                         /* Prevent PCIE link training during global reset */
2185                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2186                         reset |= (1<<29);
2187                 }
2188         }
2189
2190         /*
2191          * Set GPHY Power Down Override to leave GPHY
2192          * powered up in D0 uninitialized.
2193          */
2194         if (BGE_IS_5705_PLUS(sc))
2195                 reset |= 0x04000000;
2196
2197         /* Issue global reset */
2198         write_op(sc, BGE_MISC_CFG, reset);
2199
2200         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2201                 uint32_t status, ctrl;
2202
2203                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2204                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2205                     status | BGE_VCPU_STATUS_DRV_RESET);
2206                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2207                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2208                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2209         }
2210
2211         DELAY(1000);
2212
2213         /* XXX: Broadcom Linux driver. */
2214         if (sc->bge_flags & BGE_FLAG_PCIE) {
2215                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2216                         uint32_t v;
2217
2218                         DELAY(500000); /* wait for link training to complete */
2219                         v = pci_read_config(dev, 0xc4, 4);
2220                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2221                 }
2222                 /*
2223                  * Set PCIE max payload size to 128 bytes and
2224                  * clear error status.
2225                  */
2226                 pci_write_config(dev, 0xd8, 0xf5000, 4);
2227         }
2228
2229         /* Reset some of the PCI state that got zapped by reset */
2230         pci_write_config(dev, BGE_PCI_MISC_CTL,
2231             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2232             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2233         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2234         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2235         write_op(sc, BGE_MISC_CFG, (65 << 1));
2236
2237         /* Enable memory arbiter. */
2238         if (BGE_IS_5714_FAMILY(sc)) {
2239                 uint32_t val;
2240
2241                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2242                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2243         } else {
2244                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2245         }
2246
2247         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2248                 for (i = 0; i < BGE_TIMEOUT; i++) {
2249                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2250                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2251                                 break;
2252                         DELAY(100);
2253                 }
2254                 if (i == BGE_TIMEOUT) {
2255                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2256                         return;
2257                 }
2258         } else {
2259                 /*
2260                  * Poll until we see the 1's complement of the magic number.
2261                  * This indicates that the firmware initialization
2262                  * is complete.
2263                  */
2264                 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2265                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2266                         if (val == ~BGE_MAGIC_NUMBER)
2267                                 break;
2268                         DELAY(10);
2269                 }
2270                 if (i == BGE_FIRMWARE_TIMEOUT) {
2271                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2272                                   "timed out, found 0x%08x\n", val);
2273                         return;
2274                 }
2275         }
2276
2277         /*
2278          * XXX Wait for the value of the PCISTATE register to
2279          * return to its original pre-reset state. This is a
2280          * fairly good indicator of reset completion. If we don't
2281          * wait for the reset to fully complete, trying to read
2282          * from the device's non-PCI registers may yield garbage
2283          * results.
2284          */
2285         for (i = 0; i < BGE_TIMEOUT; i++) {
2286                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2287                         break;
2288                 DELAY(10);
2289         }
2290
2291         if (sc->bge_flags & BGE_FLAG_PCIE) {
2292                 reset = bge_readmem_ind(sc, 0x7c00);
2293                 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2294         }
2295
2296         /* Fix up byte swapping */
2297         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2298             BGE_MODECTL_BYTESWAP_DATA);
2299
2300         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2301
2302         /*
2303          * The 5704 in TBI mode apparently needs some special
2304          * adjustment to insure the SERDES drive level is set
2305          * to 1.2V.
2306          */
2307         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2308             (sc->bge_flags & BGE_FLAG_TBI)) {
2309                 uint32_t serdescfg;
2310
2311                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2312                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2313                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2314         }
2315
2316         /* XXX: Broadcom Linux driver. */
2317         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2318             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2319                 uint32_t v;
2320
2321                 v = CSR_READ_4(sc, 0x7c00);
2322                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2323         }
2324
2325         DELAY(10000);
2326 }
2327
2328 /*
2329  * Frame reception handling. This is called if there's a frame
2330  * on the receive return list.
2331  *
2332  * Note: we have to be able to handle two possibilities here:
2333  * 1) the frame is from the jumbo recieve ring
2334  * 2) the frame is from the standard receive ring
2335  */
2336
2337 static void
2338 bge_rxeof(struct bge_softc *sc)
2339 {
2340         struct ifnet *ifp;
2341         int stdcnt = 0, jumbocnt = 0;
2342         struct mbuf_chain chain[MAXCPU];
2343
2344         if (sc->bge_rx_saved_considx ==
2345             sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2346                 return;
2347
2348         ether_input_chain_init(chain);
2349
2350         ifp = &sc->arpcom.ac_if;
2351
2352         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2353                         sc->bge_cdata.bge_rx_return_ring_map,
2354                         BUS_DMASYNC_POSTREAD);
2355         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2356                         sc->bge_cdata.bge_rx_std_ring_map,
2357                         BUS_DMASYNC_POSTREAD);
2358         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2359                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2360                                 sc->bge_cdata.bge_rx_jumbo_ring_map,
2361                                 BUS_DMASYNC_POSTREAD);
2362         }
2363
2364         while (sc->bge_rx_saved_considx !=
2365                sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2366                 struct bge_rx_bd        *cur_rx;
2367                 uint32_t                rxidx;
2368                 struct mbuf             *m = NULL;
2369                 uint16_t                vlan_tag = 0;
2370                 int                     have_tag = 0;
2371
2372                 cur_rx =
2373             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2374
2375                 rxidx = cur_rx->bge_idx;
2376                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2377                 logif(rx_pkt);
2378
2379                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2380                         have_tag = 1;
2381                         vlan_tag = cur_rx->bge_vlan_tag;
2382                 }
2383
2384                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2385                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2386                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2387                         sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2388                         jumbocnt++;
2389                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2390                                 ifp->if_ierrors++;
2391                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2392                                 continue;
2393                         }
2394                         if (bge_newbuf_jumbo(sc,
2395                             sc->bge_jumbo, NULL) == ENOBUFS) {
2396                                 ifp->if_ierrors++;
2397                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2398                                 continue;
2399                         }
2400                 } else {
2401                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2402                         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2403                                         sc->bge_cdata.bge_rx_std_dmamap[rxidx],
2404                                         BUS_DMASYNC_POSTREAD);
2405                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2406                                 sc->bge_cdata.bge_rx_std_dmamap[rxidx]);
2407                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2408                         sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2409                         stdcnt++;
2410                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2411                                 ifp->if_ierrors++;
2412                                 bge_newbuf_std(sc, sc->bge_std, m);
2413                                 continue;
2414                         }
2415                         if (bge_newbuf_std(sc, sc->bge_std,
2416                             NULL) == ENOBUFS) {
2417                                 ifp->if_ierrors++;
2418                                 bge_newbuf_std(sc, sc->bge_std, m);
2419                                 continue;
2420                         }
2421                 }
2422
2423                 ifp->if_ipackets++;
2424 #ifndef __i386__
2425                 /*
2426                  * The i386 allows unaligned accesses, but for other
2427                  * platforms we must make sure the payload is aligned.
2428                  */
2429                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2430                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2431                             cur_rx->bge_len);
2432                         m->m_data += ETHER_ALIGN;
2433                 }
2434 #endif
2435                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2436                 m->m_pkthdr.rcvif = ifp;
2437
2438                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2439                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2440                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2441                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2442                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2443                         }
2444                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2445                             m->m_pkthdr.len >= BGE_MIN_FRAME) {
2446                                 m->m_pkthdr.csum_data =
2447                                         cur_rx->bge_tcp_udp_csum;
2448                                 m->m_pkthdr.csum_flags |=
2449                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2450                         }
2451                 }
2452
2453                 /*
2454                  * If we received a packet with a vlan tag, pass it
2455                  * to vlan_input() instead of ether_input().
2456                  */
2457                 if (have_tag) {
2458                         m->m_flags |= M_VLANTAG;
2459                         m->m_pkthdr.ether_vlantag = vlan_tag;
2460                         have_tag = vlan_tag = 0;
2461                 }
2462                 ether_input_chain(ifp, m, chain);
2463         }
2464
2465         ether_input_dispatch(chain);
2466
2467         if (stdcnt > 0) {
2468                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2469                                 sc->bge_cdata.bge_rx_std_ring_map,
2470                                 BUS_DMASYNC_PREWRITE);
2471         }
2472
2473         if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) {
2474                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2475                                 sc->bge_cdata.bge_rx_jumbo_ring_map,
2476                                 BUS_DMASYNC_PREWRITE);
2477         }
2478
2479         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2480         if (stdcnt)
2481                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2482         if (jumbocnt)
2483                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2484 }
2485
2486 static void
2487 bge_txeof(struct bge_softc *sc)
2488 {
2489         struct bge_tx_bd *cur_tx = NULL;
2490         struct ifnet *ifp;
2491
2492         if (sc->bge_tx_saved_considx ==
2493             sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2494                 return;
2495
2496         ifp = &sc->arpcom.ac_if;
2497
2498         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
2499                         sc->bge_cdata.bge_tx_ring_map,
2500                         BUS_DMASYNC_POSTREAD);
2501
2502         /*
2503          * Go through our tx ring and free mbufs for those
2504          * frames that have been sent.
2505          */
2506         while (sc->bge_tx_saved_considx !=
2507                sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2508                 uint32_t idx = 0;
2509
2510                 idx = sc->bge_tx_saved_considx;
2511                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2512                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2513                         ifp->if_opackets++;
2514                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2515                         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2516                                         sc->bge_cdata.bge_tx_dmamap[idx],
2517                                         BUS_DMASYNC_POSTWRITE);
2518                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2519                             sc->bge_cdata.bge_tx_dmamap[idx]);
2520                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2521                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2522                 }
2523                 sc->bge_txcnt--;
2524                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2525                 logif(tx_pkt);
2526         }
2527
2528         if (cur_tx != NULL &&
2529             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2530             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2531                 ifp->if_flags &= ~IFF_OACTIVE;
2532
2533         if (sc->bge_txcnt == 0)
2534                 ifp->if_timer = 0;
2535
2536         if (!ifq_is_empty(&ifp->if_snd))
2537                 if_devstart(ifp);
2538 }
2539
2540 #ifdef DEVICE_POLLING
2541
2542 static void
2543 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2544 {
2545         struct bge_softc *sc = ifp->if_softc;
2546         uint32_t status;
2547
2548         switch(cmd) {
2549         case POLL_REGISTER:
2550                 bge_disable_intr(sc);
2551                 break;
2552         case POLL_DEREGISTER:
2553                 bge_enable_intr(sc);
2554                 break;
2555         case POLL_AND_CHECK_STATUS:
2556                 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2557                                 sc->bge_cdata.bge_status_map,
2558                                 BUS_DMASYNC_POSTREAD);
2559
2560                 /*
2561                  * Process link state changes.
2562                  */
2563                 status = CSR_READ_4(sc, BGE_MAC_STS);
2564                 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2565                         sc->bge_link_evt = 0;
2566                         sc->bge_link_upd(sc, status);
2567                 }
2568                 /* fall through */
2569         case POLL_ONLY:
2570                 if (ifp->if_flags & IFF_RUNNING) {
2571                         bge_rxeof(sc);
2572                         bge_txeof(sc);
2573                 }
2574                 break;
2575         }
2576 }
2577
2578 #endif
2579
2580 static void
2581 bge_intr(void *xsc)
2582 {
2583         struct bge_softc *sc = xsc;
2584         struct ifnet *ifp = &sc->arpcom.ac_if;
2585         uint32_t status;
2586
2587         logif(intr);
2588
2589         /*
2590          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2591          * disable interrupts by writing nonzero like we used to, since with
2592          * our current organization this just gives complications and
2593          * pessimizations for re-enabling interrupts.  We used to have races
2594          * instead of the necessary complications.  Disabling interrupts
2595          * would just reduce the chance of a status update while we are
2596          * running (by switching to the interrupt-mode coalescence
2597          * parameters), but this chance is already very low so it is more
2598          * efficient to get another interrupt than prevent it.
2599          *
2600          * We do the ack first to ensure another interrupt if there is a
2601          * status update after the ack.  We don't check for the status
2602          * changing later because it is more efficient to get another
2603          * interrupt than prevent it, not quite as above (not checking is
2604          * a smaller optimization than not toggling the interrupt enable,
2605          * since checking doesn't involve PCI accesses and toggling require
2606          * the status check).  So toggling would probably be a pessimization
2607          * even with MSI.  It would only be needed for using a task queue.
2608          */
2609         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
2610
2611         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2612                         sc->bge_cdata.bge_status_map,
2613                         BUS_DMASYNC_POSTREAD);
2614
2615         /*
2616          * Process link state changes.
2617          */
2618         status = CSR_READ_4(sc, BGE_MAC_STS);
2619         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2620                 sc->bge_link_evt = 0;
2621                 sc->bge_link_upd(sc, status);
2622         }
2623
2624         if (ifp->if_flags & IFF_RUNNING) {
2625                 /* Check RX return ring producer/consumer */
2626                 bge_rxeof(sc);
2627
2628                 /* Check TX ring producer/consumer */
2629                 bge_txeof(sc);
2630         }
2631
2632         if (sc->bge_coal_chg)
2633                 bge_coal_change(sc);
2634 }
2635
2636 static void
2637 bge_tick(void *xsc)
2638 {
2639         struct bge_softc *sc = xsc;
2640         struct ifnet *ifp = &sc->arpcom.ac_if;
2641
2642         lwkt_serialize_enter(ifp->if_serializer);
2643
2644         if (BGE_IS_5705_PLUS(sc))
2645                 bge_stats_update_regs(sc);
2646         else
2647                 bge_stats_update(sc);
2648
2649         if (sc->bge_flags & BGE_FLAG_TBI) {
2650                 /*
2651                  * Since in TBI mode auto-polling can't be used we should poll
2652                  * link status manually. Here we register pending link event
2653                  * and trigger interrupt.
2654                  */
2655                 sc->bge_link_evt++;
2656                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2657         } else if (!sc->bge_link) {
2658                 mii_tick(device_get_softc(sc->bge_miibus));
2659         }
2660
2661         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2662
2663         lwkt_serialize_exit(ifp->if_serializer);
2664 }
2665
2666 static void
2667 bge_stats_update_regs(struct bge_softc *sc)
2668 {
2669         struct ifnet *ifp = &sc->arpcom.ac_if;
2670         struct bge_mac_stats_regs stats;
2671         uint32_t *s;
2672         int i;
2673
2674         s = (uint32_t *)&stats;
2675         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2676                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2677                 s++;
2678         }
2679
2680         ifp->if_collisions +=
2681            (stats.dot3StatsSingleCollisionFrames +
2682            stats.dot3StatsMultipleCollisionFrames +
2683            stats.dot3StatsExcessiveCollisions +
2684            stats.dot3StatsLateCollisions) -
2685            ifp->if_collisions;
2686 }
2687
2688 static void
2689 bge_stats_update(struct bge_softc *sc)
2690 {
2691         struct ifnet *ifp = &sc->arpcom.ac_if;
2692         bus_size_t stats;
2693
2694         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2695
2696 #define READ_STAT(sc, stats, stat)      \
2697         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2698
2699         ifp->if_collisions +=
2700            (READ_STAT(sc, stats,
2701                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2702             READ_STAT(sc, stats,
2703                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2704             READ_STAT(sc, stats,
2705                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2706             READ_STAT(sc, stats,
2707                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
2708            ifp->if_collisions;
2709
2710 #undef READ_STAT
2711
2712 #ifdef notdef
2713         ifp->if_collisions +=
2714            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2715            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2716            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2717            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2718            ifp->if_collisions;
2719 #endif
2720 }
2721
2722 /*
2723  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2724  * pointers to descriptors.
2725  */
2726 static int
2727 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
2728 {
2729         struct bge_tx_bd *d = NULL;
2730         uint16_t csum_flags = 0;
2731         struct bge_dmamap_arg ctx;
2732         bus_dma_segment_t segs[BGE_NSEG_NEW];
2733         bus_dmamap_t map;
2734         int error, maxsegs, idx, i;
2735         struct mbuf *m_head = *m_head0;
2736
2737         if (m_head->m_pkthdr.csum_flags) {
2738                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2739                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2740                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2741                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2742                 if (m_head->m_flags & M_LASTFRAG)
2743                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2744                 else if (m_head->m_flags & M_FRAG)
2745                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2746         }
2747
2748         idx = *txidx;
2749         map = sc->bge_cdata.bge_tx_dmamap[idx];
2750
2751         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2752         KASSERT(maxsegs >= BGE_NSEG_SPARE,
2753                 ("not enough segments %d\n", maxsegs));
2754
2755         if (maxsegs > BGE_NSEG_NEW)
2756                 maxsegs = BGE_NSEG_NEW;
2757
2758         /*
2759          * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2760          * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2761          * but when such padded frames employ the bge IP/TCP checksum
2762          * offload, the hardware checksum assist gives incorrect results
2763          * (possibly from incorporating its own padding into the UDP/TCP
2764          * checksum; who knows).  If we pad such runts with zeros, the
2765          * onboard checksum comes out correct.
2766          */
2767         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2768             m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2769                 error = m_devpad(m_head, BGE_MIN_FRAME);
2770                 if (error)
2771                         goto back;
2772         }
2773
2774         ctx.bge_segs = segs;
2775         ctx.bge_maxsegs = maxsegs;
2776         error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map, m_head,
2777                                      bge_dma_map_mbuf, &ctx, BUS_DMA_NOWAIT);
2778         if (error == EFBIG || ctx.bge_maxsegs == 0) {
2779                 struct mbuf *m_new;
2780
2781                 if (!error)
2782                         bus_dmamap_unload(sc->bge_cdata.bge_mtag, map);
2783
2784                 m_new = m_defrag(m_head, MB_DONTWAIT);
2785                 if (m_new == NULL) {
2786                         if_printf(&sc->arpcom.ac_if,
2787                                   "could not defrag TX mbuf\n");
2788                         error = ENOBUFS;
2789                         goto back;
2790                 } else {
2791                         m_head = m_new;
2792                         *m_head0 = m_head;
2793                 }
2794
2795                 ctx.bge_segs = segs;
2796                 ctx.bge_maxsegs = maxsegs;
2797                 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2798                                              m_head, bge_dma_map_mbuf, &ctx,
2799                                              BUS_DMA_NOWAIT);
2800                 if (error || ctx.bge_maxsegs == 0) {
2801                         if_printf(&sc->arpcom.ac_if,
2802                                   "could not defrag TX mbuf\n");
2803                         if (!error) {
2804                                 bus_dmamap_unload(sc->bge_cdata.bge_mtag, map);
2805                                 error = EFBIG;
2806                         }
2807                         goto back;
2808                 }
2809         } else if (error) {
2810                 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
2811                 goto back;
2812         }
2813
2814         bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE);
2815
2816         for (i = 0; ; i++) {
2817                 d = &sc->bge_ldata.bge_tx_ring[idx];
2818
2819                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[i].ds_addr);
2820                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[i].ds_addr);
2821                 d->bge_len = segs[i].ds_len;
2822                 d->bge_flags = csum_flags;
2823
2824                 if (i == ctx.bge_maxsegs - 1)
2825                         break;
2826                 BGE_INC(idx, BGE_TX_RING_CNT);
2827         }
2828         /* Mark the last segment as end of packet... */
2829         d->bge_flags |= BGE_TXBDFLAG_END;
2830
2831         /* Set vlan tag to the first segment of the packet. */
2832         d = &sc->bge_ldata.bge_tx_ring[*txidx];
2833         if (m_head->m_flags & M_VLANTAG) {
2834                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2835                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
2836         } else {
2837                 d->bge_vlan_tag = 0;
2838         }
2839
2840         /*
2841          * Insure that the map for this transmission is placed at
2842          * the array index of the last descriptor in this chain.
2843          */
2844         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2845         sc->bge_cdata.bge_tx_dmamap[idx] = map;
2846         sc->bge_cdata.bge_tx_chain[idx] = m_head;
2847         sc->bge_txcnt += ctx.bge_maxsegs;
2848
2849         BGE_INC(idx, BGE_TX_RING_CNT);
2850         *txidx = idx;
2851 back:
2852         if (error) {
2853                 m_freem(m_head);
2854                 *m_head0 = NULL;
2855         }
2856         return error;
2857 }
2858
2859 /*
2860  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2861  * to the mbuf data regions directly in the transmit descriptors.
2862  */
2863 static void
2864 bge_start(struct ifnet *ifp)
2865 {
2866         struct bge_softc *sc = ifp->if_softc;
2867         struct mbuf *m_head = NULL;
2868         uint32_t prodidx;
2869         int need_trans;
2870
2871         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2872                 return;
2873
2874         prodidx = sc->bge_tx_prodidx;
2875
2876         need_trans = 0;
2877         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2878                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2879                 if (m_head == NULL)
2880                         break;
2881
2882                 /*
2883                  * XXX
2884                  * The code inside the if() block is never reached since we
2885                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2886                  * requests to checksum TCP/UDP in a fragmented packet.
2887                  *
2888                  * XXX
2889                  * safety overkill.  If this is a fragmented packet chain
2890                  * with delayed TCP/UDP checksums, then only encapsulate
2891                  * it if we have enough descriptors to handle the entire
2892                  * chain at once.
2893                  * (paranoia -- may not actually be needed)
2894                  */
2895                 if ((m_head->m_flags & M_FIRSTFRAG) &&
2896                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
2897                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2898                             m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
2899                                 ifp->if_flags |= IFF_OACTIVE;
2900                                 ifq_prepend(&ifp->if_snd, m_head);
2901                                 break;
2902                         }
2903                 }
2904
2905                 /*
2906                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2907                  * descriptors of the end of the ring.  Also make
2908                  * sure there are BGE_NSEG_SPARE descriptors for
2909                  * jumbo buffers' defragmentation.
2910                  */
2911                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2912                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
2913                         ifp->if_flags |= IFF_OACTIVE;
2914                         ifq_prepend(&ifp->if_snd, m_head);
2915                         break;
2916                 }
2917
2918                 /*
2919                  * Pack the data into the transmit ring. If we
2920                  * don't have room, set the OACTIVE flag and wait
2921                  * for the NIC to drain the ring.
2922                  */
2923                 if (bge_encap(sc, &m_head, &prodidx)) {
2924                         ifp->if_flags |= IFF_OACTIVE;
2925                         ifp->if_oerrors++;
2926                         break;
2927                 }
2928                 need_trans = 1;
2929
2930                 ETHER_BPF_MTAP(ifp, m_head);
2931         }
2932
2933         if (!need_trans)
2934                 return;
2935
2936         /* Transmit */
2937         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2938         /* 5700 b2 errata */
2939         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2940                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2941
2942         sc->bge_tx_prodidx = prodidx;
2943
2944         /*
2945          * Set a timeout in case the chip goes out to lunch.
2946          */
2947         ifp->if_timer = 5;
2948 }
2949
2950 static void
2951 bge_init(void *xsc)
2952 {
2953         struct bge_softc *sc = xsc;
2954         struct ifnet *ifp = &sc->arpcom.ac_if;
2955         uint16_t *m;
2956
2957         ASSERT_SERIALIZED(ifp->if_serializer);
2958
2959         if (ifp->if_flags & IFF_RUNNING)
2960                 return;
2961
2962         /* Cancel pending I/O and flush buffers. */
2963         bge_stop(sc);
2964         bge_reset(sc);
2965         bge_chipinit(sc);
2966
2967         /*
2968          * Init the various state machines, ring
2969          * control blocks and firmware.
2970          */
2971         if (bge_blockinit(sc)) {
2972                 if_printf(ifp, "initialization failure\n");
2973                 return;
2974         }
2975
2976         /* Specify MTU. */
2977         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2978             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2979
2980         /* Load our MAC address. */
2981         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2982         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2983         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2984
2985         /* Enable or disable promiscuous mode as needed. */
2986         bge_setpromisc(sc);
2987
2988         /* Program multicast filter. */
2989         bge_setmulti(sc);
2990
2991         /* Init RX ring. */
2992         bge_init_rx_ring_std(sc);
2993
2994         /*
2995          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2996          * memory to insure that the chip has in fact read the first
2997          * entry of the ring.
2998          */
2999         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3000                 uint32_t                v, i;
3001                 for (i = 0; i < 10; i++) {
3002                         DELAY(20);
3003                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3004                         if (v == (MCLBYTES - ETHER_ALIGN))
3005                                 break;
3006                 }
3007                 if (i == 10)
3008                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3009         }
3010
3011         /* Init jumbo RX ring. */
3012         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
3013                 bge_init_rx_ring_jumbo(sc);
3014
3015         /* Init our RX return ring index */
3016         sc->bge_rx_saved_considx = 0;
3017
3018         /* Init TX ring. */
3019         bge_init_tx_ring(sc);
3020
3021         /* Turn on transmitter */
3022         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
3023
3024         /* Turn on receiver */
3025         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3026
3027         /* Tell firmware we're alive. */
3028         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3029
3030         /* Enable host interrupts if polling(4) is not enabled. */
3031         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
3032 #ifdef DEVICE_POLLING
3033         if (ifp->if_flags & IFF_POLLING)
3034                 bge_disable_intr(sc);
3035         else
3036 #endif
3037         bge_enable_intr(sc);
3038
3039         bge_ifmedia_upd(ifp);
3040
3041         ifp->if_flags |= IFF_RUNNING;
3042         ifp->if_flags &= ~IFF_OACTIVE;
3043
3044         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3045 }
3046
3047 /*
3048  * Set media options.
3049  */
3050 static int
3051 bge_ifmedia_upd(struct ifnet *ifp)
3052 {
3053         struct bge_softc *sc = ifp->if_softc;
3054
3055         /* If this is a 1000baseX NIC, enable the TBI port. */
3056         if (sc->bge_flags & BGE_FLAG_TBI) {
3057                 struct ifmedia *ifm = &sc->bge_ifmedia;
3058
3059                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3060                         return(EINVAL);
3061
3062                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3063                 case IFM_AUTO:
3064                         /*
3065                          * The BCM5704 ASIC appears to have a special
3066                          * mechanism for programming the autoneg
3067                          * advertisement registers in TBI mode.
3068                          */
3069                         if (!bge_fake_autoneg &&
3070                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3071                                 uint32_t sgdig;
3072
3073                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3074                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3075                                 sgdig |= BGE_SGDIGCFG_AUTO |
3076                                          BGE_SGDIGCFG_PAUSE_CAP |
3077                                          BGE_SGDIGCFG_ASYM_PAUSE;
3078                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3079                                             sgdig | BGE_SGDIGCFG_SEND);
3080                                 DELAY(5);
3081                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3082                         }
3083                         break;
3084                 case IFM_1000_SX:
3085                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3086                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3087                                     BGE_MACMODE_HALF_DUPLEX);
3088                         } else {
3089                                 BGE_SETBIT(sc, BGE_MAC_MODE,
3090                                     BGE_MACMODE_HALF_DUPLEX);
3091                         }
3092                         break;
3093                 default:
3094                         return(EINVAL);
3095                 }
3096         } else {
3097                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3098
3099                 sc->bge_link_evt++;
3100                 sc->bge_link = 0;
3101                 if (mii->mii_instance) {
3102                         struct mii_softc *miisc;
3103
3104                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3105                                 mii_phy_reset(miisc);
3106                 }
3107                 mii_mediachg(mii);
3108         }
3109         return(0);
3110 }
3111
3112 /*
3113  * Report current media status.
3114  */
3115 static void
3116 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3117 {
3118         struct bge_softc *sc = ifp->if_softc;
3119
3120         if (sc->bge_flags & BGE_FLAG_TBI) {
3121                 ifmr->ifm_status = IFM_AVALID;
3122                 ifmr->ifm_active = IFM_ETHER;
3123                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3124                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3125                         ifmr->ifm_status |= IFM_ACTIVE;
3126                 } else {
3127                         ifmr->ifm_active |= IFM_NONE;
3128                         return;
3129                 }
3130
3131                 ifmr->ifm_active |= IFM_1000_SX;
3132                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3133                         ifmr->ifm_active |= IFM_HDX;
3134                 else
3135                         ifmr->ifm_active |= IFM_FDX;
3136         } else {
3137                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3138
3139                 mii_pollstat(mii);
3140                 ifmr->ifm_active = mii->mii_media_active;
3141                 ifmr->ifm_status = mii->mii_media_status;
3142         }
3143 }
3144
3145 static int
3146 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3147 {
3148         struct bge_softc *sc = ifp->if_softc;
3149         struct ifreq *ifr = (struct ifreq *)data;
3150         int mask, error = 0;
3151
3152         ASSERT_SERIALIZED(ifp->if_serializer);
3153
3154         switch (command) {
3155         case SIOCSIFMTU:
3156                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3157                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3158                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3159                         error = EINVAL;
3160                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3161                         ifp->if_mtu = ifr->ifr_mtu;
3162                         ifp->if_flags &= ~IFF_RUNNING;
3163                         bge_init(sc);
3164                 }
3165                 break;
3166         case SIOCSIFFLAGS:
3167                 if (ifp->if_flags & IFF_UP) {
3168                         if (ifp->if_flags & IFF_RUNNING) {
3169                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3170
3171                                 /*
3172                                  * If only the state of the PROMISC flag
3173                                  * changed, then just use the 'set promisc
3174                                  * mode' command instead of reinitializing
3175                                  * the entire NIC. Doing a full re-init
3176                                  * means reloading the firmware and waiting
3177                                  * for it to start up, which may take a
3178                                  * second or two.  Similarly for ALLMULTI.
3179                                  */
3180                                 if (mask & IFF_PROMISC)
3181                                         bge_setpromisc(sc);
3182                                 if (mask & IFF_ALLMULTI)
3183                                         bge_setmulti(sc);
3184                         } else {
3185                                 bge_init(sc);
3186                         }
3187                 } else {
3188                         if (ifp->if_flags & IFF_RUNNING)
3189                                 bge_stop(sc);
3190                 }
3191                 sc->bge_if_flags = ifp->if_flags;
3192                 break;
3193         case SIOCADDMULTI:
3194         case SIOCDELMULTI:
3195                 if (ifp->if_flags & IFF_RUNNING)
3196                         bge_setmulti(sc);
3197                 break;
3198         case SIOCSIFMEDIA:
3199         case SIOCGIFMEDIA:
3200                 if (sc->bge_flags & BGE_FLAG_TBI) {
3201                         error = ifmedia_ioctl(ifp, ifr,
3202                             &sc->bge_ifmedia, command);
3203                 } else {
3204                         struct mii_data *mii;
3205
3206                         mii = device_get_softc(sc->bge_miibus);
3207                         error = ifmedia_ioctl(ifp, ifr,
3208                                               &mii->mii_media, command);
3209                 }
3210                 break;
3211         case SIOCSIFCAP:
3212                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3213                 if (mask & IFCAP_HWCSUM) {
3214                         ifp->if_capenable ^= IFCAP_HWCSUM;
3215                         if (IFCAP_HWCSUM & ifp->if_capenable)
3216                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3217                         else
3218                                 ifp->if_hwassist = 0;
3219                 }
3220                 break;
3221         default:
3222                 error = ether_ioctl(ifp, command, data);
3223                 break;
3224         }
3225         return error;
3226 }
3227
3228 static void
3229 bge_watchdog(struct ifnet *ifp)
3230 {
3231         struct bge_softc *sc = ifp->if_softc;
3232
3233         if_printf(ifp, "watchdog timeout -- resetting\n");
3234
3235         ifp->if_flags &= ~IFF_RUNNING;
3236         bge_init(sc);
3237
3238         ifp->if_oerrors++;
3239
3240         if (!ifq_is_empty(&ifp->if_snd))
3241                 if_devstart(ifp);
3242 }
3243
3244 /*
3245  * Stop the adapter and free any mbufs allocated to the
3246  * RX and TX lists.
3247  */
3248 static void
3249 bge_stop(struct bge_softc *sc)
3250 {
3251         struct ifnet *ifp = &sc->arpcom.ac_if;
3252         struct ifmedia_entry *ifm;
3253         struct mii_data *mii = NULL;
3254         int mtmp, itmp;
3255
3256         ASSERT_SERIALIZED(ifp->if_serializer);
3257
3258         if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
3259                 mii = device_get_softc(sc->bge_miibus);
3260
3261         callout_stop(&sc->bge_stat_timer);
3262
3263         /*
3264          * Disable all of the receiver blocks
3265          */
3266         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3267         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3268         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3269         if (!BGE_IS_5705_PLUS(sc))
3270                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3271         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3272         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3273         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3274
3275         /*
3276          * Disable all of the transmit blocks
3277          */
3278         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3279         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3280         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3281         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3282         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3283         if (!BGE_IS_5705_PLUS(sc))
3284                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3285         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3286
3287         /*
3288          * Shut down all of the memory managers and related
3289          * state machines.
3290          */
3291         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3292         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3293         if (!BGE_IS_5705_PLUS(sc))
3294                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3295         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3296         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3297         if (!BGE_IS_5705_PLUS(sc)) {
3298                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3299                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3300         }
3301
3302         /* Disable host interrupts. */
3303         bge_disable_intr(sc);
3304
3305         /*
3306          * Tell firmware we're shutting down.
3307          */
3308         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3309
3310         /* Free the RX lists. */
3311         bge_free_rx_ring_std(sc);
3312
3313         /* Free jumbo RX list. */
3314         if (BGE_IS_JUMBO_CAPABLE(sc))
3315                 bge_free_rx_ring_jumbo(sc);
3316
3317         /* Free TX buffers. */
3318         bge_free_tx_ring(sc);
3319
3320         /*
3321          * Isolate/power down the PHY, but leave the media selection
3322          * unchanged so that things will be put back to normal when
3323          * we bring the interface back up.
3324          *
3325          * 'mii' may be NULL in the following cases:
3326          * - The device uses TBI.
3327          * - bge_stop() is called by bge_detach().
3328          */
3329         if (mii != NULL) {
3330                 itmp = ifp->if_flags;
3331                 ifp->if_flags |= IFF_UP;
3332                 ifm = mii->mii_media.ifm_cur;
3333                 mtmp = ifm->ifm_media;
3334                 ifm->ifm_media = IFM_ETHER|IFM_NONE;
3335                 mii_mediachg(mii);
3336                 ifm->ifm_media = mtmp;
3337                 ifp->if_flags = itmp;
3338         }
3339
3340         sc->bge_link = 0;
3341         sc->bge_coal_chg = 0;
3342
3343         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3344
3345         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3346         ifp->if_timer = 0;
3347 }
3348
3349 /*
3350  * Stop all chip I/O so that the kernel's probe routines don't
3351  * get confused by errant DMAs when rebooting.
3352  */
3353 static void
3354 bge_shutdown(device_t dev)
3355 {
3356         struct bge_softc *sc = device_get_softc(dev);
3357         struct ifnet *ifp = &sc->arpcom.ac_if;
3358
3359         lwkt_serialize_enter(ifp->if_serializer);
3360         bge_stop(sc);
3361         bge_reset(sc);
3362         lwkt_serialize_exit(ifp->if_serializer);
3363 }
3364
3365 static int
3366 bge_suspend(device_t dev)
3367 {
3368         struct bge_softc *sc = device_get_softc(dev);
3369         struct ifnet *ifp = &sc->arpcom.ac_if;
3370
3371         lwkt_serialize_enter(ifp->if_serializer);
3372         bge_stop(sc);
3373         lwkt_serialize_exit(ifp->if_serializer);
3374
3375         return 0;
3376 }
3377
3378 static int
3379 bge_resume(device_t dev)
3380 {
3381         struct bge_softc *sc = device_get_softc(dev);
3382         struct ifnet *ifp = &sc->arpcom.ac_if;
3383
3384         lwkt_serialize_enter(ifp->if_serializer);
3385
3386         if (ifp->if_flags & IFF_UP) {
3387                 bge_init(sc);
3388
3389                 if (!ifq_is_empty(&ifp->if_snd))
3390                         if_devstart(ifp);
3391         }
3392
3393         lwkt_serialize_exit(ifp->if_serializer);
3394
3395         return 0;
3396 }
3397
3398 static void
3399 bge_setpromisc(struct bge_softc *sc)
3400 {
3401         struct ifnet *ifp = &sc->arpcom.ac_if;
3402
3403         if (ifp->if_flags & IFF_PROMISC)
3404                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3405         else
3406                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3407 }
3408
3409 static void
3410 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3411 {
3412         struct bge_dmamap_arg *ctx = arg;
3413
3414         if (error)
3415                 return;
3416
3417         KASSERT(nsegs == 1 && ctx->bge_maxsegs == 1,
3418                 ("only one segment is allowed\n"));
3419
3420         ctx->bge_segs[0] = *segs;
3421 }
3422
3423 static void
3424 bge_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nsegs,
3425                  bus_size_t mapsz __unused, int error)
3426 {
3427         struct bge_dmamap_arg *ctx = arg;
3428         int i;
3429
3430         if (error)
3431                 return;
3432
3433         if (nsegs > ctx->bge_maxsegs) {
3434                 ctx->bge_maxsegs = 0;
3435                 return;
3436         }
3437
3438         ctx->bge_maxsegs = nsegs;
3439         for (i = 0; i < nsegs; ++i)
3440                 ctx->bge_segs[i] = segs[i];
3441 }
3442
3443 static void
3444 bge_dma_free(struct bge_softc *sc)
3445 {
3446         int i;
3447
3448         /* Destroy RX/TX mbuf DMA stuffs. */
3449         if (sc->bge_cdata.bge_mtag != NULL) {
3450                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3451                         if (sc->bge_cdata.bge_rx_std_dmamap[i]) {
3452                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3453                                     sc->bge_cdata.bge_rx_std_dmamap[i]);
3454                         }
3455                 }
3456
3457                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3458                         if (sc->bge_cdata.bge_tx_dmamap[i]) {
3459                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3460                                     sc->bge_cdata.bge_tx_dmamap[i]);
3461                         }
3462                 }
3463                 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3464         }
3465
3466         /* Destroy standard RX ring */
3467         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3468                            sc->bge_cdata.bge_rx_std_ring_map,
3469                            sc->bge_ldata.bge_rx_std_ring);
3470
3471         if (BGE_IS_JUMBO_CAPABLE(sc))
3472                 bge_free_jumbo_mem(sc);
3473
3474         /* Destroy RX return ring */
3475         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3476                            sc->bge_cdata.bge_rx_return_ring_map,
3477                            sc->bge_ldata.bge_rx_return_ring);
3478
3479         /* Destroy TX ring */
3480         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3481                            sc->bge_cdata.bge_tx_ring_map,
3482                            sc->bge_ldata.bge_tx_ring);
3483
3484         /* Destroy status block */
3485         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3486                            sc->bge_cdata.bge_status_map,
3487                            sc->bge_ldata.bge_status_block);
3488
3489         /* Destroy statistics block */
3490         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3491                            sc->bge_cdata.bge_stats_map,
3492                            sc->bge_ldata.bge_stats);
3493
3494         /* Destroy the parent tag */
3495         if (sc->bge_cdata.bge_parent_tag != NULL)
3496                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3497 }
3498
3499 static int
3500 bge_dma_alloc(struct bge_softc *sc)
3501 {
3502         struct ifnet *ifp = &sc->arpcom.ac_if;
3503         int nseg, i, error;
3504
3505         /*
3506          * Allocate the parent bus DMA tag appropriate for PCI.
3507          */
3508         error = bus_dma_tag_create(NULL, 1, 0,
3509                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3510                                    NULL, NULL,
3511                                    MAXBSIZE, BGE_NSEG_NEW,
3512                                    BUS_SPACE_MAXSIZE_32BIT,
3513                                    0, &sc->bge_cdata.bge_parent_tag);
3514         if (error) {
3515                 if_printf(ifp, "could not allocate parent dma tag\n");
3516                 return error;
3517         }
3518
3519         /*
3520          * Create DMA tag for mbufs.
3521          */
3522         nseg = BGE_NSEG_NEW;
3523         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3524                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3525                                    NULL, NULL,
3526                                    MCLBYTES * nseg, nseg, MCLBYTES,
3527                                    BUS_DMA_ALLOCNOW, &sc->bge_cdata.bge_mtag);
3528         if (error) {
3529                 if_printf(ifp, "could not allocate mbuf dma tag\n");
3530                 return error;
3531         }
3532
3533         /*
3534          * Create DMA maps for TX/RX mbufs.
3535          */
3536         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3537                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3538                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
3539                 if (error) {
3540                         int j;
3541
3542                         for (j = 0; j < i; ++j) {
3543                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3544                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3545                         }
3546                         bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3547                         sc->bge_cdata.bge_mtag = NULL;
3548
3549                         if_printf(ifp, "could not create DMA map for RX\n");
3550                         return error;
3551                 }
3552         }
3553
3554         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3555                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3556                                           &sc->bge_cdata.bge_tx_dmamap[i]);
3557                 if (error) {
3558                         int j;
3559
3560                         for (j = 0; j < BGE_STD_RX_RING_CNT; ++j) {
3561                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3562                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3563                         }
3564                         for (j = 0; j < i; ++j) {
3565                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3566                                         sc->bge_cdata.bge_tx_dmamap[j]);
3567                         }
3568                         bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3569                         sc->bge_cdata.bge_mtag = NULL;
3570
3571                         if_printf(ifp, "could not create DMA map for TX\n");
3572                         return error;
3573                 }
3574         }
3575
3576         /*
3577          * Create DMA stuffs for standard RX ring.
3578          */
3579         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3580                                     &sc->bge_cdata.bge_rx_std_ring_tag,
3581                                     &sc->bge_cdata.bge_rx_std_ring_map,
3582                                     (void **)&sc->bge_ldata.bge_rx_std_ring,
3583                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
3584         if (error) {
3585                 if_printf(ifp, "could not create std RX ring\n");
3586                 return error;
3587         }
3588
3589         /*
3590          * Create jumbo buffer pool.
3591          */
3592         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3593                 error = bge_alloc_jumbo_mem(sc);
3594                 if (error) {
3595                         if_printf(ifp, "could not create jumbo buffer pool\n");
3596                         return error;
3597                 }
3598         }
3599
3600         /*
3601          * Create DMA stuffs for RX return ring.
3602          */
3603         error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3604                                     &sc->bge_cdata.bge_rx_return_ring_tag,
3605                                     &sc->bge_cdata.bge_rx_return_ring_map,
3606                                     (void **)&sc->bge_ldata.bge_rx_return_ring,
3607                                     &sc->bge_ldata.bge_rx_return_ring_paddr);
3608         if (error) {
3609                 if_printf(ifp, "could not create RX ret ring\n");
3610                 return error;
3611         }
3612
3613         /*
3614          * Create DMA stuffs for TX ring.
3615          */
3616         error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3617                                     &sc->bge_cdata.bge_tx_ring_tag,
3618                                     &sc->bge_cdata.bge_tx_ring_map,
3619                                     (void **)&sc->bge_ldata.bge_tx_ring,
3620                                     &sc->bge_ldata.bge_tx_ring_paddr);
3621         if (error) {
3622                 if_printf(ifp, "could not create TX ring\n");
3623                 return error;
3624         }
3625
3626         /*
3627          * Create DMA stuffs for status block.
3628          */
3629         error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3630                                     &sc->bge_cdata.bge_status_tag,
3631                                     &sc->bge_cdata.bge_status_map,
3632                                     (void **)&sc->bge_ldata.bge_status_block,
3633                                     &sc->bge_ldata.bge_status_block_paddr);
3634         if (error) {
3635                 if_printf(ifp, "could not create status block\n");
3636                 return error;
3637         }
3638
3639         /*
3640          * Create DMA stuffs for statistics block.
3641          */
3642         error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3643                                     &sc->bge_cdata.bge_stats_tag,
3644                                     &sc->bge_cdata.bge_stats_map,
3645                                     (void **)&sc->bge_ldata.bge_stats,
3646                                     &sc->bge_ldata.bge_stats_paddr);
3647         if (error) {
3648                 if_printf(ifp, "could not create stats block\n");
3649                 return error;
3650         }
3651         return 0;
3652 }
3653
3654 static int
3655 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3656                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3657 {
3658         struct ifnet *ifp = &sc->arpcom.ac_if;
3659         struct bge_dmamap_arg ctx;
3660         bus_dma_segment_t seg;
3661         int error;
3662
3663         /*
3664          * Create DMA tag
3665          */
3666         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3667                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3668                                    NULL, NULL, size, 1, size, 0, tag);
3669         if (error) {
3670                 if_printf(ifp, "could not allocate dma tag\n");
3671                 return error;
3672         }
3673
3674         /*
3675          * Allocate DMA'able memory
3676          */
3677         error = bus_dmamem_alloc(*tag, addr, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3678                                  map);
3679         if (error) {
3680                 if_printf(ifp, "could not allocate dma memory\n");
3681                 bus_dma_tag_destroy(*tag);
3682                 *tag = NULL;
3683                 return error;
3684         }
3685
3686         /*
3687          * Load the DMA'able memory
3688          */
3689         ctx.bge_maxsegs = 1;
3690         ctx.bge_segs = &seg;
3691         error = bus_dmamap_load(*tag, *map, *addr, size, bge_dma_map_addr, &ctx,
3692                                 BUS_DMA_WAITOK);
3693         if (error) {
3694                 if_printf(ifp, "could not load dma memory\n");
3695                 bus_dmamem_free(*tag, *addr, *map);
3696                 bus_dma_tag_destroy(*tag);
3697                 *tag = NULL;
3698                 return error;
3699         }
3700         *paddr = ctx.bge_segs[0].ds_addr;
3701
3702         return 0;
3703 }
3704
3705 static void
3706 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3707 {
3708         if (tag != NULL) {
3709                 bus_dmamap_unload(tag, map);
3710                 bus_dmamem_free(tag, addr, map);
3711                 bus_dma_tag_destroy(tag);
3712         }
3713 }
3714
3715 /*
3716  * Grrr. The link status word in the status block does
3717  * not work correctly on the BCM5700 rev AX and BX chips,
3718  * according to all available information. Hence, we have
3719  * to enable MII interrupts in order to properly obtain
3720  * async link changes. Unfortunately, this also means that
3721  * we have to read the MAC status register to detect link
3722  * changes, thereby adding an additional register access to
3723  * the interrupt handler.
3724  *
3725  * XXX: perhaps link state detection procedure used for
3726  * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3727  */
3728 static void
3729 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3730 {
3731         struct ifnet *ifp = &sc->arpcom.ac_if;
3732         struct mii_data *mii = device_get_softc(sc->bge_miibus);
3733
3734         mii_pollstat(mii);
3735
3736         if (!sc->bge_link &&
3737             (mii->mii_media_status & IFM_ACTIVE) &&
3738             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3739                 sc->bge_link++;
3740                 if (bootverbose)
3741                         if_printf(ifp, "link UP\n");
3742         } else if (sc->bge_link &&
3743             (!(mii->mii_media_status & IFM_ACTIVE) ||
3744             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3745                 sc->bge_link = 0;
3746                 if (bootverbose)
3747                         if_printf(ifp, "link DOWN\n");
3748         }
3749
3750         /* Clear the interrupt. */
3751         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
3752         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
3753         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
3754 }
3755
3756 static void
3757 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
3758 {
3759         struct ifnet *ifp = &sc->arpcom.ac_if;
3760
3761 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3762
3763         /*
3764          * Sometimes PCS encoding errors are detected in
3765          * TBI mode (on fiber NICs), and for some reason
3766          * the chip will signal them as link changes.
3767          * If we get a link change event, but the 'PCS
3768          * encoding error' bit in the MAC status register
3769          * is set, don't bother doing a link check.
3770          * This avoids spurious "gigabit link up" messages
3771          * that sometimes appear on fiber NICs during
3772          * periods of heavy traffic.
3773          */
3774         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3775                 if (!sc->bge_link) {
3776                         sc->bge_link++;
3777                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3778                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3779                                     BGE_MACMODE_TBI_SEND_CFGS);
3780                         }
3781                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3782
3783                         if (bootverbose)
3784                                 if_printf(ifp, "link UP\n");
3785
3786                         ifp->if_link_state = LINK_STATE_UP;
3787                         if_link_state_change(ifp);
3788                 }
3789         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3790                 if (sc->bge_link) {
3791                         sc->bge_link = 0;
3792
3793                         if (bootverbose)
3794                                 if_printf(ifp, "link DOWN\n");
3795
3796                         ifp->if_link_state = LINK_STATE_DOWN;
3797                         if_link_state_change(ifp);
3798                 }
3799         }
3800
3801 #undef PCS_ENCODE_ERR
3802
3803         /* Clear the attention. */
3804         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3805             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3806             BGE_MACSTAT_LINK_CHANGED);
3807 }
3808
3809 static void
3810 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
3811 {
3812         /*
3813          * Check that the AUTOPOLL bit is set before
3814          * processing the event as a real link change.
3815          * Turning AUTOPOLL on and off in the MII read/write
3816          * functions will often trigger a link status
3817          * interrupt for no reason.
3818          */
3819         if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
3820                 struct ifnet *ifp = &sc->arpcom.ac_if;
3821                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3822
3823                 mii_pollstat(mii);
3824
3825                 if (!sc->bge_link &&
3826                     (mii->mii_media_status & IFM_ACTIVE) &&
3827                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3828                         sc->bge_link++;
3829                         if (bootverbose)
3830                                 if_printf(ifp, "link UP\n");
3831                 } else if (sc->bge_link &&
3832                     (!(mii->mii_media_status & IFM_ACTIVE) ||
3833                     IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3834                         sc->bge_link = 0;
3835                         if (bootverbose)
3836                                 if_printf(ifp, "link DOWN\n");
3837                 }
3838         }
3839
3840         /* Clear the attention. */
3841         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3842             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3843             BGE_MACSTAT_LINK_CHANGED);
3844 }
3845
3846 static int
3847 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3848 {
3849         struct bge_softc *sc = arg1;
3850
3851         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3852                                    &sc->bge_rx_coal_ticks,
3853                                    BGE_RX_COAL_TICKS_CHG);
3854 }
3855
3856 static int
3857 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3858 {
3859         struct bge_softc *sc = arg1;
3860
3861         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3862                                    &sc->bge_tx_coal_ticks,
3863                                    BGE_TX_COAL_TICKS_CHG);
3864 }
3865
3866 static int
3867 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3868 {
3869         struct bge_softc *sc = arg1;
3870
3871         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3872                                    &sc->bge_rx_max_coal_bds,
3873                                    BGE_RX_MAX_COAL_BDS_CHG);
3874 }
3875
3876 static int
3877 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3878 {
3879         struct bge_softc *sc = arg1;
3880
3881         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3882                                    &sc->bge_tx_max_coal_bds,
3883                                    BGE_TX_MAX_COAL_BDS_CHG);
3884 }
3885
3886 static int
3887 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3888                     uint32_t coal_chg_mask)
3889 {
3890         struct bge_softc *sc = arg1;
3891         struct ifnet *ifp = &sc->arpcom.ac_if;
3892         int error = 0, v;
3893
3894         lwkt_serialize_enter(ifp->if_serializer);
3895
3896         v = *coal;
3897         error = sysctl_handle_int(oidp, &v, 0, req);
3898         if (!error && req->newptr != NULL) {
3899                 if (v < 0) {
3900                         error = EINVAL;
3901                 } else {
3902                         *coal = v;
3903                         sc->bge_coal_chg |= coal_chg_mask;
3904                 }
3905         }
3906
3907         lwkt_serialize_exit(ifp->if_serializer);
3908         return error;
3909 }
3910
3911 static void
3912 bge_coal_change(struct bge_softc *sc)
3913 {
3914         struct ifnet *ifp = &sc->arpcom.ac_if;
3915         uint32_t val;
3916
3917         ASSERT_SERIALIZED(ifp->if_serializer);
3918
3919         if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
3920                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3921                             sc->bge_rx_coal_ticks);
3922                 DELAY(10);
3923                 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3924
3925                 if (bootverbose) {
3926                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3927                                   sc->bge_rx_coal_ticks);
3928                 }
3929         }
3930
3931         if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
3932                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3933                             sc->bge_tx_coal_ticks);
3934                 DELAY(10);
3935                 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3936
3937                 if (bootverbose) {
3938                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3939                                   sc->bge_tx_coal_ticks);
3940                 }
3941         }
3942
3943         if (sc->bge_coal_chg & BGE_RX_MAX_COAL_BDS_CHG) {
3944                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3945                             sc->bge_rx_max_coal_bds);
3946                 DELAY(10);
3947                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3948
3949                 if (bootverbose) {
3950                         if_printf(ifp, "rx_max_coal_bds -> %u\n",
3951                                   sc->bge_rx_max_coal_bds);
3952                 }
3953         }
3954
3955         if (sc->bge_coal_chg & BGE_TX_MAX_COAL_BDS_CHG) {
3956                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3957                             sc->bge_tx_max_coal_bds);
3958                 DELAY(10);
3959                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3960
3961                 if (bootverbose) {
3962                         if_printf(ifp, "tx_max_coal_bds -> %u\n",
3963                                   sc->bge_tx_max_coal_bds);
3964                 }
3965         }
3966
3967         sc->bge_coal_chg = 0;
3968 }
3969
3970 static void
3971 bge_enable_intr(struct bge_softc *sc)
3972 {
3973         struct ifnet *ifp = &sc->arpcom.ac_if;
3974
3975         lwkt_serialize_handler_enable(ifp->if_serializer);
3976
3977         /*
3978          * Enable interrupt.
3979          */
3980         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3981
3982         /*
3983          * Unmask the interrupt when we stop polling.
3984          */
3985         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3986
3987         /*
3988          * Trigger another interrupt, since above writing
3989          * to interrupt mailbox0 may acknowledge pending
3990          * interrupt.
3991          */
3992         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3993 }
3994
3995 static void
3996 bge_disable_intr(struct bge_softc *sc)
3997 {
3998         struct ifnet *ifp = &sc->arpcom.ac_if;
3999
4000         /*
4001          * Mask the interrupt when we start polling.
4002          */
4003         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4004
4005         /*
4006          * Acknowledge possible asserted interrupt.
4007          */
4008         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4009
4010         lwkt_serialize_handler_disable(ifp->if_serializer);
4011 }
4012
4013 static int
4014 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
4015 {
4016         uint32_t mac_addr;
4017         int ret = 1;
4018
4019         mac_addr = bge_readmem_ind(sc, 0x0c14);
4020         if ((mac_addr >> 16) == 0x484b) {
4021                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4022                 ether_addr[1] = (uint8_t)mac_addr;
4023                 mac_addr = bge_readmem_ind(sc, 0x0c18);
4024                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4025                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4026                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4027                 ether_addr[5] = (uint8_t)mac_addr;
4028                 ret = 0;
4029         }
4030         return ret;
4031 }
4032
4033 static int
4034 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
4035 {
4036         int mac_offset = BGE_EE_MAC_OFFSET;
4037
4038         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4039                 mac_offset = BGE_EE_MAC_OFFSET_5906;
4040
4041         return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4042 }
4043
4044 static int
4045 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
4046 {
4047         if (sc->bge_flags & BGE_FLAG_NO_EEPROM)
4048                 return 1;
4049
4050         return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4051                                ETHER_ADDR_LEN);
4052 }
4053
4054 static int
4055 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
4056 {
4057         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
4058                 /* NOTE: Order is critical */
4059                 bge_get_eaddr_mem,
4060                 bge_get_eaddr_nvram,
4061                 bge_get_eaddr_eeprom,
4062                 NULL
4063         };
4064         const bge_eaddr_fcn_t *func;
4065
4066         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
4067                 if ((*func)(sc, eaddr) == 0)
4068                         break;
4069         }
4070         return (*func == NULL ? ENXIO : 0);
4071 }