3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.60 2008/10/03 14:14:10 sephe Exp $
40 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
51 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
64 * o TCP/IP checksum offload for both RX and TX
66 * o High and normal priority transmit DMA rings
68 * o VLAN tag insertion and extraction
70 * o TCP large send (segmentation offload)
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
85 * o GMII and TBI ports/registers for interfacing with copper
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
91 * o Slight differences in register layout from the 8139C+
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7440, so the max MTU possible with this
111 * driver is 7422 bytes.
116 #include "opt_polling.h"
118 #include <sys/param.h>
120 #include <sys/endian.h>
121 #include <sys/kernel.h>
122 #include <sys/in_cksum.h>
123 #include <sys/interrupt.h>
124 #include <sys/malloc.h>
125 #include <sys/mbuf.h>
126 #include <sys/rman.h>
127 #include <sys/serialize.h>
128 #include <sys/socket.h>
129 #include <sys/sockio.h>
130 #include <sys/sysctl.h>
133 #include <net/ethernet.h>
135 #include <net/ifq_var.h>
136 #include <net/if_arp.h>
137 #include <net/if_dl.h>
138 #include <net/if_media.h>
139 #include <net/if_types.h>
140 #include <net/vlan/if_vlan_var.h>
141 #include <net/vlan/if_vlan_ether.h>
143 #include <netinet/ip.h>
145 #include <dev/netif/mii_layer/mii.h>
146 #include <dev/netif/mii_layer/miivar.h>
148 #include <bus/pci/pcidevs.h>
149 #include <bus/pci/pcireg.h>
150 #include <bus/pci/pcivar.h>
152 /* "device miibus" required. See GENERIC if you get errors here. */
153 #include "miibus_if.h"
155 #include <dev/netif/re/if_rereg.h>
156 #include <dev/netif/re/if_revar.h>
158 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
160 #define RE_DISABLE_HWCSUM
164 * Various supported device vendors/types and their names.
166 static const struct re_type re_devs[] = {
167 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, RE_HWREV_8169S,
168 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
169 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, RE_HWREV_8139CPLUS,
170 "RealTek 8139C+ 10/100BaseTX" },
171 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, RE_HWREV_8101E,
172 "RealTek 8101E PCIe 10/100baseTX" },
173 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, RE_HWREV_8102EL,
174 "RealTek 8102EL PCIe 10/100baseTX" },
175 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN1,
176 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
177 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN2,
178 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
179 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN3,
180 "RealTek 8168B/8111B PCIe Gigabit Ethernet" },
181 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168C,
182 "RealTek 8168C/8111C PCIe Gigabit Ethernet" },
183 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169,
184 "RealTek 8169 Gigabit Ethernet" },
185 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169S,
186 "RealTek 8169S Single-chip Gigabit Ethernet" },
187 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SB,
188 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" },
189 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SC,
190 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
191 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, RE_HWREV_8169_8110SC,
192 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
193 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8110S,
194 "RealTek 8110S Single-chip Gigabit Ethernet" },
195 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, RE_HWREV_8169S,
196 "Corega CG-LAPCIGT Gigabit Ethernet" },
197 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, RE_HWREV_8169S,
198 "Linksys EG1032 Gigabit Ethernet" },
199 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, RE_HWREV_8169S,
200 "US Robotics 997902 Gigabit Ethernet" },
204 static const struct re_hwrev re_hwrevs[] = {
205 { RE_HWREV_8139CPLUS, RE_8139CPLUS, RE_F_HASMPC, 0, "C+" },
206 { RE_HWREV_8168_SPIN1, RE_8169, RE_F_PCIE, 0, "8168" },
207 { RE_HWREV_8168_SPIN2, RE_8169,
208 RE_F_PCIE | RE_F_JUMBO_SWCSUM, RE_SWCSUM_LIM_8168B, "8168" },
209 { RE_HWREV_8168_SPIN3, RE_8169, RE_F_PCIE, 0, "8168" },
210 { RE_HWREV_8168C, RE_8169, RE_F_PCIE, 0, "8168C" },
211 { RE_HWREV_8169, RE_8169,
212 RE_F_HASMPC | RE_F_JUMBO_SWCSUM, RE_SWCSUM_LIM_8169, "8169" },
213 { RE_HWREV_8169S, RE_8169, RE_F_HASMPC, 0, "8169S" },
214 { RE_HWREV_8110S, RE_8169, RE_F_HASMPC, 0, "8110S" },
215 { RE_HWREV_8169_8110SB, RE_8169, RE_F_HASMPC, 0, "8169SB" },
216 { RE_HWREV_8169_8110SC, RE_8169, 0, 0, "8169SC" },
217 { RE_HWREV_8100E, RE_8169, RE_F_HASMPC, 0, "8100E" },
218 { RE_HWREV_8101E, RE_8169, RE_F_PCIE, 0, "8101E" },
219 { RE_HWREV_8102EL, RE_8169, RE_F_PCIE, 0, "8102EL" },
223 static int re_probe(device_t);
224 static int re_attach(device_t);
225 static int re_detach(device_t);
226 static int re_suspend(device_t);
227 static int re_resume(device_t);
228 static void re_shutdown(device_t);
230 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int);
231 static void re_dma_map_desc(void *, bus_dma_segment_t *, int,
233 static int re_allocmem(device_t);
234 static void re_freemem(device_t);
235 static void re_freebufmem(struct re_softc *, int, int);
236 static int re_encap(struct re_softc *, struct mbuf **, int *);
237 static int re_newbuf(struct re_softc *, int, int);
238 static void re_setup_rxdesc(struct re_softc *, int);
239 static int re_rx_list_init(struct re_softc *);
240 static int re_tx_list_init(struct re_softc *);
241 static void re_rxeof(struct re_softc *);
242 static void re_txeof(struct re_softc *);
243 static void re_intr(void *);
244 static void re_tick(void *);
245 static void re_tick_serialized(void *);
247 static void re_start(struct ifnet *);
248 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
249 static void re_init(void *);
250 static void re_stop(struct re_softc *);
251 static void re_watchdog(struct ifnet *);
252 static int re_ifmedia_upd(struct ifnet *);
253 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
255 static void re_eeprom_putbyte(struct re_softc *, int);
256 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *);
257 static void re_read_eeprom(struct re_softc *, caddr_t, int, int);
258 static int re_gmii_readreg(device_t, int, int);
259 static int re_gmii_writereg(device_t, int, int, int);
261 static int re_miibus_readreg(device_t, int, int);
262 static int re_miibus_writereg(device_t, int, int, int);
263 static void re_miibus_statchg(device_t);
265 static void re_setmulti(struct re_softc *);
266 static void re_reset(struct re_softc *);
267 static int re_pad_frame(struct mbuf *);
270 static int re_diag(struct re_softc *);
273 #ifdef DEVICE_POLLING
274 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
277 static int re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS);
279 static device_method_t re_methods[] = {
280 /* Device interface */
281 DEVMETHOD(device_probe, re_probe),
282 DEVMETHOD(device_attach, re_attach),
283 DEVMETHOD(device_detach, re_detach),
284 DEVMETHOD(device_suspend, re_suspend),
285 DEVMETHOD(device_resume, re_resume),
286 DEVMETHOD(device_shutdown, re_shutdown),
289 DEVMETHOD(bus_print_child, bus_generic_print_child),
290 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
293 DEVMETHOD(miibus_readreg, re_miibus_readreg),
294 DEVMETHOD(miibus_writereg, re_miibus_writereg),
295 DEVMETHOD(miibus_statchg, re_miibus_statchg),
300 static driver_t re_driver = {
303 sizeof(struct re_softc)
306 static devclass_t re_devclass;
308 DECLARE_DUMMY_MODULE(if_re);
309 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0);
310 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0);
311 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
314 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
317 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
320 re_free_rxchain(struct re_softc *sc)
322 if (sc->re_head != NULL) {
323 m_freem(sc->re_head);
324 sc->re_head = sc->re_tail = NULL;
329 * Send a read command and address to the EEPROM, check for ACK.
332 re_eeprom_putbyte(struct re_softc *sc, int addr)
336 d = addr | (RE_9346_READ << sc->re_eewidth);
339 * Feed in each bit and strobe the clock.
341 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) {
343 EE_SET(RE_EE_DATAIN);
345 EE_CLR(RE_EE_DATAIN);
355 * Read a word of data stored in the EEPROM at address 'addr.'
358 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
364 * Send address of word we want to read.
366 re_eeprom_putbyte(sc, addr);
369 * Start reading bits from EEPROM.
371 for (i = 0x8000; i != 0; i >>= 1) {
374 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
384 * Read a sequence of words from the EEPROM.
387 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt)
390 uint16_t word = 0, *ptr;
392 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
395 for (i = 0; i < cnt; i++) {
396 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL);
397 re_eeprom_getword(sc, off + i, &word);
398 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL);
399 ptr = (uint16_t *)(dest + (i * 2));
403 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
407 re_gmii_readreg(device_t dev, int phy, int reg)
409 struct re_softc *sc = device_get_softc(dev);
416 /* Let the rgephy driver read the GMEDIASTAT register */
418 if (reg == RE_GMEDIASTAT)
419 return(CSR_READ_1(sc, RE_GMEDIASTAT));
421 CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
424 for (i = 0; i < RE_TIMEOUT; i++) {
425 rval = CSR_READ_4(sc, RE_PHYAR);
426 if (rval & RE_PHYAR_BUSY)
431 if (i == RE_TIMEOUT) {
432 device_printf(dev, "PHY read failed\n");
436 return(rval & RE_PHYAR_PHYDATA);
440 re_gmii_writereg(device_t dev, int phy, int reg, int data)
442 struct re_softc *sc = device_get_softc(dev);
446 CSR_WRITE_4(sc, RE_PHYAR,
447 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
450 for (i = 0; i < RE_TIMEOUT; i++) {
451 rval = CSR_READ_4(sc, RE_PHYAR);
452 if ((rval & RE_PHYAR_BUSY) == 0)
458 device_printf(dev, "PHY write failed\n");
464 re_miibus_readreg(device_t dev, int phy, int reg)
466 struct re_softc *sc = device_get_softc(dev);
468 uint16_t re8139_reg = 0;
470 if (sc->re_type == RE_8169) {
471 rval = re_gmii_readreg(dev, phy, reg);
475 /* Pretend the internal PHY is only at address 0 */
481 re8139_reg = RE_BMCR;
484 re8139_reg = RE_BMSR;
487 re8139_reg = RE_ANAR;
490 re8139_reg = RE_ANER;
493 re8139_reg = RE_LPAR;
499 * Allow the rlphy driver to read the media status
500 * register. If we have a link partner which does not
501 * support NWAY, this is the register which will tell
502 * us the results of parallel detection.
505 return(CSR_READ_1(sc, RE_MEDIASTAT));
507 device_printf(dev, "bad phy register\n");
510 rval = CSR_READ_2(sc, re8139_reg);
511 if (sc->re_type == RE_8139CPLUS && re8139_reg == RE_BMCR) {
512 /* 8139C+ has different bit layout. */
513 rval &= ~(BMCR_LOOP | BMCR_ISO);
519 re_miibus_writereg(device_t dev, int phy, int reg, int data)
521 struct re_softc *sc= device_get_softc(dev);
522 u_int16_t re8139_reg = 0;
524 if (sc->re_type == RE_8169)
525 return(re_gmii_writereg(dev, phy, reg, data));
527 /* Pretend the internal PHY is only at address 0 */
533 re8139_reg = RE_BMCR;
534 if (sc->re_type == RE_8139CPLUS) {
535 /* 8139C+ has different bit layout. */
536 data &= ~(BMCR_LOOP | BMCR_ISO);
540 re8139_reg = RE_BMSR;
543 re8139_reg = RE_ANAR;
546 re8139_reg = RE_ANER;
549 re8139_reg = RE_LPAR;
555 device_printf(dev, "bad phy register\n");
558 CSR_WRITE_2(sc, re8139_reg, data);
563 re_miibus_statchg(device_t dev)
568 * Program the 64-bit multicast hash filter.
571 re_setmulti(struct re_softc *sc)
573 struct ifnet *ifp = &sc->arpcom.ac_if;
575 uint32_t hashes[2] = { 0, 0 };
576 struct ifmultiaddr *ifma;
580 rxfilt = CSR_READ_4(sc, RE_RXCFG);
582 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
583 rxfilt |= RE_RXCFG_RX_MULTI;
584 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
585 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
586 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
590 /* first, zot all the existing hash bits */
591 CSR_WRITE_4(sc, RE_MAR0, 0);
592 CSR_WRITE_4(sc, RE_MAR4, 0);
594 /* now program new ones */
595 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
596 if (ifma->ifma_addr->sa_family != AF_LINK)
598 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
599 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
601 hashes[0] |= (1 << h);
603 hashes[1] |= (1 << (h - 32));
608 rxfilt |= RE_RXCFG_RX_MULTI;
610 rxfilt &= ~RE_RXCFG_RX_MULTI;
612 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
615 * For some unfathomable reason, RealTek decided to reverse
616 * the order of the multicast hash registers in the PCI Express
617 * parts. This means we have to write the hash pattern in reverse
618 * order for those devices.
620 if (sc->re_flags & RE_F_PCIE) {
621 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[0]));
622 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[1]));
624 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
625 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
630 re_reset(struct re_softc *sc)
634 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
636 for (i = 0; i < RE_TIMEOUT; i++) {
638 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
642 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
644 CSR_WRITE_1(sc, 0x82, 1);
649 * The following routine is designed to test for a defect on some
650 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
651 * lines connected to the bus, however for a 32-bit only card, they
652 * should be pulled high. The result of this defect is that the
653 * NIC will not work right if you plug it into a 64-bit slot: DMA
654 * operations will be done with 64-bit transfers, which will fail
655 * because the 64-bit data lines aren't connected.
657 * There's no way to work around this (short of talking a soldering
658 * iron to the board), however we can detect it. The method we use
659 * here is to put the NIC into digital loopback mode, set the receiver
660 * to promiscuous mode, and then try to send a frame. We then compare
661 * the frame data we sent to what was received. If the data matches,
662 * then the NIC is working correctly, otherwise we know the user has
663 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
664 * slot. In the latter case, there's no way the NIC can work correctly,
665 * so we print out a message on the console and abort the device attach.
669 re_diag(struct re_softc *sc)
671 struct ifnet *ifp = &sc->arpcom.ac_if;
673 struct ether_header *eh;
674 struct re_desc *cur_rx;
677 int total_len, i, error = 0, phyaddr;
678 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
679 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
681 /* Allocate a single mbuf */
683 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
688 * Initialize the NIC in test mode. This sets the chip up
689 * so that it can send and receive frames, but performs the
690 * following special functions:
691 * - Puts receiver in promiscuous mode
692 * - Enables digital loopback mode
693 * - Leaves interrupts turned off
696 ifp->if_flags |= IFF_PROMISC;
701 if (sc->re_type == RE_8169)
706 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET);
707 for (i = 0; i < RE_TIMEOUT; i++) {
708 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR);
709 if (!(status & BMCR_RESET))
713 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP);
714 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG);
718 /* Put some data in the mbuf */
720 eh = mtod(m0, struct ether_header *);
721 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
722 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
723 eh->ether_type = htons(ETHERTYPE_IP);
724 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
727 * Queue the packet, start transmission.
728 * Note: ifq_handoff() ultimately calls re_start() for us.
731 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
732 error = ifq_handoff(ifp, m0, NULL);
739 /* Wait for it to propagate through the chip */
742 for (i = 0; i < RE_TIMEOUT; i++) {
743 status = CSR_READ_2(sc, RE_ISR);
744 CSR_WRITE_2(sc, RE_ISR, status);
745 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
746 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
751 if (i == RE_TIMEOUT) {
752 if_printf(ifp, "diagnostic failed to receive packet "
753 "in loopback mode\n");
759 * The packet should have been dumped into the first
760 * entry in the RX DMA ring. Grab it from there.
763 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
764 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
765 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0],
766 BUS_DMASYNC_POSTWRITE);
767 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]);
769 m0 = sc->re_ldata.re_rx_mbuf[0];
770 sc->re_ldata.re_rx_mbuf[0] = NULL;
771 eh = mtod(m0, struct ether_header *);
773 cur_rx = &sc->re_ldata.re_rx_list[0];
774 total_len = RE_RXBYTES(cur_rx);
775 rxstat = le32toh(cur_rx->re_cmdstat);
777 if (total_len != ETHER_MIN_LEN) {
778 if_printf(ifp, "diagnostic failed, received short packet\n");
783 /* Test that the received packet data matches what we sent. */
785 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
786 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
787 be16toh(eh->ether_type) != ETHERTYPE_IP) {
788 if_printf(ifp, "WARNING, DMA FAILURE!\n");
789 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
790 dst, ":", src, ":", ETHERTYPE_IP);
791 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
792 eh->ether_dhost, ":", eh->ether_shost, ":",
793 ntohs(eh->ether_type));
794 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
795 "into a 64-bit PCI slot.\n");
796 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
797 "for proper operation.\n");
798 if_printf(ifp, "Read the re(4) man page for more details.\n");
803 /* Turn interface off, release resources */
807 ifp->if_flags &= ~IFF_PROMISC;
817 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
818 * IDs against our list and return a device name if we find a match.
821 re_probe(device_t dev)
823 const struct re_type *t;
827 uint16_t vendor, product;
829 vendor = pci_get_vendor(dev);
830 product = pci_get_device(dev);
833 * Only attach to rev.3 of the Linksys EG1032 adapter.
834 * Rev.2 is supported by sk(4).
836 if (vendor == PCI_VENDOR_LINKSYS &&
837 product == PCI_PRODUCT_LINKSYS_EG1032 &&
838 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3)
841 for (t = re_devs; t->re_name != NULL; t++) {
842 if (product == t->re_did && vendor == t->re_vid)
847 * Check if we found a RealTek device.
849 if (t->re_name == NULL)
853 * Temporarily map the I/O space so we can read the chip ID register.
855 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
857 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
859 if (sc->re_res == NULL) {
860 device_printf(dev, "couldn't map ports/memory\n");
865 sc->re_btag = rman_get_bustag(sc->re_res);
866 sc->re_bhandle = rman_get_bushandle(sc->re_res);
868 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
869 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
873 * and continue matching for the specific chip...
875 for (; t->re_name != NULL; t++) {
876 if (product == t->re_did && vendor == t->re_vid &&
877 t->re_basetype == hwrev) {
878 device_set_desc(dev, t->re_name);
884 kprintf("re: unknown hwrev %#x\n", hwrev);
889 re_dma_map_desc(void *xarg, bus_dma_segment_t *segs, int nsegs,
890 bus_size_t mapsize, int error)
892 struct re_dmaload_arg *arg = xarg;
898 if (nsegs > arg->re_nsegs) {
903 arg->re_nsegs = nsegs;
904 for (i = 0; i < nsegs; ++i)
905 arg->re_segs[i] = segs[i];
909 * Map a single buffer address.
913 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
920 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
922 *addr = segs->ds_addr;
926 re_allocmem(device_t dev)
928 struct re_softc *sc = device_get_softc(dev);
932 * Allocate the parent bus DMA tag appropriate for PCI.
934 error = bus_dma_tag_create(NULL, /* parent */
935 1, 0, /* alignment, boundary */
936 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
937 BUS_SPACE_MAXADDR, /* highaddr */
938 NULL, NULL, /* filter, filterarg */
939 MAXBSIZE, RE_MAXSEGS, /* maxsize, nsegments */
940 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
941 BUS_DMA_ALLOCNOW, /* flags */
944 device_printf(dev, "could not allocate parent dma tag\n");
948 /* Allocate tag for TX descriptor list. */
949 error = bus_dma_tag_create(sc->re_parent_tag,
951 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
953 RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ,
955 &sc->re_ldata.re_tx_list_tag);
957 device_printf(dev, "could not allocate TX ring dma tag\n");
961 /* Allocate DMA'able memory for the TX ring */
962 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag,
963 (void **)&sc->re_ldata.re_tx_list,
964 BUS_DMA_WAITOK | BUS_DMA_ZERO,
965 &sc->re_ldata.re_tx_list_map);
967 device_printf(dev, "could not allocate TX ring\n");
968 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
969 sc->re_ldata.re_tx_list_tag = NULL;
973 /* Load the map for the TX ring. */
974 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag,
975 sc->re_ldata.re_tx_list_map,
976 sc->re_ldata.re_tx_list, RE_TX_LIST_SZ,
977 re_dma_map_addr, &sc->re_ldata.re_tx_list_addr,
980 device_printf(dev, "could not get address of TX ring\n");
981 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
982 sc->re_ldata.re_tx_list,
983 sc->re_ldata.re_tx_list_map);
984 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
985 sc->re_ldata.re_tx_list_tag = NULL;
989 /* Allocate tag for RX descriptor list. */
990 error = bus_dma_tag_create(sc->re_parent_tag,
992 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
994 RE_RX_LIST_SZ, 1, RE_RX_LIST_SZ,
996 &sc->re_ldata.re_rx_list_tag);
998 device_printf(dev, "could not allocate RX ring dma tag\n");
1002 /* Allocate DMA'able memory for the RX ring */
1003 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag,
1004 (void **)&sc->re_ldata.re_rx_list,
1005 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1006 &sc->re_ldata.re_rx_list_map);
1008 device_printf(dev, "could not allocate RX ring\n");
1009 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1010 sc->re_ldata.re_rx_list_tag = NULL;
1014 /* Load the map for the RX ring. */
1015 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag,
1016 sc->re_ldata.re_rx_list_map,
1017 sc->re_ldata.re_rx_list, RE_RX_LIST_SZ,
1018 re_dma_map_addr, &sc->re_ldata.re_rx_list_addr,
1021 device_printf(dev, "could not get address of RX ring\n");
1022 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1023 sc->re_ldata.re_rx_list,
1024 sc->re_ldata.re_rx_list_map);
1025 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1026 sc->re_ldata.re_rx_list_tag = NULL;
1030 /* Allocate map for RX/TX mbufs. */
1031 error = bus_dma_tag_create(sc->re_parent_tag,
1033 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1035 RE_JUMBO_FRAMELEN, RE_MAXSEGS, MCLBYTES,
1037 &sc->re_ldata.re_mtag);
1039 device_printf(dev, "could not allocate buf dma tag\n");
1043 /* Create spare DMA map for RX */
1044 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
1045 &sc->re_ldata.re_rx_spare);
1047 device_printf(dev, "can't create spare DMA map for RX\n");
1048 bus_dma_tag_destroy(sc->re_ldata.re_mtag);
1049 sc->re_ldata.re_mtag = NULL;
1053 /* Create DMA maps for TX buffers */
1054 for (i = 0; i < RE_TX_DESC_CNT; i++) {
1055 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
1056 &sc->re_ldata.re_tx_dmamap[i]);
1058 device_printf(dev, "can't create DMA map for TX buf\n");
1059 re_freebufmem(sc, i, 0);
1064 /* Create DMA maps for RX buffers */
1065 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1066 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
1067 &sc->re_ldata.re_rx_dmamap[i]);
1069 device_printf(dev, "can't create DMA map for RX buf\n");
1070 re_freebufmem(sc, RE_TX_DESC_CNT, i);
1078 re_freebufmem(struct re_softc *sc, int tx_cnt, int rx_cnt)
1082 /* Destroy all the RX and TX buffer maps */
1083 if (sc->re_ldata.re_mtag) {
1084 for (i = 0; i < tx_cnt; i++) {
1085 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1086 sc->re_ldata.re_tx_dmamap[i]);
1088 for (i = 0; i < rx_cnt; i++) {
1089 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1090 sc->re_ldata.re_rx_dmamap[i]);
1092 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1093 sc->re_ldata.re_rx_spare);
1094 bus_dma_tag_destroy(sc->re_ldata.re_mtag);
1099 re_freemem(device_t dev)
1101 struct re_softc *sc = device_get_softc(dev);
1103 /* Unload and free the RX DMA ring memory and map */
1104 if (sc->re_ldata.re_rx_list_tag) {
1105 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1106 sc->re_ldata.re_rx_list_map);
1107 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1108 sc->re_ldata.re_rx_list,
1109 sc->re_ldata.re_rx_list_map);
1110 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1113 /* Unload and free the TX DMA ring memory and map */
1114 if (sc->re_ldata.re_tx_list_tag) {
1115 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1116 sc->re_ldata.re_tx_list_map);
1117 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1118 sc->re_ldata.re_tx_list,
1119 sc->re_ldata.re_tx_list_map);
1120 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1123 /* Free RX/TX buf DMA stuffs */
1124 re_freebufmem(sc, RE_TX_DESC_CNT, RE_RX_DESC_CNT);
1126 /* Unload and free the stats buffer and map */
1127 if (sc->re_ldata.re_stag) {
1128 bus_dmamap_unload(sc->re_ldata.re_stag,
1129 sc->re_ldata.re_rx_list_map);
1130 bus_dmamem_free(sc->re_ldata.re_stag,
1131 sc->re_ldata.re_stats,
1132 sc->re_ldata.re_smap);
1133 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1136 if (sc->re_parent_tag)
1137 bus_dma_tag_destroy(sc->re_parent_tag);
1141 * Attach the interface. Allocate softc structures, do ifmedia
1142 * setup and ethernet/BPF attach.
1145 re_attach(device_t dev)
1147 struct re_softc *sc = device_get_softc(dev);
1149 const struct re_hwrev *hw_rev;
1150 uint8_t eaddr[ETHER_ADDR_LEN];
1151 uint16_t as[ETHER_ADDR_LEN / 2];
1152 uint16_t re_did = 0;
1154 int error = 0, rid, i;
1156 callout_init(&sc->re_timer);
1161 RE_ENABLE_TX_MODERATION(sc);
1163 sysctl_ctx_init(&sc->re_sysctl_ctx);
1164 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx,
1165 SYSCTL_STATIC_CHILDREN(_hw),
1167 device_get_nameunit(dev),
1169 if (sc->re_sysctl_tree == NULL) {
1170 device_printf(dev, "can't add sysctl node\n");
1174 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1175 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1176 OID_AUTO, "tx_moderation",
1177 CTLTYPE_INT | CTLFLAG_RW,
1178 sc, 0, re_sysctl_tx_moderation, "I",
1179 "Enable/Disable TX moderation");
1181 #ifndef BURN_BRIDGES
1183 * Handle power management nonsense.
1186 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1187 uint32_t membase, irq;
1189 /* Save important PCI config data. */
1190 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1191 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1193 /* Reset the power state. */
1194 device_printf(dev, "chip is in D%d power mode "
1195 "-- setting to D0\n", pci_get_powerstate(dev));
1197 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1199 /* Restore PCI config data. */
1200 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1201 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1205 * Map control/status registers.
1207 pci_enable_busmaster(dev);
1210 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1213 if (sc->re_res == NULL) {
1214 device_printf(dev, "couldn't map ports\n");
1219 sc->re_btag = rman_get_bustag(sc->re_res);
1220 sc->re_bhandle = rman_get_bushandle(sc->re_res);
1222 /* Allocate interrupt */
1224 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1225 RF_SHAREABLE | RF_ACTIVE);
1227 if (sc->re_irq == NULL) {
1228 device_printf(dev, "couldn't map interrupt\n");
1233 /* Reset the adapter. */
1236 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
1237 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) {
1238 if (hw_rev->re_rev == hwrev) {
1239 sc->re_type = hw_rev->re_type;
1240 sc->re_flags = hw_rev->re_flags;
1241 sc->re_swcsum_lim = hw_rev->re_swcsum_lim;
1245 device_printf(dev, "hardware rev. 0x%08x\n", hwrev);
1248 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1249 if (re_did != 0x8129)
1253 * Get station address from the EEPROM.
1255 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3);
1256 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1257 as[i] = le16toh(as[i]);
1258 bcopy(as, eaddr, sizeof(eaddr));
1260 if (sc->re_type == RE_8169) {
1261 /* Set RX length mask */
1262 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1263 sc->re_txstart = RE_GTXSTART;
1265 /* Set RX length mask */
1266 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1267 sc->re_txstart = RE_TXSTART;
1270 /* Allocate DMA stuffs */
1271 error = re_allocmem(dev);
1276 if (mii_phy_probe(dev, &sc->re_miibus,
1277 re_ifmedia_upd, re_ifmedia_sts)) {
1278 device_printf(dev, "MII without any phy!\n");
1283 ifp = &sc->arpcom.ac_if;
1285 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1286 ifp->if_mtu = ETHERMTU;
1287 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1288 ifp->if_ioctl = re_ioctl;
1289 ifp->if_start = re_start;
1290 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1293 case RE_HWREV_8168C:
1294 case RE_HWREV_8102EL:
1296 * XXX Hardware checksum does not work yet on 8168C
1297 * and 8102EL. Disble it.
1299 ifp->if_capabilities &= ~IFCAP_HWCSUM;
1302 ifp->if_capabilities |= IFCAP_HWCSUM;
1305 #ifdef DEVICE_POLLING
1306 ifp->if_poll = re_poll;
1308 ifp->if_watchdog = re_watchdog;
1309 ifp->if_init = re_init;
1310 if (sc->re_type == RE_8169)
1311 ifp->if_baudrate = 1000000000;
1313 ifp->if_baudrate = 100000000;
1314 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN);
1315 ifq_set_ready(&ifp->if_snd);
1317 #ifdef RE_DISABLE_HWCSUM
1318 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1319 ifp->if_hwassist = 0;
1321 ifp->if_capenable = ifp->if_capabilities;
1322 if (ifp->if_capabilities & IFCAP_HWCSUM)
1323 ifp->if_hwassist = RE_CSUM_FEATURES;
1325 ifp->if_hwassist = 0;
1326 #endif /* RE_DISABLE_HWCSUM */
1329 * Call MI attach routine.
1331 ether_ifattach(ifp, eaddr, NULL);
1335 * Perform hardware diagnostic on the original RTL8169.
1336 * Some 32-bit cards were incorrectly wired and would
1337 * malfunction if plugged into a 64-bit slot.
1339 if (hwrev == RE_HWREV_8169) {
1340 lwkt_serialize_enter(ifp->if_serializer);
1341 error = re_diag(sc);
1342 lwkt_serialize_exit(ifp->if_serializer);
1345 device_printf(dev, "hardware diagnostic failure\n");
1346 ether_ifdetach(ifp);
1350 #endif /* RE_DIAG */
1352 /* Hook interrupt last to avoid having to lock softc */
1353 error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc,
1354 &sc->re_intrhand, ifp->if_serializer);
1357 device_printf(dev, "couldn't set up irq\n");
1358 ether_ifdetach(ifp);
1362 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->re_irq));
1363 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1373 * Shutdown hardware and free up resources. This can be called any
1374 * time after the mutex has been initialized. It is called in both
1375 * the error case in attach and the normal detach case so it needs
1376 * to be careful about only freeing resources that have actually been
1380 re_detach(device_t dev)
1382 struct re_softc *sc = device_get_softc(dev);
1383 struct ifnet *ifp = &sc->arpcom.ac_if;
1385 /* These should only be active if attach succeeded */
1386 if (device_is_attached(dev)) {
1387 lwkt_serialize_enter(ifp->if_serializer);
1389 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1390 lwkt_serialize_exit(ifp->if_serializer);
1392 ether_ifdetach(ifp);
1395 device_delete_child(dev, sc->re_miibus);
1396 bus_generic_detach(dev);
1398 if (sc->re_sysctl_tree != NULL)
1399 sysctl_ctx_free(&sc->re_sysctl_ctx);
1402 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1404 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1408 /* Free DMA stuffs */
1415 re_setup_rxdesc(struct re_softc *sc, int idx)
1421 paddr = sc->re_ldata.re_rx_paddr[idx];
1422 d = &sc->re_ldata.re_rx_list[idx];
1424 d->re_bufaddr_lo = htole32(RE_ADDR_LO(paddr));
1425 d->re_bufaddr_hi = htole32(RE_ADDR_HI(paddr));
1427 cmdstat = MCLBYTES | RE_RDESC_CMD_OWN;
1428 if (idx == (RE_RX_DESC_CNT - 1))
1429 cmdstat |= RE_TDESC_CMD_EOR;
1430 d->re_cmdstat = htole32(cmdstat);
1434 re_newbuf(struct re_softc *sc, int idx, int init)
1436 struct re_dmaload_arg arg;
1437 bus_dma_segment_t seg;
1442 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1447 if_printf(&sc->arpcom.ac_if, "m_getcl failed\n");
1453 m->m_len = m->m_pkthdr.len = MCLBYTES;
1457 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer
1458 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1463 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag,
1464 sc->re_ldata.re_rx_spare, m,
1465 re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1466 if (error || arg.re_nsegs == 0) {
1468 if_printf(&sc->arpcom.ac_if, "too many segments?!\n");
1469 bus_dmamap_unload(sc->re_ldata.re_mtag,
1470 sc->re_ldata.re_rx_spare);
1476 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
1484 bus_dmamap_sync(sc->re_ldata.re_mtag,
1485 sc->re_ldata.re_rx_dmamap[idx],
1486 BUS_DMASYNC_POSTREAD);
1487 bus_dmamap_unload(sc->re_ldata.re_mtag,
1488 sc->re_ldata.re_rx_dmamap[idx]);
1490 sc->re_ldata.re_rx_mbuf[idx] = m;
1491 sc->re_ldata.re_rx_paddr[idx] = seg.ds_addr;
1493 map = sc->re_ldata.re_rx_dmamap[idx];
1494 sc->re_ldata.re_rx_dmamap[idx] = sc->re_ldata.re_rx_spare;
1495 sc->re_ldata.re_rx_spare = map;
1497 re_setup_rxdesc(sc, idx);
1502 re_tx_list_init(struct re_softc *sc)
1504 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ);
1505 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *));
1507 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1508 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
1509 sc->re_ldata.re_tx_prodidx = 0;
1510 sc->re_ldata.re_tx_considx = 0;
1511 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT;
1517 re_rx_list_init(struct re_softc *sc)
1521 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ);
1522 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *));
1524 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1525 error = re_newbuf(sc, i, 1);
1530 /* Flush the RX descriptors */
1532 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1533 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
1535 sc->re_ldata.re_rx_prodidx = 0;
1536 sc->re_head = sc->re_tail = NULL;
1542 * RX handler for C+ and 8169. For the gigE chips, we support
1543 * the reception of jumbo frames that have been fragmented
1544 * across multiple 2K mbuf cluster buffers.
1547 re_rxeof(struct re_softc *sc)
1549 struct ifnet *ifp = &sc->arpcom.ac_if;
1551 struct re_desc *cur_rx;
1552 uint32_t rxstat, rxvlan;
1554 struct mbuf_chain chain[MAXCPU];
1556 /* Invalidate the descriptor memory */
1558 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1559 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
1561 ether_input_chain_init(chain);
1563 for (i = sc->re_ldata.re_rx_prodidx;
1564 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0; RE_DESC_INC(i)) {
1565 cur_rx = &sc->re_ldata.re_rx_list[i];
1566 m = sc->re_ldata.re_rx_mbuf[i];
1567 total_len = RE_RXBYTES(cur_rx);
1568 rxstat = le32toh(cur_rx->re_cmdstat);
1569 rxvlan = le32toh(cur_rx->re_vlanctl);
1571 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1572 if (sc->re_drop_rxfrag) {
1573 re_setup_rxdesc(sc, i);
1577 if (re_newbuf(sc, i, 0)) {
1578 /* Drop upcoming fragments */
1579 sc->re_drop_rxfrag = 1;
1583 m->m_len = MCLBYTES;
1584 if (sc->re_head == NULL) {
1585 sc->re_head = sc->re_tail = m;
1587 sc->re_tail->m_next = m;
1591 } else if (sc->re_drop_rxfrag) {
1593 * Last fragment of a multi-fragment packet.
1595 * Since error already happened, this fragment
1596 * must be dropped as well as the fragment chain.
1598 re_setup_rxdesc(sc, i);
1599 re_free_rxchain(sc);
1600 sc->re_drop_rxfrag = 0;
1605 * NOTE: for the 8139C+, the frame length field
1606 * is always 12 bits in size, but for the gigE chips,
1607 * it is 13 bits (since the max RX frame length is 16K).
1608 * Unfortunately, all 32 bits in the status word
1609 * were already used, so to make room for the extra
1610 * length bit, RealTek took out the 'frame alignment
1611 * error' bit and shifted the other status bits
1612 * over one slot. The OWN, EOR, FS and LS bits are
1613 * still in the same places. We have already extracted
1614 * the frame length and checked the OWN bit, so rather
1615 * than using an alternate bit mapping, we shift the
1616 * status bits one space to the right so we can evaluate
1617 * them using the 8169 status as though it was in the
1618 * same format as that of the 8139C+.
1620 if (sc->re_type == RE_8169)
1623 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1626 * If this is part of a multi-fragment packet,
1627 * discard all the pieces.
1629 re_free_rxchain(sc);
1630 re_setup_rxdesc(sc, i);
1635 * If allocating a replacement mbuf fails,
1636 * reload the current one.
1639 if (re_newbuf(sc, i, 0)) {
1641 re_free_rxchain(sc);
1645 if (sc->re_head != NULL) {
1646 m->m_len = total_len % MCLBYTES;
1648 * Special case: if there's 4 bytes or less
1649 * in this buffer, the mbuf can be discarded:
1650 * the last 4 bytes is the CRC, which we don't
1651 * care about anyway.
1653 if (m->m_len <= ETHER_CRC_LEN) {
1654 sc->re_tail->m_len -=
1655 (ETHER_CRC_LEN - m->m_len);
1658 m->m_len -= ETHER_CRC_LEN;
1659 sc->re_tail->m_next = m;
1662 sc->re_head = sc->re_tail = NULL;
1663 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1665 m->m_pkthdr.len = m->m_len =
1666 (total_len - ETHER_CRC_LEN);
1670 m->m_pkthdr.rcvif = ifp;
1672 /* Do RX checksumming if enabled */
1674 if (ifp->if_capenable & IFCAP_RXCSUM) {
1675 /* Check IP header checksum */
1676 if (rxstat & RE_RDESC_STAT_PROTOID)
1677 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1678 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
1679 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1681 /* Check TCP/UDP checksum */
1682 if ((RE_TCPPKT(rxstat) &&
1683 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
1684 (RE_UDPPKT(rxstat) &&
1685 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) {
1686 m->m_pkthdr.csum_flags |=
1687 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
1688 CSUM_FRAG_NOT_CHECKED;
1689 m->m_pkthdr.csum_data = 0xffff;
1693 if (rxvlan & RE_RDESC_VLANCTL_TAG) {
1694 m->m_flags |= M_VLANTAG;
1695 m->m_pkthdr.ether_vlantag =
1696 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA));
1698 ether_input_chain(ifp, m, chain);
1701 ether_input_dispatch(chain);
1703 /* Flush the RX DMA ring */
1705 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1706 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
1708 sc->re_ldata.re_rx_prodidx = i;
1712 re_txeof(struct re_softc *sc)
1714 struct ifnet *ifp = &sc->arpcom.ac_if;
1718 /* Invalidate the TX descriptor list */
1720 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1721 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_POSTREAD);
1723 for (idx = sc->re_ldata.re_tx_considx;
1724 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT; RE_DESC_INC(idx)) {
1725 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
1726 if (txstat & RE_TDESC_CMD_OWN)
1729 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0;
1732 * We only stash mbufs in the last descriptor
1733 * in a fragment chain, which also happens to
1734 * be the only place where the TX status bits
1737 if (txstat & RE_TDESC_CMD_EOF) {
1738 m_freem(sc->re_ldata.re_tx_mbuf[idx]);
1739 sc->re_ldata.re_tx_mbuf[idx] = NULL;
1740 bus_dmamap_unload(sc->re_ldata.re_mtag,
1741 sc->re_ldata.re_tx_dmamap[idx]);
1742 if (txstat & (RE_TDESC_STAT_EXCESSCOL|
1743 RE_TDESC_STAT_COLCNT))
1744 ifp->if_collisions++;
1745 if (txstat & RE_TDESC_STAT_TXERRSUM)
1750 sc->re_ldata.re_tx_free++;
1752 sc->re_ldata.re_tx_considx = idx;
1754 /* There is enough free TX descs */
1755 if (sc->re_ldata.re_tx_free > RE_TXDESC_SPARE)
1756 ifp->if_flags &= ~IFF_OACTIVE;
1759 * Some chips will ignore a second TX request issued while an
1760 * existing transmission is in progress. If the transmitter goes
1761 * idle but there are still packets waiting to be sent, we need
1762 * to restart the channel here to flush them out. This only seems
1763 * to be required with the PCIe devices.
1765 if (sc->re_ldata.re_tx_free < RE_TX_DESC_CNT)
1766 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
1771 * If not all descriptors have been released reaped yet,
1772 * reload the timer so that we will eventually get another
1773 * interrupt that will cause us to re-enter this routine.
1774 * This is done in case the transmitter has gone idle.
1776 if (RE_TX_MODERATION_IS_ENABLED(sc) &&
1777 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT)
1778 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1784 struct re_softc *sc = xsc;
1786 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1787 re_tick_serialized(xsc);
1788 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1792 re_tick_serialized(void *xsc)
1794 struct re_softc *sc = xsc;
1795 struct ifnet *ifp = &sc->arpcom.ac_if;
1796 struct mii_data *mii;
1798 ASSERT_SERIALIZED(ifp->if_serializer);
1800 mii = device_get_softc(sc->re_miibus);
1803 if (!(mii->mii_media_status & IFM_ACTIVE))
1806 if (mii->mii_media_status & IFM_ACTIVE &&
1807 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1809 if (!ifq_is_empty(&ifp->if_snd))
1814 callout_reset(&sc->re_timer, hz, re_tick, sc);
1817 #ifdef DEVICE_POLLING
1820 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1822 struct re_softc *sc = ifp->if_softc;
1824 ASSERT_SERIALIZED(ifp->if_serializer);
1828 /* disable interrupts */
1829 CSR_WRITE_2(sc, RE_IMR, 0x0000);
1831 case POLL_DEREGISTER:
1832 /* enable interrupts */
1833 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
1836 sc->rxcycles = count;
1840 if (!ifq_is_empty(&ifp->if_snd))
1843 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1846 status = CSR_READ_2(sc, RE_ISR);
1847 if (status == 0xffff)
1850 CSR_WRITE_2(sc, RE_ISR, status);
1853 * XXX check behaviour on receiver stalls.
1856 if (status & RE_ISR_SYSTEM_ERR) {
1864 #endif /* DEVICE_POLLING */
1869 struct re_softc *sc = arg;
1870 struct ifnet *ifp = &sc->arpcom.ac_if;
1873 ASSERT_SERIALIZED(ifp->if_serializer);
1875 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0)
1879 status = CSR_READ_2(sc, RE_ISR);
1880 /* If the card has gone away the read returns 0xffff. */
1881 if (status == 0xffff)
1884 CSR_WRITE_2(sc, RE_ISR, status);
1886 if ((status & sc->re_intrs) == 0)
1889 if (status & (RE_ISR_RX_OK | RE_ISR_RX_ERR | RE_ISR_FIFO_OFLOW))
1892 if ((status & sc->re_tx_ack) ||
1893 (status & RE_ISR_TX_ERR) ||
1894 (status & RE_ISR_TX_DESC_UNAVAIL))
1897 if (status & RE_ISR_SYSTEM_ERR) {
1902 if (status & RE_ISR_LINKCHG) {
1903 callout_stop(&sc->re_timer);
1904 re_tick_serialized(sc);
1908 if (!ifq_is_empty(&ifp->if_snd))
1913 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx0)
1915 struct ifnet *ifp = &sc->arpcom.ac_if;
1917 struct re_dmaload_arg arg;
1918 bus_dma_segment_t segs[RE_MAXSEGS];
1920 int error, maxsegs, idx, i;
1921 struct re_desc *d, *tx_ring;
1922 uint32_t csum_flags;
1924 KASSERT(sc->re_ldata.re_tx_free > RE_TXDESC_SPARE,
1925 ("not enough free TX desc\n"));
1928 map = sc->re_ldata.re_tx_dmamap[*idx0];
1931 * Set up checksum offload. Note: checksum offload bits must
1932 * appear in all descriptors of a multi-descriptor transmit
1933 * attempt. (This is according to testing done with an 8169
1934 * chip. I'm not sure if this is a requirement or a bug.)
1937 if (m->m_pkthdr.csum_flags & CSUM_IP)
1938 csum_flags |= RE_TDESC_CMD_IPCSUM;
1939 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1940 csum_flags |= RE_TDESC_CMD_TCPCSUM;
1941 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1942 csum_flags |= RE_TDESC_CMD_UDPCSUM;
1944 if (m->m_pkthdr.len > sc->re_swcsum_lim &&
1945 (m->m_pkthdr.csum_flags & (CSUM_DELAY_IP | CSUM_DELAY_DATA)) &&
1946 (sc->re_flags & RE_F_JUMBO_SWCSUM)) {
1947 struct ether_header *eh;
1951 m = m_pullup(m, sizeof(struct ether_header *));
1956 eh = mtod(m, struct ether_header *);
1959 if (eh->ether_type == ETHERTYPE_VLAN)
1960 offset = sizeof(struct ether_vlan_header);
1962 offset = sizeof(struct ether_header);
1964 m = m_pullup(m, offset + sizeof(struct ip *));
1969 ip = (struct ip *)(mtod(m, uint8_t *) + offset);
1971 if (m->m_pkthdr.csum_flags & CSUM_DELAY_DATA) {
1974 offset += IP_VHL_HL(ip->ip_vhl) << 2;
1975 csum = in_cksum_skip(m, ntohs(ip->ip_len), offset);
1976 if (m->m_pkthdr.csum_flags & CSUM_UDP && csum == 0)
1978 offset += m->m_pkthdr.csum_data; /* checksum offset */
1979 *(u_short *)(m->m_data + offset) = csum;
1981 m->m_pkthdr.csum_flags &= ~CSUM_DELAY_DATA;
1983 if (m->m_pkthdr.csum_flags & CSUM_DELAY_IP) {
1985 if (ip->ip_vhl == IP_VHL_BORING) {
1986 ip->ip_sum = in_cksum_hdr(ip);
1989 in_cksum(m, IP_VHL_HL(ip->ip_vhl) << 2);
1991 m->m_pkthdr.csum_flags &= ~CSUM_DELAY_IP;
1993 *m_head = m; /* 'm' may be changed by above two m_pullup() */
1997 * With some of the RealTek chips, using the checksum offload
1998 * support in conjunction with the autopadding feature results
1999 * in the transmission of corrupt frames. For example, if we
2000 * need to send a really small IP fragment that's less than 60
2001 * bytes in size, and IP header checksumming is enabled, the
2002 * resulting ethernet frame that appears on the wire will
2003 * have garbled payload. To work around this, if TX checksum
2004 * offload is enabled, we always manually pad short frames out
2005 * to the minimum ethernet frame size. We do this by pretending
2006 * the mbuf chain has too many fragments so the coalescing code
2007 * below can assemble the packet into a single buffer that's
2008 * padded out to the mininum frame size.
2010 * Note: this appears unnecessary for TCP, and doing it for TCP
2011 * with PCIe adapters seems to result in bad checksums.
2013 if (csum_flags && !(csum_flags & RE_TDESC_CMD_TCPCSUM) &&
2014 m->m_pkthdr.len < RE_MIN_FRAMELEN) {
2015 error = re_pad_frame(m);
2020 maxsegs = sc->re_ldata.re_tx_free;
2021 if (maxsegs > RE_MAXSEGS)
2022 maxsegs = RE_MAXSEGS;
2024 arg.re_nsegs = maxsegs;
2026 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, m,
2027 re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
2028 if (error && error != EFBIG) {
2029 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2034 * Too many segments to map, coalesce into a single mbuf
2036 if (!error && arg.re_nsegs == 0) {
2037 bus_dmamap_unload(sc->re_ldata.re_mtag, map);
2043 m_new = m_defrag(m, MB_DONTWAIT);
2044 if (m_new == NULL) {
2045 if_printf(ifp, "can't defrag TX mbuf\n");
2049 *m_head = m = m_new;
2052 arg.re_nsegs = maxsegs;
2054 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, m,
2055 re_dma_map_desc, &arg,
2057 if (error || arg.re_nsegs == 0) {
2059 bus_dmamap_unload(sc->re_ldata.re_mtag, map);
2062 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2066 bus_dmamap_sync(sc->re_ldata.re_mtag, map, BUS_DMASYNC_PREWRITE);
2069 * Map the segment array into descriptors. We also keep track
2070 * of the end of the ring and set the end-of-ring bits as needed,
2071 * and we set the ownership bits in all except the very first
2072 * descriptor, whose ownership bits will be turned on later.
2074 tx_ring = sc->re_ldata.re_tx_list;
2082 cmdstat = segs[i].ds_len;
2083 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
2084 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
2086 cmdstat |= RE_TDESC_CMD_SOF;
2088 cmdstat |= RE_TDESC_CMD_OWN;
2089 if (idx == (RE_TX_DESC_CNT - 1))
2090 cmdstat |= RE_TDESC_CMD_EOR;
2091 d->re_cmdstat = htole32(cmdstat | csum_flags);
2094 if (i == arg.re_nsegs)
2098 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
2101 * Set up hardware VLAN tagging. Note: vlan tag info must
2102 * appear in the first descriptor of a multi-descriptor
2103 * transmission attempt.
2105 if (m->m_flags & M_VLANTAG) {
2106 tx_ring[*idx0].re_vlanctl =
2107 htole32(htobe16(m->m_pkthdr.ether_vlantag) |
2108 RE_TDESC_VLANCTL_TAG);
2111 /* Transfer ownership of packet to the chip. */
2112 d->re_cmdstat |= htole32(RE_TDESC_CMD_OWN);
2114 tx_ring[*idx0].re_cmdstat |= htole32(RE_TDESC_CMD_OWN);
2117 * Insure that the map for this transmission
2118 * is placed at the array index of the last descriptor
2121 sc->re_ldata.re_tx_dmamap[*idx0] = sc->re_ldata.re_tx_dmamap[idx];
2122 sc->re_ldata.re_tx_dmamap[idx] = map;
2124 sc->re_ldata.re_tx_mbuf[idx] = m;
2125 sc->re_ldata.re_tx_free -= arg.re_nsegs;
2138 * Main transmit routine for C+ and gigE NICs.
2142 re_start(struct ifnet *ifp)
2144 struct re_softc *sc = ifp->if_softc;
2145 struct mbuf *m_head;
2146 int idx, need_trans;
2148 ASSERT_SERIALIZED(ifp->if_serializer);
2151 ifq_purge(&ifp->if_snd);
2155 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
2158 idx = sc->re_ldata.re_tx_prodidx;
2161 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
2162 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) {
2163 ifp->if_flags |= IFF_OACTIVE;
2167 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2171 if (re_encap(sc, &m_head, &idx)) {
2172 /* m_head is freed by re_encap(), if we reach here */
2174 ifp->if_flags |= IFF_OACTIVE;
2181 * If there's a BPF listener, bounce a copy of this frame
2184 ETHER_BPF_MTAP(ifp, m_head);
2188 if (RE_TX_MODERATION_IS_ENABLED(sc) &&
2189 sc->re_ldata.re_tx_free != RE_TX_DESC_CNT)
2190 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
2194 /* Flush the TX descriptors */
2195 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
2196 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
2198 sc->re_ldata.re_tx_prodidx = idx;
2201 * RealTek put the TX poll request register in a different
2202 * location on the 8169 gigE chip. I don't know why.
2204 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2206 if (RE_TX_MODERATION_IS_ENABLED(sc)) {
2208 * Use the countdown timer for interrupt moderation.
2209 * 'TX done' interrupts are disabled. Instead, we reset the
2210 * countdown timer, which will begin counting until it hits
2211 * the value in the TIMERINT register, and then trigger an
2212 * interrupt. Each time we write to the TIMERCNT register,
2213 * the timer count is reset to 0.
2215 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
2219 * Set a timeout in case the chip goes out to lunch.
2227 struct re_softc *sc = xsc;
2228 struct ifnet *ifp = &sc->arpcom.ac_if;
2229 struct mii_data *mii;
2233 ASSERT_SERIALIZED(ifp->if_serializer);
2235 mii = device_get_softc(sc->re_miibus);
2238 * Cancel pending I/O and free all RX/TX buffers.
2243 * Enable C+ RX and TX mode, as well as VLAN stripping and
2244 * RX checksum offload. We must configure the C+ register
2245 * before all others.
2247 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
2248 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP |
2249 (ifp->if_capenable & IFCAP_RXCSUM ?
2250 RE_CPLUSCMD_RXCSUM_ENB : 0));
2253 * Init our MAC address. Even though the chipset
2254 * documentation doesn't mention it, we need to enter "Config
2255 * register write enable" mode to modify the ID registers.
2257 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
2258 CSR_WRITE_4(sc, RE_IDR0,
2259 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0])));
2260 CSR_WRITE_2(sc, RE_IDR4,
2261 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4])));
2262 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
2265 * For C+ mode, initialize the RX descriptors and mbufs.
2267 error = re_rx_list_init(sc);
2272 error = re_tx_list_init(sc);
2279 * Load the addresses of the RX and TX lists into the chip.
2281 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
2282 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2283 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2284 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2286 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2287 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2288 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2289 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2292 * Enable transmit and receive.
2294 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2297 * Set the initial TX and RX configuration.
2299 if (sc->re_testmode) {
2300 if (sc->re_type == RE_8169)
2301 CSR_WRITE_4(sc, RE_TXCFG,
2302 RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
2304 CSR_WRITE_4(sc, RE_TXCFG,
2305 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
2307 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
2309 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16);
2311 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
2313 /* Set the individual bit to receive frames for this host only. */
2314 rxcfg = CSR_READ_4(sc, RE_RXCFG);
2315 rxcfg |= RE_RXCFG_RX_INDIV;
2317 /* If we want promiscuous mode, set the allframes bit. */
2318 if (ifp->if_flags & IFF_PROMISC) {
2319 rxcfg |= RE_RXCFG_RX_ALLPHYS;
2320 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2322 rxcfg &= ~RE_RXCFG_RX_ALLPHYS;
2323 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2327 * Set capture broadcast bit to capture broadcast frames.
2329 if (ifp->if_flags & IFF_BROADCAST) {
2330 rxcfg |= RE_RXCFG_RX_BROAD;
2331 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2333 rxcfg &= ~RE_RXCFG_RX_BROAD;
2334 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2338 * Program the multicast filter, if necessary.
2342 #ifdef DEVICE_POLLING
2344 * Disable interrupts if we are polling.
2346 if (ifp->if_flags & IFF_POLLING)
2347 CSR_WRITE_2(sc, RE_IMR, 0);
2348 else /* otherwise ... */
2349 #endif /* DEVICE_POLLING */
2351 * Enable interrupts.
2353 if (sc->re_testmode)
2354 CSR_WRITE_2(sc, RE_IMR, 0);
2356 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
2357 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs);
2359 /* Set initial TX threshold */
2360 sc->re_txthresh = RE_TX_THRESH_INIT;
2362 /* Start RX/TX process. */
2363 if (sc->re_flags & RE_F_HASMPC)
2364 CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
2366 /* Enable receiver and transmitter. */
2367 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2370 if (RE_TX_MODERATION_IS_ENABLED(sc)) {
2372 * Initialize the timer interrupt register so that
2373 * a timer interrupt will be generated once the timer
2374 * reaches a certain number of ticks. The timer is
2375 * reloaded on each transmit. This gives us TX interrupt
2376 * moderation, which dramatically improves TX frame rate.
2378 if (sc->re_type == RE_8169)
2379 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800);
2381 CSR_WRITE_4(sc, RE_TIMERINT, 0x400);
2385 * For 8169 gigE NICs, set the max allowed RX packet
2386 * size so we can receive jumbo frames.
2388 if (sc->re_type == RE_8169)
2389 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2391 if (sc->re_testmode) {
2397 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2399 ifp->if_flags |= IFF_RUNNING;
2400 ifp->if_flags &= ~IFF_OACTIVE;
2403 callout_reset(&sc->re_timer, hz, re_tick, sc);
2407 * Set media options.
2410 re_ifmedia_upd(struct ifnet *ifp)
2412 struct re_softc *sc = ifp->if_softc;
2413 struct mii_data *mii;
2415 ASSERT_SERIALIZED(ifp->if_serializer);
2417 mii = device_get_softc(sc->re_miibus);
2424 * Report current media status.
2427 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2429 struct re_softc *sc = ifp->if_softc;
2430 struct mii_data *mii;
2432 ASSERT_SERIALIZED(ifp->if_serializer);
2434 mii = device_get_softc(sc->re_miibus);
2437 ifmr->ifm_active = mii->mii_media_active;
2438 ifmr->ifm_status = mii->mii_media_status;
2442 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2444 struct re_softc *sc = ifp->if_softc;
2445 struct ifreq *ifr = (struct ifreq *) data;
2446 struct mii_data *mii;
2449 ASSERT_SERIALIZED(ifp->if_serializer);
2453 if (ifr->ifr_mtu > RE_JUMBO_MTU)
2455 ifp->if_mtu = ifr->ifr_mtu;
2458 if (ifp->if_flags & IFF_UP)
2460 else if (ifp->if_flags & IFF_RUNNING)
2470 mii = device_get_softc(sc->re_miibus);
2471 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2474 ifp->if_capenable &= ~(IFCAP_HWCSUM);
2475 ifp->if_capenable |=
2476 ifr->ifr_reqcap & (IFCAP_HWCSUM);
2477 if (ifp->if_capenable & IFCAP_TXCSUM)
2478 ifp->if_hwassist = RE_CSUM_FEATURES;
2480 ifp->if_hwassist = 0;
2481 if (ifp->if_flags & IFF_RUNNING)
2485 error = ether_ioctl(ifp, command, data);
2492 re_watchdog(struct ifnet *ifp)
2494 struct re_softc *sc = ifp->if_softc;
2496 ASSERT_SERIALIZED(ifp->if_serializer);
2498 if_printf(ifp, "watchdog timeout\n");
2507 if (!ifq_is_empty(&ifp->if_snd))
2512 * Stop the adapter and free any mbufs allocated to the
2516 re_stop(struct re_softc *sc)
2518 struct ifnet *ifp = &sc->arpcom.ac_if;
2521 ASSERT_SERIALIZED(ifp->if_serializer);
2524 callout_stop(&sc->re_timer);
2526 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2528 CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2529 CSR_WRITE_2(sc, RE_IMR, 0x0000);
2530 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
2532 re_free_rxchain(sc);
2533 sc->re_drop_rxfrag = 0;
2535 /* Free the TX list buffers. */
2536 for (i = 0; i < RE_TX_DESC_CNT; i++) {
2537 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2538 bus_dmamap_unload(sc->re_ldata.re_mtag,
2539 sc->re_ldata.re_tx_dmamap[i]);
2540 m_freem(sc->re_ldata.re_tx_mbuf[i]);
2541 sc->re_ldata.re_tx_mbuf[i] = NULL;
2545 /* Free the RX list buffers. */
2546 for (i = 0; i < RE_RX_DESC_CNT; i++) {
2547 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2548 bus_dmamap_unload(sc->re_ldata.re_mtag,
2549 sc->re_ldata.re_rx_dmamap[i]);
2550 m_freem(sc->re_ldata.re_rx_mbuf[i]);
2551 sc->re_ldata.re_rx_mbuf[i] = NULL;
2557 * Device suspend routine. Stop the interface and save some PCI
2558 * settings in case the BIOS doesn't restore them properly on
2562 re_suspend(device_t dev)
2564 #ifndef BURN_BRIDGES
2567 struct re_softc *sc = device_get_softc(dev);
2568 struct ifnet *ifp = &sc->arpcom.ac_if;
2570 lwkt_serialize_enter(ifp->if_serializer);
2574 #ifndef BURN_BRIDGES
2575 for (i = 0; i < 5; i++)
2576 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2577 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2578 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2579 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2580 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2585 lwkt_serialize_exit(ifp->if_serializer);
2591 * Device resume routine. Restore some PCI settings in case the BIOS
2592 * doesn't, re-enable busmastering, and restart the interface if
2596 re_resume(device_t dev)
2598 struct re_softc *sc = device_get_softc(dev);
2599 struct ifnet *ifp = &sc->arpcom.ac_if;
2600 #ifndef BURN_BRIDGES
2604 lwkt_serialize_enter(ifp->if_serializer);
2606 #ifndef BURN_BRIDGES
2607 /* better way to do this? */
2608 for (i = 0; i < 5; i++)
2609 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2610 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2611 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2612 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2613 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2615 /* reenable busmastering */
2616 pci_enable_busmaster(dev);
2617 pci_enable_io(dev, SYS_RES_IOPORT);
2620 /* reinitialize interface if necessary */
2621 if (ifp->if_flags & IFF_UP)
2626 lwkt_serialize_exit(ifp->if_serializer);
2632 * Stop all chip I/O so that the kernel's probe routines don't
2633 * get confused by errant DMAs when rebooting.
2636 re_shutdown(device_t dev)
2638 struct re_softc *sc = device_get_softc(dev);
2639 struct ifnet *ifp = &sc->arpcom.ac_if;
2641 lwkt_serialize_enter(ifp->if_serializer);
2643 lwkt_serialize_exit(ifp->if_serializer);
2647 re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS)
2649 struct re_softc *sc = arg1;
2650 struct ifnet *ifp = &sc->arpcom.ac_if;
2651 int error = 0, mod, mod_old;
2653 lwkt_serialize_enter(ifp->if_serializer);
2655 mod_old = mod = RE_TX_MODERATION_IS_ENABLED(sc);
2657 error = sysctl_handle_int(oidp, &mod, 0, req);
2658 if (error || req->newptr == NULL || mod == mod_old)
2660 if (mod != 0 && mod != 1) {
2666 RE_ENABLE_TX_MODERATION(sc);
2668 RE_DISABLE_TX_MODERATION(sc);
2670 if ((ifp->if_flags & (IFF_RUNNING | IFF_UP)) == (IFF_RUNNING | IFF_UP))
2673 lwkt_serialize_exit(ifp->if_serializer);
2678 re_pad_frame(struct mbuf *pkt)
2680 struct mbuf *last = NULL;
2683 padlen = RE_MIN_FRAMELEN - pkt->m_pkthdr.len;
2685 /* if there's only the packet-header and we can pad there, use it. */
2686 if (pkt->m_pkthdr.len == pkt->m_len &&
2687 M_TRAILINGSPACE(pkt) >= padlen) {
2691 * Walk packet chain to find last mbuf. We will either
2692 * pad there, or append a new mbuf and pad it
2694 for (last = pkt; last->m_next != NULL; last = last->m_next)
2697 /* `last' now points to last in chain. */
2698 if (M_TRAILINGSPACE(last) < padlen) {
2701 /* Allocate new empty mbuf, pad it. Compact later. */
2702 MGET(n, MB_DONTWAIT, MT_DATA);
2710 KKASSERT(M_TRAILINGSPACE(last) >= padlen);
2711 KKASSERT(M_WRITABLE(last));
2713 /* Now zero the pad area, to avoid the re cksum-assist bug */
2714 bzero(mtod(last, char *) + last->m_len, padlen);
2715 last->m_len += padlen;
2716 pkt->m_pkthdr.len += padlen;